From patchwork Wed Dec 8 17:14:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12664871 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9C303C4167B for ; Wed, 8 Dec 2021 17:14:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=bh9H6OWl73286Fv9PqtMvUw3UON4ztr/SSpW7Avqfuw=; b=weY6l/4oV5iRQ1 1YNCNvdzNTfn+W78YT31X7PT3v8tFX0WZbNyf+eA+hkpcGqKU6cjcB5d5S2GB92cvn8DC3mniSf2V Khw/6l2Ixj3DzzDn/Uj4hGqStJGH5kEHeWtYdVMxR50oHisoLrXCtuz4TrDD87Bs2Y3KoAED/2BDK fQPptaoSLdi4FmMphfhwSA7ce8wmFH3kCmRz262Wh+ZAqQ9VqV3bmAE3tWeFbmASJS+sS2tEN+MDb 9Ggk7pdyjIPtObZkglZSkAD0Y2jNBDR1Qp5mYAicizN6ObRkd60PBnPN/RNpT7E4FSP37NcSBFaws B0GMT68FZbz9C08PU+VQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mv0Wq-00Dgr6-1L; Wed, 08 Dec 2021 17:14:52 +0000 Received: from mail-lj1-x232.google.com ([2a00:1450:4864:20::232]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mv0Wn-00Dgoa-NH for linux-phy@lists.infradead.org; Wed, 08 Dec 2021 17:14:51 +0000 Received: by mail-lj1-x232.google.com with SMTP id 207so4874112ljf.10 for ; Wed, 08 Dec 2021 09:14:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yjQ+4ebAvK4TgGM0msltCvsHoQYHGywItHMmPjFkemE=; b=F+YB75eAU4+VnIscZjwlg3KpvkeQcqQGAPfad+e4MWNIJjy7sJQ/QRUFtPtLaJcdTx cewORztLE2EXONA4yCZ0pfwQkw0OuabI8kFjcTRZVXSa1YN5yGgV/lXhOW2yAvbwr2BX /8umLnlt9GDu/peOKMirQCcpYD3fe5CILMuyluzWFNc7DVNdtLqQsW0AWQs85hskcAm6 4INrhSrvsGBf/4ESEXDLfOWj+vNlelTWqQpGpmRTEVlnERpqq+QUz9Ai9uETULYB4hmB 1+/NNhnkd5aSDeguuRjdf7qPJrmoxkS3xwOk+VvV/zUx3RpR68JIe60w+jUYlFZ84e+8 A7ow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yjQ+4ebAvK4TgGM0msltCvsHoQYHGywItHMmPjFkemE=; b=gqMwBNOaXgx+AaIgsAceBRyJH2QYQDtJPaCkn2XAN0SCt2lI44o6f/44R3BypOSQU5 SsovPxHf614+XIr+0ilaztQo/mWKu6jKgb6YmQBi7jJFpN9LQMhIjSti8CjttWFC11W9 aQp7RHuNK3M+roqcnagyENs+7NpVNUEEuRv1RW/Haq2Do6G0IUA7DttByAMnCureT4lf wlnKV832o6Yk7IUK19f6UpfrRsU55R5gfuRHCh6QNp7VwKqQp/03mauZjNr/4afNDk+p /Qqp8nTVCS8zXqMkk7D2ADSRb2ZGYcI3p1hmZEK2Ac5ebNr/Y/caO8AMgr1KEpGk0X5P aqFA== X-Gm-Message-State: AOAM533m/TwEJt2+dxHFNtKZUs3YhOcEHfO6xEURqs711BNzv8c70RIk g9cVYAPczCrSJqpBoGzSiaWnWg== X-Google-Smtp-Source: ABdhPJyz6P6nKJo7YPgJedqZFrFW20JXqTwDyoDTi4tl3rnRuIMtTdTCVwJQAc5vZEC8ctIbp5biUg== X-Received: by 2002:a2e:390c:: with SMTP id g12mr774710lja.118.1638983687525; Wed, 08 Dec 2021 09:14:47 -0800 (PST) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id t9sm307213lfe.88.2021.12.08.09.14.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Dec 2021 09:14:46 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Vinod Koul , Kishon Vijay Abraham I , Stanimir Varbanov , Lorenzo Pieralisi Cc: Bjorn Helgaas , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v2 01/10] dt-bindings: pci: qcom: Document PCIe bindings for SM8450 Date: Wed, 8 Dec 2021 20:14:33 +0300 Message-Id: <20211208171442.1327689-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211208171442.1327689-1-dmitry.baryshkov@linaro.org> References: <20211208171442.1327689-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211208_091449_786153_DF4B0862 X-CRM114-Status: UNSURE ( 9.68 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Document the PCIe DT bindings for SM8450 SoC.The PCIe IP is similar to the one used on SM8250. Add the compatible for SM8450. Signed-off-by: Dmitry Baryshkov Acked-by: Manivannan Sadhasivam --- .../devicetree/bindings/pci/qcom,pcie.txt | 21 ++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index a0ae024c2d0c..73bc763c5009 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -15,6 +15,7 @@ - "qcom,pcie-sc8180x" for sc8180x - "qcom,pcie-sdm845" for sdm845 - "qcom,pcie-sm8250" for sm8250 + - "qcom,pcie-sm8450" for sm8450 - "qcom,pcie-ipq6018" for ipq6018 - reg: @@ -169,6 +170,24 @@ - "ddrss_sf_tbu" PCIe SF TBU clock - "pipe" PIPE clock +- clock-names: + Usage: required for sm8450 + Value type: + Definition: Should contain the following entries + - "aux" Auxiliary clock + - "cfg" Configuration clock + - "bus_master" Master AXI clock + - "bus_slave" Slave AXI clock + - "slave_q2a" Slave Q2A clock + - "tbu" PCIe TBU clock + - "ddrss_sf_tbu" PCIe SF TBU clock + - "pipe" PIPE clock + - "pipe_mux" PIPE MUX + - "phy_pipe" PIPE output clock + - "ref" REFERENCE clock + - "aggre0" Aggre NoC PCIe0 AXI clock + - "aggre1" Aggre NoC PCIe1 AXI clock + - resets: Usage: required Value type: @@ -246,7 +265,7 @@ - "ahb" AHB reset - reset-names: - Usage: required for sc8180x, sdm845 and sm8250 + Usage: required for sc8180x, sdm845, sm8250 and sm8450 Value type: Definition: Should contain the following entries - "pci" PCIe core reset From patchwork Wed Dec 8 17:14:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12664873 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A1DA8C433FE for ; Wed, 8 Dec 2021 17:14:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=445XhlDHaJIW+vwRKtr1v1Q2SgYJcI2bzl8u1nJ5/OM=; b=dXSAw1XCIEFGgg Ndh/mFWjL68aMyYPcq5DdTG7TL1v3ys45OzCaX4Awinn0IJ6n+uD7UhPFtQXG075Mepzr4zBdUUlP hv4eBaij6pAO0Z5NtWykqyYEf7Kcovf/tjPbypfI3iePhFcZKk7/ZNTJElXd0Wg9cUkAn3PEw7tT0 1SPEaRpkW+/cZuVMALTHXn4asqaAQNZQ1ZI8UTSYij3K8XNGTRBSfjvDWMw3se2jlSSTiFanfG8Z+ WFl/hHepd2hGnfhYYfkLadOlmiH7ZElxNSczHfM1Z0YkPhpOVmcN+45Qmg5vM+t2MZ6+JeZWFA5jG 54hQWuuyBhwWF+DYkpgg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mv0Wu-00DgtU-4q; Wed, 08 Dec 2021 17:14:56 +0000 Received: from mail-lf1-x133.google.com ([2a00:1450:4864:20::133]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mv0Wr-00Dgqw-9Z for linux-phy@lists.infradead.org; Wed, 08 Dec 2021 17:14:54 +0000 Received: by mail-lf1-x133.google.com with SMTP id c32so6953285lfv.4 for ; Wed, 08 Dec 2021 09:14:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2Gomy4ei7qSbDbo9NwD3wFRtHE34eVnEHILbspr7bME=; b=GiqsfntNaSI82qioDW6hnyhFjU2z/SUV02rzfFzcleBRXBxUMikcAcJFBXER2lPphX hpBEYZ7hK5iBY7fYYy/i3V8SfPqpvRrcF2mT+YSRJhapPmqS9sD6hbI2ymtweqzyavGl vszyLNUCXuolhEDzCPT3qYx9wNxRRZ4TJTVqKGCgoW39G80U4VLGO8DG8IBEMv3Nb/gs Uh/SDY4c+B7KM0eS3r/sbWVlo25+NAM6HnRD65Ub2XteBisifxcPp6dBhwg//8ZxPGBD iy7qzxRFCNgWpfr0fUJwpArWrtgTGKHuQbrmr90V29ZaplojI8HdoEGPbKl56AumC9x7 UR9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2Gomy4ei7qSbDbo9NwD3wFRtHE34eVnEHILbspr7bME=; b=sJyxwgqvcATy0e1Xbsh4EeQJS2YtWnJbNsSB2jInurdEX5tkUQrquN3JI4lEHQi8vA UXYq9TMlk9KtEcrGcyip6K/VqqqfH+un0VZcYihtXbrFSDdYNzV/+znSFNQLpUTfiAT1 Vr60LY3+DcNy9npf/IElMGt2AsR+1R8fSnCNPHSjA6pjJn20tftWCsiiJq8ZSUApa0Ne eU3hvnUtIb6+oDlvvGUpxwj/s8bKM+PgPPj1pdloHxwTUFGH5pnZ/mEThDufmY4OH64s cUgjX/3MRTbPrLf+sxVAgeZOauT8HuLCWLS1e9uGekRPbhPjqtmyHCJtdfXD00vVNIkc an3w== X-Gm-Message-State: AOAM530KSZlcedYBOHwxnobO5VZA47HOEAFWylM0Uh382hyL1pdxM1pD AFt5MRvhc94JsNbXp1ryVHbq7Q== X-Google-Smtp-Source: ABdhPJyLmmHF1K32biMOFJNZVCgRuWge+W86qVR9zXqexHcmbBmvI04a7YqLiRvCokbc8UUgzqQsBQ== X-Received: by 2002:a05:6512:3090:: with SMTP id z16mr701620lfd.335.1638983691372; Wed, 08 Dec 2021 09:14:51 -0800 (PST) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id t9sm307213lfe.88.2021.12.08.09.14.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Dec 2021 09:14:49 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Vinod Koul , Kishon Vijay Abraham I , Stanimir Varbanov , Lorenzo Pieralisi Cc: Bjorn Helgaas , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v2 02/10] dt-bindings: phy: qcom, qmp: Add SM8450 PCIe PHY bindings Date: Wed, 8 Dec 2021 20:14:34 +0300 Message-Id: <20211208171442.1327689-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211208171442.1327689-1-dmitry.baryshkov@linaro.org> References: <20211208171442.1327689-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211208_091453_366172_415D5E4A X-CRM114-Status: UNSURE ( 8.26 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org There are two different PCIe PHYs on SM8450, one having one lane and another with two lanes. Add DT bindings for the first one. Support for second PCIe host and PHY will be submitted separately. Signed-off-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson --- Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml index c59bbca9a900..d18075cb2b5d 100644 --- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml @@ -50,6 +50,7 @@ properties: - qcom,sm8350-qmp-ufs-phy - qcom,sm8350-qmp-usb3-phy - qcom,sm8350-qmp-usb3-uni-phy + - qcom,sm8450-qmp-gen3x1-pcie-phy - qcom,sm8450-qmp-ufs-phy - qcom,sdx55-qmp-pcie-phy - qcom,sdx55-qmp-usb3-uni-phy @@ -333,6 +334,7 @@ allOf: - qcom,sm8250-qmp-gen3x1-pcie-phy - qcom,sm8250-qmp-gen3x2-pcie-phy - qcom,sm8250-qmp-modem-pcie-phy + - qcom,sm8450-qmp-gen3x1-pcie-phy then: properties: clocks: From patchwork Wed Dec 8 17:14:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12664875 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D8D1EC43217 for ; Wed, 8 Dec 2021 17:15:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Jq4Q6iUVycoUS+Hc8SxDegcJCxOYZNmau8UJgp64cHM=; b=y5YP7ZJls1eoiG x+74XqWCRw0UM7q3K/tqcIaNXr0mUjR70c5H8KMoLbE6icxLBACU+4WNRw8M80zwzQLrqxqDXZP17 SlicVjbCGQQHOB2CbBC2+ts9jiqOUq4HDbPmp+Xd9VOg6bSDDCS+5PE04l4Jf4fJRAi6ZzkyMImRI 0vJZcu3Sz7+zTNKHH17DuL/yL2Z/ZNIqAvw3LLOhoub9b6o8qHWbW5by6+iFuUHgxg+6QOOMfreRC BHoethsZIkQeVByCMVgVQFbbJ8bVvqXfIBMP2qEl9X0zftwbKZo/mHFOXzdc176nq+4U1H3Zu2X6Y hFbBzxPYJqdbt5GvJOGw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mv0X2-00Dgxc-9v; Wed, 08 Dec 2021 17:15:04 +0000 Received: from mail-lf1-x12a.google.com ([2a00:1450:4864:20::12a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mv0Wz-00Dgux-Jl for linux-phy@lists.infradead.org; Wed, 08 Dec 2021 17:15:03 +0000 Received: by mail-lf1-x12a.google.com with SMTP id bu18so7060299lfb.0 for ; Wed, 08 Dec 2021 09:15:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3QmlZvAh7iE/Q8WPF7ITSjRQNObeLp5qdEom4fHXBjw=; b=fu7mc+q9xj7hcAq0J/znnfYmQkeo+klIrk1ewOUUkav/ZDGpspSxeBogzPuYDCPJVV 0L/txLQOWFt42LetTkl/Ub86987ZKVBI38DSZ97jThvK16liWaHpBVC2JpPZn4RUzo0v diFOtXpj2P/jnTo/8+qLDsEgyVNTqS3MaGgauX5QKpCpK6A/z9glvF1cnIaPPlI1CtCl ShV+ea0rxIS8wcD4aqeE7M95i9DTncgY0wKIEpkdVwEk+OXgn+mDHqgdRKpl6W/JRhut bVNfMzcGTYxRzZw2QwzQ08EUuNW8Zj1XMIjCViurkPIezU0OktEUxLMaW46AqjnC4Uti AmAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3QmlZvAh7iE/Q8WPF7ITSjRQNObeLp5qdEom4fHXBjw=; b=0EWJxFiXkrRSndnZsquxqasbVLvn2FyLCvahR7B79+0L1C8r1+mvN5tdChQr8rHNTq ZKCtQiZVgGhrrX6Y9eJJzDu1SIvnXC0E5MJK2M4gi0g+p4Bln6S+dEqfM8XxlL3DgSho FQsfP6AyHYZt+W4PlMXkwR2hnII500/2UQPP7LvzERDR35FBmp0oDr2vDLHJDu4Pd/ss +3QNGDK6Aahi3qZi2fAmv+0haHFqQmX28TLj3JXDN4nqi6uGI6bAkIRFsMpE11zFpT8I nyHRm0BepVBYsBRpZSpGo6v4OGCybZ79T+lehbcUTQwph200KohlG2X5Gqlf/LcTr3MA jC8A== X-Gm-Message-State: AOAM5320hXFEeLfjZkTsfc3evN0ZB0shcIobqxwtG/8jwiHx8wph/Nu1 /61hC0Ocj2f+cindAQcRfC/jfQ== X-Google-Smtp-Source: ABdhPJx5Iemr5za6frkAhIiKiHqy9YnUIZLQBDmHlrmw9kbrKQ591J8XBGhwqU8mwAuh7RWChPCWqQ== X-Received: by 2002:a05:6512:138c:: with SMTP id p12mr686133lfa.300.1638983699513; Wed, 08 Dec 2021 09:14:59 -0800 (PST) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id t9sm307213lfe.88.2021.12.08.09.14.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Dec 2021 09:14:55 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Vinod Koul , Kishon Vijay Abraham I , Stanimir Varbanov , Lorenzo Pieralisi Cc: Bjorn Helgaas , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v2 03/10] phy: qcom-qmp: Add SM8450 PCIe0 PHY support Date: Wed, 8 Dec 2021 20:14:35 +0300 Message-Id: <20211208171442.1327689-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211208171442.1327689-1-dmitry.baryshkov@linaro.org> References: <20211208171442.1327689-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211208_091501_679786_DF8BEDC1 X-CRM114-Status: GOOD ( 12.42 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org There are two different PCIe PHYs on SM8450, one having one lane (v5) and another with two lanes (v5.20). This commit adds support for the first PCIe phy only, support for the second PCIe PHY is coming in next commits. Signed-off-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp.c | 125 ++++++++++++++++++++++++++++ drivers/phy/qualcomm/phy-qcom-qmp.h | 33 ++++++++ 2 files changed, 158 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c index a959c97a699f..19c17678b999 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -2866,6 +2866,97 @@ static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), }; +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), +}; + +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04), +}; + +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), +}; + +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), +}; + +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), +}; + struct qmp_phy; /* struct qmp_phy_cfg - per-PHY initialization config */ @@ -4116,6 +4207,37 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = { .is_dual_lane_phy = true, }; +static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = { + .type = PHY_TYPE_PCIE, + .nlanes = 1, + + .serdes_tbl = sm8450_qmp_gen3x1_pcie_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl), + .tx_tbl = sm8450_qmp_gen3x1_pcie_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl), + .rx_tbl = sm8450_qmp_gen3x1_pcie_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl), + .pcs_tbl = sm8450_qmp_gen3x1_pcie_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl), + .pcs_misc_tbl = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl, + .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl), + .clk_list = sdm845_pciephy_clk_l, + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), + .reset_list = sdm845_pciephy_reset_l, + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = sm8250_pcie_regs_layout, + + .start_ctrl = SERDES_START | PCS_START, + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status = PHYSTATUS, + + .has_pwrdn_delay = true, + .pwrdn_delay_min = 995, /* us */ + .pwrdn_delay_max = 1005, /* us */ +}; + static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = { .type = PHY_TYPE_USB3, .nlanes = 1, @@ -5774,6 +5896,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = { }, { .compatible = "qcom,sm8350-qmp-usb3-uni-phy", .data = &sm8350_usb3_uniphy_cfg, + }, { + .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy", + .data = &sm8450_qmp_gen3x1_pciephy_cfg, }, { .compatible = "qcom,sm8450-qmp-ufs-phy", .data = &sm8450_ufsphy_cfg, diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h index e15f461065bb..08422037f81b 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h @@ -1069,6 +1069,15 @@ #define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2 0x828 /* Only for QMP V5 PHY - QSERDES COM registers */ +#define QSERDES_V5_COM_SSC_EN_CENTER 0x010 +#define QSERDES_V5_COM_SSC_PER1 0x01c +#define QSERDES_V5_COM_SSC_PER2 0x020 +#define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0 0x024 +#define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0 0x028 +#define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1 0x030 +#define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1 0x034 +#define QSERDES_V5_COM_CLK_ENABLE1 0x048 +#define QSERDES_V5_COM_SYSCLK_BUF_ENABLE 0x050 #define QSERDES_V5_COM_PLL_IVCO 0x058 #define QSERDES_V5_COM_CP_CTRL_MODE0 0x074 #define QSERDES_V5_COM_CP_CTRL_MODE1 0x078 @@ -1084,10 +1093,22 @@ #define QSERDES_V5_COM_DEC_START_MODE0 0x0bc #define QSERDES_V5_COM_LOCK_CMP2_MODE1 0x0b8 #define QSERDES_V5_COM_DEC_START_MODE1 0x0c4 +#define QSERDES_V5_COM_DIV_FRAC_START1_MODE0 0x0cc +#define QSERDES_V5_COM_DIV_FRAC_START2_MODE0 0x0d0 +#define QSERDES_V5_COM_DIV_FRAC_START3_MODE0 0x0d4 +#define QSERDES_V5_COM_DIV_FRAC_START1_MODE1 0x0d8 +#define QSERDES_V5_COM_DIV_FRAC_START2_MODE1 0x0dc +#define QSERDES_V5_COM_DIV_FRAC_START3_MODE1 0x0e0 #define QSERDES_V5_COM_VCO_TUNE_MAP 0x10c +#define QSERDES_V5_COM_VCO_TUNE1_MODE0 0x110 +#define QSERDES_V5_COM_VCO_TUNE2_MODE0 0x114 +#define QSERDES_V5_COM_VCO_TUNE1_MODE1 0x118 +#define QSERDES_V5_COM_VCO_TUNE2_MODE1 0x11c #define QSERDES_V5_COM_VCO_TUNE_INITVAL2 0x124 +#define QSERDES_V5_COM_CLK_SELECT 0x154 #define QSERDES_V5_COM_HSCLK_SEL 0x158 #define QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL 0x15c +#define QSERDES_V5_COM_CORECLK_DIV_MODE1 0x16c #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0 #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4 @@ -1130,6 +1151,7 @@ #define QSERDES_V5_RX_AC_JTAG_ENABLE 0x068 #define QSERDES_V5_RX_AC_JTAG_MODE 0x078 #define QSERDES_V5_RX_RX_TERM_BW 0x080 +#define QSERDES_V5_RX_TX_ADAPT_POST_THRESH 0x0cc #define QSERDES_V5_RX_VGA_CAL_CNTRL1 0x0d4 #define QSERDES_V5_RX_VGA_CAL_CNTRL2 0x0d8 #define QSERDES_V5_RX_GM_CAL 0x0dc @@ -1167,6 +1189,17 @@ #define QSERDES_V5_RX_DCC_CTRL1 0x1a8 #define QSERDES_V5_RX_VTH_CODE 0x1b0 +/* Only for QMP V5 PHY - USB/PCIe PCS registers */ +#define QPHY_V5_PCS_REFGEN_REQ_CONFIG1 0x0dc +#define QPHY_V5_PCS_RX_SIGDET_LVL 0x188 +#define QPHY_V5_PCS_RATE_SLEW_CNTRL1 0x198 + +/* Only for QMP V5 PHY - PCS_PCIE registers */ +#define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20 +#define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x54 +#define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS 0x94 +#define QPHY_V5_PCS_PCIE_EQ_CONFIG2 0xa8 + /* Only for QMP V5 PHY - UFS PCS registers */ #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010 From patchwork Wed Dec 8 17:14:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12664879 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1422FC4167D for ; Wed, 8 Dec 2021 17:15:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=RPWXr5NJruG0Wqx4zvvMKKryhA3U14JlfO8TmZCu6WI=; b=PEAHE4JxNZ8Mqn H3StXcB1wEVRgeEB5Bu9g5loj14RAAJM9izrVaBbLMfJoubm1Fu0AFM0mnEJpwdsezKNYDn9XRaOK RR2QFtwnDJFnHXlsrOS2dLuPlhnqZpo5eq6TsU01NUeVfSYe4qke0MNGPmdOGBCGR56YoRe3yiiJO UGF8G+SO9w7v/lEAKKMEzG7Rc9mtPMS/KnBw+uj9n9m130E5GDbso77aqaREQef9uGM6cpw7cBeB/ liYBvi5lseuc4fSm8ORQhSRJ/gZ9vi3+XiskoU11iGsxrHPWRB0eDgA/gpt68Yio795I84sulLq3p q5nn+7VlTftVA+NaptSA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mv0X3-00DgyN-EG; Wed, 08 Dec 2021 17:15:05 +0000 Received: from mail-lf1-x133.google.com ([2a00:1450:4864:20::133]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mv0X0-00DgvN-I4 for linux-phy@lists.infradead.org; Wed, 08 Dec 2021 17:15:04 +0000 Received: by mail-lf1-x133.google.com with SMTP id bu18so7060485lfb.0 for ; Wed, 08 Dec 2021 09:15:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6Y2ZRqeUmO4YUgR9WAjDKyt8+cTdgMvUnERg/yjIeS0=; b=GuOsyfhM7U8NLOaFPbHfTXydlacGVNIdo07Wcp/KXWEYEYEMUmVMPIHUIWmOgm7t2B sab7GvFpCsGpnL4wA7MiW3fzZ9jkqyeom90ws7C5jh9QrCfTPEfpXrZ5MUlx62ietrXQ em6yKkQHe98RtyuxPOHOl9FOGbq/UJ4LDNrwa7Im22p/jxScmUmPKpEP7CagzLgdWtlL AOfN8W7iriFNAvIdCeT2eLNfcz0yHnt3hXsMWQqPtKyiUL0XrY5D9cJNLVqz1evr5AYh ls4Vcwg+JIQw5vl6GWxfTe/YO7VQbaIG88na09Eyar8q5O8Whha7ZkaYh1867lECjdSE PbCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6Y2ZRqeUmO4YUgR9WAjDKyt8+cTdgMvUnERg/yjIeS0=; b=xyKpMN/Ui8J46vjaRQj58gTztTqRpnOqwQ3gadUGmjw92oxwm6SGTcWqY4sWmrPMZZ ls7ZpsfsWeDUAgNJHQLZhTTKGrKFDWhSBL9TXaFbDt3KZgco6qRKnMlM12gB+vS+38ED 3o+c0x6dxSN4VS+zHuOInitlpXtHyOwOteiU73+jpQ1UxAciPTRXPVlSH0UYxNI6fTCw prPGREx2fASF3D4SvNuU3cLUOJc/23mbwiX5p20LAZTyEGLppDhdIWHYnfqtIH1yueWI 0gZCBuQ89M/rJx0Jk2CeGZVsE2BFKr/JxDXDv4Ev+5VswarCBWjjKBY5yb+UmYi5eyHc YY6w== X-Gm-Message-State: AOAM5310eI4616hVzHupuu7WdSlLIXtZJvmyNfv30lAWyaWLbUbzWmee 0rczswbHDR2v8Bwm9x1d1S6pGQ== X-Google-Smtp-Source: ABdhPJx3H6nIbQd3ebp/Xslw3u28UjBJZ0zTZlwzG9437QXxZijY/iAplLEbcHACPOnr0cLngF/DqQ== X-Received: by 2002:ac2:455c:: with SMTP id j28mr720603lfm.582.1638983701136; Wed, 08 Dec 2021 09:15:01 -0800 (PST) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id t9sm307213lfe.88.2021.12.08.09.14.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Dec 2021 09:15:00 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Vinod Koul , Kishon Vijay Abraham I , Stanimir Varbanov , Lorenzo Pieralisi Cc: Bjorn Helgaas , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v2 04/10] PCI: qcom: Remove redundancy between qcom_pcie and qcom_pcie_cfg Date: Wed, 8 Dec 2021 20:14:36 +0300 Message-Id: <20211208171442.1327689-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211208171442.1327689-1-dmitry.baryshkov@linaro.org> References: <20211208171442.1327689-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211208_091502_680113_93A3E9A2 X-CRM114-Status: GOOD ( 15.47 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org In preparation to adding more flags to configuration data, use struct qcom_pcie_cfg directly inside struct qcom_pcie, rather than duplicating all its fields. This would save us from the boilerplate code that just copies flags values from one sruct to another one. Signed-off-by: Dmitry Baryshkov --- drivers/pci/controller/dwc/pcie-qcom.c | 39 +++++++++++--------------- 1 file changed, 17 insertions(+), 22 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 1c3d1116bb60..51a0475173fb 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -204,8 +204,7 @@ struct qcom_pcie { union qcom_pcie_resources res; struct phy *phy; struct gpio_desc *reset; - const struct qcom_pcie_ops *ops; - unsigned int pipe_clk_need_muxing:1; + const struct qcom_pcie_cfg *cfg; }; #define to_qcom_pcie(x) dev_get_drvdata((x)->dev) @@ -229,8 +228,8 @@ static int qcom_pcie_start_link(struct dw_pcie *pci) struct qcom_pcie *pcie = to_qcom_pcie(pci); /* Enable Link Training state machine */ - if (pcie->ops->ltssm_enable) - pcie->ops->ltssm_enable(pcie); + if (pcie->cfg->ops->ltssm_enable) + pcie->cfg->ops->ltssm_enable(pcie); return 0; } @@ -1176,7 +1175,7 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) if (ret < 0) return ret; - if (pcie->pipe_clk_need_muxing) { + if (pcie->cfg->pipe_clk_need_muxing) { res->pipe_clk_src = devm_clk_get(dev, "pipe_mux"); if (IS_ERR(res->pipe_clk_src)) return PTR_ERR(res->pipe_clk_src); @@ -1209,7 +1208,7 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) } /* Set TCXO as clock source for pcie_pipe_clk_src */ - if (pcie->pipe_clk_need_muxing) + if (pcie->cfg->pipe_clk_need_muxing) clk_set_parent(res->pipe_clk_src, res->ref_clk_src); ret = clk_bulk_prepare_enable(res->num_clks, res->clks); @@ -1284,7 +1283,7 @@ static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie) struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; /* Set pipe clock as clock source for pcie_pipe_clk_src */ - if (pcie->pipe_clk_need_muxing) + if (pcie->cfg->pipe_clk_need_muxing) clk_set_parent(res->pipe_clk_src, res->phy_pipe_clk); return clk_prepare_enable(res->pipe_clk); @@ -1384,7 +1383,7 @@ static int qcom_pcie_host_init(struct pcie_port *pp) qcom_ep_reset_assert(pcie); - ret = pcie->ops->init(pcie); + ret = pcie->cfg->ops->init(pcie); if (ret) return ret; @@ -1392,16 +1391,16 @@ static int qcom_pcie_host_init(struct pcie_port *pp) if (ret) goto err_deinit; - if (pcie->ops->post_init) { - ret = pcie->ops->post_init(pcie); + if (pcie->cfg->ops->post_init) { + ret = pcie->cfg->ops->post_init(pcie); if (ret) goto err_disable_phy; } qcom_ep_reset_deassert(pcie); - if (pcie->ops->config_sid) { - ret = pcie->ops->config_sid(pcie); + if (pcie->cfg->ops->config_sid) { + ret = pcie->cfg->ops->config_sid(pcie); if (ret) goto err; } @@ -1410,12 +1409,12 @@ static int qcom_pcie_host_init(struct pcie_port *pp) err: qcom_ep_reset_assert(pcie); - if (pcie->ops->post_deinit) - pcie->ops->post_deinit(pcie); + if (pcie->cfg->ops->post_deinit) + pcie->cfg->ops->post_deinit(pcie); err_disable_phy: phy_power_off(pcie->phy); err_deinit: - pcie->ops->deinit(pcie); + pcie->cfg->ops->deinit(pcie); return ret; } @@ -1531,7 +1530,6 @@ static int qcom_pcie_probe(struct platform_device *pdev) struct pcie_port *pp; struct dw_pcie *pci; struct qcom_pcie *pcie; - const struct qcom_pcie_cfg *pcie_cfg; int ret; pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); @@ -1553,15 +1551,12 @@ static int qcom_pcie_probe(struct platform_device *pdev) pcie->pci = pci; - pcie_cfg = of_device_get_match_data(dev); - if (!pcie_cfg || !pcie_cfg->ops) { + pcie->cfg = of_device_get_match_data(dev); + if (!pcie->cfg || !pcie->cfg->ops) { dev_err(dev, "Invalid platform data\n"); return -EINVAL; } - pcie->ops = pcie_cfg->ops; - pcie->pipe_clk_need_muxing = pcie_cfg->pipe_clk_need_muxing; - pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH); if (IS_ERR(pcie->reset)) { ret = PTR_ERR(pcie->reset); @@ -1586,7 +1581,7 @@ static int qcom_pcie_probe(struct platform_device *pdev) goto err_pm_runtime_put; } - ret = pcie->ops->get_resources(pcie); + ret = pcie->cfg->ops->get_resources(pcie); if (ret) goto err_pm_runtime_put; From patchwork Wed Dec 8 17:14:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12664877 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 18A9EC4167E for ; Wed, 8 Dec 2021 17:15:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=rIV4dIqRST5IuMLH5xzjqak+i4UQfmUFtkD1mHyP0hc=; b=halIYpvFcMYpJJ uIk2uRs25n85tqBLrc6RWgJ6YGYROyZiUBC/AHg6fca6QvH3rLd4uhK+gdcbDoYKDjt+idIk35Sgu hNeq4Z0ecHW5v10sQUJ5sQWSyTl0xc5YUWQ0t/4Uut++g7KviEyZH9MiFhFD4ulmhTXwLeV2fhk+N S95I1YbeoMa3+Un6x2Ey8JCCnAVpheQcqeTY+ALOLVr24oYGNdsnnd7SaCEbNFY8wIZ6RbTT06IXg betUYNSROOChosu7MDCNCeu76VzIkUVDi3ECIgEh/rVyB8rkQ3MZ8u2RZVkOseq7+gdUA28R4i4bC gI7bV1mHBKaxNbVyxoaQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mv0X4-00DgzM-HF; Wed, 08 Dec 2021 17:15:06 +0000 Received: from mail-lf1-x135.google.com ([2a00:1450:4864:20::135]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mv0X1-00DgwN-Kr for linux-phy@lists.infradead.org; Wed, 08 Dec 2021 17:15:05 +0000 Received: by mail-lf1-x135.google.com with SMTP id n12so6976016lfe.1 for ; Wed, 08 Dec 2021 09:15:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Dt6ihFbYfqd5aPj9M//CpdMA5RnM8gPqGCN6JmxEFho=; b=LePC9wR8Kh0skORad1zbzTg5eJWAWBKeXylgYw9knG0Vxk8T8GsXoxJaioFtGaFzeL C2bt1KVKbQ3Q21iibLRhyiSFHCosVpbVT5xb1uu0uSBTYCFQUYPjE3j3megDsB3iSsG3 PgDEhLsG/0Ne1iDK0fBEzwciTVkgF3XRcnWdDaBFfJzPOBfssvW9/T8jcV/9iawJcO/N UGJhGuglrshHw4YyWLMafwepsGXGpgrL7N9L1dXjqYDbFcaisDIkTG0syTfvr/1nNAGD 2jC4C6K7Q9tKnJv1QyXRfBQJe5fKLpvv160FW+XuxwhIpiS+zdSYjB7UPJdCHPwROPCp Q6Qg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Dt6ihFbYfqd5aPj9M//CpdMA5RnM8gPqGCN6JmxEFho=; b=4IAIQJFyGkYxdKc42LcPxxH5gSbPUPUwQ/WY52tOtZDN0zCrNodyItqaWZfPfxd6nZ sy7HMOuiYKR8YT8Sil7dJOYLzs4eF+aupkL3V1TxRhpFsxEveQg4GTFkzv0hYl2vQDj4 jlsybL10yEtAoIji6xBRp6r7/Ha8RwVtMPed75i+E/CX0psQ+WwC7PbUA3NpbVyf64vU oE3WGBrl8OOoMOvz9gQm225Q3SLmOy5jrUPBy5kJSgowCqEzl7Km8Fn+TqnR2fpxC4Xr DajcEFEBw5TF1sB3B/oPPrOQsNUBvovAlt+aDF6JnehwZOaEg29n8R54aiNRWKJmCIjk +OxA== X-Gm-Message-State: AOAM533PjWgp24rr4fv6kLnv6iFOTt0ve1Pk0MfgTvIpxd2If+SNjPF4 5LsqBvoKrc55Oo9GcPQ1KAIoXA== X-Google-Smtp-Source: ABdhPJwp2iyfGP9Wq/y45iLN3gPhc74Dj8WW6mUkO3BHNWh/VJp8RSvtgMIqv51PhVPdfpyoprGjIg== X-Received: by 2002:a05:6512:1194:: with SMTP id g20mr716006lfr.58.1638983702065; Wed, 08 Dec 2021 09:15:02 -0800 (PST) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id t9sm307213lfe.88.2021.12.08.09.15.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Dec 2021 09:15:01 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Vinod Koul , Kishon Vijay Abraham I , Stanimir Varbanov , Lorenzo Pieralisi Cc: Bjorn Helgaas , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v2 05/10] PCI: qcom: Add ddrss_sf_tbu flag Date: Wed, 8 Dec 2021 20:14:37 +0300 Message-Id: <20211208171442.1327689-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211208171442.1327689-1-dmitry.baryshkov@linaro.org> References: <20211208171442.1327689-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211208_091503_730746_2CE671CD X-CRM114-Status: GOOD ( 14.46 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Qualcomm PCIe driver uses compatible string to check if the ddrss_sf_tbu clock should be used. Since sc7280 support has added flags, switch to the new mechanism to check if this clock should be used. Signed-off-by: Dmitry Baryshkov --- drivers/pci/controller/dwc/pcie-qcom.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 51a0475173fb..803d3ac18c56 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -194,7 +194,9 @@ struct qcom_pcie_ops { struct qcom_pcie_cfg { const struct qcom_pcie_ops *ops; + /* flags for ops 2.7.0 and 1.9.0 */ unsigned int pipe_clk_need_muxing:1; + unsigned int has_ddrss_sf_tbu_clk:1; }; struct qcom_pcie { @@ -1164,7 +1166,7 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) res->clks[3].id = "bus_slave"; res->clks[4].id = "slave_q2a"; res->clks[5].id = "tbu"; - if (of_device_is_compatible(dev->of_node, "qcom,pcie-sm8250")) { + if (pcie->cfg->has_ddrss_sf_tbu_clk) { res->clks[6].id = "ddrss_sf_tbu"; res->num_clks = 7; } else { @@ -1512,6 +1514,7 @@ static const struct qcom_pcie_cfg sdm845_cfg = { static const struct qcom_pcie_cfg sm8250_cfg = { .ops = &ops_1_9_0, + .has_ddrss_sf_tbu_clk = true, }; static const struct qcom_pcie_cfg sc7280_cfg = { From patchwork Wed Dec 8 17:14:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12664881 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2CFAEC433FE for ; Wed, 8 Dec 2021 17:15:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=XjZuboVjt/zzMLV5clsUVsPH0Z66SCphWyWZPvQix6Q=; b=TTSvdnFwXLdk7E Ko+vuhxjXfnM+tibyGX7AQQKdP2P+DazVuxtR6CLEeLc7Y/phjcozrjHynypZc2Wk3MBhL4L9dcWw U/5oyb8DI6E3KR3nX3dCME1Y0WDKCZTbJu95ACVxYuI/6BjCGRQ69YiSmzIryxefflm+7o7dDPEj9 KJgc6JJIy+J6b2gwMO5jjzmRgwozSxIKVft21NeCerHz10tQX3sIe+7zIP/UgWl8pt3D8/9d8imXR Rx3S2Q53zNdWWUmD7rx+dfz16FiQIgiS1RpMQ96dDlXZ7sBYMahLyH30kd9wIxTlXip6EMzzHovOP hAJQRBJHxaeVeW8Npg0Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mv0X6-00Dh0r-Jc; Wed, 08 Dec 2021 17:15:08 +0000 Received: from mail-lj1-x22e.google.com ([2a00:1450:4864:20::22e]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mv0X3-00Dgxa-Ot for linux-phy@lists.infradead.org; Wed, 08 Dec 2021 17:15:07 +0000 Received: by mail-lj1-x22e.google.com with SMTP id z8so4893557ljz.9 for ; Wed, 08 Dec 2021 09:15:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wEPXQzVdIaAJaFajHhqNAXwmFj0RX6vAN5FVOMJLSsk=; b=rN6jv71K4LGKobQVhVdpNWOgk9+iLv6QEF/uy9rylBKEc3blVGAVdn0xcMnPYIt67J cWxFj2f7hEIaEilkcdPEttCvx/ixWvXTYOfR1xUP6qj7RLIeY5S7tirDAffcWDgSzwom 1QcFaIYQ4dPXzqGDy8N67d6gfo4Rf0eWxshbikHSwkDEEN8FcXLKsbTwbkr0lM1+W3Df O0Ut3IwQtZ/3h83dHDxG9pfXhzgf6qmgKc+OKSxPIF9GPzfQb2y+iXMK3HK85yzAEzwj S64xXzgJ4krKuH7EkcB8SVPPHkEV8P/SlxnIPF+q2kFpnsFc66Yg2iEIXGgkLApM0NJ8 Dpow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wEPXQzVdIaAJaFajHhqNAXwmFj0RX6vAN5FVOMJLSsk=; b=nWiw7KdoVIqxzyBVo1vXfNiraoT8G5Fh3KUS6rwXtXHfMnRUZlf+pMk3GwF3RTBXT4 eSiPlxRYpbm680YP/9UM6rqCh07rIHNWNRUegBCTlk5XHNZoXv8KwphPm+KLdJ8+P1JH UwUQ/ZMvL8kV/p/LBxwT55GmNjSq86z9AqbyU0BcCzDrF2/wcpK7B9TuOPTYLXzwCyeO f+o+OF656lptuQoVyOZ028bSQm0JNe+VCCDTQ1yhVbDDmTiuNoxzjotkhT6/Lgh37lFF ScUsIIl60KpK3FMnWkGbQACuvD+rEteduLN/W63hOOvD0V6pfhRA877+zqW0wm38xuT3 TUgw== X-Gm-Message-State: AOAM533xqdYcxjGVLXCIahzm6RLtpbqMesQtbz/si0w9g/XPyh6gf817 DLL+qPYuBka6Gy9wfYjgQRFGRA== X-Google-Smtp-Source: ABdhPJx32CKp99LVFZ3P41COc4C540SCCKzrsNCmmBwCsFfb+GoSOsUsPry1MCqXdxnvpzZeEYYKwQ== X-Received: by 2002:a2e:7a11:: with SMTP id v17mr696837ljc.33.1638983703685; Wed, 08 Dec 2021 09:15:03 -0800 (PST) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id t9sm307213lfe.88.2021.12.08.09.15.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Dec 2021 09:15:03 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Vinod Koul , Kishon Vijay Abraham I , Stanimir Varbanov , Lorenzo Pieralisi Cc: Bjorn Helgaas , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v2 06/10] PCI: qcom: Add SM8450 PCIe support Date: Wed, 8 Dec 2021 20:14:38 +0300 Message-Id: <20211208171442.1327689-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211208171442.1327689-1-dmitry.baryshkov@linaro.org> References: <20211208171442.1327689-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211208_091505_844668_8133E3BF X-CRM114-Status: GOOD ( 14.77 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org On SM8450 platform PCIe hosts do not use all the clocks (and add several additional clocks), so expand the driver to handle these requirements. Signed-off-by: Dmitry Baryshkov --- drivers/pci/controller/dwc/pcie-qcom.c | 47 +++++++++++++++++++------- 1 file changed, 34 insertions(+), 13 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 803d3ac18c56..ada9c816395d 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -161,7 +161,7 @@ struct qcom_pcie_resources_2_3_3 { /* 6 clocks typically, 7 for sm8250 */ struct qcom_pcie_resources_2_7_0 { - struct clk_bulk_data clks[7]; + struct clk_bulk_data clks[9]; int num_clks; struct regulator_bulk_data supplies[2]; struct reset_control *pci_reset; @@ -196,7 +196,10 @@ struct qcom_pcie_cfg { const struct qcom_pcie_ops *ops; /* flags for ops 2.7.0 and 1.9.0 */ unsigned int pipe_clk_need_muxing:1; + unsigned int has_tbu_clk:1; unsigned int has_ddrss_sf_tbu_clk:1; + unsigned int has_aggre0_clk:1; + unsigned int has_aggre1_clk:1; }; struct qcom_pcie { @@ -1147,6 +1150,7 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; struct dw_pcie *pci = pcie->pci; struct device *dev = pci->dev; + unsigned int idx; int ret; res->pci_reset = devm_reset_control_get_exclusive(dev, "pci"); @@ -1160,18 +1164,22 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) if (ret) return ret; - res->clks[0].id = "aux"; - res->clks[1].id = "cfg"; - res->clks[2].id = "bus_master"; - res->clks[3].id = "bus_slave"; - res->clks[4].id = "slave_q2a"; - res->clks[5].id = "tbu"; - if (pcie->cfg->has_ddrss_sf_tbu_clk) { - res->clks[6].id = "ddrss_sf_tbu"; - res->num_clks = 7; - } else { - res->num_clks = 6; - } + idx = 0; + res->clks[idx++].id = "aux"; + res->clks[idx++].id = "cfg"; + res->clks[idx++].id = "bus_master"; + res->clks[idx++].id = "bus_slave"; + res->clks[idx++].id = "slave_q2a"; + if (pcie->cfg->has_tbu_clk) + res->clks[idx++].id = "tbu"; + if (pcie->cfg->has_ddrss_sf_tbu_clk) + res->clks[idx++].id = "ddrss_sf_tbu"; + if (pcie->cfg->has_aggre0_clk) + res->clks[idx++].id = "aggre0"; + if (pcie->cfg->has_aggre1_clk) + res->clks[idx++].id = "aggre1"; + + res->num_clks = idx; ret = devm_clk_bulk_get(dev, res->num_clks, res->clks); if (ret < 0) @@ -1510,15 +1518,27 @@ static const struct qcom_pcie_cfg ipq4019_cfg = { static const struct qcom_pcie_cfg sdm845_cfg = { .ops = &ops_2_7_0, + .has_tbu_clk = true, }; static const struct qcom_pcie_cfg sm8250_cfg = { .ops = &ops_1_9_0, + .has_tbu_clk = true, .has_ddrss_sf_tbu_clk = true, }; +/* Only for the PCIe0! */ +static const struct qcom_pcie_cfg sm8450_cfg = { + .ops = &ops_1_9_0, + .has_ddrss_sf_tbu_clk = true, + .pipe_clk_need_muxing = true, + .has_aggre0_clk = true, + .has_aggre1_clk = true, +}; + static const struct qcom_pcie_cfg sc7280_cfg = { .ops = &ops_1_9_0, + .has_tbu_clk = true, .pipe_clk_need_muxing = true, }; @@ -1626,6 +1646,7 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-sdm845", .data = &sdm845_cfg }, { .compatible = "qcom,pcie-sm8250", .data = &sm8250_cfg }, { .compatible = "qcom,pcie-sc8180x", .data = &sm8250_cfg }, + { .compatible = "qcom,pcie-sm8450", .data = &sm8450_cfg }, { .compatible = "qcom,pcie-sc7280", .data = &sc7280_cfg }, { } }; From patchwork Wed Dec 8 17:14:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12664885 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3E145C433F5 for ; Wed, 8 Dec 2021 17:15:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=nSOjRwv2q/pBXUSupE26jWWm7Xki7L6+zWDFqgSDLj4=; b=hKN8R10+jsseRP JZtFCDx/q546eiRlDFULH7axXaEqPr0sU9MhF3r7y9rlV9mqKsWzO9O1TqWCh3I3+VqFeOycYc3LH NjAf20m/LTHEKOKH5MsCJA8NTxYRrX9TsSTnOp8HM1C0UKOTyfuwi9tdNhlNK+1J6X8wExmQpa/zL hwxX9gwjbQGATn2ogFixsjXXsn0d048yzlZV1bd4QBrBEOGidXEjC62J37yOqSoFwmdmYN2ADGZey 5XQjVENOghuYGkJ2tj6ujetKsyeeVHjwP8y8MLC4wjhU4qwMtUu1DGJgXCbcfWV2w1ErKpZITOx9B kyWqs5/8kXDNhy+6BP3Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mv0X7-00Dh1v-NE; Wed, 08 Dec 2021 17:15:09 +0000 Received: from mail-lj1-x229.google.com ([2a00:1450:4864:20::229]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mv0X4-00DgyM-VS for linux-phy@lists.infradead.org; Wed, 08 Dec 2021 17:15:08 +0000 Received: by mail-lj1-x229.google.com with SMTP id a37so3816474ljq.13 for ; Wed, 08 Dec 2021 09:15:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Wy6PRuTmEIMuhgtUQE9Eh1epb/l1hlZtagcw8/LrEbU=; b=kvTv6C4DVypWGEwARfUKPOmofEd1AiPIkwobEqg4MZlDhOF4WnIH4Yc3JT3QIhWNdQ nnZDDPRhH9Qyow80n+YW0gw5pATWqYmYKcg0Xqte8qvcO4LOWzMpYM+lc1iV3H+y9muY CF+HraWcBKwBpbCrdyTufnd0qWrNmuclZ5EDJuw+wZrfjT77S9dx4jfz9cX3TXR+ER8A jcu/X/7E7Tqdw/rPFE+eWM1vGm3XTHBSYoMdMS7mxOZlApLeEWMIuxH0ZNUmVnTgp0UU 5pC/RXqbhetm5rVWCtxqh7Y4ilRfmSF4QXNWD0K3LGG9aIDHstzV8IrBdXwXqj0vWygE IuQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Wy6PRuTmEIMuhgtUQE9Eh1epb/l1hlZtagcw8/LrEbU=; b=OAOZB8fgenzJc85hdEew6FWEhIRhPSRrRdoIWHxqGjUNfswvGtpENFfPLuzhDpxeq2 XpjyK7e5S6PHPQX6wJU4ObG3yFb6k5sto5AEA+O6EPHHSx6xFmwjqDCHjZHFIEOA3YOS RILVfbpHP6XLbN4t0ZGtDmhTcmwOa2YO/Gu8w7r27Lgfg0fZux0mUEMaLgPm21QIqwYw NrQv/6LQxwrheT3xttHLq/PkEm9B4C4VAZduxbewtcXZsrQdIAcDPtNadIXWwgO8wIDw W0gAv8nOc1bKvTDvQHDfBQHpwVykm2WQXDJ7ZOQAgDUcvYAH3st62Ln8ck/Iy6b+w2JS 7NnA== X-Gm-Message-State: AOAM533JSnfsu2X9bGZZdhkFRYwkeaR/vhtUS/5/YYgWtbSjxikVevvs 6egfRFsermJdZ46fJ8PlyPK0EQ== X-Google-Smtp-Source: ABdhPJzWt+rW3M5J9Q9k2uKuS7PJ5quzNSxtn7Zouh8GMb+UI2nU8BN3fSgMDl7upQs9oJGaG6smuQ== X-Received: by 2002:a2e:9dcf:: with SMTP id x15mr780862ljj.432.1638983704839; Wed, 08 Dec 2021 09:15:04 -0800 (PST) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id t9sm307213lfe.88.2021.12.08.09.15.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Dec 2021 09:15:04 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Vinod Koul , Kishon Vijay Abraham I , Stanimir Varbanov , Lorenzo Pieralisi Cc: Bjorn Helgaas , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v2 07/10] arm64: dts: qcom: sm8450: add PCIe0 PHY node Date: Wed, 8 Dec 2021 20:14:39 +0300 Message-Id: <20211208171442.1327689-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211208171442.1327689-1-dmitry.baryshkov@linaro.org> References: <20211208171442.1327689-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211208_091507_084305_1462758E X-CRM114-Status: UNSURE ( 9.78 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Add device tree node for the first PCIe PHY device found on the Qualcomm SM8450 platform. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 42 ++++++++++++++++++++++++++-- 1 file changed, 40 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 16a789cacb65..a047d8a22897 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -558,8 +558,12 @@ gcc: clock-controller@100000 { #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; - clock-names = "bi_tcxo", "sleep_clk"; - clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&pcie0_lane>, + <&sleep_clk>; + clock-names = "bi_tcxo", + "pcie_0_pipe_clk", + "sleep_clk"; }; qupv3_id_0: geniqup@9c0000 { @@ -625,6 +629,40 @@ i2c14: i2c@a98000 { }; }; + pcie0_phy: phy@1c06000 { + compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy"; + reg = <0 0x01c06000 0 0x200>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_CLKREF_EN>, + <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "refgen"; + + resets = <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + status = "disabled"; + + pcie0_lane: lanes@1c06200 { + reg = <0 0x1c06e00 0 0x200>, /* tx */ + <0 0x1c07000 0 0x200>, /* rx */ + <0 0x1c06200 0 0x200>, /* pcs */ + <0 0x1c06600 0 0x200>; /* pcs_pcie */ + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names = "pipe0"; + + #clock-cells = <0>; + #phy-cells = <0>; + clock-output-names = "pcie_0_pipe_clk"; + }; + }; + config_noc: interconnect@1500000 { compatible = "qcom,sm8450-config-noc"; reg = <0 0x01500000 0 0x1c000>; From patchwork Wed Dec 8 17:14:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12664883 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 588FFC4332F for ; Wed, 8 Dec 2021 17:15:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=R6Y8P25HJ35nvUuuhLRQf9zDrHp8yxeo9ITi2sjQ498=; b=3kO8dQF0/egH6O b8IStGTBMtLOe5slOiogK/DS9hLYChS9AuaGfy28VxynGZRFMlf1jXW0OWhpC+RaPVYH4DJdbQq65 +dB6ZIlT4jrN+6X2/ZWdKdraCNFjGxYc9Qdxtu9DYM2kyc4u9vehaRYC9RSWgmozBtoWbgAXHw1ta RwbKJFozQRhk1pEp50nQRAeklmdNlj+Uw2Gbg02+YhBjYA+cMcbeWPMy18dWApelO2uNUZ+Lo0cVj pbjB4J64G4xtvP2NCqanmuxDHldF1tNjH4k9xkMbj9hcbtGFom/4J8jilz6Xr8nnfMHpDYCphRoyq 92L/YBO4uCRcuXQKYZRA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mv0X7-00Dh27-Qf; Wed, 08 Dec 2021 17:15:09 +0000 Received: from mail-lf1-x133.google.com ([2a00:1450:4864:20::133]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mv0X5-00DgzE-3K for linux-phy@lists.infradead.org; Wed, 08 Dec 2021 17:15:08 +0000 Received: by mail-lf1-x133.google.com with SMTP id bu18so7060889lfb.0 for ; Wed, 08 Dec 2021 09:15:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CkjJueskC61HJ/9+LZZr5rRLuA13RiM7nsIGLfBSnLA=; b=InXqlkb8bYIUHb0nJPDLrzLzo+1jrkcmFWO4SNdew8tYqlxT0PUSRd7ud3TFEIXGkG htH+v8JbkW5jmOK5zn989xk9zKjoRULkuw+ghHgD3vWyNtsmN1tIRcFGLHCqk0P5TUpw sjFC/goO/2Wu50E8aHMM/ftC02Jh/OhK1NqSdPUES3zBaTCo86qrldTxI+j0ssuLqsQc kCtA8j3xKjPLTQ9IHQ8MnNcn3Tf0seYV1PRv5Py3m9Jpvqxgje1Kx1RBk9pVEUkgM0qa s0VEHnPD8WZrzxy4ZMT1gLxRykx9kdYYTfAyyw05Sq6C3dKYxxmNXrdlF5Tgj8ZsKmTe BlGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CkjJueskC61HJ/9+LZZr5rRLuA13RiM7nsIGLfBSnLA=; b=qFiWnUomA5x0ULpXXa5SNRCD3gfXdwXwwtbR2XO5XfIw6+gVEEOzktEBUJMDAkAVb2 AtuVOUvy92p1ECUraXGfSR+RkU1SnEntgtcagUORkhv7pTLBteanAM9jKRThFte1sS+h D7/BEaHRZyf8YfVgwEG7iDmP1QWd0Am6HhZfL5M2bz3cbbuNLeiw4vO0+Y+ndR0jxqhG /5rvpWqe2t+Yq2hTXfTn6jdkaufEgn6/Namzf62qpGI9z+SsNj3+L1i9OznYwqSxadVY 7JeJT/MqKIaCZbNJXomD+cp/XTmV+b4ysWTPVQzWFsseyszkPGSs6UiotT7o0xn3vS3L S4Jw== X-Gm-Message-State: AOAM533PzgKIon1Gmp9qPMUYcWuZyqjAntHMFkAeSIT8c2xcamvDlWiI CzToxwQHJLyHyU8ghd7P7fpNcQ== X-Google-Smtp-Source: ABdhPJy7w2PoI4pjdcMwTMAP8qXMGY5JW498WPPj2dVvRdOn3JxwFH7bVFzXWEGU2mhNJmADz/8mLQ== X-Received: by 2002:a05:6512:6c7:: with SMTP id u7mr702294lff.636.1638983705646; Wed, 08 Dec 2021 09:15:05 -0800 (PST) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id t9sm307213lfe.88.2021.12.08.09.15.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Dec 2021 09:15:05 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Vinod Koul , Kishon Vijay Abraham I , Stanimir Varbanov , Lorenzo Pieralisi Cc: Bjorn Helgaas , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v2 08/10] arm64: dts: qcom: sm8450: add PCIe0 RC device Date: Wed, 8 Dec 2021 20:14:40 +0300 Message-Id: <20211208171442.1327689-9-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211208171442.1327689-1-dmitry.baryshkov@linaro.org> References: <20211208171442.1327689-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211208_091507_182075_9BBDA2F5 X-CRM114-Status: UNSURE ( 9.53 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Add device tree node for the first PCIe host found on the Qualcomm SM8450 platform. Signed-off-by: Dmitry Baryshkov Acked-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 101 +++++++++++++++++++++++++++ 1 file changed, 101 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index a047d8a22897..09087a34a007 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -627,6 +627,84 @@ i2c14: i2c@a98000 { #size-cells = <0>; status = "disabled"; }; + ]; + + pcie0: pci@1c00000 { + compatible = "qcom,pcie-sm8450"; + reg = <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, + <&pcie0_lane>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; + clock-names = "pipe", + "pipe_mux", + "phy_pipe", + "ref", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ddrss_sf_tbu", + "aggre0", + "aggre1"; + + iommus = <&apps_smmu 0x1c00 0x7f>; + iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, + <0x100 &apps_smmu 0x1c01 0x1>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_0_GDSC>; + power-domain-names = "gdsc"; + + phys = <&pcie0_lane>; + phy-names = "pciephy"; + + perst-gpio = <&tlmm 94 GPIO_ACTIVE_LOW>; + enable-gpio = <&tlmm 96 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_default_state>; + + interconnects = <&pcie_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>; + interconnect-names = "pci"; + + status = "disabled"; }; pcie0_phy: phy@1c06000 { @@ -763,6 +841,29 @@ tlmm: pinctrl@f100000 { gpio-ranges = <&tlmm 0 0 211>; wakeup-parent = <&pdc>; + pcie0_default_state: pcie0-default { + perst { + pins = "gpio94"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq { + pins = "gpio95"; + function = "pcie0_clkreqn"; + drive-strength = <2>; + bias-pull-up; + }; + + wake { + pins = "gpio96"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + qup_i2c13_default_state: qup-i2c13-default-state { mux { pins = "gpio48", "gpio49";