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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; Received: from SATLEXMB03.amd.com (165.204.84.17) by CO1NAM11FT058.mail.protection.outlook.com (10.13.174.164) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4755.13 via Frontend Transport; Wed, 8 Dec 2021 17:44:13 +0000 Received: from yaz-ethanolx.amd.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Wed, 8 Dec 2021 11:44:12 -0600 From: Yazen Ghannam To: CC: , , , , , , , , "Yazen Ghannam" Subject: [PATCH 1/4] EDAC: Add RDDR5 and LRDDR5 memory types Date: Wed, 8 Dec 2021 17:43:53 +0000 Message-ID: <20211208174356.1997855-2-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211208174356.1997855-1-yazen.ghannam@amd.com> References: <20211208174356.1997855-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB03.amd.com (10.181.40.144) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 80710411-ae93-4b3b-0a86-08d9ba725955 X-MS-TrafficTypeDiagnostic: DM6PR12MB4810:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2733; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Dec 2021 17:44:13.5857 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 80710411-ae93-4b3b-0a86-08d9ba725955 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT058.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4810 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Include Registered-DDR5 and Load-Reduced DDR5 in the list of memory types. Signed-off-by: Yazen Ghannam --- drivers/edac/edac_mc.c | 2 ++ include/linux/edac.h | 6 ++++++ 2 files changed, 8 insertions(+) diff --git a/drivers/edac/edac_mc.c b/drivers/edac/edac_mc.c index 9f82ca295353..9d9aabdec96b 100644 --- a/drivers/edac/edac_mc.c +++ b/drivers/edac/edac_mc.c @@ -162,6 +162,8 @@ const char * const edac_mem_types[] = { [MEM_LPDDR4] = "Low-Power-DDR4-RAM", [MEM_LRDDR4] = "Load-Reduced-DDR4-RAM", [MEM_DDR5] = "Unbuffered-DDR5", + [MEM_RDDR5] = "Registered-DDR5", + [MEM_LRDDR5] = "Load-Reduced-DDR5-RAM", [MEM_NVDIMM] = "Non-volatile-RAM", [MEM_WIO2] = "Wide-IO-2", [MEM_HBM2] = "High-bandwidth-memory-Gen2", diff --git a/include/linux/edac.h b/include/linux/edac.h index 4207d06996a4..e730b3468719 100644 --- a/include/linux/edac.h +++ b/include/linux/edac.h @@ -182,6 +182,8 @@ static inline char *mc_event_error_type(const unsigned int err_type) * @MEM_LRDDR4: Load-Reduced DDR4 memory. * @MEM_LPDDR4: Low-Power DDR4 memory. * @MEM_DDR5: Unbuffered DDR5 RAM + * @MEM_RDDR5: Registered DDR5 RAM + * @MEM_LRDDR5: Load-Reduced DDR5 memory. * @MEM_NVDIMM: Non-volatile RAM * @MEM_WIO2: Wide I/O 2. * @MEM_HBM2: High bandwidth Memory Gen 2. @@ -211,6 +213,8 @@ enum mem_type { MEM_LRDDR4, MEM_LPDDR4, MEM_DDR5, + MEM_RDDR5, + MEM_LRDDR5, MEM_NVDIMM, MEM_WIO2, MEM_HBM2, @@ -239,6 +243,8 @@ enum mem_type { #define MEM_FLAG_LRDDR4 BIT(MEM_LRDDR4) #define MEM_FLAG_LPDDR4 BIT(MEM_LPDDR4) #define MEM_FLAG_DDR5 BIT(MEM_DDR5) +#define MEM_FLAG_RDDR5 BIT(MEM_RDDR5) +#define MEM_FLAG_LRDDR5 BIT(MEM_LRDDR5) #define MEM_FLAG_NVDIMM BIT(MEM_NVDIMM) #define MEM_FLAG_WIO2 BIT(MEM_WIO2) #define MEM_FLAG_HBM2 BIT(MEM_HBM2) From patchwork Wed Dec 8 17:43:54 2021 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Dec 2021 17:44:15.8667 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8ab5cb03-c45a-42b8-1b01-08d9ba725ab1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT058.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4375 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Add a new family type for AMD Family 19h Models 10h to 1Fh. Use this new family type for Models A0h to AFh also. Increase the maximum number of controllers from 8 to 12. Signed-off-by: Yazen Ghannam --- drivers/edac/amd64_edac.c | 21 ++++++++++++++++++++- drivers/edac/amd64_edac.h | 5 ++++- 2 files changed, 24 insertions(+), 2 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index ca0c67bc25c6..ff29267e46a6 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -2925,6 +2925,16 @@ static struct amd64_family_type family_types[] = { .dbam_to_cs = f17_addr_mask_to_cs_size, } }, + [F19_M10H_CPUS] = { + .ctl_name = "F19h_M10h", + .f0_id = PCI_DEVICE_ID_AMD_19H_M10H_DF_F0, + .f6_id = PCI_DEVICE_ID_AMD_19H_M10H_DF_F6, + .max_mcs = 12, + .ops = { + .early_channel_count = f17_early_channel_count, + .dbam_to_cs = f17_addr_mask_to_cs_size, + } + }, }; /* @@ -3962,11 +3972,20 @@ static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt) break; case 0x19: - if (pvt->model >= 0x20 && pvt->model <= 0x2f) { + if (pvt->model >= 0x10 && pvt->model <= 0x1f) { + fam_type = &family_types[F19_M10H_CPUS]; + pvt->ops = &family_types[F19_M10H_CPUS].ops; + break; + } else if (pvt->model >= 0x20 && pvt->model <= 0x2f) { fam_type = &family_types[F17_M70H_CPUS]; pvt->ops = &family_types[F17_M70H_CPUS].ops; fam_type->ctl_name = "F19h_M20h"; break; + } else if (pvt->model >= 0xa0 && pvt->model <= 0xaf) { + fam_type = &family_types[F19_M10H_CPUS]; + pvt->ops = &family_types[F19_M10H_CPUS].ops; + fam_type->ctl_name = "F19h_MA0h"; + break; } fam_type = &family_types[F19_CPUS]; pvt->ops = &family_types[F19_CPUS].ops; diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h index 85aa820bc165..650cab401e21 100644 --- a/drivers/edac/amd64_edac.h +++ b/drivers/edac/amd64_edac.h @@ -96,7 +96,7 @@ /* Hardware limit on ChipSelect rows per MC and processors per system */ #define NUM_CHIPSELECTS 8 #define DRAM_RANGES 8 -#define NUM_CONTROLLERS 8 +#define NUM_CONTROLLERS 12 #define ON true #define OFF false @@ -126,6 +126,8 @@ #define PCI_DEVICE_ID_AMD_17H_M70H_DF_F6 0x1446 #define PCI_DEVICE_ID_AMD_19H_DF_F0 0x1650 #define PCI_DEVICE_ID_AMD_19H_DF_F6 0x1656 +#define PCI_DEVICE_ID_AMD_19H_M10H_DF_F0 0x14ad +#define PCI_DEVICE_ID_AMD_19H_M10H_DF_F6 0x14b3 /* * Function 1 - Address Map @@ -298,6 +300,7 @@ enum amd_families { F17_M60H_CPUS, F17_M70H_CPUS, F19_CPUS, + F19_M10H_CPUS, NUM_FAMILIES, }; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; Received: from SATLEXMB03.amd.com (165.204.84.17) by CO1NAM11FT059.mail.protection.outlook.com (10.13.174.160) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4755.13 via Frontend Transport; Wed, 8 Dec 2021 17:44:17 +0000 Received: from yaz-ethanolx.amd.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Wed, 8 Dec 2021 11:44:16 -0600 From: Yazen Ghannam To: CC: , , , , , , , , "Yazen Ghannam" Subject: [PATCH 3/4] EDAC/amd64: Check register values from all UMCs Date: Wed, 8 Dec 2021 17:43:55 +0000 Message-ID: <20211208174356.1997855-4-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211208174356.1997855-1-yazen.ghannam@amd.com> References: <20211208174356.1997855-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB03.amd.com (10.181.40.144) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b9a9d846-2938-4dae-8e5e-08d9ba725bd6 X-MS-TrafficTypeDiagnostic: BY5PR12MB3794:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4125; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Dec 2021 17:44:17.7889 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b9a9d846-2938-4dae-8e5e-08d9ba725bd6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT059.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB3794 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Loop over all UMCs and create bitmasks to check the values of the DIMM_CFG and UMC_CFG registers rather than just checking the values from the first two UMCs. Signed-off-by: Yazen Ghannam --- drivers/edac/amd64_edac.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index ff29267e46a6..1df763128483 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1621,9 +1621,16 @@ static void determine_memory_type(struct amd64_pvt *pvt) u32 dram_ctrl, dcsm; if (pvt->umc) { - if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(5)) + u32 umc_cfg = 0, dimm_cfg = 0, i = 0; + + for_each_umc(i) { + umc_cfg |= pvt->umc[i].umc_cfg; + dimm_cfg |= pvt->umc[i].dimm_cfg; + } + + if (dimm_cfg & BIT(5)) pvt->dram_type = MEM_LRDDR4; - else if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(4)) + else if (dimm_cfg & BIT(4)) pvt->dram_type = MEM_RDDR4; else pvt->dram_type = MEM_DDR4; From patchwork Wed Dec 8 17:43:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12664951 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20818C433F5 for ; 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Wed, 8 Dec 2021 11:44:18 -0600 From: Yazen Ghannam To: CC: , , , , , , , , "Yazen Ghannam" Subject: [PATCH 4/4] EDAC/amd64: Add DDR5 support and related register changes Date: Wed, 8 Dec 2021 17:43:56 +0000 Message-ID: <20211208174356.1997855-5-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211208174356.1997855-1-yazen.ghannam@amd.com> References: <20211208174356.1997855-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB03.amd.com (10.181.40.144) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 84e825d9-9b06-4add-0c82-08d9ba725cd6 X-MS-TrafficTypeDiagnostic: MWHPR12MB1311:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6108; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: CHyF1d2sfXtmEqUlP869L3eAfzLF3P+hJ8zrTivmehf+rzpjdPnszHiARBpGExVZlfcG1VxSmpnLn9g/fQqwy+35WuLzLMDzlA3nPrFiD4NaVWxwtCgM7AtxHZi4XzFWqql4QPSLFayIAjiYOS8EzjnhLBlmwZfgy2DeE65ho8SZkJVl1cobgHDVlvvjqWod1664PjfRQo5mf48YCSeThRMgdArnr6mOl0idfpRWAxT5w1B4xV5yxSrxF7iUd9vfPHIchxaq4IA+ZNUUtySMNyS11JI5vECMziVatEF1qoygZtTXBpWM1Vv9dz5Dczh73rKxN9uPA1JZlRUPVeVBK1q1K0MXYxigd/MPHnjZy/9PmVJRyS0pBT4GDuiVA6Q6Pf+CyWt1I09/pS88q+T2wy+yVsjLFxb0293N/On2RTTK9z0CcqCc2TTMrpFj+AF7Yiw0ZvzUVCJDw17tPa0BiDV0AjauOHRoCfqxUDEUccVrVUp7TrW9EgOTMLMLQvRHRYYqfz3l9FLD1vt+U7Rb9aNL9ctv7uzrGh7BgecSwK0s+gQzNWb9OPNjImAkSp3Pcc9vwCl6UtlJbczCNJWuUV+gkdLXADO1zlhfDG2y2gcGu67goiWu6fOirCswNrpkjLRFkKrbDPmjYHK/8Z9a0q+9pYP6q+ksVmQ12qHIa9HOuneePKJeDa7c2PbUQRt9vHI3M1iFZ+lwAaZji3Kr+79034Ra7b5jgBR2fRNBpsCNbGfrs7zfEA5EeTZTjiPTowUoTc8rPithgjp9pYKLYAuc6QEqQMo7fnrV0kUxAsQ= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(40470700001)(7696005)(8936002)(2616005)(44832011)(36860700001)(82310400004)(70206006)(356005)(70586007)(81166007)(316002)(26005)(54906003)(5660300002)(508600001)(2906002)(6666004)(1076003)(40460700001)(8676002)(426003)(186003)(4326008)(86362001)(83380400001)(336012)(47076005)(16526019)(36756003)(6916009)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Dec 2021 17:44:19.4643 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 84e825d9-9b06-4add-0c82-08d9ba725cd6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT065.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1311 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Future AMD systems will support DDR5. Add support for changes in register addresses for these systems. Introduce a "family flags" bitmask that can be used to indicate any special behavior needed on a per-family basis. Signed-off-by: Yazen Ghannam --- drivers/edac/amd64_edac.c | 61 +++++++++++++++++++++++++++++++++++---- drivers/edac/amd64_edac.h | 11 +++++++ 2 files changed, 66 insertions(+), 6 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 1df763128483..e37a8e0cef7e 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -15,6 +15,36 @@ static struct msr __percpu *msrs; static struct amd64_family_type *fam_type; +/* Family flag helpers */ +static inline bool has_ddr5(void) +{ + return fam_type->flags.has_ddr5; +} + +static inline u64 get_addr_cfg(void) +{ + if (has_ddr5()) + return UMCCH_ADDR_CFG_DDR5; + + return UMCCH_ADDR_CFG; +} + +static inline u64 get_addr_mask_sec(void) +{ + if (has_ddr5()) + return UMCCH_ADDR_MASK_SEC_DDR5; + + return UMCCH_ADDR_MASK_SEC; +} + +static inline u64 get_dimm_cfg(void) +{ + if (has_ddr5()) + return UMCCH_DIMM_CFG_DDR5; + + return UMCCH_DIMM_CFG; +} + /* Per-node stuff */ static struct ecc_settings **ecc_stngs; @@ -1429,8 +1459,10 @@ static void __dump_misc_regs_df(struct amd64_pvt *pvt) edac_dbg(1, "UMC%d x16 DIMMs present: %s\n", i, (umc->dimm_cfg & BIT(7)) ? "yes" : "no"); - if (pvt->dram_type == MEM_LRDDR4) { - amd_smn_read(pvt->mc_node_id, umc_base + UMCCH_ADDR_CFG, &tmp); + if (pvt->dram_type == MEM_LRDDR4 || pvt->dram_type == MEM_LRDDR5) { + amd_smn_read(pvt->mc_node_id, + umc_base + get_addr_cfg(), + &tmp); edac_dbg(1, "UMC%d LRDIMM %dx rank multiply\n", i, 1 << ((tmp >> 4) & 0x3)); } @@ -1505,7 +1537,7 @@ static void prep_chip_selects(struct amd64_pvt *pvt) for_each_umc(umc) { pvt->csels[umc].b_cnt = 4; - pvt->csels[umc].m_cnt = 2; + pvt->csels[umc].m_cnt = has_ddr5() ? 4 : 2; } } else { @@ -1545,7 +1577,7 @@ static void read_umc_base_mask(struct amd64_pvt *pvt) } umc_mask_reg = get_umc_base(umc) + UMCCH_ADDR_MASK; - umc_mask_reg_sec = get_umc_base(umc) + UMCCH_ADDR_MASK_SEC; + umc_mask_reg_sec = get_umc_base(umc) + get_addr_mask_sec(); for_each_chip_select_mask(cs, umc, pvt) { mask = &pvt->csels[umc].csmasks[cs]; @@ -1628,6 +1660,17 @@ static void determine_memory_type(struct amd64_pvt *pvt) dimm_cfg |= pvt->umc[i].dimm_cfg; } + /* Check if system supports DDR5 and has DDR5 DIMMs in use. */ + if (has_ddr5() && (umc_cfg & BIT(0))) { + if (dimm_cfg & BIT(5)) + pvt->dram_type = MEM_LRDDR5; + else if (dimm_cfg & BIT(4)) + pvt->dram_type = MEM_RDDR5; + else + pvt->dram_type = MEM_DDR5; + return; + } + if (dimm_cfg & BIT(5)) pvt->dram_type = MEM_LRDDR4; else if (dimm_cfg & BIT(4)) @@ -2174,8 +2217,13 @@ static int f17_addr_mask_to_cs_size(struct amd64_pvt *pvt, u8 umc, * There is one mask per DIMM, and two Chip Selects per DIMM. * CS0 and CS1 -> DIMM0 * CS2 and CS3 -> DIMM1 + * + * Systems with DDR5 support have one mask per Chip Select. */ - dimm = csrow_nr >> 1; + if (has_ddr5()) + dimm = csrow_nr; + else + dimm = csrow_nr >> 1; /* Asymmetric dual-rank DIMM support. */ if ((csrow_nr & 1) && (cs_mode & CS_ODD_SECONDARY)) @@ -2937,6 +2985,7 @@ static struct amd64_family_type family_types[] = { .f0_id = PCI_DEVICE_ID_AMD_19H_M10H_DF_F0, .f6_id = PCI_DEVICE_ID_AMD_19H_M10H_DF_F6, .max_mcs = 12, + .flags.has_ddr5 = 1, .ops = { .early_channel_count = f17_early_channel_count, .dbam_to_cs = f17_addr_mask_to_cs_size, @@ -3365,7 +3414,7 @@ static void __read_mc_regs_df(struct amd64_pvt *pvt) umc_base = get_umc_base(i); umc = &pvt->umc[i]; - amd_smn_read(nid, umc_base + UMCCH_DIMM_CFG, &umc->dimm_cfg); + amd_smn_read(nid, umc_base + get_dimm_cfg(), &umc->dimm_cfg); amd_smn_read(nid, umc_base + UMCCH_UMC_CFG, &umc->umc_cfg); amd_smn_read(nid, umc_base + UMCCH_SDP_CTRL, &umc->sdp_ctrl); amd_smn_read(nid, umc_base + UMCCH_ECC_CTRL, &umc->ecc_ctrl); diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h index 650cab401e21..48cba95451cb 100644 --- a/drivers/edac/amd64_edac.h +++ b/drivers/edac/amd64_edac.h @@ -271,8 +271,11 @@ #define UMCCH_BASE_ADDR_SEC 0x10 #define UMCCH_ADDR_MASK 0x20 #define UMCCH_ADDR_MASK_SEC 0x28 +#define UMCCH_ADDR_MASK_SEC_DDR5 0x30 #define UMCCH_ADDR_CFG 0x30 +#define UMCCH_ADDR_CFG_DDR5 0x40 #define UMCCH_DIMM_CFG 0x80 +#define UMCCH_DIMM_CFG_DDR5 0x90 #define UMCCH_UMC_CFG 0x100 #define UMCCH_SDP_CTRL 0x104 #define UMCCH_ECC_CTRL 0x14C @@ -477,11 +480,19 @@ struct low_ops { unsigned cs_mode, int cs_mask_nr); }; +struct amd64_family_flags { + /* Indicates that the family supports DDR5 and associated register changes. */ + __u64 has_ddr5 : 1, + + __reserved : 63; +}; + struct amd64_family_type { const char *ctl_name; u16 f0_id, f1_id, f2_id, f6_id; /* Maximum number of memory controllers per die/node. */ u8 max_mcs; + struct amd64_family_flags flags; struct low_ops ops; };