From patchwork Wed Dec 8 22:50:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 12665459 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6897C433FE for ; Wed, 8 Dec 2021 22:50:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240729AbhLHWyO (ORCPT ); Wed, 8 Dec 2021 17:54:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45146 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240704AbhLHWyN (ORCPT ); Wed, 8 Dec 2021 17:54:13 -0500 Received: from mail-il1-x130.google.com (mail-il1-x130.google.com [IPv6:2607:f8b0:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 38587C061746; Wed, 8 Dec 2021 14:50:41 -0800 (PST) Received: by mail-il1-x130.google.com with SMTP id 15so3664324ilq.2; Wed, 08 Dec 2021 14:50:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=25U6Yhax0BXTLLFHy75HSeiByRDthooJoTH4u1dV5LA=; b=IoYpEX/ULICdxAUXcRO4zYu+4e6lAYdr09BYwsVnPD4m2n62fAvPHlC4El3MNgAy+e nWfBtwYKW/o6D0eclIrJECJ1nRUmoPWCYs+eESR/s4gbZ29GlWbHuxnFKSQuE7+w0IAr R753ClJyqt9hIi214ogONAWVz/TinGE1Auusbyr5W95IVRH/H7TqcSWV93CRrTb2Z4gp C5xHNWuGFIn9bcOWnqI4EjqYNzoOa0SeLYkprDPT9h4E82qjdq5taOtVcc8VNw9F8BYE Pc0LJ8+UpagLLPFXr9G43kxBjwYPigf7va8nNaulIJz2UkcwdHSTUAlVxOE736k8qW3w FVKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=25U6Yhax0BXTLLFHy75HSeiByRDthooJoTH4u1dV5LA=; b=ETOK1roNtQboMT/NuAVr/BOvh5KJgRWr7XBfCtZWvko1JVYY+th9WS8YUuro9qUbOm TtZwZWLJgOxXpq9xfGzKaRAufC9Xk8pE98buWQgeiXvaNUJ9lf6ioKqJ+WIXqYcxKO+B MkzDe2x+uuPmPhLavrT416gTAKxUiQ6xdtk4250IjJxLOYE7tBXEx3VotFeht99GiXo9 kTW6Ay3PPPkTSQnPPCpK+dqjc0s1Snk1cok5UDQFLNN+/TahmLRdjmhggiJsvLUVIpCh 7D/ufKAR7B3zMvTJwea+m0ZjLJ2MbAUoerk5EyyncSFrlgQ53OrF/THy5P6dpp2rnlUh vddw== X-Gm-Message-State: AOAM531mU98Bt4Tbwtlw01jgxgRWQX8qG2Xb2OdMTJ/tEE31N3uTuWVw Px5j5rct3R5RuB+DuDl8OVLNndhhQQIG7Q== X-Google-Smtp-Source: ABdhPJzYh5UPP8BPYPny3NBqelVcmvIDzON4ttwf3iKAX0NCfy6JGIDBcalxJHp5I8V2AFvLNA8f/A== X-Received: by 2002:a05:6e02:10ce:: with SMTP id s14mr9697999ilj.320.1639003840061; Wed, 08 Dec 2021 14:50:40 -0800 (PST) Received: from aford-IdeaCentre-A730.lan ([2601:448:8400:9e8:269a:1aa2:f1d9:8dbb]) by smtp.gmail.com with ESMTPSA id t6sm2378751ioi.51.2021.12.08.14.50.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Dec 2021 14:50:39 -0800 (PST) From: Adam Ford To: linux-media@vger.kernel.org Cc: benjamin.gaignard@collabora.com, cphealy@gmail.com, aford@beaconembedded.com, nicolas@ndufresne.ca, Lucas Stach , Ezequiel Garcia , Philipp Zabel , Mauro Carvalho Chehab , Rob Herring , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Greg Kroah-Hartman , linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev Subject: [PATCH 01/10] dt-bindings: power: imx8mq: add defines for VPU blk-ctrl domains Date: Wed, 8 Dec 2021 16:50:20 -0600 Message-Id: <20211208225030.2018923-2-aford173@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211208225030.2018923-1-aford173@gmail.com> References: <20211208225030.2018923-1-aford173@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Lucas Stach This adds the defines for the power domains provided by the VPU blk-ctrl on the i.MX8MQ. Signed-off-by: Lucas Stach --- include/dt-bindings/power/imx8mq-power.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/dt-bindings/power/imx8mq-power.h b/include/dt-bindings/power/imx8mq-power.h index 8a513bd9166e..9f7d0f1e7c32 100644 --- a/include/dt-bindings/power/imx8mq-power.h +++ b/include/dt-bindings/power/imx8mq-power.h @@ -18,4 +18,7 @@ #define IMX8M_POWER_DOMAIN_MIPI_CSI2 9 #define IMX8M_POWER_DOMAIN_PCIE2 10 +#define IMX8MQ_VPUBLK_PD_G1 0 +#define IMX8MQ_VPUBLK_PD_G2 1 + #endif From patchwork Wed Dec 8 22:50:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 12665461 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 280C0C433EF for ; Wed, 8 Dec 2021 22:50:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240736AbhLHWyR (ORCPT ); Wed, 8 Dec 2021 17:54:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45160 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240746AbhLHWyP (ORCPT ); Wed, 8 Dec 2021 17:54:15 -0500 Received: from mail-io1-xd2f.google.com (mail-io1-xd2f.google.com [IPv6:2607:f8b0:4864:20::d2f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8CEFFC0617A1; Wed, 8 Dec 2021 14:50:43 -0800 (PST) Received: by mail-io1-xd2f.google.com with SMTP id y16so4573278ioc.8; Wed, 08 Dec 2021 14:50:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KH5Jne9WcYen8VLv63slDNPB/A+EenVaY1NFcEd7AL0=; b=L/0F/biiGi3tDtP9CI9j6864dUmuoHZqb5Q/X+GvYmx3Mm4HEg/p+c1Czc7Da9LgCJ UdWNefGwzk2WM3YfKmKSx6UqxjG7dDFvD9B9OTTcsRJZhQOnncisacdL8YqrNSg47xgD rQu2I+AaqWvqmWpKxrnpSn19UHABu0IYr4OEyxgaqWZEfbmhsu8TTIGd6UavLZfh6gmd +Xy69KNHKLECsBts3AJOTyR6p1u4SZEFJtKw13Nzcd2BVcUJU8mTMHx7t9KLoKT5E0KX +a5UArm9mpUYNwbK8NUrrre05LuU9GHXmYgFgcND4O9A9/pKvuYXyppMP0TLqs6d2IwD xncA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KH5Jne9WcYen8VLv63slDNPB/A+EenVaY1NFcEd7AL0=; b=E1flWGuxiBSi1Cmf10RIeqCHbNhd5Y6qE38f0incPFvv15Df9XDsllKYx87RL8aFnu G6WrFtD+tJ5j0NDVH+CJjb76jfkShweCrO+gpafjfTYmo3q/ZVzutV+VrnOLoYTR1A8T rsqnxxLCG9CZqfRKqBH2vZrNZ4k0nvPKbBLtfp6XQOtx4suQ8XnFZHE+9kiv6yduLh3k K36HzG6ZgIbB4A5HChcT7Pkx8NvsIfmRogd6dmBxYZ+K0mmYRGno0s2uRq1OKo+/qZrl BsPrVGtUGRdyk6/aQbt+iC6y56IGK4C1matvv4Ks28Wr0hye9qHx+OEbgpRL4XEvx2uK LscA== X-Gm-Message-State: AOAM531nE/8W6uV8QVXpL2NDlQ9+omyg9maUlFdikAdL7fpbzAlLFtiI 7Qz8EmHXu7Rwz5skv9PZw/WhlnMxu9ujRA== X-Google-Smtp-Source: ABdhPJycuHd5Hezj4qLt3M/C9skFUUVnANcKtzFop7/ugQMyK2ceqeFxYBtgBpPkudeWLp6OnqmLcg== X-Received: by 2002:a05:6638:140c:: with SMTP id k12mr3463194jad.89.1639003842466; Wed, 08 Dec 2021 14:50:42 -0800 (PST) Received: from aford-IdeaCentre-A730.lan ([2601:448:8400:9e8:269a:1aa2:f1d9:8dbb]) by smtp.gmail.com with ESMTPSA id t6sm2378751ioi.51.2021.12.08.14.50.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Dec 2021 14:50:42 -0800 (PST) From: Adam Ford To: linux-media@vger.kernel.org Cc: benjamin.gaignard@collabora.com, cphealy@gmail.com, aford@beaconembedded.com, nicolas@ndufresne.ca, Lucas Stach , Adam Ford , Ezequiel Garcia , Philipp Zabel , Mauro Carvalho Chehab , Rob Herring , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Greg Kroah-Hartman , linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev Subject: [PATCH 02/10] dt-bindings: soc: add binding for i.MX8MQ VPU blk-ctrl Date: Wed, 8 Dec 2021 16:50:21 -0600 Message-Id: <20211208225030.2018923-3-aford173@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211208225030.2018923-1-aford173@gmail.com> References: <20211208225030.2018923-1-aford173@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Lucas Stach This adds the DT binding for the i.MX8MQ VPU blk-ctrl. Signed-off-by: Lucas Stach Signed-off-by: Adam Ford --- .../soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml | 71 +++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml new file mode 100644 index 000000000000..7263ebedf09f --- /dev/null +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8MQ VPU blk-ctrl + +maintainers: + - Lucas Stach + +description: + The i.MX8MQ VPU blk-ctrl is a top-level peripheral providing access to + the NoC and ensuring proper power sequencing of the VPU peripherals + located in the VPU domain of the SoC. + +properties: + compatible: + items: + - const: fsl,imx8mq-vpu-blk-ctrl + + reg: + maxItems: 1 + + '#power-domain-cells': + const: 1 + + power-domains: + minItems: 3 + maxItems: 3 + + power-domain-names: + items: + - const: bus + - const: g1 + - const: g2 + + clocks: + minItems: 2 + maxItems: 2 + + clock-names: + items: + - const: g1 + - const: g2 + +required: + - compatible + - reg + - power-domains + - power-domain-names + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + + vpu_blk_ctrl: blk-ctrl@38320000 { + compatible = "fsl,imx8mq-vpu-blk-ctrl"; + reg = <0x38320000 0x100>; + power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>; + power-domain-names = "bus", "g1", "g2"; + clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, + <&clk IMX8MQ_CLK_VPU_G2_ROOT>; + clock-names = "g1", "g2"; + #power-domain-cells = <1>; + }; From patchwork Wed Dec 8 22:50:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 12665471 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 46E79C433FE for ; Wed, 8 Dec 2021 22:51:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240822AbhLHWyV (ORCPT ); Wed, 8 Dec 2021 17:54:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45176 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240776AbhLHWyS (ORCPT ); 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Wed, 08 Dec 2021 14:50:44 -0800 (PST) From: Adam Ford To: linux-media@vger.kernel.org Cc: benjamin.gaignard@collabora.com, cphealy@gmail.com, aford@beaconembedded.com, nicolas@ndufresne.ca, Lucas Stach , Adam Ford , Ezequiel Garcia , Philipp Zabel , Mauro Carvalho Chehab , Rob Herring , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Greg Kroah-Hartman , linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev Subject: [PATCH 03/10] soc: imx: imx8m-blk-ctrl: add i.MX8MQ VPU blk-ctrl Date: Wed, 8 Dec 2021 16:50:22 -0600 Message-Id: <20211208225030.2018923-4-aford173@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211208225030.2018923-1-aford173@gmail.com> References: <20211208225030.2018923-1-aford173@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Lucas Stach This adds the necessary bits to drive the VPU blk-ctrl on the i.MX8MQ, to avoid putting more of this functionality into the decoder driver. Signed-off-by: Lucas Stach Signed-off-by: Adam Ford --- drivers/soc/imx/imx8m-blk-ctrl.c | 68 +++++++++++++++++++++++++++++++- 1 file changed, 67 insertions(+), 1 deletion(-) diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c index 519b3651d1d9..a7c12e8fa89b 100644 --- a/drivers/soc/imx/imx8m-blk-ctrl.c +++ b/drivers/soc/imx/imx8m-blk-ctrl.c @@ -14,6 +14,7 @@ #include #include +#include #define BLK_SFT_RSTN 0x0 #define BLK_CLK_EN 0x4 @@ -498,6 +499,68 @@ static const struct imx8m_blk_ctrl_data imx8mm_disp_blk_ctl_dev_data = { .num_domains = ARRAY_SIZE(imx8mm_disp_blk_ctl_domain_data), }; +static int imx8mq_vpu_power_notifier(struct notifier_block *nb, + unsigned long action, void *data) +{ + struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl, + power_nb); + + if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF) + return NOTIFY_OK; + + /* + * The ADB in the VPUMIX domain has no separate reset and clock + * enable bits, but is ungated and reset together with the VPUs. The + * reset and clock enable inputs to the ADB is a logical OR of the + * VPU bits. In order to set the G2 fuse bits, the G2 clock must + * also be enabled. + */ + regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(0) | BIT(1)); + regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(0) | BIT(1)); + + if (action == GENPD_NOTIFY_ON) { + /* + * On power up we have no software backchannel to the GPC to + * wait for the ADB handshake to happen, so we just delay for a + * bit. On power down the GPC driver waits for the handshake. + */ + udelay(5); + + /* set "fuse" bits to enable the VPUs */ + regmap_set_bits(bc->regmap, 0x8, 0xffffffff); + regmap_set_bits(bc->regmap, 0xc, 0xffffffff); + regmap_set_bits(bc->regmap, 0x10, 0xffffffff); + } + + return NOTIFY_OK; +} + +static const struct imx8m_blk_ctrl_domain_data imx8mq_vpu_blk_ctl_domain_data[] = { + [IMX8MQ_VPUBLK_PD_G1] = { + .name = "vpublk-g1", + .clk_names = (const char *[]){ "g1", }, + .num_clks = 1, + .gpc_name = "g1", + .rst_mask = BIT(1), + .clk_mask = BIT(1), + }, + [IMX8MQ_VPUBLK_PD_G2] = { + .name = "vpublk-g2", + .clk_names = (const char *[]){ "g2", }, + .num_clks = 1, + .gpc_name = "g2", + .rst_mask = BIT(0), + .clk_mask = BIT(0), + }, +}; + +static const struct imx8m_blk_ctrl_data imx8mq_vpu_blk_ctl_dev_data = { + .max_reg = 0x14, + .power_notifier_fn = imx8mq_vpu_power_notifier, + .domains = imx8mq_vpu_blk_ctl_domain_data, + .num_domains = ARRAY_SIZE(imx8mq_vpu_blk_ctl_domain_data), +}; + static const struct of_device_id imx8m_blk_ctrl_of_match[] = { { .compatible = "fsl,imx8mm-vpu-blk-ctrl", @@ -505,7 +568,10 @@ static const struct of_device_id imx8m_blk_ctrl_of_match[] = { }, { .compatible = "fsl,imx8mm-disp-blk-ctrl", .data = &imx8mm_disp_blk_ctl_dev_data - } ,{ + }, { + .compatible = "fsl,imx8mq-vpu-blk-ctrl", + .data = &imx8mq_vpu_blk_ctl_dev_data + }, { /* Sentinel */ } }; From patchwork Wed Dec 8 22:50:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 12665463 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A29A4C433FE for ; Wed, 8 Dec 2021 22:50:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240876AbhLHWyX (ORCPT ); Wed, 8 Dec 2021 17:54:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45190 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240803AbhLHWyU (ORCPT ); Wed, 8 Dec 2021 17:54:20 -0500 Received: from mail-il1-x12b.google.com (mail-il1-x12b.google.com [IPv6:2607:f8b0:4864:20::12b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 55E8EC061746; Wed, 8 Dec 2021 14:50:48 -0800 (PST) Received: by mail-il1-x12b.google.com with SMTP id h16so3668469ila.4; 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Wed, 08 Dec 2021 14:50:47 -0800 (PST) Received: from aford-IdeaCentre-A730.lan ([2601:448:8400:9e8:269a:1aa2:f1d9:8dbb]) by smtp.gmail.com with ESMTPSA id t6sm2378751ioi.51.2021.12.08.14.50.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Dec 2021 14:50:46 -0800 (PST) From: Adam Ford To: linux-media@vger.kernel.org Cc: benjamin.gaignard@collabora.com, cphealy@gmail.com, aford@beaconembedded.com, nicolas@ndufresne.ca, Adam Ford , Ezequiel Garcia , Philipp Zabel , Mauro Carvalho Chehab , Rob Herring , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Greg Kroah-Hartman , Lucas Stach , linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev Subject: [PATCH 04/10] dt-bindings: media: nxp,imx8mq-vpu: Support split G1 and G2 nodes with vpu-blk-ctrl Date: Wed, 8 Dec 2021 16:50:23 -0600 Message-Id: <20211208225030.2018923-5-aford173@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211208225030.2018923-1-aford173@gmail.com> References: <20211208225030.2018923-1-aford173@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The G1 and G2 are separate decoder blocks that are enabled by the vpu-blk-ctrl power-domain controller, which now has a proper driver. Update the bindings to support separate nodes for the G1 and G2 decoders using the proper driver or the older unified node with the legacy controls. To be compatible with older DT the driver, mark certain items as deprecated and retain the backwards compatible example. Signed-off-by: Adam Ford --- .../bindings/media/nxp,imx8mq-vpu.yaml | 83 ++++++++++++++----- 1 file changed, 64 insertions(+), 19 deletions(-) diff --git a/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml b/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml index 762be3f96ce9..eeb7bd6281f9 100644 --- a/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml +++ b/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml @@ -15,29 +15,39 @@ description: properties: compatible: - const: nxp,imx8mq-vpu + oneOf: + - const: nxp,imx8mq-vpu + deprecated: true + - const: nxp,imx8mq-vpu-g1 + - const: nxp,imx8mq-vpu-g2 reg: + minItems: 1 maxItems: 3 reg-names: + minItems: 1 items: - const: g1 - const: g2 - const: ctrl interrupts: + minItems: 1 maxItems: 2 interrupt-names: + minItems: 1 items: - const: g1 - const: g2 clocks: + minItems: 1 maxItems: 3 clock-names: + minItems: 1 items: - const: g1 - const: g2 @@ -58,22 +68,57 @@ required: additionalProperties: false examples: + # Device node example backwards compatibility - | - #include - #include - - vpu: video-codec@38300000 { - compatible = "nxp,imx8mq-vpu"; - reg = <0x38300000 0x10000>, - <0x38310000 0x10000>, - <0x38320000 0x10000>; - reg-names = "g1", "g2", "ctrl"; - interrupts = , - ; - interrupt-names = "g1", "g2"; - clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, - <&clk IMX8MQ_CLK_VPU_G2_ROOT>, - <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; - clock-names = "g1", "g2", "bus"; - power-domains = <&pgc_vpu>; - }; + #include + #include + + vpu: video-codec@38300000 { + compatible = "nxp,imx8mq-vpu"; + reg = <0x38300000 0x10000>, + <0x38310000 0x10000>, + <0x38320000 0x10000>; + reg-names = "g1", "g2", "ctrl"; + interrupts = , + ; + interrupt-names = "g1", "g2"; + clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, + <&clk IMX8MQ_CLK_VPU_G2_ROOT>, + <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; + clock-names = "g1", "g2", "bus"; + power-domains = <&pgc_vpu>; + }; + + # VPU G1 with vpu-blk-ctrl + - | + #include + #include + #include + + vpu_g1: video-codec@38300000 { + compatible = "nxp,imx8mq-vpu-g1"; + reg = <0x38300000 0x10000>; + reg-names "g1"; + interrupts = ; + interrupt-names = "g1"; + clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>; + clock-names = "g1"; + power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>; + }; + + # VPU G2 with vpu-blk-ctrl + - | + #include + #include + #include + + vpu_g2: video-codec@38310000 { + compatible = "nxp,imx8mq-vpu-g2"; + reg = <0x38310000 0x10000>; + reg-names "g2"; + interrupts = ; + interrupt-names = "g2"; + clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>; + clock-names = "g2"; + power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>; + }; From patchwork Wed Dec 8 22:50:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 12665467 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1FF9C433FE for ; Wed, 8 Dec 2021 22:51:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240853AbhLHWya (ORCPT ); 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Wed, 08 Dec 2021 14:50:49 -0800 (PST) From: Adam Ford To: linux-media@vger.kernel.org Cc: benjamin.gaignard@collabora.com, cphealy@gmail.com, aford@beaconembedded.com, nicolas@ndufresne.ca, Adam Ford , Ezequiel Garcia , Philipp Zabel , Mauro Carvalho Chehab , Rob Herring , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Greg Kroah-Hartman , Lucas Stach , linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev Subject: [PATCH 05/10] media: hantro: Allow i.MX8MQ G1 and G2 to run independently Date: Wed, 8 Dec 2021 16:50:24 -0600 Message-Id: <20211208225030.2018923-6-aford173@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211208225030.2018923-1-aford173@gmail.com> References: <20211208225030.2018923-1-aford173@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The VPU in the i.MX8MQ is really the combination of Hantro G1 and Hantro G2. With the updated vpu-blk-ctrl, the power domains system can enable and disable them separately as well as pull them out of reset. This simplifies the code and lets them run independently while still retaining backwards compatibility with older device trees for those using G1. Signed-off-by: Adam Ford --- drivers/staging/media/hantro/hantro_drv.c | 1 + drivers/staging/media/hantro/hantro_hw.h | 1 + drivers/staging/media/hantro/imx8m_vpu_hw.c | 56 ++++++++++++++++----- 3 files changed, 45 insertions(+), 13 deletions(-) diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c index ab2467998d29..e7afda388ee5 100644 --- a/drivers/staging/media/hantro/hantro_drv.c +++ b/drivers/staging/media/hantro/hantro_drv.c @@ -609,6 +609,7 @@ static const struct of_device_id of_hantro_match[] = { #endif #ifdef CONFIG_VIDEO_HANTRO_IMX8M { .compatible = "nxp,imx8mq-vpu", .data = &imx8mq_vpu_variant, }, + { .compatible = "nxp,imx8mq-vpu-g1", .data = &imx8mq_vpu_g1_variant }, { .compatible = "nxp,imx8mq-vpu-g2", .data = &imx8mq_vpu_g2_variant }, #endif #ifdef CONFIG_VIDEO_HANTRO_SAMA5D4 diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h index cff817ca8d22..96b14b43a4af 100644 --- a/drivers/staging/media/hantro/hantro_hw.h +++ b/drivers/staging/media/hantro/hantro_hw.h @@ -299,6 +299,7 @@ enum hantro_enc_fmt { ROCKCHIP_VPU_ENC_FMT_UYVY422 = 3, }; +extern const struct hantro_variant imx8mq_vpu_g1_variant; extern const struct hantro_variant imx8mq_vpu_g2_variant; extern const struct hantro_variant imx8mq_vpu_variant; extern const struct hantro_variant px30_vpu_variant; diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c index 1a43f6fceef9..e0af4b93d3c6 100644 --- a/drivers/staging/media/hantro/imx8m_vpu_hw.c +++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c @@ -223,13 +223,6 @@ static void imx8m_vpu_g1_reset(struct hantro_ctx *ctx) imx8m_soft_reset(vpu, RESET_G1); } -static void imx8m_vpu_g2_reset(struct hantro_ctx *ctx) -{ - struct hantro_dev *vpu = ctx->dev; - - imx8m_soft_reset(vpu, RESET_G2); -} - /* * Supported codec ops. */ @@ -255,17 +248,33 @@ static const struct hantro_codec_ops imx8mq_vpu_codec_ops[] = { }, }; +static const struct hantro_codec_ops imx8mq_vpu_g1_codec_ops[] = { + [HANTRO_MODE_MPEG2_DEC] = { + .run = hantro_g1_mpeg2_dec_run, + .init = hantro_mpeg2_dec_init, + .exit = hantro_mpeg2_dec_exit, + }, + [HANTRO_MODE_VP8_DEC] = { + .run = hantro_g1_vp8_dec_run, + .init = hantro_vp8_dec_init, + .exit = hantro_vp8_dec_exit, + }, + [HANTRO_MODE_H264_DEC] = { + .run = hantro_g1_h264_dec_run, + .init = hantro_h264_dec_init, + .exit = hantro_h264_dec_exit, + }, +}; + static const struct hantro_codec_ops imx8mq_vpu_g2_codec_ops[] = { [HANTRO_MODE_HEVC_DEC] = { .run = hantro_g2_hevc_dec_run, - .reset = imx8m_vpu_g2_reset, .init = hantro_hevc_dec_init, .exit = hantro_hevc_dec_exit, }, [HANTRO_MODE_VP9_DEC] = { .run = hantro_g2_vp9_dec_run, .done = hantro_g2_vp9_dec_done, - .reset = imx8m_vpu_g2_reset, .init = hantro_vp9_dec_init, .exit = hantro_vp9_dec_exit, }, @@ -285,6 +294,10 @@ static const struct hantro_irq imx8mq_g2_irqs[] = { static const char * const imx8mq_clk_names[] = { "g1", "g2", "bus" }; static const char * const imx8mq_reg_names[] = { "g1", "g2", "ctrl" }; +static const char * const imx8mq_g1_clk_names[] = { "g1" }; +static const char * const imx8mq_g1_reg_names[] = { "g1" }; +static const char * const imx8mq_g2_clk_names[] = { "g2" }; +static const char * const imx8mq_g2_reg_names[] = { "g2" }; const struct hantro_variant imx8mq_vpu_variant = { .dec_fmts = imx8m_vpu_dec_fmts, @@ -305,6 +318,23 @@ const struct hantro_variant imx8mq_vpu_variant = { .num_regs = ARRAY_SIZE(imx8mq_reg_names) }; +const struct hantro_variant imx8mq_vpu_g1_variant = { + .dec_fmts = imx8m_vpu_dec_fmts, + .num_dec_fmts = ARRAY_SIZE(imx8m_vpu_dec_fmts), + .postproc_fmts = imx8m_vpu_postproc_fmts, + .num_postproc_fmts = ARRAY_SIZE(imx8m_vpu_postproc_fmts), + .postproc_ops = &hantro_g1_postproc_ops, + .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER | + HANTRO_H264_DECODER, + .codec_ops = imx8mq_vpu_g1_codec_ops, + .irqs = imx8mq_irqs, + .num_irqs = ARRAY_SIZE(imx8mq_irqs), + .clk_names = imx8mq_g1_clk_names, + .num_clocks = ARRAY_SIZE(imx8mq_g1_clk_names), + .reg_names = imx8mq_g1_reg_names, + .num_regs = ARRAY_SIZE(imx8mq_g1_reg_names), +}; + const struct hantro_variant imx8mq_vpu_g2_variant = { .dec_offset = 0x0, .dec_fmts = imx8m_vpu_g2_dec_fmts, @@ -314,10 +344,10 @@ const struct hantro_variant imx8mq_vpu_g2_variant = { .postproc_ops = &hantro_g2_postproc_ops, .codec = HANTRO_HEVC_DECODER | HANTRO_VP9_DECODER, .codec_ops = imx8mq_vpu_g2_codec_ops, - .init = imx8mq_vpu_hw_init, - .runtime_resume = imx8mq_runtime_resume, .irqs = imx8mq_g2_irqs, .num_irqs = ARRAY_SIZE(imx8mq_g2_irqs), - .clk_names = imx8mq_clk_names, - .num_clocks = ARRAY_SIZE(imx8mq_clk_names), + .clk_names = imx8mq_g2_clk_names, + .num_clocks = ARRAY_SIZE(imx8mq_g2_clk_names), + .reg_names = imx8mq_g2_reg_names, + .num_regs = ARRAY_SIZE(imx8mq_g2_reg_names), }; From patchwork Wed Dec 8 22:50:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 12665465 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3DE40C433F5 for ; Wed, 8 Dec 2021 22:50:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240929AbhLHWy2 (ORCPT ); Wed, 8 Dec 2021 17:54:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45234 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240863AbhLHWyZ (ORCPT ); Wed, 8 Dec 2021 17:54:25 -0500 Received: from mail-io1-xd32.google.com (mail-io1-xd32.google.com [IPv6:2607:f8b0:4864:20::d32]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 00B9AC0617A1; Wed, 8 Dec 2021 14:50:52 -0800 (PST) Received: by mail-io1-xd32.google.com with SMTP id m9so4670428iop.0; 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Wed, 08 Dec 2021 14:50:51 -0800 (PST) Received: from aford-IdeaCentre-A730.lan ([2601:448:8400:9e8:269a:1aa2:f1d9:8dbb]) by smtp.gmail.com with ESMTPSA id t6sm2378751ioi.51.2021.12.08.14.50.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Dec 2021 14:50:51 -0800 (PST) From: Adam Ford To: linux-media@vger.kernel.org Cc: benjamin.gaignard@collabora.com, cphealy@gmail.com, aford@beaconembedded.com, nicolas@ndufresne.ca, Adam Ford , Ezequiel Garcia , Philipp Zabel , Mauro Carvalho Chehab , Rob Herring , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Greg Kroah-Hartman , Lucas Stach , linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev Subject: [PATCH 06/10] arm64: dts: imx8mq: Enable both G1 and G2 VPU's with vpu-blk-ctrl Date: Wed, 8 Dec 2021 16:50:25 -0600 Message-Id: <20211208225030.2018923-7-aford173@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211208225030.2018923-1-aford173@gmail.com> References: <20211208225030.2018923-1-aford173@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org With the Hantro G1 and G2 now setup to run independently, update the device tree to allow both to operate. This requires the vpu-blk-ctrl node to be configured. Since vpu-blk-ctrl needs certain clock enabled to handle the gating of the G1 and G2 fuses, the clock-parents and clock-rates for the various VPU's to be moved into the pgc_vpu because they cannot get re-parented once enabled, and the pgc_vpu is the highest in the chain. Signed-off-by: Adam Ford --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 69 +++++++++++++++-------- 1 file changed, 45 insertions(+), 24 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 972766b67a15..3ed2644bd500 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -711,7 +711,21 @@ pgc_gpu: power-domain@5 { pgc_vpu: power-domain@6 { #power-domain-cells = <0>; reg = ; - clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; + clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>, + <&clk IMX8MQ_CLK_VPU_G1_ROOT>, + <&clk IMX8MQ_CLK_VPU_G2_ROOT>; + assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, + <&clk IMX8MQ_CLK_VPU_G2>, + <&clk IMX8MQ_CLK_VPU_BUS>, + <&clk IMX8MQ_VPU_PLL_BYPASS>; + assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, + <&clk IMX8MQ_VPU_PLL_OUT>, + <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_VPU_PLL>; + assigned-clock-rates = <600000000>, + <600000000>, + <800000000>, + <0>; }; pgc_disp: power-domain@7 { @@ -1432,30 +1446,37 @@ usb3_phy1: usb-phy@382f0040 { status = "disabled"; }; - vpu: video-codec@38300000 { - compatible = "nxp,imx8mq-vpu"; - reg = <0x38300000 0x10000>, - <0x38310000 0x10000>, - <0x38320000 0x10000>; - reg-names = "g1", "g2", "ctrl"; - interrupts = , - ; - interrupt-names = "g1", "g2"; + vpu_g1: video-codec@38300000 { + compatible = "nxp,imx8mq-vpu-g1"; + reg = <0x38300000 0x10000>; + reg-names = "g1"; + interrupts = ; + interrupt-names = "g1"; + clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>; + clock-names = "g1"; + power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>; + }; + + vpu_g2: video-codec@38310000 { + compatible = "nxp,imx8mq-vpu-g2"; + reg = <0x38310000 0x10000>; + reg-names = "g2"; + interrupts = ; + interrupt-names = "g2"; + clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>; + clock-names = "g2"; + power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>; + }; + + vpu_blk_ctrl: blk-ctrl@38320000 { + compatible = "fsl,imx8mq-vpu-blk-ctrl"; + reg = <0x38320000 0x100>; + power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>; + power-domain-names = "bus", "g1", "g2"; clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, - <&clk IMX8MQ_CLK_VPU_G2_ROOT>, - <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; - clock-names = "g1", "g2", "bus"; - assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, - <&clk IMX8MQ_CLK_VPU_G2>, - <&clk IMX8MQ_CLK_VPU_BUS>, - <&clk IMX8MQ_VPU_PLL_BYPASS>; - assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, - <&clk IMX8MQ_VPU_PLL_OUT>, - <&clk IMX8MQ_SYS1_PLL_800M>, - <&clk IMX8MQ_VPU_PLL>; - assigned-clock-rates = <600000000>, <600000000>, - <800000000>, <0>; - power-domains = <&pgc_vpu>; + <&clk IMX8MQ_CLK_VPU_G2_ROOT>; + clock-names = "g1", "g2"; + #power-domain-cells = <1>; }; pcie0: pcie@33800000 { From patchwork Wed Dec 8 22:50:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 12665473 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D296DC433EF for ; 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Wed, 08 Dec 2021 14:50:53 -0800 (PST) From: Adam Ford To: linux-media@vger.kernel.org Cc: benjamin.gaignard@collabora.com, cphealy@gmail.com, aford@beaconembedded.com, nicolas@ndufresne.ca, Adam Ford , Ezequiel Garcia , Philipp Zabel , Mauro Carvalho Chehab , Rob Herring , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Greg Kroah-Hartman , Lucas Stach , linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev Subject: [PATCH 07/10] arm64: dts: imx8mm: Fix VPU Hanging Date: Wed, 8 Dec 2021 16:50:26 -0600 Message-Id: <20211208225030.2018923-8-aford173@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211208225030.2018923-1-aford173@gmail.com> References: <20211208225030.2018923-1-aford173@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The vpumix power domain has a reset assigned to it, however when used, it causes a system hang. Testing has shown that it does not appear to be needed anywhere. Fixes: d39d4bb15310 ("arm64: dts: imx8mm: add GPC node") Signed-off-by: Adam Ford --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index c2f3f118f82e..f13d31ebfcbd 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -681,7 +681,6 @@ pgc_vpumix: power-domain@6 { clocks = <&clk IMX8MM_CLK_VPU_DEC_ROOT>; assigned-clocks = <&clk IMX8MM_CLK_VPU_BUS>; assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>; - resets = <&src IMX8MQ_RESET_VPU_RESET>; }; pgc_vpu_g1: power-domain@7 { From patchwork Wed Dec 8 22:50:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 12665469 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2E1CCC433EF for ; Wed, 8 Dec 2021 22:51:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240872AbhLHWye (ORCPT ); Wed, 8 Dec 2021 17:54:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45282 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240945AbhLHWyb (ORCPT ); Wed, 8 Dec 2021 17:54:31 -0500 Received: from mail-io1-xd2c.google.com (mail-io1-xd2c.google.com [IPv6:2607:f8b0:4864:20::d2c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2394FC061D5F; Wed, 8 Dec 2021 14:50:58 -0800 (PST) Received: by mail-io1-xd2c.google.com with SMTP id c3so4600411iob.6; Wed, 08 Dec 2021 14:50:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5uDGT+bQdOGd9jInpMhbePhooiUuliLL4k3ARcsSlNE=; b=SMrAIUyTmmwqq2KE5GitKXfURAPHk0xEp2DVv8M6//mv/uHw1hSIFsZ95PEHPiUUFr KpIizsH+p/xMLD8jfZiYd9/1Kqc0Glt26WUGdmpb1qnAB+gAjxwklaY4KS1yKOhY/7Tt 9/b2Ctl7g9uhk6aCy2qxaH1JX1xbvvy7b/gXAF3SjLJqmuruA14QH/zL25f/rL9dbdPB gAB94PIy3CnlEB9M4HXQt/BiSyBfOQt3ssknZkE/fhXXfB6jt4TVgd2R/XppIocMvUWT tnIJ1BM6sybxx2Go9kNp7yu8VmuTlh19RBGTTLNAvz8GhZCYwd/AF6cDn0WIadvqji9O 581g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5uDGT+bQdOGd9jInpMhbePhooiUuliLL4k3ARcsSlNE=; b=CtFis6Gma1vMVNXLx4XT5dO6pNEyJxiR+V9mG9tm0o0NpHb//0BUkRV/Fy5zeSJOoQ uIK0e1e7irnyp3tFdB/PrcSbNyTBX2/vaO75IpzKttbut7VZ8C8dBA2xEsq0v7AJI3Oe oQS3+IuxfRRYuYtrIiIC2mJ9tq/tI/6ikJdWUIET/GoKJM4S+xYXYj7wxJdD5gDfP/Ff tm/aTSyyCVPcZBDugdM+cLP7DCwyBh5EK/1oLka8BDy/2VSQZsDjrczY3KuqE7OknkdO 6VbhJDYUnRws8EoHDq19VywRDqYGqE60MeVhz9K1ZZS73HBcu613SYz1w9mbOpFlLrtA IqkQ== X-Gm-Message-State: AOAM531A1AbcvA+tSL4GkCsnBQrvJKBZRwgVH40H71PZw0pZidiQ3gOP hfOzhnj2rsSe7GGZamOv+W8Ai1odlCDEyA== X-Google-Smtp-Source: ABdhPJzyhQ8e0ZLCj/Du9L9st0l3VnW5IAfRW7Fn4vUJ5oaWO5af3oiXkAFyrdj38nTMLmZxbd0vtA== X-Received: by 2002:a6b:8ed4:: with SMTP id q203mr9777949iod.200.1639003857077; Wed, 08 Dec 2021 14:50:57 -0800 (PST) Received: from aford-IdeaCentre-A730.lan ([2601:448:8400:9e8:269a:1aa2:f1d9:8dbb]) by smtp.gmail.com with ESMTPSA id t6sm2378751ioi.51.2021.12.08.14.50.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Dec 2021 14:50:56 -0800 (PST) From: Adam Ford To: linux-media@vger.kernel.org Cc: benjamin.gaignard@collabora.com, cphealy@gmail.com, aford@beaconembedded.com, nicolas@ndufresne.ca, Adam Ford , Ezequiel Garcia , Philipp Zabel , Mauro Carvalho Chehab , Rob Herring , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Greg Kroah-Hartman , Lucas Stach , linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev Subject: [PATCH 08/10] dt-bindings: media: nxp,imx8mq-vpu: Enable support for i.MX8M Mini Date: Wed, 8 Dec 2021 16:50:27 -0600 Message-Id: <20211208225030.2018923-9-aford173@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211208225030.2018923-1-aford173@gmail.com> References: <20211208225030.2018923-1-aford173@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The i.MX8M mini appears to have a similar G1 and G2 decoder but the post-procesing isn't present. Add compatible flags to support G1 and G2 without post-processing. Signed-off-by: Adam Ford --- Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml b/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml index eeb7bd6281f9..fb6c2ab1b2dc 100644 --- a/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml +++ b/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml @@ -20,6 +20,8 @@ properties: deprecated: true - const: nxp,imx8mq-vpu-g1 - const: nxp,imx8mq-vpu-g2 + - const: nxp, imx8mm-vpu-g1 + - const: nxp, imx8mm-vpu-g2 reg: minItems: 1 From patchwork Wed Dec 8 22:50:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 12665475 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA102C433F5 for ; Wed, 8 Dec 2021 22:51:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241083AbhLHWyn (ORCPT ); Wed, 8 Dec 2021 17:54:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45272 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240974AbhLHWyc (ORCPT ); Wed, 8 Dec 2021 17:54:32 -0500 Received: from mail-il1-x130.google.com (mail-il1-x130.google.com [IPv6:2607:f8b0:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 72D7DC0617A2; Wed, 8 Dec 2021 14:51:00 -0800 (PST) Received: by mail-il1-x130.google.com with SMTP id a11so3651418ilj.6; Wed, 08 Dec 2021 14:51:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hdJ89QiMEvN3VGs2DFynThgfT2ETzQmQafALw9z6ufA=; b=BZvVdS+LC5Kq8GGv8p0rF08hRwd5fXxBjQHWcaVL0zCr6b7qnv0mKs6RrGj0CY4HlW YMaUyYT5Zi/RUWVfolzS9c/zPH3BQtHPG5/+XDDTdlVM8UN7DOEGlXIJm1NQEc+m1tYM 4MUsiIiBWvHee8OWqdAskMcDgAgWEe8Q0BFQIhPuJ00Mm4l6Wv0HL5IaP1wGXooWyKFm LrnGEjso0C07827b6UDc34mOGub6ZTuf5O0fFWhf9zlCY6yYk5iV0ivGCcOGayUk2k8n okladLKCnnlC27c/ijLrPuITJmcidaAjPe62XHwJ42DFI/kiN/+0F9HeugBK+hx8B0KU LVUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hdJ89QiMEvN3VGs2DFynThgfT2ETzQmQafALw9z6ufA=; b=RTSKAxzIYX/naxCZCjARkqY0Pm1K9nR5N1PRQ2CqjIXKN25kM3bgVrP1zwgPASGbSu WQ9IDW8UhrwXQ55HsJIEpJUeOAdYpdEZLs/Gk/3sI2xpZNFKs/B7AlkZrVaHPEifDSJM rEG54DawVzkgcPMlVImU3LJow3pxSf4s2nMOKVSXW+7JYcFKBi8A1pB5MbkEPM7yRxHF ALKRxHDqz9MG8qGELjBMHK42zh0jfbgVui1z23fKSegRCe7Arxewc965gQu/DqzzjQlp UgmcEhIaDS4OA+9mihpgR4Os69NRn7pWtMEXPlQfUuDgJv76qWpxlCMFZhSARWpNuSXL 6ivg== X-Gm-Message-State: AOAM530ekCjVczIwT507xH7zKeKxZaIqSaKGU6bp1pLzlASIjapNWGRe oe+W2MT5pbYC3ZJNj7WXQNX+bNzs0fzOMQ== X-Google-Smtp-Source: ABdhPJzHxIGfj2xcbAZPXs0NHLze6piLYIoq+N8EHlF0Bz33z0T9C/q5u3c6+hKZAolZnZr2kuz0Qw== X-Received: by 2002:a05:6e02:18c9:: with SMTP id s9mr9705872ilu.86.1639003859402; Wed, 08 Dec 2021 14:50:59 -0800 (PST) Received: from aford-IdeaCentre-A730.lan ([2601:448:8400:9e8:269a:1aa2:f1d9:8dbb]) by smtp.gmail.com with ESMTPSA id t6sm2378751ioi.51.2021.12.08.14.50.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Dec 2021 14:50:59 -0800 (PST) From: Adam Ford To: linux-media@vger.kernel.org Cc: benjamin.gaignard@collabora.com, cphealy@gmail.com, aford@beaconembedded.com, nicolas@ndufresne.ca, Adam Ford , Ezequiel Garcia , Philipp Zabel , Mauro Carvalho Chehab , Rob Herring , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Greg Kroah-Hartman , Lucas Stach , linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev Subject: [PATCH 09/10] media: hantro: Add support for i.MX8MM Date: Wed, 8 Dec 2021 16:50:28 -0600 Message-Id: <20211208225030.2018923-10-aford173@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211208225030.2018923-1-aford173@gmail.com> References: <20211208225030.2018923-1-aford173@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The i.MX8MM has a G1 and G2 video decoder, so add support in the driver for it with the post-processing removed. Signed-off-by: Adam Ford --- drivers/staging/media/hantro/hantro_drv.c | 2 ++ drivers/staging/media/hantro/hantro_hw.h | 2 ++ drivers/staging/media/hantro/imx8m_vpu_hw.c | 28 +++++++++++++++++++++ 3 files changed, 32 insertions(+) diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c index e7afda388ee5..118c4fa3d556 100644 --- a/drivers/staging/media/hantro/hantro_drv.c +++ b/drivers/staging/media/hantro/hantro_drv.c @@ -608,6 +608,8 @@ static const struct of_device_id of_hantro_match[] = { { .compatible = "rockchip,rk3399-vpu", .data = &rk3399_vpu_variant, }, #endif #ifdef CONFIG_VIDEO_HANTRO_IMX8M + { .compatible = "nxp,imx8mm-vpu-g1", .data = &imx8mm_vpu_g1_variant, }, + { .compatible = "nxp,imx8mm-vpu-g2", .data = &imx8mm_vpu_g2_variant }, { .compatible = "nxp,imx8mq-vpu", .data = &imx8mq_vpu_variant, }, { .compatible = "nxp,imx8mq-vpu-g1", .data = &imx8mq_vpu_g1_variant }, { .compatible = "nxp,imx8mq-vpu-g2", .data = &imx8mq_vpu_g2_variant }, diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h index 96b14b43a4af..6ae1aeed2e16 100644 --- a/drivers/staging/media/hantro/hantro_hw.h +++ b/drivers/staging/media/hantro/hantro_hw.h @@ -299,6 +299,8 @@ enum hantro_enc_fmt { ROCKCHIP_VPU_ENC_FMT_UYVY422 = 3, }; +extern const struct hantro_variant imx8mm_vpu_g1_variant; +extern const struct hantro_variant imx8mm_vpu_g2_variant; extern const struct hantro_variant imx8mq_vpu_g1_variant; extern const struct hantro_variant imx8mq_vpu_g2_variant; extern const struct hantro_variant imx8mq_vpu_variant; diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c index e0af4b93d3c6..65bb6f464dc9 100644 --- a/drivers/staging/media/hantro/imx8m_vpu_hw.c +++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c @@ -351,3 +351,31 @@ const struct hantro_variant imx8mq_vpu_g2_variant = { .reg_names = imx8mq_g2_reg_names, .num_regs = ARRAY_SIZE(imx8mq_g2_reg_names), }; + +const struct hantro_variant imx8mm_vpu_g1_variant = { + .dec_fmts = imx8m_vpu_dec_fmts, + .num_dec_fmts = ARRAY_SIZE(imx8m_vpu_dec_fmts), + .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER | + HANTRO_H264_DECODER, + .codec_ops = imx8mq_vpu_g1_codec_ops, + .irqs = imx8mq_irqs, + .num_irqs = ARRAY_SIZE(imx8mq_irqs), + .clk_names = imx8mq_g1_clk_names, + .num_clocks = ARRAY_SIZE(imx8mq_g1_clk_names), + .reg_names = imx8mq_g1_reg_names, + .num_regs = ARRAY_SIZE(imx8mq_g1_reg_names), +}; + +const struct hantro_variant imx8mm_vpu_g2_variant = { + .dec_offset = 0x0, + .dec_fmts = imx8m_vpu_g2_dec_fmts, + .num_dec_fmts = ARRAY_SIZE(imx8m_vpu_g2_dec_fmts), + .codec = HANTRO_HEVC_DECODER | HANTRO_VP9_DECODER, + .codec_ops = imx8mq_vpu_g2_codec_ops, + .irqs = imx8mq_g2_irqs, + .num_irqs = ARRAY_SIZE(imx8mq_g2_irqs), + .clk_names = imx8mq_g2_clk_names, + .num_clocks = ARRAY_SIZE(imx8mq_g2_clk_names), + .reg_names = imx8mq_g2_reg_names, + .num_regs = ARRAY_SIZE(imx8mq_g2_reg_names), +}; From patchwork Wed Dec 8 22:50:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 12665477 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 54CA4C433FE for ; Wed, 8 Dec 2021 22:51:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241096AbhLHWyt (ORCPT ); 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Wed, 08 Dec 2021 14:51:01 -0800 (PST) From: Adam Ford To: linux-media@vger.kernel.org Cc: benjamin.gaignard@collabora.com, cphealy@gmail.com, aford@beaconembedded.com, nicolas@ndufresne.ca, Adam Ford , Ezequiel Garcia , Philipp Zabel , Mauro Carvalho Chehab , Rob Herring , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Greg Kroah-Hartman , Lucas Stach , linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev Subject: [PATCH 10/10] arm64: dts: imx8mm: Enable Hantro G1 and G2 video decoders Date: Wed, 8 Dec 2021 16:50:29 -0600 Message-Id: <20211208225030.2018923-11-aford173@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211208225030.2018923-1-aford173@gmail.com> References: <20211208225030.2018923-1-aford173@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org There are two decoders on the i.MX8M Mini controlled by the vpu-blk-ctrl. The G1 supports H264 and VP8 while the G2 support HEVC and VP9. Signed-off-by: Adam Ford --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 28 +++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index f13d31ebfcbd..4682f1f5238d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1196,6 +1196,28 @@ gpu_2d: gpu@38008000 { power-domains = <&pgc_gpu>; }; + vpu_g1: video-codec@38300000 { + compatible = "nxp,imx8mm-vpu-g1"; + reg = <0x38300000 0x10000>; + reg-names = "g1"; + interrupts = ; + interrupt-names = "g1"; + clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>; + clock-names = "g1"; + power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G1>; + }; + + vpu_g2: video-codec@38310000 { + compatible = "nxp,imx8mm-vpu-g2"; + reg = <0x38310000 0x10000>; + reg-names = "g2"; + interrupts = ; + interrupt-names = "g2"; + clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>; + clock-names = "g2"; + power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G2>; + }; + vpu_blk_ctrl: blk-ctrl@38330000 { compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon"; reg = <0x38330000 0x100>; @@ -1206,6 +1228,12 @@ vpu_blk_ctrl: blk-ctrl@38330000 { <&clk IMX8MM_CLK_VPU_G2_ROOT>, <&clk IMX8MM_CLK_VPU_H1_ROOT>; clock-names = "g1", "g2", "h1"; + assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>, + <&clk IMX8MM_CLK_VPU_G2>; + assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>, + <&clk IMX8MM_VPU_PLL_OUT>; + assigned-clock-rates = <600000000>, + <600000000>; #power-domain-cells = <1>; };