From patchwork Thu Dec 9 12:29:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 12666481 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 949DBC433F5 for ; Thu, 9 Dec 2021 12:29:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236081AbhLIMdU (ORCPT ); Thu, 9 Dec 2021 07:33:20 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:50895 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229919AbhLIMdU (ORCPT ); Thu, 9 Dec 2021 07:33:20 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1639052987; x=1670588987; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Xd9Rwi9IKDoW7SY8FYHsa3ZNF0l93uiiSgNbg2ztoig=; b=oxaw43OmLAoQlcotiJz9V2tRWzs0gTwgmYXy9rFIv118HB8l6nvbSysY wX7pihN10OPnqglBbRWDT1RdZ6vO7j32EcdijIZIwlVEp72AvHBU+1XBO e6La026u+9iqQPPoIgp/Qmy/LG6WTotAMH4VLfeXELCvZDwj+y/uBCn2d +vdaOcxFs3rsedo1NpFgPG4Utd8IjDEBLlwmikjc9UzKfOQ3YiGgJKXek vg6WIQYmdCkJuBs9AxkTBxuP2vc2JhHx0/4c1j+ueUJN6kSVdlK2AwHhJ o2KTEJHW3aSB88E+rKDxJo+5kbwxKkEN/HLOVvPD3n9hVFB1mMTGOCKA1 g==; IronPort-SDR: Jsuv8MMuzlCCj2a9A9IE96GxHYar/oz9bADe2OdIP/rQ/y5SHHUjSLjGrM91LiIfkT6PVddxEP RHe9ZVDlJUMWYBtoIZqGZRI6BgfMWNbjj68X/BESkwZVgCSwZq+zaejc3daoO6T9dHiq0gtj8x 01O+5FTskkfH9njODe9MlZfndpVMFKPR2il9oDxteheHjSGxpeZK8gAdR2ZPRSbrbzSyEuUlpi rLORDV0m6C3YzQImfIpU7AMCrR/s/SP4VOjiYY+Z1Sntxckt0GbZ4qsUsQ7omGrSkBCU9vV9sv 9LGSw7wUFX3ZfcCGBhGztpZF X-IronPort-AV: E=Sophos;i="5.88,192,1635231600"; d="scan'208";a="154857067" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 09 Dec 2021 05:29:46 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Thu, 9 Dec 2021 05:29:46 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Thu, 9 Dec 2021 05:29:43 -0700 From: Tudor Ambarus To: , CC: , , , , , , , Tudor Ambarus Subject: [PATCH 1/2] dt-bindings: spi: atmel,quadspi: Convert to json-schema Date: Thu, 9 Dec 2021 14:29:38 +0200 Message-ID: <20211209122939.339810-2-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211209122939.339810-1-tudor.ambarus@microchip.com> References: <20211209122939.339810-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Convert the Atmel QuadSPI controller Device Tree binding documentation to json-schema. Signed-off-by: Tudor Ambarus Reviewed-by: Rob Herring --- .../bindings/spi/atmel,quadspi.yaml | 87 +++++++++++++++++++ .../devicetree/bindings/spi/atmel-quadspi.txt | 37 -------- 2 files changed, 87 insertions(+), 37 deletions(-) create mode 100644 Documentation/devicetree/bindings/spi/atmel,quadspi.yaml delete mode 100644 Documentation/devicetree/bindings/spi/atmel-quadspi.txt diff --git a/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml b/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml new file mode 100644 index 000000000000..7d0408f53c5f --- /dev/null +++ b/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/atmel,quadspi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel Quad Serial Peripheral Interface (QSPI) + +maintainers: + - Tudor Ambarus + +allOf: + - $ref: spi-controller.yaml# + +properties: + compatible: + enum: + - atmel,sama5d2-qspi + - microchip,sam9x60-qspi + + reg: + items: + - description: base registers + - description: mapped memory + + reg-names: + items: + - const: qspi_base + - const: qspi_mmap + + clocks: + minItems: 1 + items: + - description: peripheral clock + - description: system clock, if available + + clock-names: + minItems: 1 + items: + - const: pclk + - const: qspick + + interrupts: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +required: + - compatible + - reg + - reg-names + - interrupts + - clocks + - clock-names + - '#address-cells' + - '#size-cells' + +unevaluatedProperties: false + +examples: + - | + #include + #include + spi@f0020000 { + compatible = "atmel,sama5d2-qspi"; + reg = <0xf0020000 0x100>, <0xd0000000 0x8000000>; + reg-names = "qspi_base", "qspi_mmap"; + interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 52>; + clock-names = "pclk"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0_default>; + + flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + reg = <0>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + }; + }; diff --git a/Documentation/devicetree/bindings/spi/atmel-quadspi.txt b/Documentation/devicetree/bindings/spi/atmel-quadspi.txt deleted file mode 100644 index 7c40ea694352..000000000000 --- a/Documentation/devicetree/bindings/spi/atmel-quadspi.txt +++ /dev/null @@ -1,37 +0,0 @@ -* Atmel Quad Serial Peripheral Interface (QSPI) - -Required properties: -- compatible: Should be one of the following: - - "atmel,sama5d2-qspi" - - "microchip,sam9x60-qspi" -- reg: Should contain the locations and lengths of the base registers - and the mapped memory. -- reg-names: Should contain the resource reg names: - - qspi_base: configuration register address space - - qspi_mmap: memory mapped address space -- interrupts: Should contain the interrupt for the device. -- clocks: Should reference the peripheral clock and the QSPI system - clock if available. -- clock-names: Should contain "pclk" for the peripheral clock and "qspick" - for the system clock when available. -- #address-cells: Should be <1>. -- #size-cells: Should be <0>. - -Example: - -spi@f0020000 { - compatible = "atmel,sama5d2-qspi"; - reg = <0xf0020000 0x100>, <0xd0000000 0x8000000>; - reg-names = "qspi_base", "qspi_mmap"; - interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 52>; - clock-names = "pclk"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0_default>; - - m25p80@0 { - ... - }; -}; From patchwork Thu Dec 9 12:29:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 12666483 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1CD27C433EF for ; Thu, 9 Dec 2021 12:29:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237357AbhLIMdY (ORCPT ); Thu, 9 Dec 2021 07:33:24 -0500 Received: from esa.microchip.iphmx.com ([68.232.154.123]:52831 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229919AbhLIMdX (ORCPT ); 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d="scan'208";a="141843400" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 09 Dec 2021 05:29:49 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Thu, 9 Dec 2021 05:29:49 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Thu, 9 Dec 2021 05:29:46 -0700 From: Tudor Ambarus To: , CC: , , , , , , , Tudor Ambarus Subject: [PATCH 2/2] dt-bindings: spi: atmel,quadspi: Define sama7g5 QSPI Date: Thu, 9 Dec 2021 14:29:39 +0200 Message-ID: <20211209122939.339810-3-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211209122939.339810-1-tudor.ambarus@microchip.com> References: <20211209122939.339810-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org sama7g5 embedds 2 instances of the QSPI controller: 1/ One Octal Serial Peripheral Interface (QSPI0) Supporting up to 200 MHz DDR. Octal, TwinQuad, HyperFlash and OctaFlash Protocols Supported 2/ One Quad Serial Peripheral Interface (QSPI1) Supporting Up to 90 MHz DDR/133 MHz SDR Signed-off-by: Tudor Ambarus Reviewed-by: Rob Herring --- .../devicetree/bindings/spi/atmel,quadspi.yaml | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml b/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml index 7d0408f53c5f..1d493add4053 100644 --- a/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml +++ b/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml @@ -17,6 +17,8 @@ properties: enum: - atmel,sama5d2-qspi - microchip,sam9x60-qspi + - microchip,sama7g5-qspi + - microchip,sama7g5-ospi reg: items: @@ -32,17 +34,27 @@ properties: minItems: 1 items: - description: peripheral clock - - description: system clock, if available + - description: system clock or generic clock, if available clock-names: minItems: 1 items: - const: pclk - - const: qspick + - enum: [ qspick, gclk ] interrupts: maxItems: 1 + dmas: + items: + - description: tx DMA channel + - description: rx DMA channel + + dma-names: + items: + - const: tx + - const: rx + '#address-cells': const: 1