From patchwork Thu Dec 9 16:37:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nikita Travkin X-Patchwork-Id: 12667049 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CCCC7C43217 for ; Thu, 9 Dec 2021 16:45:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241252AbhLIQsl (ORCPT ); Thu, 9 Dec 2021 11:48:41 -0500 Received: from box.trvn.ru ([194.87.146.52]:59783 "EHLO box.trvn.ru" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237930AbhLIQsj (ORCPT ); Thu, 9 Dec 2021 11:48:39 -0500 Received: from authenticated-user (box.trvn.ru [194.87.146.52]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by box.trvn.ru (Postfix) with ESMTPSA id 0E7E641F11; Thu, 9 Dec 2021 21:37:32 +0500 (+05) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=trvn.ru; s=mail; t=1639067853; bh=R94w1FLumb+TBnOujhfbT4mF8MJQyo9KAMn2JGNsyvk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=tGlY3TItarPP7YzRj3umBlYniqehPgj05qATx12yKmD+z7CmqyHhgctXYQGXhDl09 ppFc3nuWV5Hq1YD/UnradrDcrUbzEQESnNHsJEgCIDeOnRgOp8FPRlr6dOkf7C08FA fUMacTUCJunJs6xUeVMap4ZmQc8w8nR/TppyFSbFs33kM0qF5AIFdNpUX9Wvb5Oc29 gACk0DGjgR7RSTLTU6KePaNhPq4cyY91fcCODiyfgESNpfoOz/zojEnywcFYzMnZYQ WuNribOaxk/ABYDXqsy7JvoGRzusvqV74iIb3jraHoSzootLqzSPoju1jM4+H7f5Cd 97LVCUtAQJOtw== From: Nikita Travkin To: mturquette@baylibre.com, sboyd@kernel.org, linus.walleij@linaro.org Cc: bjorn.andersson@linaro.org, agross@kernel.org, tdas@codeaurora.org, joonwoop@codeaurora.org, svarbanov@mm-sol.com, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Nikita Travkin Subject: [PATCH 1/4] clk: qcom: clk-rcg2: Fail Duty-Cycle configuration if MND divider is not enabled. Date: Thu, 9 Dec 2021 21:37:17 +0500 Message-Id: <20211209163720.106185-2-nikita@trvn.ru> In-Reply-To: <20211209163720.106185-1-nikita@trvn.ru> References: <20211209163720.106185-1-nikita@trvn.ru> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org In cases when MND is not enabled (e.g. when only Half Integer Divider is used), setting D registers makes no effect. Fail instead of making ineffective write. Fixes: 7f891faf596e ("clk: qcom: clk-rcg2: Add support for duty-cycle for RCG") Signed-off-by: Nikita Travkin --- drivers/clk/qcom/clk-rcg2.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index e1b1b426fae4..6964cf914b60 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -396,7 +396,7 @@ static int clk_rcg2_get_duty_cycle(struct clk_hw *hw, struct clk_duty *duty) static int clk_rcg2_set_duty_cycle(struct clk_hw *hw, struct clk_duty *duty) { struct clk_rcg2 *rcg = to_clk_rcg2(hw); - u32 notn_m, n, m, d, not2d, mask, duty_per; + u32 notn_m, n, m, d, not2d, mask, duty_per, cfg; int ret; /* Duty-cycle cannot be modified for non-MND RCGs */ @@ -407,6 +407,11 @@ static int clk_rcg2_set_duty_cycle(struct clk_hw *hw, struct clk_duty *duty) regmap_read(rcg->clkr.regmap, RCG_N_OFFSET(rcg), ¬n_m); regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m); + regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg); + + /* Duty-cycle cannot be modified if MND divider is in bypass mode. */ + if (!(cfg & CFG_MODE_MASK)) + return -EINVAL; n = (~(notn_m) + m) & mask; From patchwork Thu Dec 9 16:37:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nikita Travkin X-Patchwork-Id: 12667047 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 861DFC4332F for ; Thu, 9 Dec 2021 16:45:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241248AbhLIQsl (ORCPT ); Thu, 9 Dec 2021 11:48:41 -0500 Received: from box.trvn.ru ([194.87.146.52]:43699 "EHLO box.trvn.ru" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240363AbhLIQsj (ORCPT ); Thu, 9 Dec 2021 11:48:39 -0500 Received: from authenticated-user (box.trvn.ru [194.87.146.52]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by box.trvn.ru (Postfix) with ESMTPSA id E472241F22; Thu, 9 Dec 2021 21:37:33 +0500 (+05) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=trvn.ru; s=mail; t=1639067855; bh=4UAl5FlZiuT0MWj7WWv0Ooo6qEkHhQ4HRAJs5eOrKXI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=c7f28H7Y8aZipmfd5LDWI5mN/ln4IINxJGEs3eUHyPXwPOW6/w+4smmLBz7SXgKPc Xy8qL0V9c1B9jkduMbGutTg/U9C2AQ7jsQdT4wBiGWRDeCvnUqVl8BAbQ4t+zw/cUR 4lBxAVL57QZvXOrU0H6ghYnQkZudxDsQ4YEA+oLwmVL7+fOlxkBed76BxLDvT45l76 4E9tL5ZID5PSMkRQIt2ZjJQY8T476tEx6aAfeBRvDpCaYq+H5ej406bkrgKy6U8tdc woBhenn6laVgTf7aYAZxCj8tqyx/28t2V8FgKfzCYbNAAajZS1YPrwDzj0uCZtldPf jqoLGuS7eKJwg== From: Nikita Travkin To: mturquette@baylibre.com, sboyd@kernel.org, linus.walleij@linaro.org Cc: bjorn.andersson@linaro.org, agross@kernel.org, tdas@codeaurora.org, joonwoop@codeaurora.org, svarbanov@mm-sol.com, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Nikita Travkin Subject: [PATCH 2/4] clk: qcom: clk-rcg2: Make sure to not write d=0 to the NMD register Date: Thu, 9 Dec 2021 21:37:18 +0500 Message-Id: <20211209163720.106185-3-nikita@trvn.ru> In-Reply-To: <20211209163720.106185-1-nikita@trvn.ru> References: <20211209163720.106185-1-nikita@trvn.ru> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Sometimes calculation of d value may result in 0 because of the rounding after integer division. This causes the following error: [ 113.969689] camss_gp1_clk_src: rcg didn't update its configuration. [ 113.969754] WARNING: CPU: 3 PID: 35 at drivers/clk/qcom/clk-rcg2.c:122 update_config+0xc8/0xdc Make sure that D value is never zero. Fixes: 7f891faf596e ("clk: qcom: clk-rcg2: Add support for duty-cycle for RCG") Signed-off-by: Nikita Travkin --- drivers/clk/qcom/clk-rcg2.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index 6964cf914b60..fdfd43e2a01b 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -424,6 +424,10 @@ static int clk_rcg2_set_duty_cycle(struct clk_hw *hw, struct clk_duty *duty) if (d > mask) d = mask; + /* Hardware can't handle d=0, make sure it's at least 1 */ + if (!d) + d = 1; + if ((d / 2) > (n - m)) d = (n - m) * 2; else if ((d / 2) < (m / 2)) From patchwork Thu Dec 9 16:37:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nikita Travkin X-Patchwork-Id: 12667045 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78F0EC433FE for ; Thu, 9 Dec 2021 16:45:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236389AbhLIQsj (ORCPT ); Thu, 9 Dec 2021 11:48:39 -0500 Received: from box.trvn.ru ([194.87.146.52]:33089 "EHLO box.trvn.ru" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240288AbhLIQsi (ORCPT ); Thu, 9 Dec 2021 11:48:38 -0500 Received: from authenticated-user (box.trvn.ru [194.87.146.52]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by box.trvn.ru (Postfix) with ESMTPSA id 8940041F24; Thu, 9 Dec 2021 21:37:35 +0500 (+05) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=trvn.ru; s=mail; t=1639067856; bh=IKXmKvCFlWItZeQ+S4YnIO8PPn2o910X9uFp4aTBE+8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RZCmQ2WNBDgHvQUnHrFmWvrFwtiQ1M2QXZS8ZsDPTLP3+lhmvKRSwdej9thSxnEpH DtgyMv9edIkNn2biC790j05OjFb1UgCA9cZ8l5rFRrWHvM0vs3/3rmfbYVdciWyUpx YkZloMS//iWZovSbDWaRcZ7N9ztRtumLdVAUPIAo1Zvh2NW8dl1jaBEA2tVX+vqoyp ON5RUWO4HzqhY1le/SbN+1/obb2mmuAG0Cx0m9WnDIeaehgRNHt4gwvcWlMdYWd63b O8jJgFKTn55b90pJ/HgyKgkkI1Gl4hgdut4izLm7tU3EcZ7RAVFefMxtGR9GQg1HGt wSO/5pbOpcdpw== From: Nikita Travkin To: mturquette@baylibre.com, sboyd@kernel.org, linus.walleij@linaro.org Cc: bjorn.andersson@linaro.org, agross@kernel.org, tdas@codeaurora.org, joonwoop@codeaurora.org, svarbanov@mm-sol.com, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Nikita Travkin Subject: [PATCH 3/4] pinctrl: qcom: msm8916: Allow CAMSS GP clocks to be muxed Date: Thu, 9 Dec 2021 21:37:19 +0500 Message-Id: <20211209163720.106185-4-nikita@trvn.ru> In-Reply-To: <20211209163720.106185-1-nikita@trvn.ru> References: <20211209163720.106185-1-nikita@trvn.ru> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org GPIO 31, 32 can be muxed to GCC_CAMSS_GP(1,2)_CLK respectively but the function was never assigned to the pingroup (even though the function exists already). Add this mode to the related pins. Fixes: 5373a2c5abb6 ("pinctrl: qcom: Add msm8916 pinctrl driver") Signed-off-by: Nikita Travkin --- drivers/pinctrl/qcom/pinctrl-msm8916.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-msm8916.c b/drivers/pinctrl/qcom/pinctrl-msm8916.c index 396db12ae904..bf68913ba821 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8916.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8916.c @@ -844,8 +844,8 @@ static const struct msm_pingroup msm8916_groups[] = { PINGROUP(28, pwr_modem_enabled_a, NA, NA, NA, NA, NA, qdss_tracedata_b, NA, atest_combodac), PINGROUP(29, cci_i2c, NA, NA, NA, NA, NA, qdss_tracedata_b, NA, atest_combodac), PINGROUP(30, cci_i2c, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_b), - PINGROUP(31, cci_timer0, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(32, cci_timer1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(31, cci_timer0, flash_strobe, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(32, cci_timer1, flash_strobe, NA, NA, NA, NA, NA, NA, NA), PINGROUP(33, cci_async, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_b), PINGROUP(34, pwr_nav_enabled_a, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_b), PINGROUP(35, pwr_crypto_enabled_a, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_b), From patchwork Thu Dec 9 16:37:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nikita Travkin X-Patchwork-Id: 12667043 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 045A5C43219 for ; Thu, 9 Dec 2021 16:45:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240500AbhLIQsi (ORCPT ); Thu, 9 Dec 2021 11:48:38 -0500 Received: from box.trvn.ru ([194.87.146.52]:53005 "EHLO box.trvn.ru" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236389AbhLIQsh (ORCPT ); Thu, 9 Dec 2021 11:48:37 -0500 Received: from authenticated-user (box.trvn.ru [194.87.146.52]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by box.trvn.ru (Postfix) with ESMTPSA id D13DF41F30; Thu, 9 Dec 2021 21:37:39 +0500 (+05) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=trvn.ru; s=mail; t=1639067860; bh=ITv8oy4gH8hvt2xoJZdnpKjB0KS+uuWG14QJNxq0uPI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PdTOfoNUh2FZzHLgyhKHTuJiEN7RICt1iz9vSWGI4vcYLO8WqzPb/NZBSICTfb9qY BtCUOMnbqCMLPh5/IS3tVUKlF+ijp/f6J4XH9p27bxgu/I1b/paCSmkc2TOBQ/mLeH uXYxin9jEwM1DeU+No2fparO5u8xWGaa7xRgeQ6VtiTTQ7xbvH3a8OfkcIBdiaUIVU 1Ooo5nRmWIGQp3HuTVtBYG8UwvUhCSQ+pJGEobKYUoG7gE/0OhzfPt1NX3hDtqD+cq TNhQ7WK2M4E8Y6aXr1SYd5i5STg+f7twYFsytl25htkJZT8vKlEnFKYIQLdCWdfozQ mZvCDv/ib3OVA== From: Nikita Travkin To: mturquette@baylibre.com, sboyd@kernel.org, linus.walleij@linaro.org Cc: bjorn.andersson@linaro.org, agross@kernel.org, tdas@codeaurora.org, joonwoop@codeaurora.org, svarbanov@mm-sol.com, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Nikita Travkin Subject: [PATCH 4/4] clk: qcom: gcc-msm8916: Add rates to the GP clocks Date: Thu, 9 Dec 2021 21:37:20 +0500 Message-Id: <20211209163720.106185-5-nikita@trvn.ru> In-Reply-To: <20211209163720.106185-1-nikita@trvn.ru> References: <20211209163720.106185-1-nikita@trvn.ru> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org msm8916 has (at least) 6 "General Purpose" clocks that can be muxed to SoC pins. These clocks are: GP_CLK{0, 1} : GPIO_{31, 32} (Belongs to CAMSS according to Linux) GP_CLK_{1-3}{A, B} : GPIO_{49-51, 97, 12, 13} (Belongs to GCC itself) GP_MN : GPIO_110 (Doesn't seem to be described in gcc, ignored in this patch) Those clocks may be used as e.g. PWM sources for external peripherals. Add more frequencies to the table for those clocks so it's possible for arbitrary peripherals to make use of them. Signed-off-by: Nikita Travkin Reviewed-by: Stephen Boyd --- drivers/clk/qcom/gcc-msm8916.c | 35 ++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c index 17e4a5a2a9fd..9a46794f6eb8 100644 --- a/drivers/clk/qcom/gcc-msm8916.c +++ b/drivers/clk/qcom/gcc-msm8916.c @@ -765,7 +765,20 @@ static struct clk_rcg2 cci_clk_src = { }, }; +/* + * This is a frequency table for "General Purpose" clocks. + * These clocks can be muxed to the SoC pins and may be used by + * external devices. They're often used as PWM source. + * + * See comment at ftbl_gcc_gp1_3_clk. + */ static const struct freq_tbl ftbl_gcc_camss_gp0_1_clk[] = { + F(10000, P_XO, 16, 1, 120), + F(100000, P_XO, 16, 1, 12), + F(500000, P_GPLL0, 16, 1, 100), + F(1000000, P_GPLL0, 16, 1, 50), + F(2500000, P_GPLL0, 16, 1, 20), + F(5000000, P_GPLL0, 16, 1, 10), F(100000000, P_GPLL0, 8, 0, 0), F(200000000, P_GPLL0, 4, 0, 0), { } @@ -927,7 +940,29 @@ static struct clk_rcg2 crypto_clk_src = { }, }; +/* + * This is a frequency table for "General Purpose" clocks. + * These clocks can be muxed to the SoC pins and may be used by + * external devices. They're often used as PWM source. + * + * Please note that MND divider must be enabled for duty-cycle + * control to be possible. (M != N) Also since D register is configured + * with a value multiplied by 2, and duty cycle is calculated as + * (2 * D) % 2^W + * DutyCycle = ---------------- + * 2 * (N % 2^W) + * (where W = .mnd_width) + * N must be half or less than maximum value for the register. + * Otherwise duty-cycle control would be limited. + * (e.g. for 8-bit NMD N should be less than 128) + */ static const struct freq_tbl ftbl_gcc_gp1_3_clk[] = { + F(10000, P_XO, 16, 1, 120), + F(100000, P_XO, 16, 1, 12), + F(500000, P_GPLL0, 16, 1, 100), + F(1000000, P_GPLL0, 16, 1, 50), + F(2500000, P_GPLL0, 16, 1, 20), + F(5000000, P_GPLL0, 16, 1, 10), F(19200000, P_XO, 1, 0, 0), { } };