From patchwork Thu Dec 9 16:51:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 12667633 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E164BC433F5 for ; Thu, 9 Dec 2021 17:01:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E4C1510ED68; Thu, 9 Dec 2021 16:54:53 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 691A189DF9 for ; Thu, 9 Dec 2021 16:51:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1639068700; x=1670604700; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JuAY4E3pw5w6ExDGRs7BrNoDo1uxmgql3noB6sJ23rc=; b=P1gZ+j+r6HQmoRgM+Lg5lwaV2cmJdui2LV7I+lDvnM9n9zGu2nqBvEu9 e7yh6tdTDPEb3GpQfDHEEU1cTohZWkJeqiph1lcY/pGI6jUaLsIRcVBRG SQS8zqhr2rO1xHtB1G+EfVq1+IOcJ9o2vSuDHPkgcBWMkICeqSaXgrHgi NqA+ew1dcXADc4hB2ARfUdre1XYV8o/AgXRyw6MUuamwN9X2Q4vMtKatD guXGcLGux73gBxkyJnJzhjA+Txl0+yWLE9nUABwxYYC1wSttfiDc+2z7T vsKkheMFEvyWkhjbY+ynfacAnazKg4WNWslS2qBvbHz48tRlVLvvNFj/W w==; X-IronPort-AV: E=McAfee;i="6200,9189,10193"; a="218173023" X-IronPort-AV: E=Sophos;i="5.88,193,1635231600"; d="scan'208";a="218173023" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Dec 2021 08:51:39 -0800 X-IronPort-AV: E=Sophos;i="5.88,193,1635231600"; d="scan'208";a="680401085" Received: from cwilso3-mobl.fi.intel.com (HELO localhost) ([10.252.19.112]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Dec 2021 08:51:36 -0800 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Date: Thu, 9 Dec 2021 18:51:22 +0200 Message-Id: <43ad4d437121f43d76c790ac5d4d131743d58988.1639068649.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Subject: [Intel-gfx] [PATCH 1/4] drm/i915/cdclk: move intel_atomic_check_cdclk() to intel_cdclk.c X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Rename to intel_cdclk_atomic_check() and make intel_cdclk_bw_calc_min_cdclk() static. Signed-off-by: Jani Nikula Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_cdclk.c | 55 +++++++++++++++++++- drivers/gpu/drm/i915/display/intel_cdclk.h | 3 +- drivers/gpu/drm/i915/display/intel_display.c | 55 +------------------- 3 files changed, 57 insertions(+), 56 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 639a64733f61..a216a350006d 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -24,6 +24,7 @@ #include #include "intel_atomic.h" +#include "intel_atomic_plane.h" #include "intel_audio.h" #include "intel_bw.h" #include "intel_cdclk.h" @@ -68,7 +69,7 @@ void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv, dev_priv->cdclk_funcs->get_cdclk(dev_priv, cdclk_config); } -int intel_cdclk_bw_calc_min_cdclk(struct intel_atomic_state *state) +static int intel_cdclk_bw_calc_min_cdclk(struct intel_atomic_state *state) { struct drm_i915_private *dev_priv = to_i915(state->base.dev); return dev_priv->cdclk_funcs->bw_calc_min_cdclk(state); @@ -2629,6 +2630,58 @@ intel_atomic_get_cdclk_state(struct intel_atomic_state *state) return to_intel_cdclk_state(cdclk_state); } +int intel_cdclk_atomic_check(struct intel_atomic_state *state, + bool *need_cdclk_calc) +{ + struct drm_i915_private *i915 = to_i915(state->base.dev); + const struct intel_cdclk_state *old_cdclk_state; + const struct intel_cdclk_state *new_cdclk_state; + struct intel_plane_state *plane_state; + struct intel_bw_state *new_bw_state; + struct intel_plane *plane; + int min_cdclk = 0; + enum pipe pipe; + int ret; + int i; + + /* + * active_planes bitmask has been updated, and potentially affected + * planes are part of the state. We can now compute the minimum cdclk + * for each plane. + */ + for_each_new_intel_plane_in_state(state, plane, plane_state, i) { + ret = intel_plane_calc_min_cdclk(state, plane, need_cdclk_calc); + if (ret) + return ret; + } + + old_cdclk_state = intel_atomic_get_old_cdclk_state(state); + new_cdclk_state = intel_atomic_get_new_cdclk_state(state); + + if (new_cdclk_state && + old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk) + *need_cdclk_calc = true; + + ret = intel_cdclk_bw_calc_min_cdclk(state); + if (ret) + return ret; + + new_bw_state = intel_atomic_get_new_bw_state(state); + + if (!new_cdclk_state || !new_bw_state) + return 0; + + for_each_pipe(i915, pipe) { + min_cdclk = max(new_cdclk_state->min_cdclk[pipe], min_cdclk); + + /* Currently do this change only if we need to increase */ + if (new_bw_state->min_cdclk > min_cdclk) + *need_cdclk_calc = true; + } + + return 0; +} + int intel_cdclk_init(struct drm_i915_private *dev_priv) { struct intel_cdclk_state *cdclk_state; diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h index 89ca59c46102..bb3a778c506b 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.h +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h @@ -71,7 +71,8 @@ void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config, int intel_modeset_calc_cdclk(struct intel_atomic_state *state); void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv, struct intel_cdclk_config *cdclk_config); -int intel_cdclk_bw_calc_min_cdclk(struct intel_atomic_state *state); +int intel_cdclk_atomic_check(struct intel_atomic_state *state, + bool *need_cdclk_calc); struct intel_cdclk_state * intel_atomic_get_cdclk_state(struct intel_atomic_state *state); diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 576196ff7da1..578f50bd6ab7 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -7554,59 +7554,6 @@ static int intel_atomic_check_planes(struct intel_atomic_state *state) return 0; } -static int intel_atomic_check_cdclk(struct intel_atomic_state *state, - bool *need_cdclk_calc) -{ - struct drm_i915_private *dev_priv = to_i915(state->base.dev); - const struct intel_cdclk_state *old_cdclk_state; - const struct intel_cdclk_state *new_cdclk_state; - struct intel_plane_state *plane_state; - struct intel_bw_state *new_bw_state; - struct intel_plane *plane; - int min_cdclk = 0; - enum pipe pipe; - int ret; - int i; - /* - * active_planes bitmask has been updated, and potentially - * affected planes are part of the state. We can now - * compute the minimum cdclk for each plane. - */ - for_each_new_intel_plane_in_state(state, plane, plane_state, i) { - ret = intel_plane_calc_min_cdclk(state, plane, need_cdclk_calc); - if (ret) - return ret; - } - - old_cdclk_state = intel_atomic_get_old_cdclk_state(state); - new_cdclk_state = intel_atomic_get_new_cdclk_state(state); - - if (new_cdclk_state && - old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk) - *need_cdclk_calc = true; - - ret = intel_cdclk_bw_calc_min_cdclk(state); - if (ret) - return ret; - - new_bw_state = intel_atomic_get_new_bw_state(state); - - if (!new_cdclk_state || !new_bw_state) - return 0; - - for_each_pipe(dev_priv, pipe) { - min_cdclk = max(new_cdclk_state->min_cdclk[pipe], min_cdclk); - - /* - * Currently do this change only if we need to increase - */ - if (new_bw_state->min_cdclk > min_cdclk) - *need_cdclk_calc = true; - } - - return 0; -} - static int intel_atomic_check_crtcs(struct intel_atomic_state *state) { struct intel_crtc_state *crtc_state; @@ -8055,7 +8002,7 @@ static int intel_atomic_check(struct drm_device *dev, if (ret) goto fail; - ret = intel_atomic_check_cdclk(state, &any_ms); + ret = intel_cdclk_atomic_check(state, &any_ms); if (ret) goto fail; From patchwork Thu Dec 9 16:51:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 12667673 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D34FCC433EF for ; Thu, 9 Dec 2021 17:03:28 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1D84A10F76A; Thu, 9 Dec 2021 16:55:45 +0000 (UTC) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0254F89E63 for ; Thu, 9 Dec 2021 16:51:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1639068703; x=1670604703; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=/GgfCSVrr+M5zb+1IyY2xwoVr59G06mugNoNXVPX/Iw=; b=imj9cTGDQfR+I52h6SQJw+DZwK1qOGs1B/lmA1dbxkJIFpWB2dJOTUtO Rsl0ptz140K58ZprSpQj/49eTXgprCLsPsbygk/GpID83Pxb68zaybUOp Ged+znySInY7osqQmCqku4K7hIoy3NxQR24ezgJmPMV6Hxs/qyY18SafD Fn0rOMRjOmPFCAfoWzqs5P91X7YtlNufBxUVNR2GL3aO3ZBHBBahDyV08 xMJKD0FUbxYF2mLgnzvtxeaLmkzITN7/DHG/5YFrp1gpYcjB3yWm6KJS3 7sjO9Niy3W5k9QlKmZKzshTW5YL9iWLCMq1g8LVyGfQAmVb0C+SVM1VTY w==; X-IronPort-AV: E=McAfee;i="6200,9189,10193"; a="238374006" X-IronPort-AV: E=Sophos;i="5.88,193,1635231600"; d="scan'208";a="238374006" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Dec 2021 08:51:43 -0800 X-IronPort-AV: E=Sophos;i="5.88,193,1635231600"; d="scan'208";a="516377940" Received: from cwilso3-mobl.fi.intel.com (HELO localhost) ([10.252.19.112]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Dec 2021 08:51:41 -0800 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Date: Thu, 9 Dec 2021 18:51:23 +0200 Message-Id: <66f687db7321846049a6aa524dfafd45cf0cb77f.1639068649.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Subject: [Intel-gfx] [PATCH 2/4] drm/i915/cdclk: un-inline intel_cdclk_state functions X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Hide the details better. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_cdclk.c | 18 ++++++++++++++++++ drivers/gpu/drm/i915/display/intel_cdclk.h | 13 ++++++++----- 2 files changed, 26 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index a216a350006d..84674a4f7226 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -2630,6 +2630,24 @@ intel_atomic_get_cdclk_state(struct intel_atomic_state *state) return to_intel_cdclk_state(cdclk_state); } +struct intel_cdclk_state * +to_intel_cdclk_state(struct intel_global_state *cdclk_state) +{ + return container_of(cdclk_state, struct intel_cdclk_state, base); +} + +struct intel_cdclk_state * +intel_atomic_get_old_cdclk_state(struct intel_atomic_state *state) +{ + return to_intel_cdclk_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->cdclk.obj)); +} + +struct intel_cdclk_state * +intel_atomic_get_new_cdclk_state(struct intel_atomic_state *state) +{ + return to_intel_cdclk_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->cdclk.obj)); +} + int intel_cdclk_atomic_check(struct intel_atomic_state *state, bool *need_cdclk_calc) { diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h index bb3a778c506b..77e8c8e1708f 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.h +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h @@ -76,11 +76,14 @@ int intel_cdclk_atomic_check(struct intel_atomic_state *state, struct intel_cdclk_state * intel_atomic_get_cdclk_state(struct intel_atomic_state *state); -#define to_intel_cdclk_state(x) container_of((x), struct intel_cdclk_state, base) -#define intel_atomic_get_old_cdclk_state(state) \ - to_intel_cdclk_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->cdclk.obj)) -#define intel_atomic_get_new_cdclk_state(state) \ - to_intel_cdclk_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->cdclk.obj)) +struct intel_cdclk_state * +to_intel_cdclk_state(struct intel_global_state *cdclk_state); + +struct intel_cdclk_state * +intel_atomic_get_old_cdclk_state(struct intel_atomic_state *state); + +struct intel_cdclk_state * +intel_atomic_get_new_cdclk_state(struct intel_atomic_state *state); int intel_cdclk_init(struct drm_i915_private *dev_priv); From patchwork Thu Dec 9 16:51:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 12667667 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9FAEDC433EF for ; Thu, 9 Dec 2021 17:03:17 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8752110E86C; Thu, 9 Dec 2021 16:55:41 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 76F8B89E63 for ; Thu, 9 Dec 2021 16:51:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1639068708; x=1670604708; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5ykY+ZAu2UbYQmYG7LkMW7Nv4tzwIOHQMldlV6f146E=; b=idN7bWjQtJ+6gwQv0nb+8lSNf3jC+3I+zKXKcqwkDsNQYTecSa6pl2zC mWZynGUNl8buxZy54jJ36B/5cvkrRogv2AYYHAMGZ5b9D9OJaN9qtTuT7 RLshaQr50u7a3OrdRtKpGLQyQqUsf2PtoyvQ+SwSveaf7JTf4sreSOFap l4S8xKfMviX/8uk0b8L93iwHUDBRMua6RBGrmk8/M0nVy9iiVymHrC6Rk 6jr5Qw7ZmmfsumYrIv0z/h878tAYHoBQXTB3ygWogtrvJ8fDKV0qDcy8f gGOaWtY7m5qTvmWpuMiZ345ZcFaJ5xXFJjQuD7iDW2t+t9M0wpWeCDH7u w==; X-IronPort-AV: E=McAfee;i="6200,9189,10193"; a="324411217" X-IronPort-AV: E=Sophos;i="5.88,193,1635231600"; d="scan'208";a="324411217" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Dec 2021 08:51:47 -0800 X-IronPort-AV: E=Sophos;i="5.88,193,1635231600"; d="scan'208";a="612572200" Received: from cwilso3-mobl.fi.intel.com (HELO localhost) ([10.252.19.112]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Dec 2021 08:51:45 -0800 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Date: Thu, 9 Dec 2021 18:51:24 +0200 Message-Id: X-Mailer: git-send-email 2.30.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Subject: [Intel-gfx] [PATCH 3/4] drm/i915/cdclk: hide struct intel_cdclk_vals X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The definition is not needed outside of intel_cdclk.c. Signed-off-by: Jani Nikula Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_cdclk.c | 8 ++++++++ drivers/gpu/drm/i915/display/intel_cdclk.h | 8 -------- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 84674a4f7226..56f40d9430b8 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -1219,6 +1219,14 @@ static bool has_cdclk_squasher(struct drm_i915_private *i915) return IS_DG2(i915); } +struct intel_cdclk_vals { + u32 cdclk; + u16 refclk; + u16 waveform; + u8 divider; /* CD2X divider * 2 */ + u8 ratio; +}; + static const struct intel_cdclk_vals bxt_cdclk_table[] = { { .refclk = 19200, .cdclk = 144000, .divider = 8, .ratio = 60 }, { .refclk = 19200, .cdclk = 288000, .divider = 4, .ratio = 60 }, diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h index 77e8c8e1708f..50b93226517e 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.h +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h @@ -16,14 +16,6 @@ struct drm_i915_private; struct intel_atomic_state; struct intel_crtc_state; -struct intel_cdclk_vals { - u32 cdclk; - u16 refclk; - u16 waveform; - u8 divider; /* CD2X divider * 2 */ - u8 ratio; -}; - struct intel_cdclk_state { struct intel_global_state base; From patchwork Thu Dec 9 16:51:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 12667385 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4E022C433FE for ; Thu, 9 Dec 2021 16:59:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 28E2110E1EB; Thu, 9 Dec 2021 16:54:16 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 86C4F89F08 for ; Thu, 9 Dec 2021 16:51:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1639068716; x=1670604716; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hY2mm3uEmRvWsabaP+Ck+2CS6mmBdmhazajyEwTx6Mo=; b=PbjsgSN+NrSqZP7WQJ52y4BRNXki0clTGU5fW9kn5Bd5rfW7MgQeQRx5 Mng1PotcVCflQMpmO2xY/jgmH3EMfnbZgU0apqUoFf761mptuLOcm4Iqz ClYJBNzat91YkZwjpip4Xo0OxPb22EzAURsuLfph/RgnsXDmmlOvOr/C9 VLeHNrbUe6njuoFCuf2NPQubvVky6yjdcvlGlY9aQJrby01Jp31igIeXY epBxJJ5ByDIqp4d/k0z7BIrKxV/XdrukMAAjbzQnVfUp97szEaTW9KAoX uiGjJwNE8JrvaKtvzWr/qych32Uu2NG6H0kUuCDGSDY12nl6evuWeaHJz Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10193"; a="225417987" X-IronPort-AV: E=Sophos;i="5.88,193,1635231600"; d="scan'208";a="225417987" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Dec 2021 08:51:55 -0800 X-IronPort-AV: E=Sophos;i="5.88,193,1635231600"; d="scan'208";a="462206379" Received: from cwilso3-mobl.fi.intel.com (HELO localhost) ([10.252.19.112]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Dec 2021 08:51:51 -0800 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Date: Thu, 9 Dec 2021 18:51:25 +0200 Message-Id: <5f410f0fa5fe469895c1bfbe68aa92511053d5fa.1639068649.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Subject: [Intel-gfx] [PATCH 4/4] drm/i915/cdclk: turn around i915_drv.h and intel_cdclk.h dependency X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" intel_cdclk.h only needs i915_drv.h for struct intel_cdclk_config. Move the definition to intel_cdclk.h and turn the includes around to avoid including i915_drv.h from other headers. Signed-off-by: Jani Nikula Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_atomic.c | 1 + drivers/gpu/drm/i915/display/intel_cdclk.h | 6 +++++- drivers/gpu/drm/i915/i915_drv.h | 6 +----- 3 files changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c index b4e7ac51aa31..ff17bec7a67d 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic.c +++ b/drivers/gpu/drm/i915/display/intel_atomic.c @@ -34,6 +34,7 @@ #include #include +#include "i915_drv.h" #include "intel_atomic.h" #include "intel_cdclk.h" #include "intel_display_types.h" diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h index 50b93226517e..e11db06a81c2 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.h +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h @@ -8,7 +8,6 @@ #include -#include "i915_drv.h" #include "intel_display.h" #include "intel_global_state.h" @@ -16,6 +15,11 @@ struct drm_i915_private; struct intel_atomic_state; struct intel_crtc_state; +struct intel_cdclk_config { + unsigned int cdclk, vco, ref, bypass; + u8 voltage_level; +}; + struct intel_cdclk_state { struct intel_global_state base; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index e36aea6453c2..a198f7e075d9 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -65,6 +65,7 @@ #include "i915_utils.h" #include "display/intel_bios.h" +#include "display/intel_cdclk.h" #include "display/intel_display.h" #include "display/intel_display_power.h" #include "display/intel_dmc.h" @@ -625,11 +626,6 @@ struct i915_virtual_gpu { u32 caps; }; -struct intel_cdclk_config { - unsigned int cdclk, vco, ref, bypass; - u8 voltage_level; -}; - struct i915_selftest_stash { atomic_t counter; struct ida mock_region_instances;