From patchwork Thu Dec 20 19:59:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 10739447 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C4B616C2 for ; Thu, 20 Dec 2018 19:37:42 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B4A6628B24 for ; Thu, 20 Dec 2018 19:37:42 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A8A4C28B56; Thu, 20 Dec 2018 19:37:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B8A3E28B24 for ; Thu, 20 Dec 2018 19:37:41 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 32C056F4EA; Thu, 20 Dec 2018 19:37:41 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 98E8F6F4EB for ; Thu, 20 Dec 2018 19:37:38 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Dec 2018 11:37:38 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,378,1539673200"; d="scan'208";a="103560255" Received: from linuxpresi1-desktop.iind.intel.com ([10.223.25.28]) by orsmga008.jf.intel.com with ESMTP; 20 Dec 2018 11:37:36 -0800 From: Uma Shankar To: intel-gfx@lists.freedesktop.org Date: Fri, 21 Dec 2018 01:29:38 +0530 Message-Id: <1545335981-2338-2-git-send-email-uma.shankar@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1545335981-2338-1-git-send-email-uma.shankar@intel.com> References: <1545335981-2338-1-git-send-email-uma.shankar@intel.com> Subject: [Intel-gfx] [v4 1/4] drm/i915: Remove gamma_mode state variable X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ville.syrjala@intel.com, maarten.lankhorst@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Removed crtc state variable for gamma mode as it's redundant since currently we have fixed modes on respective hardware platforms. This was making this state variable irrelevant. Credits-to: Matt Roper Signed-off-by: Uma Shankar Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/intel_color.c | 5 +---- drivers/gpu/drm/i915/intel_display.c | 3 --- drivers/gpu/drm/i915/intel_drv.h | 3 --- 3 files changed, 1 insertion(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index 37fd9dd..f32e4a7 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -370,12 +370,11 @@ static void haswell_load_luts(struct intel_crtc_state *crtc_state) * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. */ if (IS_HASWELL(dev_priv) && crtc_state->ips_enabled && - (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)) { + (I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_SPLIT)) { hsw_disable_ips(crtc_state); reenable_ips = true; } - crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT; I915_WRITE(GAMMA_MODE(crtc->pipe), GAMMA_MODE_MODE_8BIT); i9xx_load_luts(crtc_state); @@ -476,7 +475,6 @@ static void broadwell_load_luts(struct intel_crtc_state *crtc_state) bdw_load_gamma_lut(crtc_state, INTEL_INFO(dev_priv)->color.degamma_lut_size); - crtc_state->gamma_mode = GAMMA_MODE_MODE_SPLIT; I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_SPLIT); POSTING_READ(GAMMA_MODE(pipe)); @@ -532,7 +530,6 @@ static void glk_load_luts(struct intel_crtc_state *crtc_state) bdw_load_gamma_lut(crtc_state, 0); - crtc_state->gamma_mode = GAMMA_MODE_MODE_10BIT; I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_10BIT); POSTING_READ(GAMMA_MODE(pipe)); } diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 3b70948..704d9d3 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -9679,9 +9679,6 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, intel_get_pipe_src_size(crtc, pipe_config); intel_get_crtc_ycbcr_config(crtc, pipe_config); - pipe_config->gamma_mode = - I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK; - power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { power_domain_mask |= BIT_ULL(power_domain); diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 1028af8..7427a36 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -921,9 +921,6 @@ struct intel_crtc_state { struct intel_crtc_wm_state wm; - /* Gamma mode programmed on the pipe */ - uint32_t gamma_mode; - /* bitmask of visible planes (enum plane_id) */ u8 active_planes; u8 nv12_planes; From patchwork Thu Dec 20 19:59:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 10739449 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9E8216C5 for ; Thu, 20 Dec 2018 19:37:44 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 901A828B24 for ; Thu, 20 Dec 2018 19:37:44 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8408B28B56; Thu, 20 Dec 2018 19:37:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 4BE4B28B24 for ; Thu, 20 Dec 2018 19:37:44 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C8BD46F4EB; Thu, 20 Dec 2018 19:37:43 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 260226F4EB for ; Thu, 20 Dec 2018 19:37:41 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Dec 2018 11:37:40 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,378,1539673200"; d="scan'208";a="103560274" Received: from linuxpresi1-desktop.iind.intel.com ([10.223.25.28]) by orsmga008.jf.intel.com with ESMTP; 20 Dec 2018 11:37:38 -0800 From: Uma Shankar To: intel-gfx@lists.freedesktop.org Date: Fri, 21 Dec 2018 01:29:39 +0530 Message-Id: <1545335981-2338-3-git-send-email-uma.shankar@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1545335981-2338-1-git-send-email-uma.shankar@intel.com> References: <1545335981-2338-1-git-send-email-uma.shankar@intel.com> Subject: [Intel-gfx] [v4 2/4] drm/i915/icl: Add icl pipe degamma and gamma support X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ville.syrjala@intel.com, maarten.lankhorst@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Add support for icl pipe degamma and gamma. v2: Removed a POSTING_READ and corrected the Bit Definition as per Maarten's comments. v3: Addressed Matt's review comments. Removed rmw patterns as suggested by Matt. v4: Fixed Matt's review comments. Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/i915_reg.h | 3 ++ drivers/gpu/drm/i915/intel_color.c | 67 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 70 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 02af9b5..1852c33 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7092,6 +7092,9 @@ enum { #define GAMMA_MODE_MODE_12BIT (2 << 0) #define GAMMA_MODE_MODE_SPLIT (3 << 0) +#define PRE_CSC_GAMMA_ENABLE (1 << 31) +#define POST_CSC_GAMMA_ENABLE (1 << 30) + /* DMC/CSR */ #define CSR_PROGRAM(i) _MMIO(0x80000 + (i) * 4) #define CSR_SSP_BASE_ADDR_GEN9 0x00002FC0 diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index f32e4a7..e72d8d6 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -534,6 +534,71 @@ static void glk_load_luts(struct intel_crtc_state *crtc_state) POSTING_READ(GAMMA_MODE(pipe)); } +static void icl_load_degamma_lut(struct intel_crtc_state *crtc_state) +{ + struct drm_device *dev = crtc_state->base.crtc->dev; + struct drm_i915_private *dev_priv = to_i915(dev); + enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe; + const uint32_t lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size; + uint32_t i; + + /* + * When setting the auto-increment bit, the hardware seems to + * ignore the index bits, so we need to reset it to index 0 + * separately. + */ + I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), 0); + I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), PRE_CSC_GAMC_AUTO_INCREMENT); + + if (crtc_state->base.degamma_lut) { + struct drm_color_lut *lut = crtc_state->base.degamma_lut->data; + + for (i = 0; i < lut_size; i++) { + /* + * First 33 entries represent range from 0 to 1.0 + * 34th and 35th entry will represent extended range + * inputs 3.0 and 7.0 respectively, currently clamped + * at 1.0. Since the precision is 16bit, the user value + * can be directly filled to register. + * ToDo: Extend to max 7.0. + */ + I915_WRITE(PRE_CSC_GAMC_DATA(pipe), lut[i].red); + } + } else { + /* load a linear table. */ + for (i = 0; i < lut_size; i++) { + uint32_t v = (i * (1 << 16)) / (lut_size - 1); + + I915_WRITE(PRE_CSC_GAMC_DATA(pipe), v); + } + } + + /* Clamp values > 1.0. */ + while (i++ < 35) + I915_WRITE(PRE_CSC_GAMC_DATA(pipe), (1 << 16)); +} + +static void icl_load_luts(struct intel_crtc_state *crtc_state) +{ + struct drm_crtc *crtc = crtc_state->base.crtc; + struct drm_device *dev = crtc_state->base.crtc->dev; + struct drm_i915_private *dev_priv = to_i915(dev); + enum pipe pipe = to_intel_crtc(crtc)->pipe; + u32 gamma_mode = 0; + + if (crtc_state_is_legacy_gamma(crtc_state)) { + haswell_load_luts(crtc_state); + return; + } + + icl_load_degamma_lut(crtc_state); + bdw_load_gamma_lut(crtc_state, 0); + + gamma_mode = GAMMA_MODE_MODE_10BIT | PRE_CSC_GAMMA_ENABLE + | POST_CSC_GAMMA_ENABLE; + I915_WRITE(GAMMA_MODE(pipe), gamma_mode); +} + /* Loads the palette/gamma unit for the CRTC on CherryView. */ static void cherryview_load_luts(struct intel_crtc_state *crtc_state) { @@ -649,6 +714,8 @@ void intel_color_init(struct intel_crtc *crtc) } else if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) { dev_priv->display.load_csc_matrix = ilk_load_csc_matrix; dev_priv->display.load_luts = glk_load_luts; + } else if (IS_ICELAKE(dev_priv)) { + dev_priv->display.load_luts = icl_load_luts; } else { dev_priv->display.load_luts = i9xx_load_luts; } From patchwork Thu Dec 20 19:59:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 10739451 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5E6486C5 for ; Thu, 20 Dec 2018 19:37:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4E9DC28B24 for ; Thu, 20 Dec 2018 19:37:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 42E7728B56; Thu, 20 Dec 2018 19:37:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 0524F28B24 for ; Thu, 20 Dec 2018 19:37:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 84DE16F4EC; Thu, 20 Dec 2018 19:37:46 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 995B46F4EB for ; Thu, 20 Dec 2018 19:37:43 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Dec 2018 11:37:43 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,378,1539673200"; d="scan'208";a="103560287" Received: from linuxpresi1-desktop.iind.intel.com ([10.223.25.28]) by orsmga008.jf.intel.com with ESMTP; 20 Dec 2018 11:37:41 -0800 From: Uma Shankar To: intel-gfx@lists.freedesktop.org Date: Fri, 21 Dec 2018 01:29:40 +0530 Message-Id: <1545335981-2338-4-git-send-email-uma.shankar@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1545335981-2338-1-git-send-email-uma.shankar@intel.com> References: <1545335981-2338-1-git-send-email-uma.shankar@intel.com> Subject: [Intel-gfx] [v4 3/4] drm/i915/icl: Enable ICL Pipe CSC block X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ville.syrjala@intel.com, maarten.lankhorst@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Enable ICL pipe csc hardware. CSC block is enabled in CSC_MODE register instead of PLANE_COLOR_CTL. ToDO: Extend the ABI to accept 32 bit coefficient values instead of 16bit for future platforms. v2: Addressed Maarten's review comments. v3: Addressed Matt's review comments. Removed rmw patterns as suggested by Matt. v4: Addressed Matt's review comments. Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/i915_reg.h | 4 +++- drivers/gpu/drm/i915/intel_color.c | 12 ++++++++++-- 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 1852c33..565ef6a 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -9861,7 +9861,9 @@ enum skl_power_gate { #define _PIPE_A_CSC_COEFF_RV_GV 0x49020 #define _PIPE_A_CSC_COEFF_BV 0x49024 #define _PIPE_A_CSC_MODE 0x49028 -#define CSC_BLACK_SCREEN_OFFSET (1 << 2) +#define CSC_ENABLE (1 << 31) +#define OUTPUT_CSC_ENABLE (1 << 30) +#define CSC_BLACK_SCREEN_OFFSET (1 << 2) #define CSC_POSITION_BEFORE_GAMMA (1 << 1) #define CSC_MODE_YUV_TO_RGB (1 << 0) #define _PIPE_A_CSC_PREOFF_HI 0x49030 diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index e72d8d6..d5b240c 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -134,7 +134,11 @@ static void ilk_load_ycbcr_conversion_matrix(struct intel_crtc *crtc) I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), POSTOFF_RGB_TO_YUV_HI); I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), POSTOFF_RGB_TO_YUV_ME); I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), POSTOFF_RGB_TO_YUV_LO); - I915_WRITE(PIPE_CSC_MODE(pipe), 0); + + if (INTEL_GEN(dev_priv) >= 10) + I915_WRITE(PIPE_CSC_MODE(pipe), OUTPUT_CSC_ENABLE); + else + I915_WRITE(PIPE_CSC_MODE(pipe), 0); } static void ilk_load_csc_matrix(struct intel_crtc_state *crtc_state) @@ -242,7 +246,10 @@ static void ilk_load_csc_matrix(struct intel_crtc_state *crtc_state) I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); - I915_WRITE(PIPE_CSC_MODE(pipe), 0); + if (INTEL_GEN(dev_priv) >= 10) + I915_WRITE(PIPE_CSC_MODE(pipe), CSC_ENABLE); + else + I915_WRITE(PIPE_CSC_MODE(pipe), 0); } else { uint32_t mode = CSC_MODE_YUV_TO_RGB; @@ -715,6 +722,7 @@ void intel_color_init(struct intel_crtc *crtc) dev_priv->display.load_csc_matrix = ilk_load_csc_matrix; dev_priv->display.load_luts = glk_load_luts; } else if (IS_ICELAKE(dev_priv)) { + dev_priv->display.load_csc_matrix = ilk_load_csc_matrix; dev_priv->display.load_luts = icl_load_luts; } else { dev_priv->display.load_luts = i9xx_load_luts; From patchwork Thu Dec 20 19:59:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 10739453 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 816306C2 for ; Thu, 20 Dec 2018 19:37:50 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 72AAD28B24 for ; Thu, 20 Dec 2018 19:37:50 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6737C28B56; Thu, 20 Dec 2018 19:37:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 261CE28B24 for ; Thu, 20 Dec 2018 19:37:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9F3726F4EF; Thu, 20 Dec 2018 19:37:49 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id B42A86F4EC for ; Thu, 20 Dec 2018 19:37:45 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Dec 2018 11:37:45 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,378,1539673200"; d="scan'208";a="103560301" Received: from linuxpresi1-desktop.iind.intel.com ([10.223.25.28]) by orsmga008.jf.intel.com with ESMTP; 20 Dec 2018 11:37:43 -0800 From: Uma Shankar To: intel-gfx@lists.freedesktop.org Date: Fri, 21 Dec 2018 01:29:41 +0530 Message-Id: <1545335981-2338-5-git-send-email-uma.shankar@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1545335981-2338-1-git-send-email-uma.shankar@intel.com> References: <1545335981-2338-1-git-send-email-uma.shankar@intel.com> Subject: [Intel-gfx] [v4 4/4] drm/i915/icl: Add degamma and gamma lut size to gen11 caps X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ville.syrjala@intel.com, maarten.lankhorst@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Add the degamma and gamma lut sizes to gen11 capability structure. Note: Currently this doesn't account for the extended range gamma entries and this will be addressed with new segmented gamma ABI in a future patch. v2: Reorder the patch as per Maarten's suggestion. v3: Rebase v4: Updated commit message with a note as per Matt's suggestion. Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/i915_pci.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 6350db5..add5642 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -635,7 +635,8 @@ }, \ GEN(11), \ .ddb_size = 2048, \ - .has_logical_ring_elsq = 1 + .has_logical_ring_elsq = 1, \ + .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024 } static const struct intel_device_info intel_icelake_11_info = { GEN11_FEATURES,