From patchwork Fri Dec 10 17:37:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Flora Fu X-Patchwork-Id: 12670501 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 24862C433EF for ; Fri, 10 Dec 2021 17:49:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=YgJHsyE2OYRW4azBxr6zMKa9rcPTnRD7iOUIZMyLHcI=; b=X4VfIDE9KTp5tr Y/6NjQbQ1TF0xGnn3rJzK13tDJ/Prm2GUjdff1wHdILMA4b5v8e2zx0zxIvdDFNALiNYi7D9DTzD/ gQYZnq0wYLnSReqZqZm7Tj7HkZq9jXeKmVDbhVJ20iZgskNkuWxEI1RymJuqKiDJgnkAFl7oapko3 Z/qualU+K/W0G8SB5exEIGARxHRTTS+JJghRjyD0pE03aH1lZxES8AxpaA9EsOHqUD4KbZf8LHJQE 78vWk/SpGSiEgrpuaB5uPreoWsOkjLhnREHXsPl4JeBm+QKVsjH4Wt/VJFIrJurX5dcmwvevP3rA/ 59N25iV1dnKici7N6sWA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mvk1L-002zVL-UW; Fri, 10 Dec 2021 17:49:23 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mvjzx-002ynp-2O; Fri, 10 Dec 2021 17:47:58 +0000 X-UUID: c2e06fa1b7814103a6d8858d9bf51b2a-20211210 X-UUID: c2e06fa1b7814103a6d8858d9bf51b2a-20211210 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1045587814; Fri, 10 Dec 2021 10:47:54 -0700 Received: from mtkmbs10n1.mediatek.inc (172.21.101.34) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 10 Dec 2021 09:37:52 -0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Sat, 11 Dec 2021 01:37:50 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 11 Dec 2021 01:37:50 +0800 From: Flora Fu To: Matthias Brugger , Pi-Cheng Chen CC: , , , "Flora Fu" , Yong Wu , JB Tsai , Chun-Jie Chen Subject: [PATCH 1/6] dt-bindings: soc: mediatek: apu: Add MT8195 APU power domain Date: Sat, 11 Dec 2021 01:37:38 +0800 Message-ID: <20211210173743.30906-2-flora.fu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20211210173743.30906-1-flora.fu@mediatek.com> References: <20211210173743.30906-1-flora.fu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211210_094757_154333_E344A6BE X-CRM114-Status: UNSURE ( 7.43 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Document the MT8195 APU power domain bindings. Signed-off-by: Flora Fu --- .../devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml index e1b7d4030dc9..66547f899014 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml @@ -21,6 +21,7 @@ properties: items: - enum: - mediatek,mt8192-apu-pm + - mediatek,mt8195-apu-pm - const: syscon reg: From patchwork Fri Dec 10 17:37:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Flora Fu X-Patchwork-Id: 12670489 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B8013C433EF for ; Fri, 10 Dec 2021 17:41:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=pWQQ7AXZIPo3JRRBt4pbdQ5J793Wj/Lfr74RjOS8LAQ=; b=kbKd8wmr16+C+M Rv5PS3lTu/Oxm3rj1yBgOwKRIppQefn4pYr+heZwEQ5LvlHCQ5gb8mB9bZVY+1Dv02nehfvwrtO1T lw4+kUyX9hZUS07Wq3z4eBUFXASJodiTi8ggMcAJNKHUWXV21h2kEDvKShk7fV8MOyDmql+xw4UAA r18wv0cNwnkBmvx8EOld1BunyuGZuWBxEy8R50HQYqoiGXfryxXLJyoa1yUCjDsLEhBH03wTltdtQ aBmSMmqb8zff44uSoUUdCBrt8p7nOQ+3zDxrj7CM5THep9xbwHdJ2IDZet2akF5/ACVJX5PoIGtfb SlVWtk16HfDprk29nVKQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mvjtl-002vzZ-W9; Fri, 10 Dec 2021 17:41:34 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mvjqG-002u1h-0i; Fri, 10 Dec 2021 17:37:57 +0000 X-UUID: efbf31b335a94b3fb4de10a7e537a489-20211210 X-UUID: efbf31b335a94b3fb4de10a7e537a489-20211210 Received: from mtkcas67.mediatek.inc [(172.29.193.45)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 531516604; Fri, 10 Dec 2021 10:37:55 -0700 Received: from mtkmbs10n2.mediatek.inc (172.21.101.183) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 10 Dec 2021 09:37:53 -0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Sat, 11 Dec 2021 01:37:51 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 11 Dec 2021 01:37:51 +0800 From: Flora Fu To: Matthias Brugger , Pi-Cheng Chen CC: , , , "Flora Fu" , Yong Wu , JB Tsai , Chun-Jie Chen Subject: [PATCH 2/6] dt-bindings: arm: mediatek: Add MT8195 APU bindings Date: Sat, 11 Dec 2021 01:37:39 +0800 Message-ID: <20211210173743.30906-3-flora.fu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20211210173743.30906-1-flora.fu@mediatek.com> References: <20211210173743.30906-1-flora.fu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211210_093756_114359_B4256061 X-CRM114-Status: UNSURE ( 8.53 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Document the MT8195 APU bindings. Signed-off-by: Flora Fu --- .../devicetree/bindings/arm/mediatek/mediatek,apusys.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apusys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apusys.yaml index 7643c66dfaa2..fe96618ecb71 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apusys.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apusys.yaml @@ -20,6 +20,9 @@ properties: - enum: - mediatek,mt8192-apu-conn - mediatek,mt8192-apu-vcore + - mediatek,mt8195-apu-conn + - mediatek,mt8195-apu-conn1 + - mediatek,mt8195-apu-vcore - const: syscon reg: From patchwork Fri Dec 10 17:37:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Flora Fu X-Patchwork-Id: 12670495 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BE155C433F5 for ; Fri, 10 Dec 2021 17:42:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=785E0lpycolvZDJ8v3xbt0kPQlYhmJJZX7s4o27Lkqk=; b=ws3IyRM44kA8JD fItIwFnvdcEBZW1eanJuY0bAkG32qFVVGe37r/sEdWM+LFCGj7hPOZYPSYMN2GxfBTpqhpvxb2IYw ZoBkU9pef6KFB/rZPcH8TgZvbE4b4XwVA/F+oDwGb3Gyy8cRqhi9rBPxQUh/ECOcWy4r7Yuq9Eg9U oEjynByQepd0CqIo6yMmfkA61ZQ0lrfvJeYObXg2ZIBoEB6zrMhLMA5I61dvfxQSztAh3gVk20DL6 xf+1Jbep3eRymLfZf1hWydg66ahU6tju7H9GnL+KDpQZzz0sLV0Kr3cEAcoWJwPAZDB2PzHR/CzHJ p8/BeTxLmlXK0aj2v7nQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mvjuX-002wPC-ST; Fri, 10 Dec 2021 17:42:21 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mvjqP-002u88-V8; Fri, 10 Dec 2021 17:38:07 +0000 X-UUID: 4c4f88d5b99b4779b18fdfe4c3aec61d-20211210 X-UUID: 4c4f88d5b99b4779b18fdfe4c3aec61d-20211210 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 34917563; Fri, 10 Dec 2021 10:38:01 -0700 Received: from mtkexhb01.mediatek.inc (172.21.101.102) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 10 Dec 2021 09:37:59 -0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkexhb01.mediatek.inc (172.21.101.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 11 Dec 2021 01:37:52 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 11 Dec 2021 01:37:52 +0800 From: Flora Fu To: Matthias Brugger , Pi-Cheng Chen CC: , , , "Flora Fu" , Yong Wu , JB Tsai , Chun-Jie Chen Subject: [PATCH 3/6] soc: mediatek: apu: Add MT8195 apu power domain Date: Sat, 11 Dec 2021 01:37:40 +0800 Message-ID: <20211210173743.30906-4-flora.fu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20211210173743.30906-1-flora.fu@mediatek.com> References: <20211210173743.30906-1-flora.fu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211210_093806_077600_56AB484B X-CRM114-Status: GOOD ( 15.51 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Add MT8195 apu power domain settings. The clock and pll controller shall be accessed through SMC call and the power domain shall be enable before access MT8195 APU. Signed-off-by: Flora Fu --- drivers/soc/mediatek/apusys/mtk-apu-pm.c | 124 +++++++++++++++++++++++ 1 file changed, 124 insertions(+) diff --git a/drivers/soc/mediatek/apusys/mtk-apu-pm.c b/drivers/soc/mediatek/apusys/mtk-apu-pm.c index 10dd30052c46..7be5acb75d78 100644 --- a/drivers/soc/mediatek/apusys/mtk-apu-pm.c +++ b/drivers/soc/mediatek/apusys/mtk-apu-pm.c @@ -3,6 +3,7 @@ * Copyright (c) 2021 MediaTek Inc. */ +#include #include #include #include @@ -18,9 +19,12 @@ #include #include #include +#include #define APU_PD_IPUIF_HW_CG BIT(0) #define APU_PD_RPC_AUTO_BUCK BIT(1) +#define APU_PD_ACC BIT(2) +#define APU_PD_SEC_PWR BIT(3) #define APU_PD_CAPS(_pd, _x) ((_pd)->data->caps & (_x)) #define MTK_POLL_DELAY_US 10 @@ -44,6 +48,11 @@ static const struct reg_sequence mt8192_rpc_sw_type[] = { { MT8192_RPC_SW_TYPE(6), 0x3 }, }; +#define MTK_SIP_APUPWR_BUS_PROT_CG_ON 0x02U +#define MTK_SIP_APUPWR_BULK_PLL 0x03U +#define MTK_SIP_APUPWR_ACC_INIT_ALL 0x04U +#define MTK_SIP_APUPWR_ACC_TOP 0x05U + struct apu_top_domain { u32 spm_ext_buck_iso; u32 spm_ext_buck_iso_mask; @@ -81,6 +90,23 @@ static struct apu_top_domain mt8192_top_reg = { .num_rpc_sw = ARRAY_SIZE(mt8192_rpc_sw_type), }; +static struct apu_top_domain mt8195_top_reg = { + .spm_ext_buck_iso = 0x3EC, + .spm_ext_buck_iso_mask = 0x21, + .spm_cross_wake_m01 = 0x670, + .wake_apu = BIT(0), + .spm_other_pwr = 0x198, + .pwr_status = BIT(4), + .conn_clr = 0x8, + .conn1_clr = 0x8, + .vcore_clr = 0x8, + .rpc_top_con = 0x0, + .rpc_top_con_init_mask = 0x9E, + .rpc_top_sel = 0x4, + .rpc_top_intf_pwr_rdy = 0x44, + .pwr_rdy = BIT(0), +}; + struct apusys { struct device *dev; struct regmap *scpsys; @@ -125,6 +151,7 @@ static int apu_top_init_hw(struct apu_domain *pd) { struct apusys *apusys = pd->apusys; int ret; + struct arm_smccc_res res; if (APU_PD_CAPS(pd, APU_PD_IPUIF_HW_CG)) { ret = clk_prepare_enable(pd->clk_top_conn); @@ -148,6 +175,15 @@ static int apu_top_init_hw(struct apu_domain *pd) } } } else { + if (APU_PD_CAPS(pd, APU_PD_SEC_PWR)) { + arm_smccc_smc(MTK_SIP_APUSYS_CONTROL, MTK_SIP_APUPWR_BULK_PLL, + 1, 0, 0, 0, 0, 0, &res); + ret = res.a0; + if (ret) { + dev_err(apusys->dev, "apu pll smc fail: %lu\n", res.a0); + goto err_clk; + } + } ret = clk_bulk_prepare_enable(pd->num_clks, pd->clks); if (ret) goto err_clk; @@ -181,6 +217,18 @@ static int apu_top_init_hw(struct apu_domain *pd) goto err_clk; } + if (APU_PD_CAPS(pd, APU_PD_SEC_PWR)) { + if (APU_PD_CAPS(pd, APU_PD_ACC)) { + arm_smccc_smc(MTK_SIP_APUSYS_CONTROL, MTK_SIP_APUPWR_ACC_INIT_ALL, + 0, 0, 0, 0, 0, 0, &res); + ret = res.a0; + if (ret) { + dev_err(apusys->dev, "apu acc init all fail: %lu\n", res.a0); + goto err_clk; + } + } + } + if (APU_PD_CAPS(pd, APU_PD_IPUIF_HW_CG)) { clk_disable_unprepare(pd->clk_top_conn); ret = clk_set_parent(pd->clk_top_ipu_if, pd->clk_off); @@ -189,6 +237,9 @@ static int apu_top_init_hw(struct apu_domain *pd) goto err_clk; } } else { + if (APU_PD_CAPS(pd, APU_PD_SEC_PWR)) + arm_smccc_smc(MTK_SIP_APUSYS_CONTROL, MTK_SIP_APUPWR_BULK_PLL, + 0, 0, 0, 0, 0, 0, &res); clk_bulk_disable_unprepare(pd->num_clks, pd->clks); } @@ -199,6 +250,9 @@ static int apu_top_init_hw(struct apu_domain *pd) clk_disable_unprepare(pd->clk_top_conn); clk_disable_unprepare(pd->clk_top_ipu_if); } else { + if (APU_PD_CAPS(pd, APU_PD_SEC_PWR)) + arm_smccc_smc(MTK_SIP_APUSYS_CONTROL, MTK_SIP_APUPWR_BULK_PLL, + 0, 0, 0, 0, 0, 0, &res); clk_bulk_disable_unprepare(pd->num_clks, pd->clks); } @@ -214,16 +268,31 @@ static const struct apu_domain_data apu_domain_data_mt8192[] = { } }; +static const struct apu_domain_data apu_domain_data_mt8195[] = { + { + .domain_idx = 0, + .name = "apu-top", + .caps = APU_PD_RPC_AUTO_BUCK | APU_PD_ACC | APU_PD_SEC_PWR, + .topd = &mt8195_top_reg, + } +}; + static const struct apu_pm_data mt8192_apu_pm_data = { .domains_data = apu_domain_data_mt8192, .num_domains = ARRAY_SIZE(apu_domain_data_mt8192), }; +static const struct apu_pm_data mt8195_apu_pm_data = { + .domains_data = apu_domain_data_mt8195, + .num_domains = ARRAY_SIZE(apu_domain_data_mt8195), +}; + static int apu_top_power_on(struct generic_pm_domain *genpd) { struct apu_domain *pd = to_apu_domain(genpd); struct apusys *apusys = pd->apusys; int ret, tmp; + struct arm_smccc_res res; if (apusys->vsram_supply) { ret = regulator_enable(apusys->vsram_supply); @@ -269,6 +338,25 @@ static int apu_top_power_on(struct generic_pm_domain *genpd) } } } else { + if (APU_PD_CAPS(pd, APU_PD_SEC_PWR)) { + arm_smccc_smc(MTK_SIP_APUSYS_CONTROL, MTK_SIP_APUPWR_BULK_PLL, + 1, 0, 0, 0, 0, 0, &res); + ret = res.a0; + if (ret) { + dev_err(apusys->dev, "apu pll smc fail: %lu\n", res.a0); + goto err_clk; + } + + if (APU_PD_CAPS(pd, APU_PD_ACC)) { + arm_smccc_smc(MTK_SIP_APUSYS_CONTROL, MTK_SIP_APUPWR_ACC_TOP, + 1, 0, 0, 0, 0, 0, &res); + ret = res.a0; + if (ret) { + dev_err(apusys->dev, "apu acc top smc fail: %lu\n", res.a0); + goto err_clk; + } + } + } ret = clk_bulk_prepare_enable(pd->num_clks, pd->clks); if (ret) goto err_clk; @@ -301,6 +389,15 @@ static int apu_top_power_on(struct generic_pm_domain *genpd) goto err_clk; } + if (APU_PD_CAPS(pd, APU_PD_SEC_PWR)) { + arm_smccc_smc(MTK_SIP_APUSYS_CONTROL, MTK_SIP_APUPWR_BUS_PROT_CG_ON, + 0, 0, 0, 0, 0, 0, &res); + if (res.a0) { + dev_err(apusys->dev, "apu bus_prot smc fail: %lu\n", res.a0); + goto err_clk; + } + } + if (apusys->vcore) { ret = regmap_write(apusys->vcore, pd->data->topd->vcore_clr, CG_CLR); @@ -329,6 +426,9 @@ static int apu_top_power_on(struct generic_pm_domain *genpd) clk_disable_unprepare(pd->clk_top_conn); clk_disable_unprepare(pd->clk_top_ipu_if); } else { + if (APU_PD_CAPS(pd, APU_PD_SEC_PWR)) + arm_smccc_smc(MTK_SIP_APUSYS_CONTROL, MTK_SIP_APUPWR_BULK_PLL, + 0, 0, 0, 0, 0, 0, &res); clk_bulk_disable_unprepare(pd->num_clks, pd->clks); } if (pd->domain_supply) @@ -345,6 +445,7 @@ static int apu_top_power_off(struct generic_pm_domain *genpd) struct apu_domain *pd = to_apu_domain(genpd); struct apusys *apusys = pd->apusys; int ret, tmp; + struct arm_smccc_res res; if (apusys->vcore) { ret = regmap_write(apusys->vcore, @@ -405,6 +506,25 @@ static int apu_top_power_off(struct generic_pm_domain *genpd) return ret; } } else { + if (APU_PD_CAPS(pd, APU_PD_SEC_PWR)) { + if (APU_PD_CAPS(pd, APU_PD_ACC)) { + arm_smccc_smc(MTK_SIP_APUSYS_CONTROL, MTK_SIP_APUPWR_ACC_TOP, + 0, 0, 0, 0, 0, 0, &res); + ret = res.a0; + if (ret) { + dev_err(apusys->dev, "apu acc top smc fail: %lu\n", res.a0); + return ret; + } + } + + arm_smccc_smc(MTK_SIP_APUSYS_CONTROL, MTK_SIP_APUPWR_BULK_PLL, + 0, 0, 0, 0, 0, 0, &res); + ret = res.a0; + if (ret) { + dev_err(apusys->dev, "apu pll smc fail: %lu\n", res.a0); + return ret; + } + } clk_bulk_disable_unprepare(pd->num_clks, pd->clks); } @@ -610,6 +730,10 @@ static const struct of_device_id apu_pm_of_match[] = { .compatible = "mediatek,mt8192-apu-pm", .data = &mt8192_apu_pm_data, }, + { + .compatible = "mediatek,mt8195-apu-pm", + .data = &mt8195_apu_pm_data, + }, { } }; From patchwork Fri Dec 10 17:37:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Flora Fu X-Patchwork-Id: 12670493 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 003A1C433EF for ; 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Sat, 11 Dec 2021 01:37:54 +0800 From: Flora Fu To: Matthias Brugger , Pi-Cheng Chen CC: , , , "Flora Fu" , Yong Wu , JB Tsai , Chun-Jie Chen Subject: [PATCH 4/6] arm64: dts: mt8195: Add APU nodes Date: Sat, 11 Dec 2021 01:37:41 +0800 Message-ID: <20211210173743.30906-5-flora.fu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20211210173743.30906-1-flora.fu@mediatek.com> References: <20211210173743.30906-1-flora.fu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211210_093805_118064_C56FE174 X-CRM114-Status: UNSURE ( 8.21 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Add APU nodes to MT8195. Signed-off-by: Flora Fu --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 4980b8329b54..828ac8a6b95f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1360,6 +1360,21 @@ #clock-cells = <1>; }; + apu_conn: syscon@19020000 { + compatible = "mediatek,mt8195-apu-conn", "syscon"; + reg = <0 0x19020000 0 0x1000>; + }; + + apu_conn1: syscon@19024000 { + compatible = "mediatek,mt8195-apu-conn1", "syscon"; + reg = <0 0x19024000 0 0x1000>; + }; + + apu_vcore: syscon@19029000 { + compatible = "mediatek,mt8195-apu-vcore", "syscon"; + reg = <0 0x19029000 0 0x1000>; + }; + apusys_pll: clock-controller@190f3000 { compatible = "mediatek,mt8195-apusys_pll"; reg = <0 0x190f3000 0 0x1000>; From patchwork Fri Dec 10 17:37:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Flora Fu X-Patchwork-Id: 12670497 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2A32AC433EF for ; Fri, 10 Dec 2021 17:48:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=1KJMjWDOehSYZ77wIlFgOhsPrkQ0co+OsUq0XZBnSGM=; b=F7yP+qHmSye1B/ mWIbAEmK6GSky3CqGbQaFFMe2MiMh+WNTP0WVTd40FMUjSGKtexvlRNMM5XkqBy72iRJeN7XSkOEh ap6niRh35W/ws5NX4z28OOag5KYzgpXatvKSb6CPIl+NffwrnYz3oIF8JVr3COTxY/tx1J9eGkOj1 L91AvfkNy37uNZ/7mUyTPAJzLeMeLl/HGhdcP69C5P3BlL3/CLrR2hF7vKBNuIMeqpr3Rq5uPH8UF LDbsUo6BoFzQoaXAdXp0UpQvr5UjK8a4SZNGCYfsvRcWbF1QfZaUGVRBemnkXN3nAU1kxQatt07Eh SPcifSTbXNcKKT6wNV0w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mvk05-002ys4-7W; Fri, 10 Dec 2021 17:48:05 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mvjzw-002yn1-7T; Fri, 10 Dec 2021 17:47:57 +0000 X-UUID: 78fcdcf2a35f4e3f9b994fc3b46e5880-20211210 X-UUID: 78fcdcf2a35f4e3f9b994fc3b46e5880-20211210 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 864391434; Fri, 10 Dec 2021 10:47:54 -0700 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 10 Dec 2021 09:37:57 -0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 11 Dec 2021 01:37:55 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 11 Dec 2021 01:37:55 +0800 From: Flora Fu To: Matthias Brugger , Pi-Cheng Chen CC: , , , "Flora Fu" , Yong Wu , JB Tsai , Chun-Jie Chen Subject: [PATCH 5/6] arm64: dts: mt8195: Add APU power domain node Date: Sat, 11 Dec 2021 01:37:42 +0800 Message-ID: <20211210173743.30906-6-flora.fu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20211210173743.30906-1-flora.fu@mediatek.com> References: <20211210173743.30906-1-flora.fu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211210_094756_313409_5D6FD914 X-CRM114-Status: UNSURE ( 8.05 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Add APU power domain node to MT8195. Signed-off-by: Flora Fu --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 828ac8a6b95f..6e60c4a38495 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1375,6 +1375,22 @@ reg = <0 0x19029000 0 0x1000>; }; + apuspm: power-domain@190f0000 { + compatible = "mediatek,mt8195-apu-pm", "syscon"; + reg = <0 0x190f0000 0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + mediatek,scpsys = <&scpsys>; + mediatek,apu-conn = <&apu_conn>; + mediatek,apu-conn1 = <&apu_conn1>; + mediatek,apu-vcore = <&apu_vcore>; + apu_top: power-domain@0 { + reg = <0>; + #power-domain-cells = <0>; + }; + }; + apusys_pll: clock-controller@190f3000 { compatible = "mediatek,mt8195-apusys_pll"; reg = <0 0x190f3000 0 0x1000>; From patchwork Fri Dec 10 17:37:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Flora Fu X-Patchwork-Id: 12670503 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C25D1C433F5 for ; Fri, 10 Dec 2021 17:49:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=SNWwyW0sP8Pp0HslIR3D60QqYRpuGZOYAfl7r2mieCU=; b=e4ZJIXmJZveket QE/m8H6KMeBkgyLRqDeV0bJO3Rd/j7BS7taxt9k5bo5nQrWHah0g+b+PC6MpR+r8ZNyWO1vcbdnqz RKzY2fAO8zhf/R2wmfLHwidvnDIPVSqbbk/nnZaxcHVCUg1wMic7lO+wsvh79/twXjTBIOuRbUva3 K/zT/MzY4+8bA+IyU34wMtlqW8qXaUL0OlJFUBxg1b3ZuH3BMmUFWjO215lQ1E+ooxHLkXKopgLk7 CT89CtzIHEuCnWW3DenZdNVScDBtUaK5q4Z7habkdbqqkI3yNuW6srsO0X+cuQ3/GeGIUrtVXQCnT rAm/jFyRQKSoOn4r5/MQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mvk1Q-002zXa-0N; Fri, 10 Dec 2021 17:49:28 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mvjzx-002yn1-Nj; Fri, 10 Dec 2021 17:47:59 +0000 X-UUID: 189469feef5746f4b114ffed01cce2e1-20211210 X-UUID: 189469feef5746f4b114ffed01cce2e1-20211210 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1361906606; Fri, 10 Dec 2021 10:47:54 -0700 Received: from MTKMBS07N2.mediatek.inc (172.21.101.141) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 10 Dec 2021 09:37:58 -0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 11 Dec 2021 01:37:56 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 11 Dec 2021 01:37:56 +0800 From: Flora Fu To: Matthias Brugger , Pi-Cheng Chen CC: , , , "Flora Fu" , Yong Wu , JB Tsai , Chun-Jie Chen Subject: [PATCH 6/6] arm64: dts: mt8195: Set up apu power domain regulators Date: Sat, 11 Dec 2021 01:37:43 +0800 Message-ID: <20211210173743.30906-7-flora.fu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20211210173743.30906-1-flora.fu@mediatek.com> References: <20211210173743.30906-1-flora.fu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211210_094757_827149_30CA952B X-CRM114-Status: UNSURE ( 8.78 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Set up apu power domain related regulators. Signed-off-by: Flora Fu --- arch/arm64/boot/dts/mediatek/mt8195-evb.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts index c9f23742cb6f..6333cab7929f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts @@ -5,6 +5,7 @@ */ /dts-v1/; #include "mt8195.dtsi" +#include "mt6359.dtsi" / { model = "MediaTek MT8195 evaluation board"; @@ -36,6 +37,13 @@ status = "okay"; }; +&apuspm { + vsram-supply = <&mt6359_vsram_md_ldo_reg>; + apu_top: power-domain@0 { + domain-supply = <&mt6359_vproc1_buck_reg>; + }; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pin>;