From patchwork Mon Dec 13 19:02:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 12674573 X-Patchwork-Delegate: robh@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 587DDC4332F for ; Mon, 13 Dec 2021 20:00:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242745AbhLMUAQ (ORCPT ); Mon, 13 Dec 2021 15:00:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33974 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242723AbhLMUAN (ORCPT ); Mon, 13 Dec 2021 15:00:13 -0500 Received: from mail-pj1-x1031.google.com (mail-pj1-x1031.google.com [IPv6:2607:f8b0:4864:20::1031]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5E1A0C061751; Mon, 13 Dec 2021 12:00:13 -0800 (PST) Received: by mail-pj1-x1031.google.com with SMTP id gx15-20020a17090b124f00b001a695f3734aso14297883pjb.0; Mon, 13 Dec 2021 12:00:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AmoK+hw/VDuDSmUiZvkIrRjThwbV3KHs/0+W71eQGM4=; b=BfGQkA2MEDqbzbk0LyDZf6AqU+nW9QooJK1Vn/fWMRPRf0z+lSF2Zj/7K1YvIl3Rs2 IfL5YzBsa/XsKEdtLaZhl/MPj1RJ1yIUwnfXm96wBPhYNan4XSrMVbrPuI9um6wwl7r0 MV6lQr0nFa5WVhkAxZgzTAp6nOe7/4eN+UVOrI1Jh9HDpXPKhH7Tt2axtp2UI6LS/LQC UaXefzUApgvO7IOeUleAgq+0OKoHHelQeG+dnHnEIw0SvcuTDWOp8bikUlQCaz+4BbTs sv/7AjjBU7GYhE6ak8xz5OsIDkh0MQEWxlVIf7tQSF94Putdeb5NNwODdZjxTN+XYLiA duyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AmoK+hw/VDuDSmUiZvkIrRjThwbV3KHs/0+W71eQGM4=; b=3fDrNXNaI+bkhhPhEM+OP9m64nRv/KfaafoZ08XusdsMLbgRV1VBYEWIhLQOhhzqMy +szCqxzp7AWKuTQNxBSaCl5UE6tpmC/ZuUOTHwBk2vTPW7liLZLvceaWG1DWYcqLb6C6 FJ/bKN8nARIlMoGYEpub/LoiFtX0hYmog7chcJidsdsoKEmth+7wv1BI0vDqANmbK41z Af/jOnKtRACxAJ8ooPGTpBZpWVh/wVAIG/0qwCYDgZ7yS2mFzEfoguMyH4OQVZ+xDKUN hNrFOD23V9PFHBZ4w3bzAHpoNoc5JaaYRghHQ0dSClBMyKsq6rLBUEvVZ4eJ1RaPc8l5 h/sQ== X-Gm-Message-State: AOAM5334tqH54b7AfeiYfNlBPieRtpDX33Blukvop/CD94nQ/ZiWCIUm ClKBA+8Ucy7yVxcidCNIZLmdd9fBx58= X-Google-Smtp-Source: ABdhPJxZFbLjSS9SsXbrP9keog8Ej1sYIgPTr25p84FbEJ3zKlMVAz9SF25WhAf316o+myt8MeL5/Q== X-Received: by 2002:a17:90b:4d08:: with SMTP id mw8mr468152pjb.236.1639425612527; Mon, 13 Dec 2021 12:00:12 -0800 (PST) Received: from fainelli-desktop.igp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id z14sm13926195pfh.60.2021.12.13.12.00.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Dec 2021 12:00:12 -0800 (PST) From: Florian Fainelli To: devicetree@vger.kernel.org Cc: Florian Fainelli , Bjorn Helgaas , Rob Herring , Ray Jui , Scott Branden , bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM IPROC ARM ARCHITECTURE), linux-pci@vger.kernel.org (open list:PCI SUBSYSTEM), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM IPROC ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 1/6] ARM: dts: Cygnus: Fixed iProc PCIe controller properties Date: Mon, 13 Dec 2021 11:02:16 -0800 Message-Id: <20211213190221.355678-2-f.fainelli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211213190221.355678-1-f.fainelli@gmail.com> References: <20211213190221.355678-1-f.fainelli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Rename the msi controller unit name to 'msi' to avoid collisions with the 'msi-controller' boolean property. We also need to re-arrange the 'ranges' property to show the two cells as being separate instead of combined since the DT checker is not able to differentiate otherwise. Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-cygnus.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index 8ecb7861ce10..e73a19409d71 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -274,8 +274,8 @@ pcie0: pcie@18012000 { #address-cells = <3>; #size-cells = <2>; device_type = "pci"; - ranges = <0x81000000 0 0 0x28000000 0 0x00010000 - 0x82000000 0 0x20000000 0x20000000 0 0x04000000>; + ranges = <0x81000000 0 0 0x28000000 0 0x00010000>, + <0x82000000 0 0x20000000 0x20000000 0 0x04000000>; phys = <&pcie0_phy>; phy-names = "pcie-phy"; @@ -283,7 +283,7 @@ pcie0: pcie@18012000 { status = "disabled"; msi-parent = <&msi0>; - msi0: msi-controller { + msi0: msi { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>; @@ -309,8 +309,8 @@ pcie1: pcie@18013000 { #address-cells = <3>; #size-cells = <2>; device_type = "pci"; - ranges = <0x81000000 0 0 0x48000000 0 0x00010000 - 0x82000000 0 0x40000000 0x40000000 0 0x04000000>; + ranges = <0x81000000 0 0 0x48000000 0 0x00010000>, + <0x82000000 0 0x40000000 0x40000000 0 0x04000000>; phys = <&pcie1_phy>; phy-names = "pcie-phy"; @@ -318,7 +318,7 @@ pcie1: pcie@18013000 { status = "disabled"; msi-parent = <&msi1>; - msi1: msi-controller { + msi1: msi { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>; From patchwork Mon Dec 13 19:02:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 12674575 X-Patchwork-Delegate: robh@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 698BDC433F5 for ; Mon, 13 Dec 2021 20:00:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242718AbhLMUAR (ORCPT ); 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Mon, 13 Dec 2021 12:00:13 -0800 (PST) From: Florian Fainelli To: devicetree@vger.kernel.org Cc: Florian Fainelli , Bjorn Helgaas , Rob Herring , Ray Jui , Scott Branden , bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM IPROC ARM ARCHITECTURE), linux-pci@vger.kernel.org (open list:PCI SUBSYSTEM), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM IPROC ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 2/6] ARM: dts: Cygnus: Update PCIe PHY node unit name(s) Date: Mon, 13 Dec 2021 11:02:17 -0800 Message-Id: <20211213190221.355678-3-f.fainelli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211213190221.355678-1-f.fainelli@gmail.com> References: <20211213190221.355678-1-f.fainelli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Update the PCIe PHY node unit name and its sub-nodes to help with upcoming changes converting the Cygnus PCIe PHY DT binding to YAML and later the iProc PCIe controller binding to YAML. Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-cygnus.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index e73a19409d71..ad65be871938 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -112,18 +112,18 @@ otp: otp@301c800 { status = "disabled"; }; - pcie_phy: phy@301d0a0 { + pcie_phy: pcie_phy@301d0a0 { compatible = "brcm,cygnus-pcie-phy"; reg = <0x0301d0a0 0x14>; #address-cells = <1>; #size-cells = <0>; - pcie0_phy: phy@0 { + pcie0_phy: pcie-phy@0 { reg = <0>; #phy-cells = <0>; }; - pcie1_phy: phy@1 { + pcie1_phy: pcie-phy@1 { reg = <1>; #phy-cells = <0>; }; From patchwork Mon Dec 13 19:02:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 12674577 X-Patchwork-Delegate: robh@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5933C43219 for ; Mon, 13 Dec 2021 20:00:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242746AbhLMUAS (ORCPT ); Mon, 13 Dec 2021 15:00:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33996 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241818AbhLMUAQ (ORCPT ); Mon, 13 Dec 2021 15:00:16 -0500 Received: from mail-pg1-x52c.google.com (mail-pg1-x52c.google.com [IPv6:2607:f8b0:4864:20::52c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 79531C061574; Mon, 13 Dec 2021 12:00:16 -0800 (PST) Received: by mail-pg1-x52c.google.com with SMTP id j11so15505886pgs.2; Mon, 13 Dec 2021 12:00:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1v15Gl8TJzLJfCjgx7PA4whHDDqL64AFLHw1EUfuQI4=; b=iixQARDtSk/hnynCb+nf6H3vH1Cm6Kj9xlCVLmsA9ylU2hbta+X4HnexkqZW715J7y PElmkZlHwrbsoo5f/cPVVe5gXVueC9oHtwbDLASUIeqPIxlYWsO3tNCrBQWSCcYzY0hw WR6L94TfIgDmk4kW8Nf1jBfuZlq/tr9KE4n/SDW/UGAlBDKqBWjSrPJHPQkOVr/uD4wY lygaWXEMWLHWV5y8uEUR4kbaa3USDon9B/3SxBAyy9cOnovhiOQQrK4OUiFeYAcNWlTE j9jCpLn3UdYWPtm2lNXZpMTHW8tJXKfah5mO6kyVRKtKpoUJ7triVX1YLUW7INIXN3K0 +h1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1v15Gl8TJzLJfCjgx7PA4whHDDqL64AFLHw1EUfuQI4=; b=kYXXMjKWxQNRPcejlWo9FyWF3Iu5TP0Fk4HbpdLRcW+ginYw7a1+JcyqirarKkjiib beHhXznufznjkqMRc2+bfYVODpT5qtDf1LnIBBXw4Vo9Q8YKRMQUzBSAAF2QPcHVJhx6 fl/uqgBhM/HqJBH8C+BJWflQIgiNs5JqUHJ8q72AhBEUuFf2Obe52Zvhqtu4ejcvXn0Q 6nTINDdQjKf+4FCC2BtDjfvFsjC1Q0Vw+PGOdhbiKI3xrKiylZ8TZwml1oaIi4znMQJ2 74t5EjISKqIIW9QQr7UMlkUlKUx2h8ghSQgNfaPO/ywh6c9pPF73HSMlDhCaIeWUR/Ok 70yg== X-Gm-Message-State: AOAM530zbl7Ee6yTzRtKCvpFs4wu1+r9o+rNclzIesGP15Uf0MdldPzb rrmhEMZBeGUFtp2KPoAa8Sq/V3IlO30= X-Google-Smtp-Source: ABdhPJyqRiE3BaxYOaCz2My/zK2+vPXbsf9TRVJhhqR+wuXQFyWdDbqLlc0jY7X+39ePnYL2ReIjKQ== X-Received: by 2002:a63:6ecb:: with SMTP id j194mr562403pgc.46.1639425615626; Mon, 13 Dec 2021 12:00:15 -0800 (PST) Received: from fainelli-desktop.igp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id z14sm13926195pfh.60.2021.12.13.12.00.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Dec 2021 12:00:15 -0800 (PST) From: Florian Fainelli To: devicetree@vger.kernel.org Cc: Florian Fainelli , Bjorn Helgaas , Rob Herring , Ray Jui , Scott Branden , bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM IPROC ARM ARCHITECTURE), linux-pci@vger.kernel.org (open list:PCI SUBSYSTEM), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM IPROC ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 3/6] ARM: dts: HR2: Fixed iProc PCIe MSI sub-node Date: Mon, 13 Dec 2021 11:02:18 -0800 Message-Id: <20211213190221.355678-4-f.fainelli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211213190221.355678-1-f.fainelli@gmail.com> References: <20211213190221.355678-1-f.fainelli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Rename the msi controller unit name to 'msi' to avoid collisions with the 'msi-controller' boolean property. Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-hr2.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/bcm-hr2.dtsi b/arch/arm/boot/dts/bcm-hr2.dtsi index 84cda16f68a2..33e6ba63a1ee 100644 --- a/arch/arm/boot/dts/bcm-hr2.dtsi +++ b/arch/arm/boot/dts/bcm-hr2.dtsi @@ -318,7 +318,7 @@ pcie0: pcie@18012000 { status = "disabled"; msi-parent = <&msi0>; - msi0: msi-controller { + msi0: msi { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>; @@ -354,7 +354,7 @@ pcie1: pcie@18013000 { status = "disabled"; msi-parent = <&msi1>; - msi1: msi-controller { + msi1: msi { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>; From patchwork Mon Dec 13 19:02:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 12674579 X-Patchwork-Delegate: robh@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AEE19C4332F for ; Mon, 13 Dec 2021 20:00:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242723AbhLMUAU (ORCPT ); Mon, 13 Dec 2021 15:00:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34006 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242685AbhLMUAS (ORCPT ); Mon, 13 Dec 2021 15:00:18 -0500 Received: from mail-pg1-x52a.google.com (mail-pg1-x52a.google.com [IPv6:2607:f8b0:4864:20::52a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0830BC061574; Mon, 13 Dec 2021 12:00:18 -0800 (PST) Received: by mail-pg1-x52a.google.com with SMTP id a23so10896205pgm.4; Mon, 13 Dec 2021 12:00:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6PtQ+iCOtg8wKI/383IxFyqZ9i0rudNbH4n4NHCffbA=; b=JnFbMV0LMmXIzckTtX8Obr1ifAqu/wbl1vW2hpL0SUTxv3UBHRr8236i5XnOPF6sPO /xmaRwSaP2aPJfKYBB5z/JTz/wGYpZo+F2lgH+ZyruYIa2h2aI+Dote8vgXfSLqjSeaW vlhq31tGSbrL2TiIJIL+j52d4lUkYFsfhNaVeCraNz7vYVygddW7/jzYnMOsItfA0pL3 vT+fiwu1Zm2Zuucf6WkiheiR5CPbkbiEmGoJkeaH7Cj1B6aLIJY0vhlyKTxGVYKwinUo ZUuJ1oUlIuIYkeeWVtBKPgGd1kLYOLd9ehD6O2b7a51eU+5vH3pjQYmVSYwfO0vjVdGP dWcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6PtQ+iCOtg8wKI/383IxFyqZ9i0rudNbH4n4NHCffbA=; b=Bzt3NSWF/wGzMWUTGUCrpfodXA6c4HZQPV8V8QZ6+gBslc60/gPMkba9i40K/atWvM gqLfpHvtiacADmXt3F6xU9adv1Oeh1HXioWdChBDYN+IFPeNsOBjWD8NhtQswtPLZtYd acc7TNVWP1SWBEblinDn+75n/hlNgBFCxsHMhsCj92HUj8yMzsNMSUrUOmbpL0I1B69V vaHESsqfC5/FvVEIMHbIl01jCCBIORivEOCyIDYB7PYrrSmTSDaWI6q3z12S8N3jCy2p 8NtHaOV6JzykdMgw8KnnaWNhBRxzP/169e2bMo5hzsrVCG9HROKE1dT/Kc/cQxhDO/+u v7Ow== X-Gm-Message-State: AOAM530qZ8KY0nLrb/DuYhABfcuNTwAYKexJ6oqY005R5S3TfBSwcSJf KjhPyxJxzvVJmUPco4q+OkcyIi/e3S8= X-Google-Smtp-Source: ABdhPJynEU9b7rmrBmSOm+qJmtCAtScHQDgPUp9E4j+THkymCTGx2DxOrNX5I8/MSpzs3G6yoamNsA== X-Received: by 2002:a63:4516:: with SMTP id s22mr564873pga.170.1639425617194; Mon, 13 Dec 2021 12:00:17 -0800 (PST) Received: from fainelli-desktop.igp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id z14sm13926195pfh.60.2021.12.13.12.00.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Dec 2021 12:00:16 -0800 (PST) From: Florian Fainelli To: devicetree@vger.kernel.org Cc: Florian Fainelli , Bjorn Helgaas , Rob Herring , Ray Jui , Scott Branden , bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM IPROC ARM ARCHITECTURE), linux-pci@vger.kernel.org (open list:PCI SUBSYSTEM), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM IPROC ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 4/6] ARM: dts: NSP: Fixed iProc PCIe MSI sub-node Date: Mon, 13 Dec 2021 11:02:19 -0800 Message-Id: <20211213190221.355678-5-f.fainelli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211213190221.355678-1-f.fainelli@gmail.com> References: <20211213190221.355678-1-f.fainelli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Rename the msi controller unit name to 'msi' to avoid collisions with the 'msi-controller' boolean property. Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-nsp.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index 1c08daa18858..f242763c3bde 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -587,7 +587,7 @@ pcie0: pcie@18012000 { status = "disabled"; msi-parent = <&msi0>; - msi0: msi-controller { + msi0: msi { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>; @@ -624,7 +624,7 @@ pcie1: pcie@18013000 { status = "disabled"; msi-parent = <&msi1>; - msi1: msi-controller { + msi1: msi { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>; @@ -661,7 +661,7 @@ pcie2: pcie@18014000 { status = "disabled"; msi-parent = <&msi2>; - msi2: msi-controller { + msi2: msi { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>; From patchwork Mon Dec 13 19:02:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 12674581 X-Patchwork-Delegate: robh@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5D01AC43217 for ; Mon, 13 Dec 2021 20:00:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242771AbhLMUAW (ORCPT ); Mon, 13 Dec 2021 15:00:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34016 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242756AbhLMUAT (ORCPT ); Mon, 13 Dec 2021 15:00:19 -0500 Received: from mail-pf1-x432.google.com (mail-pf1-x432.google.com [IPv6:2607:f8b0:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9CB21C061574; Mon, 13 Dec 2021 12:00:19 -0800 (PST) Received: by mail-pf1-x432.google.com with SMTP id n26so15921646pff.3; Mon, 13 Dec 2021 12:00:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ew71xhC4xQ/czNjt0atU4xfLjLk+tfPXgytWCNx3psE=; b=oEz7qbA91b7EL32E744DYI2EKQc++9OsqGVl3wqm1nq0ID0SLoU42GOjWGzRF/0TQJ Z5ght3bxwcvCtLUqFvUcGFROCRg3WRX3eMxN4KrRDjytmCLb1HIlDiDBeNTvlbJTpLo7 HKTnZ0HFJg5I8nqCVmJIMPiXKTxFFM4XvDmLt5UyGL0is6YTcYQheeNaj0RvCza5ii1j eN+0ym5RxD3+CxA8DzEwPNFl2sPumhPcsHPVDXQn0D+nRcq3w/W6fCgb2iZ6vfML3gkT v3ZMuFay8tnWobQ9ThS7gJ5Ecgw1o3WMFpy2cfrK9JXmHAYIqu02S8ePYQRAK74TeopK wsqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ew71xhC4xQ/czNjt0atU4xfLjLk+tfPXgytWCNx3psE=; b=WKh3HEmouz3+DX2lsaUH9quxXLbbYoV6uH4JRpfA6AlvH0Q8SCbiJPBtRUTQVKZ41C lq/w+5hDT0lfiIwNY+sdnV7gLKXcAcmSqq/1HgfdktuUwHbiwQQseCj01sg4qa+L00qT L0NG+MwC3tO0jQ0ChY26O0iczKRJp5+058I2G2UkW21rEsalPNgg+ef1ECbPGPof/8eQ CSHp4AHXvtPt67j/GX3135mUcXsJFE75p0CikBvqfhVisftMl+YH15sA20fEpR7pfGdn fW+7POVLF7HBhF8/TQfpD1UUJHWeHDBKVby2u9LCHTNUUIZ8aByepMu0u4dUCuRhX0NS b+Uw== X-Gm-Message-State: AOAM531VTx/jXz5fNfQKtgDGC+qJ+mcVUjaKL1PSMWgqncPTBFOX9oeL UVIiHrB1cxA7VURJaw5NF+6hMBV8DOA= X-Google-Smtp-Source: ABdhPJx13a6C921vXH3bFb4F7WMUph9zGPlAxbnd0ECu/IogJfbntaCuGS9Ewf2nJhUoZioschHSHg== X-Received: by 2002:a63:85c3:: with SMTP id u186mr528580pgd.225.1639425618724; Mon, 13 Dec 2021 12:00:18 -0800 (PST) Received: from fainelli-desktop.igp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id z14sm13926195pfh.60.2021.12.13.12.00.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Dec 2021 12:00:18 -0800 (PST) From: Florian Fainelli To: devicetree@vger.kernel.org Cc: Florian Fainelli , Bjorn Helgaas , Rob Herring , Ray Jui , Scott Branden , bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM IPROC ARM ARCHITECTURE), linux-pci@vger.kernel.org (open list:PCI SUBSYSTEM), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM IPROC ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 5/6] dt-bindings: phy: Convert Cygnus PCIe PHY to YAML Date: Mon, 13 Dec 2021 11:02:20 -0800 Message-Id: <20211213190221.355678-6-f.fainelli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211213190221.355678-1-f.fainelli@gmail.com> References: <20211213190221.355678-1-f.fainelli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Convert the Broadcom Cygnus PCIe PHY Device Tree binding t YAML to help with validation. Signed-off-by: Florian Fainelli --- .../bindings/phy/brcm,cygnus-pcie-phy.txt | 47 ------------ .../bindings/phy/brcm,cygnus-pcie-phy.yaml | 76 +++++++++++++++++++ 2 files changed, 76 insertions(+), 47 deletions(-) delete mode 100644 Documentation/devicetree/bindings/phy/brcm,cygnus-pcie-phy.txt create mode 100644 Documentation/devicetree/bindings/phy/brcm,cygnus-pcie-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/brcm,cygnus-pcie-phy.txt b/Documentation/devicetree/bindings/phy/brcm,cygnus-pcie-phy.txt deleted file mode 100644 index 10efff28b52b..000000000000 --- a/Documentation/devicetree/bindings/phy/brcm,cygnus-pcie-phy.txt +++ /dev/null @@ -1,47 +0,0 @@ -Broadcom Cygnus PCIe PHY - -Required properties: -- compatible: must be "brcm,cygnus-pcie-phy" -- reg: base address and length of the PCIe PHY block -- #address-cells: must be 1 -- #size-cells: must be 0 - -Each PCIe PHY should be represented by a child node - -Required properties For the child node: -- reg: the PHY ID -0 - PCIe RC 0 -1 - PCIe RC 1 -- #phy-cells: must be 0 - -Example: - pcie_phy: phy@301d0a0 { - compatible = "brcm,cygnus-pcie-phy"; - reg = <0x0301d0a0 0x14>; - - pcie0_phy: phy@0 { - reg = <0>; - #phy-cells = <0>; - }; - - pcie1_phy: phy@1 { - reg = <1>; - #phy-cells = <0>; - }; - }; - - /* users of the PCIe phy */ - - pcie0: pcie@18012000 { - ... - ... - phys = <&pcie0_phy>; - phy-names = "pcie-phy"; - }; - - pcie1: pcie@18013000 { - ... - ... - phys = ; - phy-names = "pcie-phy"; - }; diff --git a/Documentation/devicetree/bindings/phy/brcm,cygnus-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/brcm,cygnus-pcie-phy.yaml new file mode 100644 index 000000000000..045699c65779 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/brcm,cygnus-pcie-phy.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/brcm,cygnus-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom Cygnus PCIe PHY + +maintainers: + - Ray Jui + - Scott Branden + +properties: + $nodename: + pattern: "^pcie[-|_]phy(@.*)?$" + + compatible: + items: + - const: brcm,cygnus-pcie-phy + + reg: + maxItems: 1 + description: > + Base address and length of the PCIe PHY block + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^pcie-phy@[0-9]+$": + type: object + description: > + PCIe PHY child nodes + + properties: + reg: + maxItems: 1 + description: > + The PCIe PHY port number + + "#phy-cells": + const: 0 + + required: + - reg + - "#phy-cells" + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + pcie_phy: pcie_phy@301d0a0 { + compatible = "brcm,cygnus-pcie-phy"; + reg = <0x0301d0a0 0x14>; + #address-cells = <1>; + #size-cells = <0>; + + pcie0_phy: pcie-phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + pcie1_phy: pcie-phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + }; From patchwork Mon Dec 13 19:02:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 12674583 X-Patchwork-Delegate: robh@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BE290C433FE for ; Mon, 13 Dec 2021 20:00:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242752AbhLMUAY (ORCPT ); Mon, 13 Dec 2021 15:00:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34026 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242740AbhLMUAV (ORCPT ); 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Mon, 13 Dec 2021 12:00:19 -0800 (PST) From: Florian Fainelli To: devicetree@vger.kernel.org Cc: Florian Fainelli , Bjorn Helgaas , Rob Herring , Ray Jui , Scott Branden , bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM IPROC ARM ARCHITECTURE), linux-pci@vger.kernel.org (open list:PCI SUBSYSTEM), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM IPROC ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 6/6] dt-bindings: pci: Convert iProc PCIe to YAML Date: Mon, 13 Dec 2021 11:02:21 -0800 Message-Id: <20211213190221.355678-7-f.fainelli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211213190221.355678-1-f.fainelli@gmail.com> References: <20211213190221.355678-1-f.fainelli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Conver the iProc PCIe controller Device Tree binding to YAML now that all DTS in arch/arm and arch/arm64 have been fixed to be compliant. Signed-off-by: Florian Fainelli --- .../bindings/pci/brcm,iproc-pcie.txt | 133 ------------- .../bindings/pci/brcm,iproc-pcie.yaml | 184 ++++++++++++++++++ 2 files changed, 184 insertions(+), 133 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt create mode 100644 Documentation/devicetree/bindings/pci/brcm,iproc-pcie.yaml diff --git a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt deleted file mode 100644 index df065aa53a83..000000000000 --- a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt +++ /dev/null @@ -1,133 +0,0 @@ -* Broadcom iProc PCIe controller with the platform bus interface - -Required properties: -- compatible: - "brcm,iproc-pcie" for the first generation of PAXB based controller, -used in SoCs including NSP, Cygnus, NS2, and Pegasus - "brcm,iproc-pcie-paxb-v2" for the second generation of PAXB-based -controllers, used in Stingray - "brcm,iproc-pcie-paxc" for the first generation of PAXC based -controller, used in NS2 - "brcm,iproc-pcie-paxc-v2" for the second generation of PAXC based -controller, used in Stingray - PAXB-based root complex is used for external endpoint devices. PAXC-based -root complex is connected to emulated endpoint devices internal to the ASIC -- reg: base address and length of the PCIe controller I/O register space -- #interrupt-cells: set to <1> -- interrupt-map-mask and interrupt-map, standard PCI properties to define the - mapping of the PCIe interface to interrupt numbers -- linux,pci-domain: PCI domain ID. Should be unique for each host controller -- bus-range: PCI bus numbers covered -- #address-cells: set to <3> -- #size-cells: set to <2> -- device_type: set to "pci" -- ranges: ranges for the PCI memory and I/O regions - -Optional properties: -- phys: phandle of the PCIe PHY device -- phy-names: must be "pcie-phy" -- dma-coherent: present if DMA operations are coherent -- dma-ranges: Some PAXB-based root complexes do not have inbound mapping done - by the ASIC after power on reset. In this case, SW is required to configure -the mapping, based on inbound memory regions specified by this property. - -- brcm,pcie-ob: Some iProc SoCs do not have the outbound address mapping done -by the ASIC after power on reset. In this case, SW needs to configure it - -If the brcm,pcie-ob property is present, the following properties become -effective: - -Required: -- brcm,pcie-ob-axi-offset: The offset from the AXI address to the internal -address used by the iProc PCIe core (not the PCIe address) - -MSI support (optional): - -For older platforms without MSI integrated in the GIC, iProc PCIe core provides -an event queue based MSI support. The iProc MSI uses host memories to store -MSI posted writes in the event queues - -On newer iProc platforms, gicv2m or gicv3-its based MSI support should be used - -- msi-map: Maps a Requester ID to an MSI controller and associated MSI -sideband data - -- msi-parent: Link to the device node of the MSI controller, used when no MSI -sideband data is passed between the iProc PCIe controller and the MSI -controller - -Refer to the following binding documents for more detailed description on -the use of 'msi-map' and 'msi-parent': - Documentation/devicetree/bindings/pci/pci-msi.txt - Documentation/devicetree/bindings/interrupt-controller/msi.txt - -When the iProc event queue based MSI is used, one needs to define the -following properties in the MSI device node: -- compatible: Must be "brcm,iproc-msi" -- msi-controller: claims itself as an MSI controller -- interrupts: List of interrupt IDs from its parent interrupt device - -Optional properties: -- brcm,pcie-msi-inten: Needs to be present for some older iProc platforms that -require the interrupt enable registers to be set explicitly to enable MSI - -Example: - pcie0: pcie@18012000 { - compatible = "brcm,iproc-pcie"; - reg = <0x18012000 0x1000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>; - - linux,pci-domain = <0>; - - bus-range = <0x00 0xff>; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x81000000 0 0 0x28000000 0 0x00010000 - 0x82000000 0 0x20000000 0x20000000 0 0x04000000>; - - phys = <&phy 0 5>; - phy-names = "pcie-phy"; - - brcm,pcie-ob; - brcm,pcie-ob-axi-offset = <0x00000000>; - - msi-parent = <&msi0>; - - /* iProc event queue based MSI */ - msi0: msi@18012000 { - compatible = "brcm,iproc-msi"; - msi-controller; - interrupt-parent = <&gic>; - interrupts = , - , - , - , - }; - }; - - pcie1: pcie@18013000 { - compatible = "brcm,iproc-pcie"; - reg = <0x18013000 0x1000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>; - - linux,pci-domain = <1>; - - bus-range = <0x00 0xff>; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x81000000 0 0 0x48000000 0 0x00010000 - 0x82000000 0 0x40000000 0x40000000 0 0x04000000>; - - phys = <&phy 1 6>; - phy-names = "pcie-phy"; - }; diff --git a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.yaml new file mode 100644 index 000000000000..6ce2c48b660b --- /dev/null +++ b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.yaml @@ -0,0 +1,184 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/brcm,iproc-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom iProc PCIe controller with the platform bus interface + +maintainers: + - Ray Jui + - Scott Branden + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + - $ref: /schemas/interrupt-controller/msi-controller.yaml# + +properties: + compatible: + items: + - enum: + # for the first generation of PAXB based controller, used in SoCs + # including NSP, Cygnus, NS2, and Pegasus + - brcm,iproc-pcie + # for the second generation of PAXB-based controllers, used in + # Stingray + - brcm,iproc-pcie-paxb-v2 + # For the first generation of PAXC based controller, used in NS2 + - brcm,iproc-pcie-paxc + # For the second generation of PAXC based controller, used in Stingray + - brcm,iproc-pcie-paxc-v2 + + reg: + maxItems: 1 + description: > + Base address and length of the PCIe controller I/O register space + + interrupt-map: true + + interrupt-map-mask: true + + "#interrupt-cells": + const: 1 + + ranges: + minItems: 1 + maxItems: 2 + description: > + Ranges for the PCI memory and I/O regions + + phys: + maxItems: 1 + + phy-names: + items: + - const: pcie-phy + + bus-range: true + + dma-coherent: true + + "#address-cells": true + + "#size-cells": true + + device_type: true + + brcm,pcie-ob: + type: boolean + description: > + Some iProc SoCs do not have the outbound address mapping done by the + ASIC after power on reset. In this case, SW needs to configure it + + brcm,pcie-ob-axi-offset: + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + The offset from the AXI address to the internal address used by the + iProc PCIe core (not the PCIe address) + + msi: + type: object + properties: + compatible: + items: + - const: brcm,iproc-msi + + msi-parent: true + + msi-controller: true + + brcm,pcie-msi-inten: + type: boolean + description: > + Needs to be present for some older iProc platforms that require the + interrupt enable registers to be set explicitly to enable MSI + +dependencies: + brcm,pcie-ob-axi-offset: [brcm,pcie-ob] + brcm,pcie-msi-inten: [msi-controller] + +required: + - compatible + - reg + - ranges + +if: + properties: + compatible: + contains: + enum: + - brcm,iproc-pcie +then: + required: + - interrupt-map + - interrupt-map-mask + +unevaluatedProperties: false + +examples: + - | + #include + + bus { + #address-cells = <1>; + #size-cells = <1>; + pcie0: pcie@18012000 { + compatible = "brcm,iproc-pcie"; + reg = <0x18012000 0x1000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>; + + linux,pci-domain = <0>; + + bus-range = <0x00 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0 0x28000000 0 0x00010000>, + <0x82000000 0 0x20000000 0x20000000 0 0x04000000>; + + phys = <&phy 0 5>; + phy-names = "pcie-phy"; + + brcm,pcie-ob; + brcm,pcie-ob-axi-offset = <0x00000000>; + + msi-parent = <&msi0>; + + /* iProc event queue based MSI */ + msi0: msi { + compatible = "brcm,iproc-msi"; + msi-controller; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + }; + + pcie1: pcie@18013000 { + compatible = "brcm,iproc-pcie"; + reg = <0x18013000 0x1000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>; + + linux,pci-domain = <1>; + + bus-range = <0x00 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0 0x48000000 0 0x00010000>, + <0x82000000 0 0x40000000 0x40000000 0 0x04000000>; + + phys = <&phy 1 6>; + phy-names = "pcie-phy"; + }; + };