From patchwork Thu Dec 16 13:37:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 12681215 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F3766C433EF for ; Thu, 16 Dec 2021 13:45:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=yzZgZ6twlqZNDZHjLj/9QTuI8glh5raHGQTjPCT3dXM=; b=Six7+AvpVR2ICI BEflnivxnwlRDcuT9zbUw63eXfcB2N8JxYIqtHHL22dN5g53/nkObKGBXwkpd0AeriQLjMFRT+IxB Gu0/JZJHryDgoXNpTUmHKy+vGi9V+sbszIdlkIccD8totWs98I3K3F2nwXrRjvdrgYSYZWUT3guQD F7pRgL7Uvv3tysqRsoxOdbDgdLevVQC5Gvbr02HxzY++h4OEeRyOjMKFW5rPdPNT4awtsqZLp9Zwb W6Q69XSkbfxCIoMbCAHYQXB6XP8kPFn4aI3Ijup3IG+jth2AwC6QIaYMs+qM11/S1lx+rJPZEG4KY mipM4bBxSGROlvLVkmow==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mxr4D-005uRC-Fx; Thu, 16 Dec 2021 13:45:05 +0000 Received: from laurent.telenet-ops.be ([2a02:1800:110:4::f00:19]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mxqxB-005rKS-QU for linux-riscv@lists.infradead.org; Thu, 16 Dec 2021 13:37:55 +0000 Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed20:d13f:527c:5504:a743]) by laurent.telenet-ops.be with bizsmtp id X1dg26004250X30011dgy5; Thu, 16 Dec 2021 14:37:44 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1mxqx1-005Q8v-Ff; Thu, 16 Dec 2021 14:37:39 +0100 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1mxqx0-009xu2-VC; Thu, 16 Dec 2021 14:37:38 +0100 From: Geert Uytterhoeven To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Rob Herring , Damien Le Moal , Lewis Hanly , Krzysztof Kozlowski , Conor Dooley , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Geert Uytterhoeven , Damien Le Moal Subject: [PATCH v2 01/11] riscv: dts: canaan: Fix SPI FLASH node names Date: Thu, 16 Dec 2021 14:37:25 +0100 Message-Id: <38c78c02b3b222e9738c36acf8716917530a9b2a.1639660956.git.geert@linux-m68k.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211216_053750_196750_CD30B7EF X-CRM114-Status: UNSURE ( 9.03 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org "make dtbs_check": arch/riscv/boot/dts/canaan/sipeed_maix_bit.dt.yaml: spi-flash@0: $nodename:0: 'spi-flash@0' does not match '^flash(@.*)?$' From schema: Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml Fix this by renaming all SPI FLASH nodes to "flash". Signed-off-by: Geert Uytterhoeven Reviewed-by: Damien Le Moal Reviewed-by: Krzysztof Kozlowski Tested-by: Damien Le Moal --- v2: - Add Reviewed-by, Tested-by. --- arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts | 2 +- arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts | 2 +- arch/riscv/boot/dts/canaan/sipeed_maix_go.dts | 2 +- arch/riscv/boot/dts/canaan/sipeed_maixduino.dts | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts b/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts index 0bcaf35045e795ed..984872f3d3a9b9ea 100644 --- a/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts +++ b/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts @@ -199,7 +199,7 @@ slot@0 { }; &spi3 { - spi-flash@0 { + flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <50000000>; diff --git a/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts b/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts index ac8a03f5867adbd0..7ba99b4da304218e 100644 --- a/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts +++ b/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts @@ -201,7 +201,7 @@ slot@0 { }; &spi3 { - spi-flash@0 { + flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <50000000>; diff --git a/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts b/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts index 623998194bc18aab..be9b12c9b374acb3 100644 --- a/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts +++ b/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts @@ -209,7 +209,7 @@ slot@0 { }; &spi3 { - spi-flash@0 { + flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <50000000>; diff --git a/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts b/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts index cf605ba0d67e43cd..031c0c28f8195777 100644 --- a/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts +++ b/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts @@ -174,7 +174,7 @@ slot@0 { }; &spi3 { - spi-flash@0 { + flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <50000000>; From patchwork Thu Dec 16 13:37:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 12681257 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0D16CC433F5 for ; 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Thu, 16 Dec 2021 13:45:38 +0000 Received: from laurent.telenet-ops.be ([2a02:1800:110:4::f00:19]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mxqxB-005rKY-QI for linux-riscv@lists.infradead.org; Thu, 16 Dec 2021 13:37:55 +0000 Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed20:d13f:527c:5504:a743]) by laurent.telenet-ops.be with bizsmtp id X1dg26005250X30011dgy6; Thu, 16 Dec 2021 14:37:44 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1mxqx1-005Q8w-IS; Thu, 16 Dec 2021 14:37:39 +0100 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1mxqx0-009xu8-W4; Thu, 16 Dec 2021 14:37:39 +0100 From: Geert Uytterhoeven To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Rob Herring , Damien Le Moal , Lewis Hanly , Krzysztof Kozlowski , Conor Dooley , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Geert Uytterhoeven , Damien Le Moal Subject: [PATCH v2 02/11] riscv: dts: canaan: Group tuples in interrupt properties Date: Thu, 16 Dec 2021 14:37:26 +0100 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211216_053750_194681_78E813C2 X-CRM114-Status: UNSURE ( 7.93 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org To improve human readability and enable automatic validation, the tuples in the various properties containing interrupt specifiers should be grouped. Fix this by grouping the tuples of "interrupts" and "interrupts-extended" properties using angle brackets. Signed-off-by: Geert Uytterhoeven Reviewed-by: Damien Le Moal Reviewed-by: Krzysztof Kozlowski Tested-by: Damien Le Moal --- v2: - Add Reviewed-by, Tested-by. --- arch/riscv/boot/dts/canaan/k210.dtsi | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi index 5e8ca8142482153b..56f57118c633b91a 100644 --- a/arch/riscv/boot/dts/canaan/k210.dtsi +++ b/arch/riscv/boot/dts/canaan/k210.dtsi @@ -103,8 +103,8 @@ rom0: nvmem@1000 { clint0: timer@2000000 { compatible = "canaan,k210-clint", "sifive,clint0"; reg = <0x2000000 0xC000>; - interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 - &cpu1_intc 3 &cpu1_intc 7>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>; }; plic0: interrupt-controller@c000000 { @@ -113,7 +113,7 @@ plic0: interrupt-controller@c000000 { compatible = "canaan,k210-plic", "sifive,plic-1.0.0"; reg = <0xC000000 0x4000000>; interrupt-controller; - interrupts-extended = <&cpu0_intc 11 &cpu1_intc 11>; + interrupts-extended = <&cpu0_intc 11>, <&cpu1_intc 11>; riscv,ndev = <65>; }; @@ -130,10 +130,11 @@ gpio0: gpio-controller@38001000 { compatible = "canaan,k210-gpiohs", "sifive,gpio0"; reg = <0x38001000 0x1000>; interrupt-controller; - interrupts = <34 35 36 37 38 39 40 41 - 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 - 58 59 60 61 62 63 64 65>; + interrupts = <34>, <35>, <36>, <37>, <38>, <39>, <40>, + <41>, <42>, <43>, <44>, <45>, <46>, <47>, + <48>, <49>, <50>, <51>, <52>, <53>, <54>, + <55>, <56>, <57>, <58>, <59>, <60>, <61>, + <62>, <63>, <64>, <65>; gpio-controller; ngpios = <32>; }; @@ -141,7 +142,7 @@ gpio0: gpio-controller@38001000 { dmac0: dma-controller@50000000 { compatible = "snps,axi-dma-1.01a"; reg = <0x50000000 0x1000>; - interrupts = <27 28 29 30 31 32>; + interrupts = <27>, <28>, <29>, <30>, <31>, <32>; #dma-cells = <1>; clocks = <&sysclk K210_CLK_DMA>, <&sysclk K210_CLK_DMA>; clock-names = "core-clk", "cfgr-clk"; @@ -316,7 +317,7 @@ fpioa: pinmux@502b0000 { timer0: timer@502d0000 { compatible = "snps,dw-apb-timer"; reg = <0x502D0000 0x100>; - interrupts = <14 15>; + interrupts = <14>, <15>; clocks = <&sysclk K210_CLK_TIMER0>, <&sysclk K210_CLK_APB0>; clock-names = "timer", "pclk"; @@ -326,7 +327,7 @@ timer0: timer@502d0000 { timer1: timer@502e0000 { compatible = "snps,dw-apb-timer"; reg = <0x502E0000 0x100>; - interrupts = <16 17>; + interrupts = <16>, <17>; clocks = <&sysclk K210_CLK_TIMER1>, <&sysclk K210_CLK_APB0>; clock-names = "timer", "pclk"; @@ -336,7 +337,7 @@ timer1: timer@502e0000 { timer2: timer@502f0000 { compatible = "snps,dw-apb-timer"; reg = <0x502F0000 0x100>; - interrupts = <18 19>; + interrupts = <18>, <19>; clocks = <&sysclk K210_CLK_TIMER2>, <&sysclk K210_CLK_APB0>; clock-names = "timer", "pclk"; From patchwork Thu Dec 16 13:37:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 12681213 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 198ACC433F5 for ; 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Thu, 16 Dec 2021 13:44:56 +0000 Received: from michel.telenet-ops.be ([2a02:1800:110:4::f00:18]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mxqxB-005rJq-QU for linux-riscv@lists.infradead.org; Thu, 16 Dec 2021 13:37:53 +0000 Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed20:d13f:527c:5504:a743]) by michel.telenet-ops.be with bizsmtp id X1dg2600A250X30061dgUU; Thu, 16 Dec 2021 14:37:42 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1mxqx1-005Q8x-Ic; Thu, 16 Dec 2021 14:37:39 +0100 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1mxqx1-009xuE-1a; Thu, 16 Dec 2021 14:37:39 +0100 From: Geert Uytterhoeven To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Rob Herring , Damien Le Moal , Lewis Hanly , Krzysztof Kozlowski , Conor Dooley , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 03/11] riscv: dts: microchip: mpfs: Drop empty chosen node Date: Thu, 16 Dec 2021 14:37:27 +0100 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211216_053750_211716_5EC319BE X-CRM114-Status: UNSURE ( 7.69 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org It does not make sense to have an (empty) chosen node in an SoC-specific .dtsi, as chosen is meant for system-specific configuration. It is already provided in microchip-mpfs-icicle-kit.dts anyway. Fixes: 0fa6107eca4186ad ("RISC-V: Initial DTS for Microchip ICICLE board") Signed-off-by: Geert Uytterhoeven Reviewed-by: Conor Dooley --- v2: - Add Reviewed-by. --- arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi index c9f6d205d2ba1a5e..794da883acb19256 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi @@ -9,9 +9,6 @@ / { model = "Microchip PolarFire SoC"; compatible = "microchip,mpfs"; - chosen { - }; - cpus { #address-cells = <1>; #size-cells = <0>; From patchwork Thu Dec 16 13:37:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 12681261 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F1790C433EF for ; Thu, 16 Dec 2021 13:46:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=7YYiNHNlYJsVfhr2kaR2KzQRlXtGNBppG1NlbKie/w0=; b=QMYdkE2sVF10TU YW5gimXuxTSLjtpB2eKz6VQcHgzb0O7p4YU/PY3AWB6g0UityX+uc15ijTo3LJR47i0LVa3LxUQAo iU2xAJs4M3qKPyCD8APi0u3BTme0mkrOlbP9OURRi3a2atwaxllTuYAnRz2xL7dV1W3PqucXex5q3 mNDsV6KgTEJLRe6NocJKRysXWEYMfEabzabG/fLjdrKIlhyyR66yQYsjNWWjG5HCHuCaTshWY9Ewx K6+SKyT2g5e4RwqFCevqq6kqGkhKBIgXOQhfnfAKmWeC/qWvpDNlR2JDQwXM4n7vfMyDEb2GUq64N mneMAwVWU+kVO+iF2o1Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mxr55-005uuw-Oe; Thu, 16 Dec 2021 13:45:59 +0000 Received: from michel.telenet-ops.be ([2a02:1800:110:4::f00:18]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mxqxB-005rJn-PB for linux-riscv@lists.infradead.org; Thu, 16 Dec 2021 13:37:55 +0000 Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed20:d13f:527c:5504:a743]) by michel.telenet-ops.be with bizsmtp id X1dg2600M250X30061dgUb; Thu, 16 Dec 2021 14:37:42 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1mxqx2-005Q8y-1W; Thu, 16 Dec 2021 14:37:40 +0100 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1mxqx1-009xuN-2k; Thu, 16 Dec 2021 14:37:39 +0100 From: Geert Uytterhoeven To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Rob Herring , Damien Le Moal , Lewis Hanly , Krzysztof Kozlowski , Conor Dooley , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 04/11] riscv: dts: microchip: mpfs: Fix PLIC node Date: Thu, 16 Dec 2021 14:37:28 +0100 Message-Id: <69c25dac1243e33bf5a5a893bd6895320d4c87c5.1639660956.git.geert@linux-m68k.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211216_053750_165734_72242DCD X-CRM114-Status: UNSURE ( 9.57 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Fix the device node for the Platform-Level Interrupt Controller (PLIC): - Add missing "#address-cells" property, - Sort properties according to DT bindings. Signed-off-by: Geert Uytterhoeven Reviewed-by: Krzysztof Kozlowski Reviewed-by: Conor Dooley --- v2: - Add Reviewed-by. --- arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi index 794da883acb19256..ee59751544a0d3bc 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi @@ -168,16 +168,17 @@ &cpu3_intc 3 &cpu3_intc 7 }; plic: interrupt-controller@c000000 { - #interrupt-cells = <1>; compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; reg = <0x0 0xc000000 0x0 0x4000000>; - riscv,ndev = <186>; + #address-cells = <0>; + #interrupt-cells = <1>; interrupt-controller; interrupts-extended = <&cpu0_intc 11 &cpu1_intc 11 &cpu1_intc 9 &cpu2_intc 11 &cpu2_intc 9 &cpu3_intc 11 &cpu3_intc 9 &cpu4_intc 11 &cpu4_intc 9>; + riscv,ndev = <186>; }; dma@3000000 { From patchwork Thu Dec 16 13:37:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 12681205 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A8AC6C433F5 for ; Thu, 16 Dec 2021 13:44:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=zCXPNSLFyD3u2ZvYGg9hYNcjNUBzQmO5BiKDkzzRrxg=; b=PArgBI+siY06ll I4x+zLOH6vim75/SlcgBXtlBik0r/JW8ZZIzCmFFUvSOKBaHSb5znROZ3642/Be4FbwELuFS0fTai HhVwqR/PftMxdRL8w+PzvwbUarKKAMLCPADypaQw0YV+u5dSnPkNi+gx4TPTwfqI7KBxm1XawuGtm jzB8P2fFqlIDXGMHpQ7YXPPTyQFKRBV1VhwXH5Cr4jTQIc52AL8rB/4bn3MwVpu5yYqucPg5Ep4La UcUdtU8dYjfIl8eJFq4GWVincsux0RrfCm/elt0a7/XZJUuxbTOU/9o9vEd60Bkqf3LGgbT2grmcf 8nDykOE2K977RkmcwoWw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mxr3O-005u30-H4; Thu, 16 Dec 2021 13:44:14 +0000 Received: from laurent.telenet-ops.be ([2a02:1800:110:4::f00:19]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mxqxB-005rJm-ND for linux-riscv@lists.infradead.org; Thu, 16 Dec 2021 13:37:51 +0000 Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed20:d13f:527c:5504:a743]) by laurent.telenet-ops.be with bizsmtp id X1dg26007250X30011dgy7; Thu, 16 Dec 2021 14:37:43 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1mxqx1-005Q8z-MU; Thu, 16 Dec 2021 14:37:39 +0100 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1mxqx1-009xuT-3d; Thu, 16 Dec 2021 14:37:39 +0100 From: Geert Uytterhoeven To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Rob Herring , Damien Le Moal , Lewis Hanly , Krzysztof Kozlowski , Conor Dooley , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 05/11] riscv: dts: microchip: mpfs: Fix reference clock node Date: Thu, 16 Dec 2021 14:37:29 +0100 Message-Id: <1fdb9ffe223057e0140324ae020c9cc1dc90ae5c.1639660956.git.geert@linux-m68k.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211216_053749_951148_5F727235 X-CRM114-Status: GOOD ( 10.38 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org "make dtbs_check" reports: arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dt.yaml: soc: refclk: {'compatible': ['fixed-clock'], '#clock-cells': [[0]], 'clock-frequency': [[600000000]], 'clock-output-names': ['msspllclk'], 'phandle': [[7]]} should not be valid under {'type': 'object'} From schema: dtschema/schemas/simple-bus.yaml Fix this by moving the node out of the "soc" subnode. While at it, rename it to "msspllclk", and drop the now superfluous "clock-output-names" property. Move the actual clock-frequency value to the board DTS, since it is not set until bitstream programming time. Signed-off-by: Geert Uytterhoeven Acked-by: Krzysztof Kozlowski Reviewed-by: Conor Dooley --- v2: - Add Acked-by, - Move clock-frequency to board DTS. --- .../boot/dts/microchip/microchip-mpfs-icicle-kit.dts | 4 ++++ arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 12 +++++------- 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts index fc1e5869df1b9fc5..0c748ae1b0068df7 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts @@ -35,6 +35,10 @@ memory@80000000 { }; }; +&refclk { + clock-frequency = <600000000>; +}; + &serial0 { status = "okay"; }; diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi index ee59751544a0d3bc..b372bc6459bf163a 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi @@ -139,6 +139,11 @@ cpu4_intc: interrupt-controller { }; }; + refclk: msspllclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + soc { #address-cells = <2>; #size-cells = <2>; @@ -189,13 +194,6 @@ dma@3000000 { #dma-cells = <1>; }; - refclk: refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <600000000>; - clock-output-names = "msspllclk"; - }; - clkcfg: clkcfg@20002000 { compatible = "microchip,mpfs-clkcfg"; reg = <0x0 0x20002000 0x0 0x1000>; From patchwork Thu Dec 16 13:37:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 12681207 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 67B57C433F5 for ; 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Thu, 16 Dec 2021 13:37:52 +0000 Received: from baptiste.telenet-ops.be (baptiste.telenet-ops.be [IPv6:2a02:1800:120:4::f00:13]) by leibniz.telenet-ops.be (Postfix) with ESMTPS id 4JFCpy0BYfzMqg2h for ; Thu, 16 Dec 2021 14:37:46 +0100 (CET) Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed20:d13f:527c:5504:a743]) by baptiste.telenet-ops.be with bizsmtp id X1dh26001250X30011dhRg; Thu, 16 Dec 2021 14:37:43 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1mxqx2-005Q90-8e; Thu, 16 Dec 2021 14:37:40 +0100 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1mxqx1-009xuZ-4R; Thu, 16 Dec 2021 14:37:39 +0100 From: Geert Uytterhoeven To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Rob Herring , Damien Le Moal , Lewis Hanly , Krzysztof Kozlowski , Conor Dooley , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 06/11] riscv: dts: microchip: mpfs: Fix clock controller node Date: Thu, 16 Dec 2021 14:37:30 +0100 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211216_133750_906130_F43948F8 X-CRM114-Status: UNSURE ( 7.67 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Fix the device node for the clock controller: - Remove bogus "reg-names" property, - Remove unneeded "clock-output-names" property. Signed-off-by: Geert Uytterhoeven Reviewed-by: Conor Dooley Tested-by: Conor Dooley too?) --- v2: - New. --- arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 9 --------- 1 file changed, 9 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi index b372bc6459bf163a..d9c1dee3fb25beb8 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi @@ -197,17 +197,8 @@ dma@3000000 { clkcfg: clkcfg@20002000 { compatible = "microchip,mpfs-clkcfg"; reg = <0x0 0x20002000 0x0 0x1000>; - reg-names = "mss_sysreg"; clocks = <&refclk>; #clock-cells = <1>; - clock-output-names = "cpu", "axi", "ahb", "envm", /* 0-3 */ - "mac0", "mac1", "mmc", "timer", /* 4-7 */ - "mmuart0", "mmuart1", "mmuart2", "mmuart3", /* 8-11 */ - "mmuart4", "spi0", "spi1", "i2c0", /* 12-15 */ - "i2c1", "can0", "can1", "usb", /* 16-19 */ - "rsvd", "rtc", "qspi", "gpio0", /* 20-23 */ - "gpio1", "gpio2", "ddrc", "fic0", /* 24-27 */ - "fic1", "fic2", "fic3", "athena", "cfm"; /* 28-32 */ }; serial0: serial@20000000 { From patchwork Thu Dec 16 13:37:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 12681259 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6F846C433EF for ; Thu, 16 Dec 2021 13:45:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Thu, 16 Dec 2021 14:37:40 +0100 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1mxqx1-009xuh-5F; Thu, 16 Dec 2021 14:37:39 +0100 From: Geert Uytterhoeven To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Rob Herring , Damien Le Moal , Lewis Hanly , Krzysztof Kozlowski , Conor Dooley , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 07/11] riscv: dts: microchip: mpfs: Group tuples in interrupt properties Date: Thu, 16 Dec 2021 14:37:31 +0100 Message-Id: <5920780dc81102ff11a5521d9476249141fca36b.1639660956.git.geert@linux-m68k.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211216_133752_225961_B0F520A4 X-CRM114-Status: UNSURE ( 8.16 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org To improve human readability and enable automatic validation, the tuples in the various properties containing interrupt specifiers should be grouped. Fix this by grouping the tuples of "interrupts" and "interrupts-extended" properties using angle brackets. Signed-off-by: Geert Uytterhoeven Reviewed-by: Krzysztof Kozlowski Reviewed-by: Conor Dooley --- v2: - Add Reviewed-by. --- .../boot/dts/microchip/microchip-mpfs.dtsi | 31 ++++++++++--------- 1 file changed, 16 insertions(+), 15 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi index d9c1dee3fb25beb8..869aaf0d5c066c9d 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi @@ -158,18 +158,18 @@ cache-controller@2010000 { cache-size = <2097152>; cache-unified; interrupt-parent = <&plic>; - interrupts = <1 2 3>; + interrupts = <1>, <2>, <3>; reg = <0x0 0x2010000 0x0 0x1000>; }; clint@2000000 { compatible = "sifive,fu540-c000-clint", "sifive,clint0"; reg = <0x0 0x2000000 0x0 0xC000>; - interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 - &cpu1_intc 3 &cpu1_intc 7 - &cpu2_intc 3 &cpu2_intc 7 - &cpu3_intc 3 &cpu3_intc 7 - &cpu4_intc 3 &cpu4_intc 7>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>, + <&cpu2_intc 3>, <&cpu2_intc 7>, + <&cpu3_intc 3>, <&cpu3_intc 7>, + <&cpu4_intc 3>, <&cpu4_intc 7>; }; plic: interrupt-controller@c000000 { @@ -178,11 +178,11 @@ plic: interrupt-controller@c000000 { #address-cells = <0>; #interrupt-cells = <1>; interrupt-controller; - interrupts-extended = <&cpu0_intc 11 - &cpu1_intc 11 &cpu1_intc 9 - &cpu2_intc 11 &cpu2_intc 9 - &cpu3_intc 11 &cpu3_intc 9 - &cpu4_intc 11 &cpu4_intc 9>; + interrupts-extended = <&cpu0_intc 11>, + <&cpu1_intc 11>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu2_intc 9>, + <&cpu3_intc 11>, <&cpu3_intc 9>, + <&cpu4_intc 11>, <&cpu4_intc 9>; riscv,ndev = <186>; }; @@ -190,7 +190,8 @@ dma@3000000 { compatible = "sifive,fu540-c000-pdma"; reg = <0x0 0x3000000 0x0 0x8000>; interrupt-parent = <&plic>; - interrupts = <23 24 25 26 27 28 29 30>; + interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>, + <30>; #dma-cells = <1>; }; @@ -254,7 +255,7 @@ mmc: mmc@20008000 { compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc"; reg = <0x0 0x20008000 0x0 0x1000>; interrupt-parent = <&plic>; - interrupts = <88 89>; + interrupts = <88>, <89>; clocks = <&clkcfg 6>; max-frequency = <200000000>; status = "disabled"; @@ -264,7 +265,7 @@ emac0: ethernet@20110000 { compatible = "cdns,macb"; reg = <0x0 0x20110000 0x0 0x2000>; interrupt-parent = <&plic>; - interrupts = <64 65 66 67>; + interrupts = <64>, <65>, <66>, <67>; local-mac-address = [00 00 00 00 00 00]; clocks = <&clkcfg 4>, <&clkcfg 2>; clock-names = "pclk", "hclk"; @@ -277,7 +278,7 @@ emac1: ethernet@20112000 { compatible = "cdns,macb"; reg = <0x0 0x20112000 0x0 0x2000>; interrupt-parent = <&plic>; - interrupts = <70 71 72 73>; + interrupts = <70>, <71>, <72>, <73>; local-mac-address = [00 00 00 00 00 00]; clocks = <&clkcfg 5>, <&clkcfg 2>; status = "disabled"; From patchwork Thu Dec 16 13:37:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 12681211 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 62FC7C433F5 for ; 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Thu, 16 Dec 2021 13:44:45 +0000 Received: from laurent.telenet-ops.be ([2a02:1800:110:4::f00:19]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mxqxB-005rJl-Nb for linux-riscv@lists.infradead.org; Thu, 16 Dec 2021 13:37:53 +0000 Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed20:d13f:527c:5504:a743]) by laurent.telenet-ops.be with bizsmtp id X1dg2600F250X30011dgyB; Thu, 16 Dec 2021 14:37:43 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1mxqx1-005Q92-Tt; Thu, 16 Dec 2021 14:37:39 +0100 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1mxqx1-009xup-65; Thu, 16 Dec 2021 14:37:39 +0100 From: Geert Uytterhoeven To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Rob Herring , Damien Le Moal , Lewis Hanly , Krzysztof Kozlowski , Conor Dooley , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 08/11] riscv: dts: sifive: Group tuples in interrupt properties Date: Thu, 16 Dec 2021 14:37:32 +0100 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211216_053750_119970_0D24842D X-CRM114-Status: UNSURE ( 7.95 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org To improve human readability and enable automatic validation, the tuples in the various properties containing interrupt specifiers should be grouped. Fix this by grouping the tuples of "interrupts" and "interrupts-extended" properties using angle brackets. Signed-off-by: Geert Uytterhoeven Reviewed-by: Krzysztof Kozlowski --- v2: - Add Reviewed-by. --- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 21 +++++++++++---------- arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 14 +++++++------- 2 files changed, 18 insertions(+), 17 deletions(-) diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi index 0655b5c4201d9f71..0caca0ccf6711ded 100644 --- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi @@ -145,12 +145,12 @@ plic0: interrupt-controller@c000000 { reg = <0x0 0xc000000 0x0 0x4000000>; riscv,ndev = <53>; interrupt-controller; - interrupts-extended = < - &cpu0_intc 0xffffffff - &cpu1_intc 0xffffffff &cpu1_intc 9 - &cpu2_intc 0xffffffff &cpu2_intc 9 - &cpu3_intc 0xffffffff &cpu3_intc 9 - &cpu4_intc 0xffffffff &cpu4_intc 9>; + interrupts-extended = + <&cpu0_intc 0xffffffff>, + <&cpu1_intc 0xffffffff>, <&cpu1_intc 9>, + <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>, + <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>, + <&cpu4_intc 0xffffffff>, <&cpu4_intc 9>; }; prci: clock-controller@10000000 { compatible = "sifive,fu540-c000-prci"; @@ -170,7 +170,8 @@ dma: dma@3000000 { compatible = "sifive,fu540-c000-pdma"; reg = <0x0 0x3000000 0x0 0x8000>; interrupt-parent = <&plic0>; - interrupts = <23 24 25 26 27 28 29 30>; + interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>, + <30>; #dma-cells = <1>; }; uart1: serial@10011000 { @@ -243,7 +244,7 @@ pwm0: pwm@10020000 { compatible = "sifive,fu540-c000-pwm", "sifive,pwm0"; reg = <0x0 0x10020000 0x0 0x1000>; interrupt-parent = <&plic0>; - interrupts = <42 43 44 45>; + interrupts = <42>, <43>, <44>, <45>; clocks = <&prci PRCI_CLK_TLCLK>; #pwm-cells = <3>; status = "disabled"; @@ -252,7 +253,7 @@ pwm1: pwm@10021000 { compatible = "sifive,fu540-c000-pwm", "sifive,pwm0"; reg = <0x0 0x10021000 0x0 0x1000>; interrupt-parent = <&plic0>; - interrupts = <46 47 48 49>; + interrupts = <46>, <47>, <48>, <49>; clocks = <&prci PRCI_CLK_TLCLK>; #pwm-cells = <3>; status = "disabled"; @@ -265,7 +266,7 @@ l2cache: cache-controller@2010000 { cache-size = <2097152>; cache-unified; interrupt-parent = <&plic0>; - interrupts = <1 2 3>; + interrupts = <1>, <2>, <3>; reg = <0x0 0x2010000 0x0 0x1000>; }; gpio: gpio@10060000 { diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi index abbb960f90a00ac2..8464b0e3c88791e1 100644 --- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi @@ -147,12 +147,12 @@ plic0: interrupt-controller@c000000 { reg = <0x0 0xc000000 0x0 0x4000000>; riscv,ndev = <69>; interrupt-controller; - interrupts-extended = < - &cpu0_intc 0xffffffff - &cpu1_intc 0xffffffff &cpu1_intc 9 - &cpu2_intc 0xffffffff &cpu2_intc 9 - &cpu3_intc 0xffffffff &cpu3_intc 9 - &cpu4_intc 0xffffffff &cpu4_intc 9>; + interrupts-extended = + <&cpu0_intc 0xffffffff>, + <&cpu1_intc 0xffffffff>, <&cpu1_intc 9>, + <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>, + <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>, + <&cpu4_intc 0xffffffff>, <&cpu4_intc 9>; }; prci: clock-controller@10000000 { compatible = "sifive,fu740-c000-prci"; @@ -273,7 +273,7 @@ ccache: cache-controller@2010000 { cache-size = <2097152>; cache-unified; interrupt-parent = <&plic0>; - interrupts = <19 21 22 20>; + interrupts = <19>, <21>, <22>, <20>; reg = <0x0 0x2010000 0x0 0x1000>; }; gpio: gpio@10060000 { From patchwork Thu Dec 16 13:37:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 12681255 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7CC8DC4332F for ; Thu, 16 Dec 2021 13:45:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Thu, 16 Dec 2021 14:37:39 +0100 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1mxqx1-009xuv-6t; Thu, 16 Dec 2021 14:37:39 +0100 From: Geert Uytterhoeven To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Rob Herring , Damien Le Moal , Lewis Hanly , Krzysztof Kozlowski , Conor Dooley , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 09/11] riscv: dts: sifive: Group tuples in register properties Date: Thu, 16 Dec 2021 14:37:33 +0100 Message-Id: <405f7ebe588e269ffd428b818c0ff1f472a00ea8.1639660956.git.geert@linux-m68k.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211216_053750_145616_6B162315 X-CRM114-Status: UNSURE ( 8.46 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org To improve human readability and enable automatic validation, the tuples in "reg" properties containing register blocks should be grouped using angle brackets. Signed-off-by: Geert Uytterhoeven Reviewed-by: Krzysztof Kozlowski --- v2: - Add Reviewed-by. --- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi index 0caca0ccf6711ded..e2efcf08210926f8 100644 --- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi @@ -196,8 +196,8 @@ i2c0: i2c@10030000 { }; qspi0: spi@10040000 { compatible = "sifive,fu540-c000-spi", "sifive,spi0"; - reg = <0x0 0x10040000 0x0 0x1000 - 0x0 0x20000000 0x0 0x10000000>; + reg = <0x0 0x10040000 0x0 0x1000>, + <0x0 0x20000000 0x0 0x10000000>; interrupt-parent = <&plic0>; interrupts = <51>; clocks = <&prci PRCI_CLK_TLCLK>; @@ -207,8 +207,8 @@ qspi0: spi@10040000 { }; qspi1: spi@10041000 { compatible = "sifive,fu540-c000-spi", "sifive,spi0"; - reg = <0x0 0x10041000 0x0 0x1000 - 0x0 0x30000000 0x0 0x10000000>; + reg = <0x0 0x10041000 0x0 0x1000>, + <0x0 0x30000000 0x0 0x10000000>; interrupt-parent = <&plic0>; interrupts = <52>; clocks = <&prci PRCI_CLK_TLCLK>; @@ -230,8 +230,8 @@ eth0: ethernet@10090000 { compatible = "sifive,fu540-c000-gem"; interrupt-parent = <&plic0>; interrupts = <53>; - reg = <0x0 0x10090000 0x0 0x2000 - 0x0 0x100a0000 0x0 0x1000>; + reg = <0x0 0x10090000 0x0 0x2000>, + <0x0 0x100a0000 0x0 0x1000>; local-mac-address = [00 00 00 00 00 00]; clock-names = "pclk", "hclk"; clocks = <&prci PRCI_CLK_GEMGXLPLL>, From patchwork Thu Dec 16 13:37:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 12681203 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 43B00C433F5 for ; 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Thu, 16 Dec 2021 13:44:03 +0000 Received: from michel.telenet-ops.be ([2a02:1800:110:4::f00:18]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mxqxB-005rJo-N4 for linux-riscv@lists.infradead.org; Thu, 16 Dec 2021 13:37:51 +0000 Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed20:d13f:527c:5504:a743]) by michel.telenet-ops.be with bizsmtp id X1dg2600T250X30061dgUc; Thu, 16 Dec 2021 14:37:42 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1mxqx2-005Q94-6D; Thu, 16 Dec 2021 14:37:40 +0100 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1mxqx1-009xv3-7f; Thu, 16 Dec 2021 14:37:39 +0100 From: Geert Uytterhoeven To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Rob Herring , Damien Le Moal , Lewis Hanly , Krzysztof Kozlowski , Conor Dooley , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 10/11] riscv: dts: sifive: fu540-c000: Drop bogus soc node compatible values Date: Thu, 16 Dec 2021 14:37:34 +0100 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211216_053749_968739_D779BF6E X-CRM114-Status: GOOD ( 10.87 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org "make dtbs_check": arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dt.yaml: soc: $nodename:0: '/' was expected From schema: Documentation/devicetree/bindings/riscv/sifive.yaml arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dt.yaml: soc: compatible: 'oneOf' conditional failed, one must be fixed: 'sifive,fu540-c000' is not one of ['sifive,hifive-unleashed-a00'] 'sifive,fu540-c000' is not one of ['sifive,hifive-unmatched-a00'] 'sifive,fu540-c000' was expected 'sifive,fu740-c000' was expected 'sifive,fu540' was expected 'sifive,fu740' was expected From schema: Documentation/devicetree/bindings/riscv/sifive.yaml This happens because the "soc" subnode declares compatibility with "sifive,fu540-c000" and "sifive,fu540", while these are only intended for the root node. Fix this by removing the bogus compatible values from the "soc" node. Signed-off-by: Geert Uytterhoeven Reviewed-by: Krzysztof Kozlowski --- v2: - Add Reviewed-by. --- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi index e2efcf08210926f8..b1250c16816f5c9d 100644 --- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi @@ -137,7 +137,7 @@ cpu4_intc: interrupt-controller { soc { #address-cells = <2>; #size-cells = <2>; - compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus"; + compatible = "simple-bus"; ranges; plic0: interrupt-controller@c000000 { #interrupt-cells = <1>; From patchwork Thu Dec 16 13:37:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 12681217 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 86751C433EF for ; Thu, 16 Dec 2021 13:45:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=pCSdX4zR9d1OXEmlvIWmYEYqfkLDKzxu+nXDnn6dJlM=; b=JQHBgioQWo/RoM 8hSx0gWjRATAUi3fxaCUm1YfUD9vPVDqGr5AbP/rIhwzHJrzaj2WLY9EqComrJMvYwZzdaB0kCRVE +lYAdAlB1zjsmk1sArAVwa3OPkk1lB+AWdeYS/6ASk0gnS1/FBkBXfHIwcysGeEQ2a2q44DU+UZgX 6F4xccBAbMfbWJqOPfZuBBMD6/mEdbsHyF7VBjHNN/zseR4SFWHjwLE0EEnub2TjcOKCMCiHceKFv 2OhO2puwJ8u5zVHlEi6io26+Uy4A8tOh0JHZzVYg22pSu4xMeCyX5pC0Uqa5DcH9r502xa9RunbCd QEvzLceWuvqn2ONqSPHg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mxr4O-005uYX-RE; Thu, 16 Dec 2021 13:45:16 +0000 Received: from albert.telenet-ops.be ([2a02:1800:110:4::f00:1a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mxqxB-005rJi-OQ for linux-riscv@lists.infradead.org; Thu, 16 Dec 2021 13:37:53 +0000 Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed20:d13f:527c:5504:a743]) by albert.telenet-ops.be with bizsmtp id X1dg2600T250X30061dgKF; Thu, 16 Dec 2021 14:37:42 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1mxqx2-005Q95-2q; Thu, 16 Dec 2021 14:37:40 +0100 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1mxqx1-009xv9-8N; Thu, 16 Dec 2021 14:37:39 +0100 From: Geert Uytterhoeven To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Rob Herring , Damien Le Moal , Lewis Hanly , Krzysztof Kozlowski , Conor Dooley , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 11/11] riscv: dts: sifive: fu540-c000: Fix PLIC node Date: Thu, 16 Dec 2021 14:37:35 +0100 Message-Id: <2658fb6d194ea22a8077d1475bafec43d9a39244.1639660956.git.geert@linux-m68k.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211216_053750_012158_FA467F9B X-CRM114-Status: UNSURE ( 9.82 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Fix the device node for the Platform-Level Interrupt Controller (PLIC): - Add missing "#address-cells" property, - Sort properties according to DT bindings. Signed-off-by: Geert Uytterhoeven --- v2: - New. --- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi index b1250c16816f5c9d..3eef52b1a59b5cb4 100644 --- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi @@ -140,10 +140,10 @@ soc { compatible = "simple-bus"; ranges; plic0: interrupt-controller@c000000 { - #interrupt-cells = <1>; compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; reg = <0x0 0xc000000 0x0 0x4000000>; - riscv,ndev = <53>; + #address-cells = <0>; + #interrupt-cells = <1>; interrupt-controller; interrupts-extended = <&cpu0_intc 0xffffffff>, @@ -151,6 +151,7 @@ plic0: interrupt-controller@c000000 { <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>, <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>, <&cpu4_intc 0xffffffff>, <&cpu4_intc 9>; + riscv,ndev = <53>; }; prci: clock-controller@10000000 { compatible = "sifive,fu540-c000-prci";