From patchwork Thu Dec 16 20:13:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Luiz Angelo Daros de Luca X-Patchwork-Id: 12682439 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD1F4C433FE for ; Thu, 16 Dec 2021 20:14:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239002AbhLPUOP (ORCPT ); Thu, 16 Dec 2021 15:14:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41376 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240623AbhLPUOO (ORCPT ); Thu, 16 Dec 2021 15:14:14 -0500 Received: from mail-qk1-x733.google.com (mail-qk1-x733.google.com [IPv6:2607:f8b0:4864:20::733]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8F3B4C061574 for ; Thu, 16 Dec 2021 12:14:14 -0800 (PST) Received: by mail-qk1-x733.google.com with SMTP id 132so56360qkj.11 for ; Thu, 16 Dec 2021 12:14:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AJle7xpTRi90OQxhDacPhG+DjfUCETSyA8Epf2KmwWg=; b=jsJTQmVwBLp1udcOPGPKg4qr44pfkBH8i1ORa0z8XfCg0CfWdloDneJtJbrHdeINTf 8a+8cqLzB/z8TlJk/dH31ktxXfYnknJt00miXXWS4Xo30VShdgzSR/mljGUholtnSOka rJKwZPg0Z0IcnuAl8Wy6URI8Pv+Lsa8hb7VCO+co7ni5SYoYx022TbfcZv4H0DCTX53D TBhvME7GUSI6ZByd80pgz1xd3eDjWwNwEK/lkIqJsw4txZPvS+mPyUUIQOkG3ngVVFKk tSqrWM02RjgzO89itWJS5DIsMLvEYK1g5eJtFZPM42znaJO377je/ez3Nd93JEJmbzgG lH8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AJle7xpTRi90OQxhDacPhG+DjfUCETSyA8Epf2KmwWg=; b=QdFtniB5qsh1u/o3DRvlTLNSLj94m7RTSOsAV/56Hlyt+R2kGX8L6l4n1+fOQ1/aSf T53UXLf1XSUR15MAPZwou10vOF1baC5Eo9FFCnNQ8NHrupaU9cMdLzp5EDDywcZCVAYZ C1EY0P6fpU6UdhzC83/3Q89QXCKa61015L8zachQt912dPiJhNcgjKmpTqet42Ug7DgP x0rDa+bbu4+q64kBS5LsUZbKlv0KR9BK1/LSDXCI1ro+LRUVJgSTJJ20fnMxyz1Fs0cN Ymw/bfv7dO7xibzuqH5I0X9Z9eL7Uvc81n7gXCQBmlpV+uIqP+GJ9hGwZVPoFtIYGLLt NBtA== X-Gm-Message-State: AOAM533JKChYOoQt9FVCsT2UVofQQvhvHmdMdOKJI7KYJ3+KwoSjPXOK y/NgtSABJRYiNUhPzXkhwL0LQdSx1K3A1w== X-Google-Smtp-Source: ABdhPJzPDW+JstwGXEOxdfe5YQDZ+cnYkj7Tv0ogKQbWTgFem0JRBsRM4VE83MFVHhaR2ZGLYXymoA== X-Received: by 2002:a37:8845:: with SMTP id k66mr13541663qkd.664.1639685653522; Thu, 16 Dec 2021 12:14:13 -0800 (PST) Received: from tresc043793.tre-sc.gov.br (187-049-235-234.floripa.net.br. [187.49.235.234]) by smtp.gmail.com with ESMTPSA id a15sm5110266qtb.5.2021.12.16.12.14.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Dec 2021 12:14:12 -0800 (PST) From: luizluca@gmail.com To: netdev@vger.kernel.org Cc: linus.walleij@linaro.org, andrew@lunn.ch, vivien.didelot@gmail.com, f.fainelli@gmail.com, olteanv@gmail.com, alsi@bang-olufsen.dk, arinc.unal@arinc9.com, Luiz Angelo Daros de Luca Subject: [PATCH net-next 01/13] dt-bindings: net: dsa: realtek-smi: remove unsupported switches Date: Thu, 16 Dec 2021 17:13:30 -0300 Message-Id: <20211216201342.25587-2-luizluca@gmail.com> X-Mailer: git-send-email 2.34.0 In-Reply-To: <20211216201342.25587-1-luizluca@gmail.com> References: <20211216201342.25587-1-luizluca@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Luiz Angelo Daros de Luca Remove some switch models that are not cited in the code. Although rtl8366s was kept, it looks like a stub driver (with a FIXME comment). Reviewed-by: Arınç ÜNAL Signed-off-by: Luiz Angelo Daros de Luca Reviewed-by: Alvin Šipraga --- .../devicetree/bindings/net/dsa/realtek-smi.txt | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/net/dsa/realtek-smi.txt b/Documentation/devicetree/bindings/net/dsa/realtek-smi.txt index 7959ec237983..3a60e77ceed4 100644 --- a/Documentation/devicetree/bindings/net/dsa/realtek-smi.txt +++ b/Documentation/devicetree/bindings/net/dsa/realtek-smi.txt @@ -4,20 +4,15 @@ Realtek SMI-based Switches The SMI "Simple Management Interface" is a two-wire protocol using bit-banged GPIO that while it reuses the MDIO lines MCK and MDIO does not use the MDIO protocol. This binding defines how to specify the -SMI-based Realtek devices. +SMI-based Realtek devices. The realtek-smi driver is a platform driver +and it must be inserted inside a platform node. Required properties: - compatible: must be exactly one of: "realtek,rtl8365mb" (4+1 ports) - "realtek,rtl8366" "realtek,rtl8366rb" (4+1 ports) "realtek,rtl8366s" (4+1 ports) - "realtek,rtl8367" - "realtek,rtl8367b" - "realtek,rtl8368s" (8 port) - "realtek,rtl8369" - "realtek,rtl8370" (8 port) Required properties: - mdc-gpios: GPIO line for the MDC clock line. From patchwork Thu Dec 16 20:13:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Luiz Angelo Daros de Luca X-Patchwork-Id: 12682441 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0CEBC433F5 for ; Thu, 16 Dec 2021 20:14:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241174AbhLPUOS (ORCPT ); Thu, 16 Dec 2021 15:14:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41392 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240623AbhLPUOS (ORCPT ); Thu, 16 Dec 2021 15:14:18 -0500 Received: from mail-qk1-x72c.google.com (mail-qk1-x72c.google.com [IPv6:2607:f8b0:4864:20::72c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 90159C061574 for ; Thu, 16 Dec 2021 12:14:17 -0800 (PST) Received: by mail-qk1-x72c.google.com with SMTP id t83so77974qke.8 for ; Thu, 16 Dec 2021 12:14:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Z1LxRgYPH4dSY5KH7ONVFKs9LemzJDJSixQwKamOflY=; b=Rs/ze+ZuGq9HUsp4snIQrpkhJHhTqwZHWHJgJVxXgk7c9/rPDFfuMDoPKryAFPlBPr yMliWzhjFZj1/jK6yAxy7FwtpkjRm7EXX3dgqolZA4tUeDsW9pj+Pl8sKvAMkxpMjTXW 5W49W1xmkGJzSQZ3WjVb/4HTdaOLebQK6z5pafakMk+aMPAi9sxMxOifPu3vitpJpX2M AHFqgxoXLfn6Z+9WAfTnPDSSquUUgR1EnZbhPziEbF7j03fveoraNTstfCLEjOHEoEjG +tTzM+cWEQ8DttKeIwR4Lqq+Z9ThgwWCKfCQ94h3bIPBp6wyZMHapnUEhxQnIVmzx60Q Y5NQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Z1LxRgYPH4dSY5KH7ONVFKs9LemzJDJSixQwKamOflY=; b=4cTmfNd7PoDgCeLfxeacA28cnlQehPAfSznD8QzNdLhpdZvosn5dnt+XN0JmJaTQMa EqQdVmsKFO7CacRCaUjdsLXCr1ygQtHZ0vWnBlBHuD7d5E/SKh//II5a7mo0QNTWV8pn 6gIFXa+ZaYYJXNpZ+zrjurN1MP61LV61H6p4dUxEGszbhgkv3BBbs5BM2x1ppt8Lv6/t MmVpnieUAQG4zuR82nkP5o6qAm+IX1JCvDFDhT+VqghhKDiMwCQiJZpWeQFgEXzIG/cw PAXAGdTTXL9t8yaK4CeTeG5VEZ3BaXBNsm2S0u6NxMVOXwKysNaLBfAZXeAvG3U4TLy6 otxQ== X-Gm-Message-State: AOAM532vXn+3cBIj2JV3XRN40RAqN3mUXNtWplHuA9zs37OY83BaTz0U ALzp1nksSEQChIiSFi+kSqIZ4CVh0GTBDQ== X-Google-Smtp-Source: ABdhPJwfDU/6OjHpH4A/siKW9LTT1MIffxAq6alOfJGz6LUULUzvxlSAwCgDVFQMhoU0UQMs2vBseA== X-Received: by 2002:a37:9fce:: with SMTP id i197mr13634392qke.67.1639685656450; Thu, 16 Dec 2021 12:14:16 -0800 (PST) Received: from tresc043793.tre-sc.gov.br (187-049-235-234.floripa.net.br. [187.49.235.234]) by smtp.gmail.com with ESMTPSA id a15sm5110266qtb.5.2021.12.16.12.14.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Dec 2021 12:14:16 -0800 (PST) From: luizluca@gmail.com To: netdev@vger.kernel.org Cc: linus.walleij@linaro.org, andrew@lunn.ch, vivien.didelot@gmail.com, f.fainelli@gmail.com, olteanv@gmail.com, alsi@bang-olufsen.dk, arinc.unal@arinc9.com, Luiz Angelo Daros de Luca Subject: [PATCH net-next 02/13] net: dsa: realtek-smi: move to subdirectory Date: Thu, 16 Dec 2021 17:13:31 -0300 Message-Id: <20211216201342.25587-3-luizluca@gmail.com> X-Mailer: git-send-email 2.34.0 In-Reply-To: <20211216201342.25587-1-luizluca@gmail.com> References: <20211216201342.25587-1-luizluca@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Luiz Angelo Daros de Luca Tested-by: Arınç ÜNAL Signed-off-by: Luiz Angelo Daros de Luca Reviewed-by: Alvin Šipraga Reviewed-by: Linus Walleij --- MAINTAINERS | 3 +-- drivers/net/dsa/Kconfig | 12 +----------- drivers/net/dsa/Makefile | 3 +-- drivers/net/dsa/realtek/Kconfig | 19 +++++++++++++++++++ drivers/net/dsa/realtek/Makefile | 3 +++ .../net/dsa/{ => realtek}/realtek-smi-core.c | 0 .../net/dsa/{ => realtek}/realtek-smi-core.h | 0 drivers/net/dsa/{ => realtek}/rtl8365mb.c | 0 drivers/net/dsa/{ => realtek}/rtl8366.c | 0 drivers/net/dsa/{ => realtek}/rtl8366rb.c | 0 10 files changed, 25 insertions(+), 15 deletions(-) create mode 100644 drivers/net/dsa/realtek/Kconfig create mode 100644 drivers/net/dsa/realtek/Makefile rename drivers/net/dsa/{ => realtek}/realtek-smi-core.c (100%) rename drivers/net/dsa/{ => realtek}/realtek-smi-core.h (100%) rename drivers/net/dsa/{ => realtek}/rtl8365mb.c (100%) rename drivers/net/dsa/{ => realtek}/rtl8366.c (100%) rename drivers/net/dsa/{ => realtek}/rtl8366rb.c (100%) diff --git a/MAINTAINERS b/MAINTAINERS index 19d6fccf1205..a8f949b368a8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -16153,8 +16153,7 @@ REALTEK RTL83xx SMI DSA ROUTER CHIPS M: Linus Walleij S: Maintained F: Documentation/devicetree/bindings/net/dsa/realtek-smi.txt -F: drivers/net/dsa/realtek-smi* -F: drivers/net/dsa/rtl83* +F: drivers/net/dsa/realtek/* REALTEK WIRELESS DRIVER (rtlwifi family) M: Ping-Ke Shih diff --git a/drivers/net/dsa/Kconfig b/drivers/net/dsa/Kconfig index 7b1457a6e327..1251caf0f638 100644 --- a/drivers/net/dsa/Kconfig +++ b/drivers/net/dsa/Kconfig @@ -67,17 +67,7 @@ config NET_DSA_QCA8K This enables support for the Qualcomm Atheros QCA8K Ethernet switch chips. -config NET_DSA_REALTEK_SMI - tristate "Realtek SMI Ethernet switch family support" - select NET_DSA_TAG_RTL4_A - select NET_DSA_TAG_RTL8_4 - select FIXED_PHY - select IRQ_DOMAIN - select REALTEK_PHY - select REGMAP - help - This enables support for the Realtek SMI-based switch - chips, currently only RTL8366RB. +source "drivers/net/dsa/realtek/Kconfig" config NET_DSA_SMSC_LAN9303 tristate diff --git a/drivers/net/dsa/Makefile b/drivers/net/dsa/Makefile index 8da1569a34e6..e73838c12256 100644 --- a/drivers/net/dsa/Makefile +++ b/drivers/net/dsa/Makefile @@ -9,8 +9,6 @@ obj-$(CONFIG_NET_DSA_LANTIQ_GSWIP) += lantiq_gswip.o obj-$(CONFIG_NET_DSA_MT7530) += mt7530.o obj-$(CONFIG_NET_DSA_MV88E6060) += mv88e6060.o obj-$(CONFIG_NET_DSA_QCA8K) += qca8k.o -obj-$(CONFIG_NET_DSA_REALTEK_SMI) += realtek-smi.o -realtek-smi-objs := realtek-smi-core.o rtl8366.o rtl8366rb.o rtl8365mb.o obj-$(CONFIG_NET_DSA_SMSC_LAN9303) += lan9303-core.o obj-$(CONFIG_NET_DSA_SMSC_LAN9303_I2C) += lan9303_i2c.o obj-$(CONFIG_NET_DSA_SMSC_LAN9303_MDIO) += lan9303_mdio.o @@ -23,5 +21,6 @@ obj-y += microchip/ obj-y += mv88e6xxx/ obj-y += ocelot/ obj-y += qca/ +obj-y += realtek/ obj-y += sja1105/ obj-y += xrs700x/ diff --git a/drivers/net/dsa/realtek/Kconfig b/drivers/net/dsa/realtek/Kconfig new file mode 100644 index 000000000000..bbc6e918baa6 --- /dev/null +++ b/drivers/net/dsa/realtek/Kconfig @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0-only +menuconfig NET_DSA_REALTEK + tristate "Realtek Ethernet switch family support" + depends on NET_DSA + select NET_DSA_TAG_RTL4_A + select NET_DSA_TAG_RTL8_4 + select FIXED_PHY + select IRQ_DOMAIN + select REALTEK_PHY + select REGMAP + help + Select to enable support for Realtek Ethernet switch chips. + +config NET_DSA_REALTEK_SMI + tristate "Realtek SMI connected switch driver" + depends on NET_DSA_REALTEK + default y + help + Select to enable support for registering switches connected through SMI. diff --git a/drivers/net/dsa/realtek/Makefile b/drivers/net/dsa/realtek/Makefile new file mode 100644 index 000000000000..323b921bfce0 --- /dev/null +++ b/drivers/net/dsa/realtek/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_NET_DSA_REALTEK_SMI) += realtek-smi.o +realtek-smi-objs := realtek-smi-core.o rtl8366.o rtl8366rb.o rtl8365mb.o diff --git a/drivers/net/dsa/realtek-smi-core.c b/drivers/net/dsa/realtek/realtek-smi-core.c similarity index 100% rename from drivers/net/dsa/realtek-smi-core.c rename to drivers/net/dsa/realtek/realtek-smi-core.c diff --git a/drivers/net/dsa/realtek-smi-core.h b/drivers/net/dsa/realtek/realtek-smi-core.h similarity index 100% rename from drivers/net/dsa/realtek-smi-core.h rename to drivers/net/dsa/realtek/realtek-smi-core.h diff --git a/drivers/net/dsa/rtl8365mb.c b/drivers/net/dsa/realtek/rtl8365mb.c similarity index 100% rename from drivers/net/dsa/rtl8365mb.c rename to drivers/net/dsa/realtek/rtl8365mb.c diff --git a/drivers/net/dsa/rtl8366.c b/drivers/net/dsa/realtek/rtl8366.c similarity index 100% rename from drivers/net/dsa/rtl8366.c rename to drivers/net/dsa/realtek/rtl8366.c diff --git a/drivers/net/dsa/rtl8366rb.c b/drivers/net/dsa/realtek/rtl8366rb.c similarity index 100% rename from drivers/net/dsa/rtl8366rb.c rename to drivers/net/dsa/realtek/rtl8366rb.c From patchwork Thu Dec 16 20:13:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 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[187.49.235.234]) by smtp.gmail.com with ESMTPSA id a15sm5110266qtb.5.2021.12.16.12.14.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Dec 2021 12:14:19 -0800 (PST) From: luizluca@gmail.com To: netdev@vger.kernel.org Cc: linus.walleij@linaro.org, andrew@lunn.ch, vivien.didelot@gmail.com, f.fainelli@gmail.com, olteanv@gmail.com, alsi@bang-olufsen.dk, arinc.unal@arinc9.com, Luiz Angelo Daros de Luca Subject: [PATCH net-next 03/13] net: dsa: realtek: rename realtek_smi to realtek_priv Date: Thu, 16 Dec 2021 17:13:32 -0300 Message-Id: <20211216201342.25587-4-luizluca@gmail.com> X-Mailer: git-send-email 2.34.0 In-Reply-To: <20211216201342.25587-1-luizluca@gmail.com> References: <20211216201342.25587-1-luizluca@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Luiz Angelo Daros de Luca In preparation to adding other interfaces, the private data structure was renamed to priv. Also the only two direct calls from subdrivers to realtek-smi lib were converted into references inside priv. Tested-by: Arınç ÜNAL Signed-off-by: Luiz Angelo Daros de Luca --- drivers/net/dsa/realtek/realtek-smi-core.c | 314 +++++++------- .../realtek/{realtek-smi-core.h => realtek.h} | 71 ++-- drivers/net/dsa/realtek/rtl8365mb.c | 400 +++++++++--------- drivers/net/dsa/realtek/rtl8366.c | 164 +++---- drivers/net/dsa/realtek/rtl8366rb.c | 390 ++++++++--------- 5 files changed, 669 insertions(+), 670 deletions(-) rename drivers/net/dsa/realtek/{realtek-smi-core.h => realtek.h} (56%) diff --git a/drivers/net/dsa/realtek/realtek-smi-core.c b/drivers/net/dsa/realtek/realtek-smi-core.c index aae46ada8d83..2c78eb5c0bdc 100644 --- a/drivers/net/dsa/realtek/realtek-smi-core.c +++ b/drivers/net/dsa/realtek/realtek-smi-core.c @@ -40,105 +40,105 @@ #include #include -#include "realtek-smi-core.h" +#include "realtek.h" #define REALTEK_SMI_ACK_RETRY_COUNT 5 #define REALTEK_SMI_HW_STOP_DELAY 25 /* msecs */ #define REALTEK_SMI_HW_START_DELAY 100 /* msecs */ -static inline void realtek_smi_clk_delay(struct realtek_smi *smi) +static inline void realtek_smi_clk_delay(struct realtek_priv *priv) { - ndelay(smi->clk_delay); + ndelay(priv->clk_delay); } -static void realtek_smi_start(struct realtek_smi *smi) +static void realtek_smi_start(struct realtek_priv *priv) { /* Set GPIO pins to output mode, with initial state: * SCK = 0, SDA = 1 */ - gpiod_direction_output(smi->mdc, 0); - gpiod_direction_output(smi->mdio, 1); - realtek_smi_clk_delay(smi); + gpiod_direction_output(priv->mdc, 0); + gpiod_direction_output(priv->mdio, 1); + realtek_smi_clk_delay(priv); /* CLK 1: 0 -> 1, 1 -> 0 */ - gpiod_set_value(smi->mdc, 1); - realtek_smi_clk_delay(smi); - gpiod_set_value(smi->mdc, 0); - realtek_smi_clk_delay(smi); + gpiod_set_value(priv->mdc, 1); + realtek_smi_clk_delay(priv); + gpiod_set_value(priv->mdc, 0); + realtek_smi_clk_delay(priv); /* CLK 2: */ - gpiod_set_value(smi->mdc, 1); - realtek_smi_clk_delay(smi); - gpiod_set_value(smi->mdio, 0); - realtek_smi_clk_delay(smi); - gpiod_set_value(smi->mdc, 0); - realtek_smi_clk_delay(smi); - gpiod_set_value(smi->mdio, 1); + gpiod_set_value(priv->mdc, 1); + realtek_smi_clk_delay(priv); + gpiod_set_value(priv->mdio, 0); + realtek_smi_clk_delay(priv); + gpiod_set_value(priv->mdc, 0); + realtek_smi_clk_delay(priv); + gpiod_set_value(priv->mdio, 1); } -static void realtek_smi_stop(struct realtek_smi *smi) +static void realtek_smi_stop(struct realtek_priv *priv) { - realtek_smi_clk_delay(smi); - gpiod_set_value(smi->mdio, 0); - gpiod_set_value(smi->mdc, 1); - realtek_smi_clk_delay(smi); - gpiod_set_value(smi->mdio, 1); - realtek_smi_clk_delay(smi); - gpiod_set_value(smi->mdc, 1); - realtek_smi_clk_delay(smi); - gpiod_set_value(smi->mdc, 0); - realtek_smi_clk_delay(smi); - gpiod_set_value(smi->mdc, 1); + realtek_smi_clk_delay(priv); + gpiod_set_value(priv->mdio, 0); + gpiod_set_value(priv->mdc, 1); + realtek_smi_clk_delay(priv); + gpiod_set_value(priv->mdio, 1); + realtek_smi_clk_delay(priv); + gpiod_set_value(priv->mdc, 1); + realtek_smi_clk_delay(priv); + gpiod_set_value(priv->mdc, 0); + realtek_smi_clk_delay(priv); + gpiod_set_value(priv->mdc, 1); /* Add a click */ - realtek_smi_clk_delay(smi); - gpiod_set_value(smi->mdc, 0); - realtek_smi_clk_delay(smi); - gpiod_set_value(smi->mdc, 1); + realtek_smi_clk_delay(priv); + gpiod_set_value(priv->mdc, 0); + realtek_smi_clk_delay(priv); + gpiod_set_value(priv->mdc, 1); /* Set GPIO pins to input mode */ - gpiod_direction_input(smi->mdio); - gpiod_direction_input(smi->mdc); + gpiod_direction_input(priv->mdio); + gpiod_direction_input(priv->mdc); } -static void realtek_smi_write_bits(struct realtek_smi *smi, u32 data, u32 len) +static void realtek_smi_write_bits(struct realtek_priv *priv, u32 data, u32 len) { for (; len > 0; len--) { - realtek_smi_clk_delay(smi); + realtek_smi_clk_delay(priv); /* Prepare data */ - gpiod_set_value(smi->mdio, !!(data & (1 << (len - 1)))); - realtek_smi_clk_delay(smi); + gpiod_set_value(priv->mdio, !!(data & (1 << (len - 1)))); + realtek_smi_clk_delay(priv); /* Clocking */ - gpiod_set_value(smi->mdc, 1); - realtek_smi_clk_delay(smi); - gpiod_set_value(smi->mdc, 0); + gpiod_set_value(priv->mdc, 1); + realtek_smi_clk_delay(priv); + gpiod_set_value(priv->mdc, 0); } } -static void realtek_smi_read_bits(struct realtek_smi *smi, u32 len, u32 *data) +static void realtek_smi_read_bits(struct realtek_priv *priv, u32 len, u32 *data) { - gpiod_direction_input(smi->mdio); + gpiod_direction_input(priv->mdio); for (*data = 0; len > 0; len--) { u32 u; - realtek_smi_clk_delay(smi); + realtek_smi_clk_delay(priv); /* Clocking */ - gpiod_set_value(smi->mdc, 1); - realtek_smi_clk_delay(smi); - u = !!gpiod_get_value(smi->mdio); - gpiod_set_value(smi->mdc, 0); + gpiod_set_value(priv->mdc, 1); + realtek_smi_clk_delay(priv); + u = !!gpiod_get_value(priv->mdio); + gpiod_set_value(priv->mdc, 0); *data |= (u << (len - 1)); } - gpiod_direction_output(smi->mdio, 0); + gpiod_direction_output(priv->mdio, 0); } -static int realtek_smi_wait_for_ack(struct realtek_smi *smi) +static int realtek_smi_wait_for_ack(struct realtek_priv *priv) { int retry_cnt; @@ -146,12 +146,12 @@ static int realtek_smi_wait_for_ack(struct realtek_smi *smi) do { u32 ack; - realtek_smi_read_bits(smi, 1, &ack); + realtek_smi_read_bits(priv, 1, &ack); if (ack == 0) break; if (++retry_cnt > REALTEK_SMI_ACK_RETRY_COUNT) { - dev_err(smi->dev, "ACK timeout\n"); + dev_err(priv->dev, "ACK timeout\n"); return -ETIMEDOUT; } } while (1); @@ -159,131 +159,131 @@ static int realtek_smi_wait_for_ack(struct realtek_smi *smi) return 0; } -static int realtek_smi_write_byte(struct realtek_smi *smi, u8 data) +static int realtek_smi_write_byte(struct realtek_priv *priv, u8 data) { - realtek_smi_write_bits(smi, data, 8); - return realtek_smi_wait_for_ack(smi); + realtek_smi_write_bits(priv, data, 8); + return realtek_smi_wait_for_ack(priv); } -static int realtek_smi_write_byte_noack(struct realtek_smi *smi, u8 data) +static int realtek_smi_write_byte_noack(struct realtek_priv *priv, u8 data) { - realtek_smi_write_bits(smi, data, 8); + realtek_smi_write_bits(priv, data, 8); return 0; } -static int realtek_smi_read_byte0(struct realtek_smi *smi, u8 *data) +static int realtek_smi_read_byte0(struct realtek_priv *priv, u8 *data) { u32 t; /* Read data */ - realtek_smi_read_bits(smi, 8, &t); + realtek_smi_read_bits(priv, 8, &t); *data = (t & 0xff); /* Send an ACK */ - realtek_smi_write_bits(smi, 0x00, 1); + realtek_smi_write_bits(priv, 0x00, 1); return 0; } -static int realtek_smi_read_byte1(struct realtek_smi *smi, u8 *data) +static int realtek_smi_read_byte1(struct realtek_priv *priv, u8 *data) { u32 t; /* Read data */ - realtek_smi_read_bits(smi, 8, &t); + realtek_smi_read_bits(priv, 8, &t); *data = (t & 0xff); /* Send an ACK */ - realtek_smi_write_bits(smi, 0x01, 1); + realtek_smi_write_bits(priv, 0x01, 1); return 0; } -static int realtek_smi_read_reg(struct realtek_smi *smi, u32 addr, u32 *data) +static int realtek_smi_read_reg(struct realtek_priv *priv, u32 addr, u32 *data) { unsigned long flags; u8 lo = 0; u8 hi = 0; int ret; - spin_lock_irqsave(&smi->lock, flags); + spin_lock_irqsave(&priv->lock, flags); - realtek_smi_start(smi); + realtek_smi_start(priv); /* Send READ command */ - ret = realtek_smi_write_byte(smi, smi->cmd_read); + ret = realtek_smi_write_byte(priv, priv->cmd_read); if (ret) goto out; /* Set ADDR[7:0] */ - ret = realtek_smi_write_byte(smi, addr & 0xff); + ret = realtek_smi_write_byte(priv, addr & 0xff); if (ret) goto out; /* Set ADDR[15:8] */ - ret = realtek_smi_write_byte(smi, addr >> 8); + ret = realtek_smi_write_byte(priv, addr >> 8); if (ret) goto out; /* Read DATA[7:0] */ - realtek_smi_read_byte0(smi, &lo); + realtek_smi_read_byte0(priv, &lo); /* Read DATA[15:8] */ - realtek_smi_read_byte1(smi, &hi); + realtek_smi_read_byte1(priv, &hi); *data = ((u32)lo) | (((u32)hi) << 8); ret = 0; out: - realtek_smi_stop(smi); - spin_unlock_irqrestore(&smi->lock, flags); + realtek_smi_stop(priv); + spin_unlock_irqrestore(&priv->lock, flags); return ret; } -static int realtek_smi_write_reg(struct realtek_smi *smi, +static int realtek_smi_write_reg(struct realtek_priv *priv, u32 addr, u32 data, bool ack) { unsigned long flags; int ret; - spin_lock_irqsave(&smi->lock, flags); + spin_lock_irqsave(&priv->lock, flags); - realtek_smi_start(smi); + realtek_smi_start(priv); /* Send WRITE command */ - ret = realtek_smi_write_byte(smi, smi->cmd_write); + ret = realtek_smi_write_byte(priv, priv->cmd_write); if (ret) goto out; /* Set ADDR[7:0] */ - ret = realtek_smi_write_byte(smi, addr & 0xff); + ret = realtek_smi_write_byte(priv, addr & 0xff); if (ret) goto out; /* Set ADDR[15:8] */ - ret = realtek_smi_write_byte(smi, addr >> 8); + ret = realtek_smi_write_byte(priv, addr >> 8); if (ret) goto out; /* Write DATA[7:0] */ - ret = realtek_smi_write_byte(smi, data & 0xff); + ret = realtek_smi_write_byte(priv, data & 0xff); if (ret) goto out; /* Write DATA[15:8] */ if (ack) - ret = realtek_smi_write_byte(smi, data >> 8); + ret = realtek_smi_write_byte(priv, data >> 8); else - ret = realtek_smi_write_byte_noack(smi, data >> 8); + ret = realtek_smi_write_byte_noack(priv, data >> 8); if (ret) goto out; ret = 0; out: - realtek_smi_stop(smi); - spin_unlock_irqrestore(&smi->lock, flags); + realtek_smi_stop(priv); + spin_unlock_irqrestore(&priv->lock, flags); return ret; } @@ -292,10 +292,10 @@ static int realtek_smi_write_reg(struct realtek_smi *smi, * is when issueing soft reset. Since the device reset as soon as we write * that bit, no ACK will come back for natural reasons. */ -int realtek_smi_write_reg_noack(struct realtek_smi *smi, u32 addr, +int realtek_smi_write_reg_noack(struct realtek_priv *priv, u32 addr, u32 data) { - return realtek_smi_write_reg(smi, addr, data, false); + return realtek_smi_write_reg(priv, addr, data, false); } EXPORT_SYMBOL_GPL(realtek_smi_write_reg_noack); @@ -303,16 +303,16 @@ EXPORT_SYMBOL_GPL(realtek_smi_write_reg_noack); static int realtek_smi_write(void *ctx, u32 reg, u32 val) { - struct realtek_smi *smi = ctx; + struct realtek_priv *priv = ctx; - return realtek_smi_write_reg(smi, reg, val, true); + return realtek_smi_write_reg(priv, reg, val, true); } static int realtek_smi_read(void *ctx, u32 reg, u32 *val) { - struct realtek_smi *smi = ctx; + struct realtek_priv *priv = ctx; - return realtek_smi_read_reg(smi, reg, val); + return realtek_smi_read_reg(priv, reg, val); } static const struct regmap_config realtek_smi_mdio_regmap_config = { @@ -329,49 +329,49 @@ static const struct regmap_config realtek_smi_mdio_regmap_config = { static int realtek_smi_mdio_read(struct mii_bus *bus, int addr, int regnum) { - struct realtek_smi *smi = bus->priv; + struct realtek_priv *priv = bus->priv; - return smi->ops->phy_read(smi, addr, regnum); + return priv->ops->phy_read(priv, addr, regnum); } static int realtek_smi_mdio_write(struct mii_bus *bus, int addr, int regnum, u16 val) { - struct realtek_smi *smi = bus->priv; + struct realtek_priv *priv = bus->priv; - return smi->ops->phy_write(smi, addr, regnum, val); + return priv->ops->phy_write(priv, addr, regnum, val); } -int realtek_smi_setup_mdio(struct realtek_smi *smi) +int realtek_smi_setup_mdio(struct realtek_priv *priv) { struct device_node *mdio_np; int ret; - mdio_np = of_get_compatible_child(smi->dev->of_node, "realtek,smi-mdio"); + mdio_np = of_get_compatible_child(priv->dev->of_node, "realtek,smi-mdio"); if (!mdio_np) { - dev_err(smi->dev, "no MDIO bus node\n"); + dev_err(priv->dev, "no MDIO bus node\n"); return -ENODEV; } - smi->slave_mii_bus = devm_mdiobus_alloc(smi->dev); - if (!smi->slave_mii_bus) { + priv->slave_mii_bus = devm_mdiobus_alloc(priv->dev); + if (!priv->slave_mii_bus) { ret = -ENOMEM; goto err_put_node; } - smi->slave_mii_bus->priv = smi; - smi->slave_mii_bus->name = "SMI slave MII"; - smi->slave_mii_bus->read = realtek_smi_mdio_read; - smi->slave_mii_bus->write = realtek_smi_mdio_write; - snprintf(smi->slave_mii_bus->id, MII_BUS_ID_SIZE, "SMI-%d", - smi->ds->index); - smi->slave_mii_bus->dev.of_node = mdio_np; - smi->slave_mii_bus->parent = smi->dev; - smi->ds->slave_mii_bus = smi->slave_mii_bus; - - ret = devm_of_mdiobus_register(smi->dev, smi->slave_mii_bus, mdio_np); + priv->slave_mii_bus->priv = priv; + priv->slave_mii_bus->name = "SMI slave MII"; + priv->slave_mii_bus->read = realtek_smi_mdio_read; + priv->slave_mii_bus->write = realtek_smi_mdio_write; + snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "SMI-%d", + priv->ds->index); + priv->slave_mii_bus->dev.of_node = mdio_np; + priv->slave_mii_bus->parent = priv->dev; + priv->ds->slave_mii_bus = priv->slave_mii_bus; + + ret = devm_of_mdiobus_register(priv->dev, priv->slave_mii_bus, mdio_np); if (ret) { - dev_err(smi->dev, "unable to register MDIO bus %s\n", - smi->slave_mii_bus->id); + dev_err(priv->dev, "unable to register MDIO bus %s\n", + priv->slave_mii_bus->id); goto err_put_node; } @@ -385,76 +385,76 @@ int realtek_smi_setup_mdio(struct realtek_smi *smi) static int realtek_smi_probe(struct platform_device *pdev) { - const struct realtek_smi_variant *var; + const struct realtek_variant *var; struct device *dev = &pdev->dev; - struct realtek_smi *smi; + struct realtek_priv *priv; struct device_node *np; int ret; var = of_device_get_match_data(dev); np = dev->of_node; - smi = devm_kzalloc(dev, sizeof(*smi) + var->chip_data_sz, GFP_KERNEL); - if (!smi) + priv = devm_kzalloc(dev, sizeof(*priv) + var->chip_data_sz, GFP_KERNEL); + if (!priv) return -ENOMEM; - smi->chip_data = (void *)smi + sizeof(*smi); - smi->map = devm_regmap_init(dev, NULL, smi, + priv->chip_data = (void *)priv + sizeof(*priv); + priv->map = devm_regmap_init(dev, NULL, priv, &realtek_smi_mdio_regmap_config); - if (IS_ERR(smi->map)) { - ret = PTR_ERR(smi->map); + if (IS_ERR(priv->map)) { + ret = PTR_ERR(priv->map); dev_err(dev, "regmap init failed: %d\n", ret); return ret; } /* Link forward and backward */ - smi->dev = dev; - smi->clk_delay = var->clk_delay; - smi->cmd_read = var->cmd_read; - smi->cmd_write = var->cmd_write; - smi->ops = var->ops; + priv->dev = dev; + priv->clk_delay = var->clk_delay; + priv->cmd_read = var->cmd_read; + priv->cmd_write = var->cmd_write; + priv->ops = var->ops; - dev_set_drvdata(dev, smi); - spin_lock_init(&smi->lock); + dev_set_drvdata(dev, priv); + spin_lock_init(&priv->lock); /* TODO: if power is software controlled, set up any regulators here */ /* Assert then deassert RESET */ - smi->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); - if (IS_ERR(smi->reset)) { + priv->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(priv->reset)) { dev_err(dev, "failed to get RESET GPIO\n"); - return PTR_ERR(smi->reset); + return PTR_ERR(priv->reset); } msleep(REALTEK_SMI_HW_STOP_DELAY); - gpiod_set_value(smi->reset, 0); + gpiod_set_value(priv->reset, 0); msleep(REALTEK_SMI_HW_START_DELAY); dev_info(dev, "deasserted RESET\n"); /* Fetch MDIO pins */ - smi->mdc = devm_gpiod_get_optional(dev, "mdc", GPIOD_OUT_LOW); - if (IS_ERR(smi->mdc)) - return PTR_ERR(smi->mdc); - smi->mdio = devm_gpiod_get_optional(dev, "mdio", GPIOD_OUT_LOW); - if (IS_ERR(smi->mdio)) - return PTR_ERR(smi->mdio); + priv->mdc = devm_gpiod_get_optional(dev, "mdc", GPIOD_OUT_LOW); + if (IS_ERR(priv->mdc)) + return PTR_ERR(priv->mdc); + priv->mdio = devm_gpiod_get_optional(dev, "mdio", GPIOD_OUT_LOW); + if (IS_ERR(priv->mdio)) + return PTR_ERR(priv->mdio); - smi->leds_disabled = of_property_read_bool(np, "realtek,disable-leds"); + priv->leds_disabled = of_property_read_bool(np, "realtek,disable-leds"); - ret = smi->ops->detect(smi); + ret = priv->ops->detect(priv); if (ret) { dev_err(dev, "unable to detect switch\n"); return ret; } - smi->ds = devm_kzalloc(dev, sizeof(*smi->ds), GFP_KERNEL); - if (!smi->ds) + priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL); + if (!priv->ds) return -ENOMEM; - smi->ds->dev = dev; - smi->ds->num_ports = smi->num_ports; - smi->ds->priv = smi; + priv->ds->dev = dev; + priv->ds->num_ports = priv->num_ports; + priv->ds->priv = priv; - smi->ds->ops = var->ds_ops; - ret = dsa_register_switch(smi->ds); + priv->ds->ops = var->ds_ops; + ret = dsa_register_switch(priv->ds); if (ret) { dev_err_probe(dev, ret, "unable to register switch\n"); return ret; @@ -464,15 +464,15 @@ static int realtek_smi_probe(struct platform_device *pdev) static int realtek_smi_remove(struct platform_device *pdev) { - struct realtek_smi *smi = platform_get_drvdata(pdev); + struct realtek_priv *priv = platform_get_drvdata(pdev); - if (!smi) + if (!priv) return 0; - dsa_unregister_switch(smi->ds); - if (smi->slave_mii_bus) - of_node_put(smi->slave_mii_bus->dev.of_node); - gpiod_set_value(smi->reset, 1); + dsa_unregister_switch(priv->ds); + if (priv->slave_mii_bus) + of_node_put(priv->slave_mii_bus->dev.of_node); + gpiod_set_value(priv->reset, 1); platform_set_drvdata(pdev, NULL); @@ -481,12 +481,12 @@ static int realtek_smi_remove(struct platform_device *pdev) static void realtek_smi_shutdown(struct platform_device *pdev) { - struct realtek_smi *smi = platform_get_drvdata(pdev); + struct realtek_priv *priv = platform_get_drvdata(pdev); - if (!smi) + if (!priv) return; - dsa_switch_shutdown(smi->ds); + dsa_switch_shutdown(priv->ds); platform_set_drvdata(pdev, NULL); } diff --git a/drivers/net/dsa/realtek/realtek-smi-core.h b/drivers/net/dsa/realtek/realtek.h similarity index 56% rename from drivers/net/dsa/realtek/realtek-smi-core.h rename to drivers/net/dsa/realtek/realtek.h index 5bfa53e2480a..766e79151a6c 100644 --- a/drivers/net/dsa/realtek/realtek-smi-core.h +++ b/drivers/net/dsa/realtek/realtek.h @@ -13,7 +13,7 @@ #include #include -struct realtek_smi_ops; +struct realtek_ops; struct dentry; struct inode; struct file; @@ -43,7 +43,7 @@ struct rtl8366_vlan_4k { u8 fid; }; -struct realtek_smi { +struct realtek_priv { struct device *dev; struct gpio_desc *reset; struct gpio_desc *mdc; @@ -65,7 +65,9 @@ struct realtek_smi { unsigned int num_mib_counters; struct rtl8366_mib_counter *mib_counters; - const struct realtek_smi_ops *ops; + const struct realtek_ops *ops; + int (*setup_interface)(struct dsa_switch *ds); + int (*write_reg_noack)(struct realtek_priv *priv, u32 addr, u32 data); int vlan_enabled; int vlan4k_enabled; @@ -75,60 +77,55 @@ struct realtek_smi { }; /** - * struct realtek_smi_ops - vtable for the per-SMI-chiptype operations + * struct realtek_ops - vtable for the per-SMI-chiptype operations * @detect: detects the chiptype */ -struct realtek_smi_ops { - int (*detect)(struct realtek_smi *smi); - int (*reset_chip)(struct realtek_smi *smi); - int (*setup)(struct realtek_smi *smi); - void (*cleanup)(struct realtek_smi *smi); - int (*get_mib_counter)(struct realtek_smi *smi, +struct realtek_ops { + int (*detect)(struct realtek_priv *priv); + int (*reset_chip)(struct realtek_priv *priv); + int (*setup)(struct realtek_priv *priv); + void (*cleanup)(struct realtek_priv *priv); + int (*get_mib_counter)(struct realtek_priv *priv, int port, struct rtl8366_mib_counter *mib, u64 *mibvalue); - int (*get_vlan_mc)(struct realtek_smi *smi, u32 index, + int (*get_vlan_mc)(struct realtek_priv *priv, u32 index, struct rtl8366_vlan_mc *vlanmc); - int (*set_vlan_mc)(struct realtek_smi *smi, u32 index, + int (*set_vlan_mc)(struct realtek_priv *priv, u32 index, const struct rtl8366_vlan_mc *vlanmc); - int (*get_vlan_4k)(struct realtek_smi *smi, u32 vid, + int (*get_vlan_4k)(struct realtek_priv *priv, u32 vid, struct rtl8366_vlan_4k *vlan4k); - int (*set_vlan_4k)(struct realtek_smi *smi, + int (*set_vlan_4k)(struct realtek_priv *priv, const struct rtl8366_vlan_4k *vlan4k); - int (*get_mc_index)(struct realtek_smi *smi, int port, int *val); - int (*set_mc_index)(struct realtek_smi *smi, int port, int index); - bool (*is_vlan_valid)(struct realtek_smi *smi, unsigned int vlan); - int (*enable_vlan)(struct realtek_smi *smi, bool enable); - int (*enable_vlan4k)(struct realtek_smi *smi, bool enable); - int (*enable_port)(struct realtek_smi *smi, int port, bool enable); - int (*phy_read)(struct realtek_smi *smi, int phy, int regnum); - int (*phy_write)(struct realtek_smi *smi, int phy, int regnum, + int (*get_mc_index)(struct realtek_priv *priv, int port, int *val); + int (*set_mc_index)(struct realtek_priv *priv, int port, int index); + bool (*is_vlan_valid)(struct realtek_priv *priv, unsigned int vlan); + int (*enable_vlan)(struct realtek_priv *priv, bool enable); + int (*enable_vlan4k)(struct realtek_priv *priv, bool enable); + int (*enable_port)(struct realtek_priv *priv, int port, bool enable); + int (*phy_read)(struct realtek_priv *priv, int phy, int regnum); + int (*phy_write)(struct realtek_priv *priv, int phy, int regnum, u16 val); }; -struct realtek_smi_variant { +struct realtek_variant { const struct dsa_switch_ops *ds_ops; - const struct realtek_smi_ops *ops; + const struct realtek_ops *ops; unsigned int clk_delay; u8 cmd_read; u8 cmd_write; size_t chip_data_sz; }; -/* SMI core calls */ -int realtek_smi_write_reg_noack(struct realtek_smi *smi, u32 addr, - u32 data); -int realtek_smi_setup_mdio(struct realtek_smi *smi); - /* RTL8366 library helpers */ -int rtl8366_mc_is_used(struct realtek_smi *smi, int mc_index, int *used); -int rtl8366_set_vlan(struct realtek_smi *smi, int vid, u32 member, +int rtl8366_mc_is_used(struct realtek_priv *priv, int mc_index, int *used); +int rtl8366_set_vlan(struct realtek_priv *priv, int vid, u32 member, u32 untag, u32 fid); -int rtl8366_set_pvid(struct realtek_smi *smi, unsigned int port, +int rtl8366_set_pvid(struct realtek_priv *priv, unsigned int port, unsigned int vid); -int rtl8366_enable_vlan4k(struct realtek_smi *smi, bool enable); -int rtl8366_enable_vlan(struct realtek_smi *smi, bool enable); -int rtl8366_reset_vlan(struct realtek_smi *smi); +int rtl8366_enable_vlan4k(struct realtek_priv *priv, bool enable); +int rtl8366_enable_vlan(struct realtek_priv *priv, bool enable); +int rtl8366_reset_vlan(struct realtek_priv *priv); int rtl8366_vlan_add(struct dsa_switch *ds, int port, const struct switchdev_obj_port_vlan *vlan, struct netlink_ext_ack *extack); @@ -139,7 +136,7 @@ void rtl8366_get_strings(struct dsa_switch *ds, int port, u32 stringset, int rtl8366_get_sset_count(struct dsa_switch *ds, int port, int sset); void rtl8366_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data); -extern const struct realtek_smi_variant rtl8366rb_variant; -extern const struct realtek_smi_variant rtl8365mb_variant; +extern const struct realtek_variant rtl8366rb_variant; +extern const struct realtek_variant rtl8365mb_variant; #endif /* _REALTEK_SMI_H */ diff --git a/drivers/net/dsa/realtek/rtl8365mb.c b/drivers/net/dsa/realtek/rtl8365mb.c index 3b729544798b..f562a6efb574 100644 --- a/drivers/net/dsa/realtek/rtl8365mb.c +++ b/drivers/net/dsa/realtek/rtl8365mb.c @@ -99,7 +99,7 @@ #include #include -#include "realtek-smi-core.h" +#include "realtek.h" /* Chip-specific data and limits */ #define RTL8365MB_CHIP_ID_8365MB_VC 0x6367 @@ -516,7 +516,7 @@ struct rtl8365mb_cpu { /** * struct rtl8365mb_port - private per-port data - * @smi: pointer to parent realtek_smi data + * @priv: pointer to parent realtek_priv data * @index: DSA port index, same as dsa_port::index * @stats: link statistics populated by rtl8365mb_stats_poll, ready for atomic * access via rtl8365mb_get_stats64 @@ -524,7 +524,7 @@ struct rtl8365mb_cpu { * @mib_work: delayed work for polling MIB counters */ struct rtl8365mb_port { - struct realtek_smi *smi; + struct realtek_priv *priv; unsigned int index; struct rtnl_link_stats64 stats; spinlock_t stats_lock; @@ -533,7 +533,7 @@ struct rtl8365mb_port { /** * struct rtl8365mb - private chip-specific driver data - * @smi: pointer to parent realtek_smi data + * @priv: pointer to parent realtek_priv data * @irq: registered IRQ or zero * @chip_id: chip identifier * @chip_ver: chip silicon revision @@ -548,7 +548,7 @@ struct rtl8365mb_port { * Private data for this driver. */ struct rtl8365mb { - struct realtek_smi *smi; + struct realtek_priv *priv; int irq; u32 chip_id; u32 chip_ver; @@ -561,16 +561,16 @@ struct rtl8365mb { size_t jam_size; }; -static int rtl8365mb_phy_poll_busy(struct realtek_smi *smi) +static int rtl8365mb_phy_poll_busy(struct realtek_priv *priv) { u32 val; - return regmap_read_poll_timeout(smi->map, + return regmap_read_poll_timeout(priv->map, RTL8365MB_INDIRECT_ACCESS_STATUS_REG, val, !val, 10, 100); } -static int rtl8365mb_phy_ocp_prepare(struct realtek_smi *smi, int phy, +static int rtl8365mb_phy_ocp_prepare(struct realtek_priv *priv, int phy, u32 ocp_addr) { u32 val; @@ -579,7 +579,7 @@ static int rtl8365mb_phy_ocp_prepare(struct realtek_smi *smi, int phy, /* Set OCP prefix */ val = FIELD_GET(RTL8365MB_PHY_OCP_ADDR_PREFIX_MASK, ocp_addr); ret = regmap_update_bits( - smi->map, RTL8365MB_GPHY_OCP_MSB_0_REG, + priv->map, RTL8365MB_GPHY_OCP_MSB_0_REG, RTL8365MB_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK, FIELD_PREP(RTL8365MB_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK, val)); if (ret) @@ -592,7 +592,7 @@ static int rtl8365mb_phy_ocp_prepare(struct realtek_smi *smi, int phy, ocp_addr >> 1); val |= FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_9_6_MASK, ocp_addr >> 6); - ret = regmap_write(smi->map, RTL8365MB_INDIRECT_ACCESS_ADDRESS_REG, + ret = regmap_write(priv->map, RTL8365MB_INDIRECT_ACCESS_ADDRESS_REG, val); if (ret) return ret; @@ -600,17 +600,17 @@ static int rtl8365mb_phy_ocp_prepare(struct realtek_smi *smi, int phy, return 0; } -static int rtl8365mb_phy_ocp_read(struct realtek_smi *smi, int phy, +static int rtl8365mb_phy_ocp_read(struct realtek_priv *priv, int phy, u32 ocp_addr, u16 *data) { u32 val; int ret; - ret = rtl8365mb_phy_poll_busy(smi); + ret = rtl8365mb_phy_poll_busy(priv); if (ret) return ret; - ret = rtl8365mb_phy_ocp_prepare(smi, phy, ocp_addr); + ret = rtl8365mb_phy_ocp_prepare(priv, phy, ocp_addr); if (ret) return ret; @@ -619,16 +619,16 @@ static int rtl8365mb_phy_ocp_read(struct realtek_smi *smi, int phy, RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_VALUE) | FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_RW_MASK, RTL8365MB_INDIRECT_ACCESS_CTRL_RW_READ); - ret = regmap_write(smi->map, RTL8365MB_INDIRECT_ACCESS_CTRL_REG, val); + ret = regmap_write(priv->map, RTL8365MB_INDIRECT_ACCESS_CTRL_REG, val); if (ret) return ret; - ret = rtl8365mb_phy_poll_busy(smi); + ret = rtl8365mb_phy_poll_busy(priv); if (ret) return ret; /* Get PHY register data */ - ret = regmap_read(smi->map, RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG, + ret = regmap_read(priv->map, RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG, &val); if (ret) return ret; @@ -638,22 +638,22 @@ static int rtl8365mb_phy_ocp_read(struct realtek_smi *smi, int phy, return 0; } -static int rtl8365mb_phy_ocp_write(struct realtek_smi *smi, int phy, +static int rtl8365mb_phy_ocp_write(struct realtek_priv *priv, int phy, u32 ocp_addr, u16 data) { u32 val; int ret; - ret = rtl8365mb_phy_poll_busy(smi); + ret = rtl8365mb_phy_poll_busy(priv); if (ret) return ret; - ret = rtl8365mb_phy_ocp_prepare(smi, phy, ocp_addr); + ret = rtl8365mb_phy_ocp_prepare(priv, phy, ocp_addr); if (ret) return ret; /* Set PHY register data */ - ret = regmap_write(smi->map, RTL8365MB_INDIRECT_ACCESS_WRITE_DATA_REG, + ret = regmap_write(priv->map, RTL8365MB_INDIRECT_ACCESS_WRITE_DATA_REG, data); if (ret) return ret; @@ -663,18 +663,18 @@ static int rtl8365mb_phy_ocp_write(struct realtek_smi *smi, int phy, RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_VALUE) | FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_RW_MASK, RTL8365MB_INDIRECT_ACCESS_CTRL_RW_WRITE); - ret = regmap_write(smi->map, RTL8365MB_INDIRECT_ACCESS_CTRL_REG, val); + ret = regmap_write(priv->map, RTL8365MB_INDIRECT_ACCESS_CTRL_REG, val); if (ret) return ret; - ret = rtl8365mb_phy_poll_busy(smi); + ret = rtl8365mb_phy_poll_busy(priv); if (ret) return ret; return 0; } -static int rtl8365mb_phy_read(struct realtek_smi *smi, int phy, int regnum) +static int rtl8365mb_phy_read(struct realtek_priv *priv, int phy, int regnum) { u32 ocp_addr; u16 val; @@ -688,21 +688,21 @@ static int rtl8365mb_phy_read(struct realtek_smi *smi, int phy, int regnum) ocp_addr = RTL8365MB_PHY_OCP_ADDR_PHYREG_BASE + regnum * 2; - ret = rtl8365mb_phy_ocp_read(smi, phy, ocp_addr, &val); + ret = rtl8365mb_phy_ocp_read(priv, phy, ocp_addr, &val); if (ret) { - dev_err(smi->dev, + dev_err(priv->dev, "failed to read PHY%d reg %02x @ %04x, ret %d\n", phy, regnum, ocp_addr, ret); return ret; } - dev_dbg(smi->dev, "read PHY%d register 0x%02x @ %04x, val <- %04x\n", + dev_dbg(priv->dev, "read PHY%d register 0x%02x @ %04x, val <- %04x\n", phy, regnum, ocp_addr, val); return val; } -static int rtl8365mb_phy_write(struct realtek_smi *smi, int phy, int regnum, +static int rtl8365mb_phy_write(struct realtek_priv *priv, int phy, int regnum, u16 val) { u32 ocp_addr; @@ -716,15 +716,15 @@ static int rtl8365mb_phy_write(struct realtek_smi *smi, int phy, int regnum, ocp_addr = RTL8365MB_PHY_OCP_ADDR_PHYREG_BASE + regnum * 2; - ret = rtl8365mb_phy_ocp_write(smi, phy, ocp_addr, val); + ret = rtl8365mb_phy_ocp_write(priv, phy, ocp_addr, val); if (ret) { - dev_err(smi->dev, + dev_err(priv->dev, "failed to write PHY%d reg %02x @ %04x, ret %d\n", phy, regnum, ocp_addr, ret); return ret; } - dev_dbg(smi->dev, "write PHY%d register 0x%02x @ %04x, val -> %04x\n", + dev_dbg(priv->dev, "write PHY%d register 0x%02x @ %04x, val -> %04x\n", phy, regnum, ocp_addr, val); return 0; @@ -737,7 +737,7 @@ rtl8365mb_get_tag_protocol(struct dsa_switch *ds, int port, return DSA_TAG_PROTO_RTL8_4; } -static int rtl8365mb_ext_config_rgmii(struct realtek_smi *smi, int port, +static int rtl8365mb_ext_config_rgmii(struct realtek_priv *priv, int port, phy_interface_t interface) { struct device_node *dn; @@ -748,14 +748,14 @@ static int rtl8365mb_ext_config_rgmii(struct realtek_smi *smi, int port, u32 val; int ret; - if (port == smi->cpu_port) { + if (port == priv->cpu_port) { ext_port = 1; } else { - dev_err(smi->dev, "only one EXT port is currently supported\n"); + dev_err(priv->dev, "only one EXT port is currently supported\n"); return -EINVAL; } - dp = dsa_to_port(smi->ds, port); + dp = dsa_to_port(priv->ds, port); dn = dp->dn; /* Set the RGMII TX/RX delay @@ -786,7 +786,7 @@ static int rtl8365mb_ext_config_rgmii(struct realtek_smi *smi, int port, if (val == 0 || val == 2) tx_delay = val / 2; else - dev_warn(smi->dev, + dev_warn(priv->dev, "EXT port TX delay must be 0 or 2 ns\n"); } @@ -796,12 +796,12 @@ static int rtl8365mb_ext_config_rgmii(struct realtek_smi *smi, int port, if (val <= 7) rx_delay = val; else - dev_warn(smi->dev, + dev_warn(priv->dev, "EXT port RX delay must be 0 to 2.1 ns\n"); } ret = regmap_update_bits( - smi->map, RTL8365MB_EXT_RGMXF_REG(ext_port), + priv->map, RTL8365MB_EXT_RGMXF_REG(ext_port), RTL8365MB_EXT_RGMXF_TXDELAY_MASK | RTL8365MB_EXT_RGMXF_RXDELAY_MASK, FIELD_PREP(RTL8365MB_EXT_RGMXF_TXDELAY_MASK, tx_delay) | @@ -810,7 +810,7 @@ static int rtl8365mb_ext_config_rgmii(struct realtek_smi *smi, int port, return ret; ret = regmap_update_bits( - smi->map, RTL8365MB_DIGITAL_INTERFACE_SELECT_REG(ext_port), + priv->map, RTL8365MB_DIGITAL_INTERFACE_SELECT_REG(ext_port), RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_MASK(ext_port), RTL8365MB_EXT_PORT_MODE_RGMII << RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_OFFSET( @@ -821,7 +821,7 @@ static int rtl8365mb_ext_config_rgmii(struct realtek_smi *smi, int port, return 0; } -static int rtl8365mb_ext_config_forcemode(struct realtek_smi *smi, int port, +static int rtl8365mb_ext_config_forcemode(struct realtek_priv *priv, int port, bool link, int speed, int duplex, bool tx_pause, bool rx_pause) { @@ -834,10 +834,10 @@ static int rtl8365mb_ext_config_forcemode(struct realtek_smi *smi, int port, int val; int ret; - if (port == smi->cpu_port) { + if (port == priv->cpu_port) { ext_port = 1; } else { - dev_err(smi->dev, "only one EXT port is currently supported\n"); + dev_err(priv->dev, "only one EXT port is currently supported\n"); return -EINVAL; } @@ -854,7 +854,7 @@ static int rtl8365mb_ext_config_forcemode(struct realtek_smi *smi, int port, } else if (speed == SPEED_10) { r_speed = RTL8365MB_PORT_SPEED_10M; } else { - dev_err(smi->dev, "unsupported port speed %s\n", + dev_err(priv->dev, "unsupported port speed %s\n", phy_speed_to_str(speed)); return -EINVAL; } @@ -864,7 +864,7 @@ static int rtl8365mb_ext_config_forcemode(struct realtek_smi *smi, int port, } else if (duplex == DUPLEX_HALF) { r_duplex = 0; } else { - dev_err(smi->dev, "unsupported duplex %s\n", + dev_err(priv->dev, "unsupported duplex %s\n", phy_duplex_to_str(duplex)); return -EINVAL; } @@ -886,7 +886,7 @@ static int rtl8365mb_ext_config_forcemode(struct realtek_smi *smi, int port, FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_DUPLEX_MASK, r_duplex) | FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_SPEED_MASK, r_speed); - ret = regmap_write(smi->map, + ret = regmap_write(priv->map, RTL8365MB_DIGITAL_INTERFACE_FORCE_REG(ext_port), val); if (ret) @@ -916,7 +916,7 @@ static void rtl8365mb_phylink_validate(struct dsa_switch *ds, int port, unsigned long *supported, struct phylink_link_state *state) { - struct realtek_smi *smi = ds->priv; + struct realtek_priv *priv = ds->priv; __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0 }; /* include/linux/phylink.h says: @@ -925,7 +925,7 @@ static void rtl8365mb_phylink_validate(struct dsa_switch *ds, int port, */ if (state->interface != PHY_INTERFACE_MODE_NA && !rtl8365mb_phy_mode_supported(ds, port, state->interface)) { - dev_err(smi->dev, "phy mode %s is unsupported on port %d\n", + dev_err(priv->dev, "phy mode %s is unsupported on port %d\n", phy_modes(state->interface), port); linkmode_zero(supported); return; @@ -951,26 +951,26 @@ static void rtl8365mb_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, const struct phylink_link_state *state) { - struct realtek_smi *smi = ds->priv; + struct realtek_priv *priv = ds->priv; int ret; if (!rtl8365mb_phy_mode_supported(ds, port, state->interface)) { - dev_err(smi->dev, "phy mode %s is unsupported on port %d\n", + dev_err(priv->dev, "phy mode %s is unsupported on port %d\n", phy_modes(state->interface), port); return; } if (mode != MLO_AN_PHY && mode != MLO_AN_FIXED) { - dev_err(smi->dev, + dev_err(priv->dev, "port %d supports only conventional PHY or fixed-link\n", port); return; } if (phy_interface_mode_is_rgmii(state->interface)) { - ret = rtl8365mb_ext_config_rgmii(smi, port, state->interface); + ret = rtl8365mb_ext_config_rgmii(priv, port, state->interface); if (ret) - dev_err(smi->dev, + dev_err(priv->dev, "failed to configure RGMII mode on port %d: %d\n", port, ret); return; @@ -985,20 +985,20 @@ static void rtl8365mb_phylink_mac_link_down(struct dsa_switch *ds, int port, unsigned int mode, phy_interface_t interface) { - struct realtek_smi *smi = ds->priv; + struct realtek_priv *priv = ds->priv; struct rtl8365mb_port *p; struct rtl8365mb *mb; int ret; - mb = smi->chip_data; + mb = priv->chip_data; p = &mb->ports[port]; cancel_delayed_work_sync(&p->mib_work); if (phy_interface_mode_is_rgmii(interface)) { - ret = rtl8365mb_ext_config_forcemode(smi, port, false, 0, 0, + ret = rtl8365mb_ext_config_forcemode(priv, port, false, 0, 0, false, false); if (ret) - dev_err(smi->dev, + dev_err(priv->dev, "failed to reset forced mode on port %d: %d\n", port, ret); @@ -1013,21 +1013,21 @@ static void rtl8365mb_phylink_mac_link_up(struct dsa_switch *ds, int port, int duplex, bool tx_pause, bool rx_pause) { - struct realtek_smi *smi = ds->priv; + struct realtek_priv *priv = ds->priv; struct rtl8365mb_port *p; struct rtl8365mb *mb; int ret; - mb = smi->chip_data; + mb = priv->chip_data; p = &mb->ports[port]; schedule_delayed_work(&p->mib_work, 0); if (phy_interface_mode_is_rgmii(interface)) { - ret = rtl8365mb_ext_config_forcemode(smi, port, true, speed, + ret = rtl8365mb_ext_config_forcemode(priv, port, true, speed, duplex, tx_pause, rx_pause); if (ret) - dev_err(smi->dev, + dev_err(priv->dev, "failed to force mode on port %d: %d\n", port, ret); @@ -1038,7 +1038,7 @@ static void rtl8365mb_phylink_mac_link_up(struct dsa_switch *ds, int port, static void rtl8365mb_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) { - struct realtek_smi *smi = ds->priv; + struct realtek_priv *priv = ds->priv; enum rtl8365mb_stp_state val; int msti = 0; @@ -1057,36 +1057,36 @@ static void rtl8365mb_port_stp_state_set(struct dsa_switch *ds, int port, val = RTL8365MB_STP_STATE_FORWARDING; break; default: - dev_err(smi->dev, "invalid STP state: %u\n", state); + dev_err(priv->dev, "invalid STP state: %u\n", state); return; } - regmap_update_bits(smi->map, RTL8365MB_MSTI_CTRL_REG(msti, port), + regmap_update_bits(priv->map, RTL8365MB_MSTI_CTRL_REG(msti, port), RTL8365MB_MSTI_CTRL_PORT_STATE_MASK(port), val << RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET(port)); } -static int rtl8365mb_port_set_learning(struct realtek_smi *smi, int port, +static int rtl8365mb_port_set_learning(struct realtek_priv *priv, int port, bool enable) { - struct rtl8365mb *mb = smi->chip_data; + struct rtl8365mb *mb = priv->chip_data; /* Enable/disable learning by limiting the number of L2 addresses the * port can learn. Realtek documentation states that a limit of zero * disables learning. When enabling learning, set it to the chip's * maximum. */ - return regmap_write(smi->map, RTL8365MB_LUT_PORT_LEARN_LIMIT_REG(port), + return regmap_write(priv->map, RTL8365MB_LUT_PORT_LEARN_LIMIT_REG(port), enable ? mb->learn_limit_max : 0); } -static int rtl8365mb_port_set_isolation(struct realtek_smi *smi, int port, +static int rtl8365mb_port_set_isolation(struct realtek_priv *priv, int port, u32 mask) { - return regmap_write(smi->map, RTL8365MB_PORT_ISOLATION_REG(port), mask); + return regmap_write(priv->map, RTL8365MB_PORT_ISOLATION_REG(port), mask); } -static int rtl8365mb_mib_counter_read(struct realtek_smi *smi, int port, +static int rtl8365mb_mib_counter_read(struct realtek_priv *priv, int port, u32 offset, u32 length, u64 *mibvalue) { u64 tmpvalue = 0; @@ -1098,13 +1098,13 @@ static int rtl8365mb_mib_counter_read(struct realtek_smi *smi, int port, * and then poll the control register before reading the value from some * counter registers. */ - ret = regmap_write(smi->map, RTL8365MB_MIB_ADDRESS_REG, + ret = regmap_write(priv->map, RTL8365MB_MIB_ADDRESS_REG, RTL8365MB_MIB_ADDRESS(port, offset)); if (ret) return ret; /* Poll for completion */ - ret = regmap_read_poll_timeout(smi->map, RTL8365MB_MIB_CTRL0_REG, val, + ret = regmap_read_poll_timeout(priv->map, RTL8365MB_MIB_CTRL0_REG, val, !(val & RTL8365MB_MIB_CTRL0_BUSY_MASK), 10, 100); if (ret) @@ -1126,7 +1126,7 @@ static int rtl8365mb_mib_counter_read(struct realtek_smi *smi, int port, /* Read the MIB counter 16 bits at a time */ for (i = 0; i < length; i++) { - ret = regmap_read(smi->map, + ret = regmap_read(priv->map, RTL8365MB_MIB_COUNTER_REG(offset - i), &val); if (ret) return ret; @@ -1142,21 +1142,21 @@ static int rtl8365mb_mib_counter_read(struct realtek_smi *smi, int port, static void rtl8365mb_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *data) { - struct realtek_smi *smi = ds->priv; + struct realtek_priv *priv = ds->priv; struct rtl8365mb *mb; int ret; int i; - mb = smi->chip_data; + mb = priv->chip_data; mutex_lock(&mb->mib_lock); for (i = 0; i < RTL8365MB_MIB_END; i++) { struct rtl8365mb_mib_counter *mib = &rtl8365mb_mib_counters[i]; - ret = rtl8365mb_mib_counter_read(smi, port, mib->offset, + ret = rtl8365mb_mib_counter_read(priv, port, mib->offset, mib->length, &data[i]); if (ret) { - dev_err(smi->dev, + dev_err(priv->dev, "failed to read port %d counters: %d\n", port, ret); break; @@ -1190,15 +1190,15 @@ static int rtl8365mb_get_sset_count(struct dsa_switch *ds, int port, int sset) static void rtl8365mb_get_phy_stats(struct dsa_switch *ds, int port, struct ethtool_eth_phy_stats *phy_stats) { - struct realtek_smi *smi = ds->priv; + struct realtek_priv *priv = ds->priv; struct rtl8365mb_mib_counter *mib; struct rtl8365mb *mb; - mb = smi->chip_data; + mb = priv->chip_data; mib = &rtl8365mb_mib_counters[RTL8365MB_MIB_dot3StatsSymbolErrors]; mutex_lock(&mb->mib_lock); - rtl8365mb_mib_counter_read(smi, port, mib->offset, mib->length, + rtl8365mb_mib_counter_read(priv, port, mib->offset, mib->length, &phy_stats->SymbolErrorDuringCarrier); mutex_unlock(&mb->mib_lock); } @@ -1226,12 +1226,12 @@ static void rtl8365mb_get_mac_stats(struct dsa_switch *ds, int port, [RTL8365MB_MIB_dot3StatsExcessiveCollisions] = 1, }; - struct realtek_smi *smi = ds->priv; + struct realtek_priv *priv = ds->priv; struct rtl8365mb *mb; int ret; int i; - mb = smi->chip_data; + mb = priv->chip_data; mutex_lock(&mb->mib_lock); for (i = 0; i < RTL8365MB_MIB_END; i++) { @@ -1241,7 +1241,7 @@ static void rtl8365mb_get_mac_stats(struct dsa_switch *ds, int port, if (!cnt[i]) continue; - ret = rtl8365mb_mib_counter_read(smi, port, mib->offset, + ret = rtl8365mb_mib_counter_read(priv, port, mib->offset, mib->length, &cnt[i]); if (ret) break; @@ -1291,20 +1291,20 @@ static void rtl8365mb_get_mac_stats(struct dsa_switch *ds, int port, static void rtl8365mb_get_ctrl_stats(struct dsa_switch *ds, int port, struct ethtool_eth_ctrl_stats *ctrl_stats) { - struct realtek_smi *smi = ds->priv; + struct realtek_priv *priv = ds->priv; struct rtl8365mb_mib_counter *mib; struct rtl8365mb *mb; - mb = smi->chip_data; + mb = priv->chip_data; mib = &rtl8365mb_mib_counters[RTL8365MB_MIB_dot3ControlInUnknownOpcodes]; mutex_lock(&mb->mib_lock); - rtl8365mb_mib_counter_read(smi, port, mib->offset, mib->length, + rtl8365mb_mib_counter_read(priv, port, mib->offset, mib->length, &ctrl_stats->UnsupportedOpcodesReceived); mutex_unlock(&mb->mib_lock); } -static void rtl8365mb_stats_update(struct realtek_smi *smi, int port) +static void rtl8365mb_stats_update(struct realtek_priv *priv, int port) { u64 cnt[RTL8365MB_MIB_END] = { [RTL8365MB_MIB_ifOutOctets] = 1, @@ -1323,7 +1323,7 @@ static void rtl8365mb_stats_update(struct realtek_smi *smi, int port) [RTL8365MB_MIB_dot3StatsFCSErrors] = 1, [RTL8365MB_MIB_dot3StatsLateCollisions] = 1, }; - struct rtl8365mb *mb = smi->chip_data; + struct rtl8365mb *mb = priv->chip_data; struct rtnl_link_stats64 *stats; int ret; int i; @@ -1338,7 +1338,7 @@ static void rtl8365mb_stats_update(struct realtek_smi *smi, int port) if (!cnt[i]) continue; - ret = rtl8365mb_mib_counter_read(smi, port, c->offset, + ret = rtl8365mb_mib_counter_read(priv, port, c->offset, c->length, &cnt[i]); if (ret) break; @@ -1388,9 +1388,9 @@ static void rtl8365mb_stats_poll(struct work_struct *work) struct rtl8365mb_port *p = container_of(to_delayed_work(work), struct rtl8365mb_port, mib_work); - struct realtek_smi *smi = p->smi; + struct realtek_priv *priv = p->priv; - rtl8365mb_stats_update(smi, p->index); + rtl8365mb_stats_update(priv, p->index); schedule_delayed_work(&p->mib_work, RTL8365MB_STATS_INTERVAL_JIFFIES); } @@ -1398,11 +1398,11 @@ static void rtl8365mb_stats_poll(struct work_struct *work) static void rtl8365mb_get_stats64(struct dsa_switch *ds, int port, struct rtnl_link_stats64 *s) { - struct realtek_smi *smi = ds->priv; + struct realtek_priv *priv = ds->priv; struct rtl8365mb_port *p; struct rtl8365mb *mb; - mb = smi->chip_data; + mb = priv->chip_data; p = &mb->ports[port]; spin_lock(&p->stats_lock); @@ -1410,9 +1410,9 @@ static void rtl8365mb_get_stats64(struct dsa_switch *ds, int port, spin_unlock(&p->stats_lock); } -static void rtl8365mb_stats_setup(struct realtek_smi *smi) +static void rtl8365mb_stats_setup(struct realtek_priv *priv) { - struct rtl8365mb *mb = smi->chip_data; + struct rtl8365mb *mb = priv->chip_data; int i; /* Per-chip global mutex to protect MIB counter access, since doing @@ -1420,10 +1420,10 @@ static void rtl8365mb_stats_setup(struct realtek_smi *smi) */ mutex_init(&mb->mib_lock); - for (i = 0; i < smi->num_ports; i++) { + for (i = 0; i < priv->num_ports; i++) { struct rtl8365mb_port *p = &mb->ports[i]; - if (dsa_is_unused_port(smi->ds, i)) + if (dsa_is_unused_port(priv->ds, i)) continue; /* Per-port spinlock to protect the stats64 data */ @@ -1436,45 +1436,45 @@ static void rtl8365mb_stats_setup(struct realtek_smi *smi) } } -static void rtl8365mb_stats_teardown(struct realtek_smi *smi) +static void rtl8365mb_stats_teardown(struct realtek_priv *priv) { - struct rtl8365mb *mb = smi->chip_data; + struct rtl8365mb *mb = priv->chip_data; int i; - for (i = 0; i < smi->num_ports; i++) { + for (i = 0; i < priv->num_ports; i++) { struct rtl8365mb_port *p = &mb->ports[i]; - if (dsa_is_unused_port(smi->ds, i)) + if (dsa_is_unused_port(priv->ds, i)) continue; cancel_delayed_work_sync(&p->mib_work); } } -static int rtl8365mb_get_and_clear_status_reg(struct realtek_smi *smi, u32 reg, +static int rtl8365mb_get_and_clear_status_reg(struct realtek_priv *priv, u32 reg, u32 *val) { int ret; - ret = regmap_read(smi->map, reg, val); + ret = regmap_read(priv->map, reg, val); if (ret) return ret; - return regmap_write(smi->map, reg, *val); + return regmap_write(priv->map, reg, *val); } static irqreturn_t rtl8365mb_irq(int irq, void *data) { - struct realtek_smi *smi = data; + struct realtek_priv *priv = data; unsigned long line_changes = 0; struct rtl8365mb *mb; u32 stat; int line; int ret; - mb = smi->chip_data; + mb = priv->chip_data; - ret = rtl8365mb_get_and_clear_status_reg(smi, RTL8365MB_INTR_STATUS_REG, + ret = rtl8365mb_get_and_clear_status_reg(priv, RTL8365MB_INTR_STATUS_REG, &stat); if (ret) goto out_error; @@ -1485,14 +1485,14 @@ static irqreturn_t rtl8365mb_irq(int irq, void *data) u32 val; ret = rtl8365mb_get_and_clear_status_reg( - smi, RTL8365MB_PORT_LINKUP_IND_REG, &val); + priv, RTL8365MB_PORT_LINKUP_IND_REG, &val); if (ret) goto out_error; linkup_ind = FIELD_GET(RTL8365MB_PORT_LINKUP_IND_MASK, val); ret = rtl8365mb_get_and_clear_status_reg( - smi, RTL8365MB_PORT_LINKDOWN_IND_REG, &val); + priv, RTL8365MB_PORT_LINKDOWN_IND_REG, &val); if (ret) goto out_error; @@ -1504,8 +1504,8 @@ static irqreturn_t rtl8365mb_irq(int irq, void *data) if (!line_changes) goto out_none; - for_each_set_bit(line, &line_changes, smi->num_ports) { - int child_irq = irq_find_mapping(smi->irqdomain, line); + for_each_set_bit(line, &line_changes, priv->num_ports) { + int child_irq = irq_find_mapping(priv->irqdomain, line); handle_nested_irq(child_irq); } @@ -1513,7 +1513,7 @@ static irqreturn_t rtl8365mb_irq(int irq, void *data) return IRQ_HANDLED; out_error: - dev_err(smi->dev, "failed to read interrupt status: %d\n", ret); + dev_err(priv->dev, "failed to read interrupt status: %d\n", ret); out_none: return IRQ_NONE; @@ -1548,27 +1548,27 @@ static const struct irq_domain_ops rtl8365mb_irqdomain_ops = { .xlate = irq_domain_xlate_onecell, }; -static int rtl8365mb_set_irq_enable(struct realtek_smi *smi, bool enable) +static int rtl8365mb_set_irq_enable(struct realtek_priv *priv, bool enable) { - return regmap_update_bits(smi->map, RTL8365MB_INTR_CTRL_REG, + return regmap_update_bits(priv->map, RTL8365MB_INTR_CTRL_REG, RTL8365MB_INTR_LINK_CHANGE_MASK, FIELD_PREP(RTL8365MB_INTR_LINK_CHANGE_MASK, enable ? 1 : 0)); } -static int rtl8365mb_irq_enable(struct realtek_smi *smi) +static int rtl8365mb_irq_enable(struct realtek_priv *priv) { - return rtl8365mb_set_irq_enable(smi, true); + return rtl8365mb_set_irq_enable(priv, true); } -static int rtl8365mb_irq_disable(struct realtek_smi *smi) +static int rtl8365mb_irq_disable(struct realtek_priv *priv) { - return rtl8365mb_set_irq_enable(smi, false); + return rtl8365mb_set_irq_enable(priv, false); } -static int rtl8365mb_irq_setup(struct realtek_smi *smi) +static int rtl8365mb_irq_setup(struct realtek_priv *priv) { - struct rtl8365mb *mb = smi->chip_data; + struct rtl8365mb *mb = priv->chip_data; struct device_node *intc; u32 irq_trig; int virq; @@ -1577,9 +1577,9 @@ static int rtl8365mb_irq_setup(struct realtek_smi *smi) int ret; int i; - intc = of_get_child_by_name(smi->dev->of_node, "interrupt-controller"); + intc = of_get_child_by_name(priv->dev->of_node, "interrupt-controller"); if (!intc) { - dev_err(smi->dev, "missing child interrupt-controller node\n"); + dev_err(priv->dev, "missing child interrupt-controller node\n"); return -EINVAL; } @@ -1587,24 +1587,24 @@ static int rtl8365mb_irq_setup(struct realtek_smi *smi) irq = of_irq_get(intc, 0); if (irq <= 0) { if (irq != -EPROBE_DEFER) - dev_err(smi->dev, "failed to get parent irq: %d\n", + dev_err(priv->dev, "failed to get parent irq: %d\n", irq); ret = irq ? irq : -EINVAL; goto out_put_node; } - smi->irqdomain = irq_domain_add_linear(intc, smi->num_ports, - &rtl8365mb_irqdomain_ops, smi); - if (!smi->irqdomain) { - dev_err(smi->dev, "failed to add irq domain\n"); + priv->irqdomain = irq_domain_add_linear(intc, priv->num_ports, + &rtl8365mb_irqdomain_ops, priv); + if (!priv->irqdomain) { + dev_err(priv->dev, "failed to add irq domain\n"); ret = -ENOMEM; goto out_put_node; } - for (i = 0; i < smi->num_ports; i++) { - virq = irq_create_mapping(smi->irqdomain, i); + for (i = 0; i < priv->num_ports; i++) { + virq = irq_create_mapping(priv->irqdomain, i); if (!virq) { - dev_err(smi->dev, + dev_err(priv->dev, "failed to create irq domain mapping\n"); ret = -EINVAL; goto out_remove_irqdomain; @@ -1625,40 +1625,40 @@ static int rtl8365mb_irq_setup(struct realtek_smi *smi) val = RTL8365MB_INTR_POLARITY_LOW; break; default: - dev_err(smi->dev, "unsupported irq trigger type %u\n", + dev_err(priv->dev, "unsupported irq trigger type %u\n", irq_trig); ret = -EINVAL; goto out_remove_irqdomain; } - ret = regmap_update_bits(smi->map, RTL8365MB_INTR_POLARITY_REG, + ret = regmap_update_bits(priv->map, RTL8365MB_INTR_POLARITY_REG, RTL8365MB_INTR_POLARITY_MASK, FIELD_PREP(RTL8365MB_INTR_POLARITY_MASK, val)); if (ret) goto out_remove_irqdomain; /* Disable the interrupt in case the chip has it enabled on reset */ - ret = rtl8365mb_irq_disable(smi); + ret = rtl8365mb_irq_disable(priv); if (ret) goto out_remove_irqdomain; /* Clear the interrupt status register */ - ret = regmap_write(smi->map, RTL8365MB_INTR_STATUS_REG, + ret = regmap_write(priv->map, RTL8365MB_INTR_STATUS_REG, RTL8365MB_INTR_ALL_MASK); if (ret) goto out_remove_irqdomain; ret = request_threaded_irq(irq, NULL, rtl8365mb_irq, IRQF_ONESHOT, - "rtl8365mb", smi); + "rtl8365mb", priv); if (ret) { - dev_err(smi->dev, "failed to request irq: %d\n", ret); + dev_err(priv->dev, "failed to request irq: %d\n", ret); goto out_remove_irqdomain; } /* Store the irq so that we know to free it during teardown */ mb->irq = irq; - ret = rtl8365mb_irq_enable(smi); + ret = rtl8365mb_irq_enable(priv); if (ret) goto out_free_irq; @@ -1667,17 +1667,17 @@ static int rtl8365mb_irq_setup(struct realtek_smi *smi) return 0; out_free_irq: - free_irq(mb->irq, smi); + free_irq(mb->irq, priv); mb->irq = 0; out_remove_irqdomain: - for (i = 0; i < smi->num_ports; i++) { - virq = irq_find_mapping(smi->irqdomain, i); + for (i = 0; i < priv->num_ports; i++) { + virq = irq_find_mapping(priv->irqdomain, i); irq_dispose_mapping(virq); } - irq_domain_remove(smi->irqdomain); - smi->irqdomain = NULL; + irq_domain_remove(priv->irqdomain); + priv->irqdomain = NULL; out_put_node: of_node_put(intc); @@ -1685,36 +1685,36 @@ static int rtl8365mb_irq_setup(struct realtek_smi *smi) return ret; } -static void rtl8365mb_irq_teardown(struct realtek_smi *smi) +static void rtl8365mb_irq_teardown(struct realtek_priv *priv) { - struct rtl8365mb *mb = smi->chip_data; + struct rtl8365mb *mb = priv->chip_data; int virq; int i; if (mb->irq) { - free_irq(mb->irq, smi); + free_irq(mb->irq, priv); mb->irq = 0; } - if (smi->irqdomain) { - for (i = 0; i < smi->num_ports; i++) { - virq = irq_find_mapping(smi->irqdomain, i); + if (priv->irqdomain) { + for (i = 0; i < priv->num_ports; i++) { + virq = irq_find_mapping(priv->irqdomain, i); irq_dispose_mapping(virq); } - irq_domain_remove(smi->irqdomain); - smi->irqdomain = NULL; + irq_domain_remove(priv->irqdomain); + priv->irqdomain = NULL; } } -static int rtl8365mb_cpu_config(struct realtek_smi *smi) +static int rtl8365mb_cpu_config(struct realtek_priv *priv) { - struct rtl8365mb *mb = smi->chip_data; + struct rtl8365mb *mb = priv->chip_data; struct rtl8365mb_cpu *cpu = &mb->cpu; u32 val; int ret; - ret = regmap_update_bits(smi->map, RTL8365MB_CPU_PORT_MASK_REG, + ret = regmap_update_bits(priv->map, RTL8365MB_CPU_PORT_MASK_REG, RTL8365MB_CPU_PORT_MASK_MASK, FIELD_PREP(RTL8365MB_CPU_PORT_MASK_MASK, cpu->mask)); @@ -1729,23 +1729,23 @@ static int rtl8365mb_cpu_config(struct realtek_smi *smi) FIELD_PREP(RTL8365MB_CPU_CTRL_TRAP_PORT_MASK, cpu->trap_port) | FIELD_PREP(RTL8365MB_CPU_CTRL_TRAP_PORT_EXT_MASK, cpu->trap_port >> 3); - ret = regmap_write(smi->map, RTL8365MB_CPU_CTRL_REG, val); + ret = regmap_write(priv->map, RTL8365MB_CPU_CTRL_REG, val); if (ret) return ret; return 0; } -static int rtl8365mb_switch_init(struct realtek_smi *smi) +static int rtl8365mb_switch_init(struct realtek_priv *priv) { - struct rtl8365mb *mb = smi->chip_data; + struct rtl8365mb *mb = priv->chip_data; int ret; int i; /* Do any chip-specific init jam before getting to the common stuff */ if (mb->jam_table) { for (i = 0; i < mb->jam_size; i++) { - ret = regmap_write(smi->map, mb->jam_table[i].reg, + ret = regmap_write(priv->map, mb->jam_table[i].reg, mb->jam_table[i].val); if (ret) return ret; @@ -1754,7 +1754,7 @@ static int rtl8365mb_switch_init(struct realtek_smi *smi) /* Common init jam */ for (i = 0; i < ARRAY_SIZE(rtl8365mb_init_jam_common); i++) { - ret = regmap_write(smi->map, rtl8365mb_init_jam_common[i].reg, + ret = regmap_write(priv->map, rtl8365mb_init_jam_common[i].reg, rtl8365mb_init_jam_common[i].val); if (ret) return ret; @@ -1763,11 +1763,11 @@ static int rtl8365mb_switch_init(struct realtek_smi *smi) return 0; } -static int rtl8365mb_reset_chip(struct realtek_smi *smi) +static int rtl8365mb_reset_chip(struct realtek_priv *priv) { u32 val; - realtek_smi_write_reg_noack(smi, RTL8365MB_CHIP_RESET_REG, + priv->write_reg_noack(priv, RTL8365MB_CHIP_RESET_REG, FIELD_PREP(RTL8365MB_CHIP_RESET_HW_MASK, 1)); @@ -1775,63 +1775,63 @@ static int rtl8365mb_reset_chip(struct realtek_smi *smi) * for 100 ms before accessing any registers to prevent ACK timeouts. */ msleep(100); - return regmap_read_poll_timeout(smi->map, RTL8365MB_CHIP_RESET_REG, val, + return regmap_read_poll_timeout(priv->map, RTL8365MB_CHIP_RESET_REG, val, !(val & RTL8365MB_CHIP_RESET_HW_MASK), 20000, 1e6); } static int rtl8365mb_setup(struct dsa_switch *ds) { - struct realtek_smi *smi = ds->priv; + struct realtek_priv *priv = ds->priv; struct rtl8365mb *mb; int ret; int i; - mb = smi->chip_data; + mb = priv->chip_data; - ret = rtl8365mb_reset_chip(smi); + ret = rtl8365mb_reset_chip(priv); if (ret) { - dev_err(smi->dev, "failed to reset chip: %d\n", ret); + dev_err(priv->dev, "failed to reset chip: %d\n", ret); goto out_error; } /* Configure switch to vendor-defined initial state */ - ret = rtl8365mb_switch_init(smi); + ret = rtl8365mb_switch_init(priv); if (ret) { - dev_err(smi->dev, "failed to initialize switch: %d\n", ret); + dev_err(priv->dev, "failed to initialize switch: %d\n", ret); goto out_error; } /* Set up cascading IRQs */ - ret = rtl8365mb_irq_setup(smi); + ret = rtl8365mb_irq_setup(priv); if (ret == -EPROBE_DEFER) return ret; else if (ret) - dev_info(smi->dev, "no interrupt support\n"); + dev_info(priv->dev, "no interrupt support\n"); /* Configure CPU tagging */ - ret = rtl8365mb_cpu_config(smi); + ret = rtl8365mb_cpu_config(priv); if (ret) goto out_teardown_irq; /* Configure ports */ - for (i = 0; i < smi->num_ports; i++) { + for (i = 0; i < priv->num_ports; i++) { struct rtl8365mb_port *p = &mb->ports[i]; - if (dsa_is_unused_port(smi->ds, i)) + if (dsa_is_unused_port(priv->ds, i)) continue; /* Set up per-port private data */ - p->smi = smi; + p->priv = priv; p->index = i; /* Forward only to the CPU */ - ret = rtl8365mb_port_set_isolation(smi, i, BIT(smi->cpu_port)); + ret = rtl8365mb_port_set_isolation(priv, i, BIT(priv->cpu_port)); if (ret) goto out_teardown_irq; /* Disable learning */ - ret = rtl8365mb_port_set_learning(smi, i, false); + ret = rtl8365mb_port_set_learning(priv, i, false); if (ret) goto out_teardown_irq; @@ -1839,29 +1839,31 @@ static int rtl8365mb_setup(struct dsa_switch *ds) * ports will still forward frames to the CPU despite being * administratively down by default. */ - rtl8365mb_port_stp_state_set(smi->ds, i, BR_STATE_DISABLED); + rtl8365mb_port_stp_state_set(priv->ds, i, BR_STATE_DISABLED); } /* Set maximum packet length to 1536 bytes */ - ret = regmap_update_bits(smi->map, RTL8365MB_CFG0_MAX_LEN_REG, + ret = regmap_update_bits(priv->map, RTL8365MB_CFG0_MAX_LEN_REG, RTL8365MB_CFG0_MAX_LEN_MASK, FIELD_PREP(RTL8365MB_CFG0_MAX_LEN_MASK, 1536)); if (ret) goto out_teardown_irq; - ret = realtek_smi_setup_mdio(smi); - if (ret) { - dev_err(smi->dev, "could not set up MDIO bus\n"); - goto out_teardown_irq; + if (priv->setup_interface != NULL) { + ret = priv->setup_interface(ds); + if (ret) { + dev_err(priv->dev, "could not set up MDIO bus\n"); + goto out_teardown_irq; + } } /* Start statistics counter polling */ - rtl8365mb_stats_setup(smi); + rtl8365mb_stats_setup(priv); return 0; out_teardown_irq: - rtl8365mb_irq_teardown(smi); + rtl8365mb_irq_teardown(priv); out_error: return ret; @@ -1869,10 +1871,10 @@ static int rtl8365mb_setup(struct dsa_switch *ds) static void rtl8365mb_teardown(struct dsa_switch *ds) { - struct realtek_smi *smi = ds->priv; + struct realtek_priv *priv = ds->priv; - rtl8365mb_stats_teardown(smi); - rtl8365mb_irq_teardown(smi); + rtl8365mb_stats_teardown(priv); + rtl8365mb_irq_teardown(priv); } static int rtl8365mb_get_chip_id_and_ver(struct regmap *map, u32 *id, u32 *ver) @@ -1902,40 +1904,40 @@ static int rtl8365mb_get_chip_id_and_ver(struct regmap *map, u32 *id, u32 *ver) return 0; } -static int rtl8365mb_detect(struct realtek_smi *smi) +static int rtl8365mb_detect(struct realtek_priv *priv) { - struct rtl8365mb *mb = smi->chip_data; + struct rtl8365mb *mb = priv->chip_data; u32 chip_id; u32 chip_ver; int ret; - ret = rtl8365mb_get_chip_id_and_ver(smi->map, &chip_id, &chip_ver); + ret = rtl8365mb_get_chip_id_and_ver(priv->map, &chip_id, &chip_ver); if (ret) { - dev_err(smi->dev, "failed to read chip id and version: %d\n", + dev_err(priv->dev, "failed to read chip id and version: %d\n", ret); return ret; } switch (chip_id) { case RTL8365MB_CHIP_ID_8365MB_VC: - dev_info(smi->dev, + dev_info(priv->dev, "found an RTL8365MB-VC switch (ver=0x%04x)\n", chip_ver); - smi->cpu_port = RTL8365MB_CPU_PORT_NUM_8365MB_VC; - smi->num_ports = smi->cpu_port + 1; + priv->cpu_port = RTL8365MB_CPU_PORT_NUM_8365MB_VC; + priv->num_ports = priv->cpu_port + 1; - mb->smi = smi; + mb->priv = priv; mb->chip_id = chip_id; mb->chip_ver = chip_ver; - mb->port_mask = BIT(smi->num_ports) - 1; + mb->port_mask = BIT(priv->num_ports) - 1; mb->learn_limit_max = RTL8365MB_LEARN_LIMIT_MAX_8365MB_VC; mb->jam_table = rtl8365mb_init_jam_8365mb_vc; mb->jam_size = ARRAY_SIZE(rtl8365mb_init_jam_8365mb_vc); mb->cpu.enable = 1; - mb->cpu.mask = BIT(smi->cpu_port); - mb->cpu.trap_port = smi->cpu_port; + mb->cpu.mask = BIT(priv->cpu_port); + mb->cpu.trap_port = priv->cpu_port; mb->cpu.insert = RTL8365MB_CPU_INSERT_TO_ALL; mb->cpu.position = RTL8365MB_CPU_POS_AFTER_SA; mb->cpu.rx_length = RTL8365MB_CPU_RXLEN_64BYTES; @@ -1943,7 +1945,7 @@ static int rtl8365mb_detect(struct realtek_smi *smi) break; default: - dev_err(smi->dev, + dev_err(priv->dev, "found an unknown Realtek switch (id=0x%04x, ver=0x%04x)\n", chip_id, chip_ver); return -ENODEV; @@ -1970,15 +1972,15 @@ static const struct dsa_switch_ops rtl8365mb_switch_ops = { .get_stats64 = rtl8365mb_get_stats64, }; -static const struct realtek_smi_ops rtl8365mb_smi_ops = { +static const struct realtek_ops rtl8365mb_ops = { .detect = rtl8365mb_detect, .phy_read = rtl8365mb_phy_read, .phy_write = rtl8365mb_phy_write, }; -const struct realtek_smi_variant rtl8365mb_variant = { +const struct realtek_variant rtl8365mb_variant = { .ds_ops = &rtl8365mb_switch_ops, - .ops = &rtl8365mb_smi_ops, + .ops = &rtl8365mb_ops, .clk_delay = 10, .cmd_read = 0xb9, .cmd_write = 0xb8, diff --git a/drivers/net/dsa/realtek/rtl8366.c b/drivers/net/dsa/realtek/rtl8366.c index bdb8d8d34880..dc5f75be3017 100644 --- a/drivers/net/dsa/realtek/rtl8366.c +++ b/drivers/net/dsa/realtek/rtl8366.c @@ -11,18 +11,18 @@ #include #include -#include "realtek-smi-core.h" +#include "realtek.h" -int rtl8366_mc_is_used(struct realtek_smi *smi, int mc_index, int *used) +int rtl8366_mc_is_used(struct realtek_priv *priv, int mc_index, int *used) { int ret; int i; *used = 0; - for (i = 0; i < smi->num_ports; i++) { + for (i = 0; i < priv->num_ports; i++) { int index = 0; - ret = smi->ops->get_mc_index(smi, i, &index); + ret = priv->ops->get_mc_index(priv, i, &index); if (ret) return ret; @@ -38,13 +38,13 @@ EXPORT_SYMBOL_GPL(rtl8366_mc_is_used); /** * rtl8366_obtain_mc() - retrieve or allocate a VLAN member configuration - * @smi: the Realtek SMI device instance + * @priv: the Realtek SMI device instance * @vid: the VLAN ID to look up or allocate * @vlanmc: the pointer will be assigned to a pointer to a valid member config * if successful * @return: index of a new member config or negative error number */ -static int rtl8366_obtain_mc(struct realtek_smi *smi, int vid, +static int rtl8366_obtain_mc(struct realtek_priv *priv, int vid, struct rtl8366_vlan_mc *vlanmc) { struct rtl8366_vlan_4k vlan4k; @@ -52,10 +52,10 @@ static int rtl8366_obtain_mc(struct realtek_smi *smi, int vid, int i; /* Try to find an existing member config entry for this VID */ - for (i = 0; i < smi->num_vlan_mc; i++) { - ret = smi->ops->get_vlan_mc(smi, i, vlanmc); + for (i = 0; i < priv->num_vlan_mc; i++) { + ret = priv->ops->get_vlan_mc(priv, i, vlanmc); if (ret) { - dev_err(smi->dev, "error searching for VLAN MC %d for VID %d\n", + dev_err(priv->dev, "error searching for VLAN MC %d for VID %d\n", i, vid); return ret; } @@ -65,19 +65,19 @@ static int rtl8366_obtain_mc(struct realtek_smi *smi, int vid, } /* We have no MC entry for this VID, try to find an empty one */ - for (i = 0; i < smi->num_vlan_mc; i++) { - ret = smi->ops->get_vlan_mc(smi, i, vlanmc); + for (i = 0; i < priv->num_vlan_mc; i++) { + ret = priv->ops->get_vlan_mc(priv, i, vlanmc); if (ret) { - dev_err(smi->dev, "error searching for VLAN MC %d for VID %d\n", + dev_err(priv->dev, "error searching for VLAN MC %d for VID %d\n", i, vid); return ret; } if (vlanmc->vid == 0 && vlanmc->member == 0) { /* Update the entry from the 4K table */ - ret = smi->ops->get_vlan_4k(smi, vid, &vlan4k); + ret = priv->ops->get_vlan_4k(priv, vid, &vlan4k); if (ret) { - dev_err(smi->dev, "error looking for 4K VLAN MC %d for VID %d\n", + dev_err(priv->dev, "error looking for 4K VLAN MC %d for VID %d\n", i, vid); return ret; } @@ -86,30 +86,30 @@ static int rtl8366_obtain_mc(struct realtek_smi *smi, int vid, vlanmc->member = vlan4k.member; vlanmc->untag = vlan4k.untag; vlanmc->fid = vlan4k.fid; - ret = smi->ops->set_vlan_mc(smi, i, vlanmc); + ret = priv->ops->set_vlan_mc(priv, i, vlanmc); if (ret) { - dev_err(smi->dev, "unable to set/update VLAN MC %d for VID %d\n", + dev_err(priv->dev, "unable to set/update VLAN MC %d for VID %d\n", i, vid); return ret; } - dev_dbg(smi->dev, "created new MC at index %d for VID %d\n", + dev_dbg(priv->dev, "created new MC at index %d for VID %d\n", i, vid); return i; } } /* MC table is full, try to find an unused entry and replace it */ - for (i = 0; i < smi->num_vlan_mc; i++) { + for (i = 0; i < priv->num_vlan_mc; i++) { int used; - ret = rtl8366_mc_is_used(smi, i, &used); + ret = rtl8366_mc_is_used(priv, i, &used); if (ret) return ret; if (!used) { /* Update the entry from the 4K table */ - ret = smi->ops->get_vlan_4k(smi, vid, &vlan4k); + ret = priv->ops->get_vlan_4k(priv, vid, &vlan4k); if (ret) return ret; @@ -117,23 +117,23 @@ static int rtl8366_obtain_mc(struct realtek_smi *smi, int vid, vlanmc->member = vlan4k.member; vlanmc->untag = vlan4k.untag; vlanmc->fid = vlan4k.fid; - ret = smi->ops->set_vlan_mc(smi, i, vlanmc); + ret = priv->ops->set_vlan_mc(priv, i, vlanmc); if (ret) { - dev_err(smi->dev, "unable to set/update VLAN MC %d for VID %d\n", + dev_err(priv->dev, "unable to set/update VLAN MC %d for VID %d\n", i, vid); return ret; } - dev_dbg(smi->dev, "recycled MC at index %i for VID %d\n", + dev_dbg(priv->dev, "recycled MC at index %i for VID %d\n", i, vid); return i; } } - dev_err(smi->dev, "all VLAN member configurations are in use\n"); + dev_err(priv->dev, "all VLAN member configurations are in use\n"); return -ENOSPC; } -int rtl8366_set_vlan(struct realtek_smi *smi, int vid, u32 member, +int rtl8366_set_vlan(struct realtek_priv *priv, int vid, u32 member, u32 untag, u32 fid) { struct rtl8366_vlan_mc vlanmc; @@ -141,31 +141,31 @@ int rtl8366_set_vlan(struct realtek_smi *smi, int vid, u32 member, int mc; int ret; - if (!smi->ops->is_vlan_valid(smi, vid)) + if (!priv->ops->is_vlan_valid(priv, vid)) return -EINVAL; - dev_dbg(smi->dev, + dev_dbg(priv->dev, "setting VLAN%d 4k members: 0x%02x, untagged: 0x%02x\n", vid, member, untag); /* Update the 4K table */ - ret = smi->ops->get_vlan_4k(smi, vid, &vlan4k); + ret = priv->ops->get_vlan_4k(priv, vid, &vlan4k); if (ret) return ret; vlan4k.member |= member; vlan4k.untag |= untag; vlan4k.fid = fid; - ret = smi->ops->set_vlan_4k(smi, &vlan4k); + ret = priv->ops->set_vlan_4k(priv, &vlan4k); if (ret) return ret; - dev_dbg(smi->dev, + dev_dbg(priv->dev, "resulting VLAN%d 4k members: 0x%02x, untagged: 0x%02x\n", vid, vlan4k.member, vlan4k.untag); /* Find or allocate a member config for this VID */ - ret = rtl8366_obtain_mc(smi, vid, &vlanmc); + ret = rtl8366_obtain_mc(priv, vid, &vlanmc); if (ret < 0) return ret; mc = ret; @@ -176,12 +176,12 @@ int rtl8366_set_vlan(struct realtek_smi *smi, int vid, u32 member, vlanmc.fid = fid; /* Commit updates to the MC entry */ - ret = smi->ops->set_vlan_mc(smi, mc, &vlanmc); + ret = priv->ops->set_vlan_mc(priv, mc, &vlanmc); if (ret) - dev_err(smi->dev, "failed to commit changes to VLAN MC index %d for VID %d\n", + dev_err(priv->dev, "failed to commit changes to VLAN MC index %d for VID %d\n", mc, vid); else - dev_dbg(smi->dev, + dev_dbg(priv->dev, "resulting VLAN%d MC members: 0x%02x, untagged: 0x%02x\n", vid, vlanmc.member, vlanmc.untag); @@ -189,37 +189,37 @@ int rtl8366_set_vlan(struct realtek_smi *smi, int vid, u32 member, } EXPORT_SYMBOL_GPL(rtl8366_set_vlan); -int rtl8366_set_pvid(struct realtek_smi *smi, unsigned int port, +int rtl8366_set_pvid(struct realtek_priv *priv, unsigned int port, unsigned int vid) { struct rtl8366_vlan_mc vlanmc; int mc; int ret; - if (!smi->ops->is_vlan_valid(smi, vid)) + if (!priv->ops->is_vlan_valid(priv, vid)) return -EINVAL; /* Find or allocate a member config for this VID */ - ret = rtl8366_obtain_mc(smi, vid, &vlanmc); + ret = rtl8366_obtain_mc(priv, vid, &vlanmc); if (ret < 0) return ret; mc = ret; - ret = smi->ops->set_mc_index(smi, port, mc); + ret = priv->ops->set_mc_index(priv, port, mc); if (ret) { - dev_err(smi->dev, "set PVID: failed to set MC index %d for port %d\n", + dev_err(priv->dev, "set PVID: failed to set MC index %d for port %d\n", mc, port); return ret; } - dev_dbg(smi->dev, "set PVID: the PVID for port %d set to %d using existing MC index %d\n", + dev_dbg(priv->dev, "set PVID: the PVID for port %d set to %d using existing MC index %d\n", port, vid, mc); return 0; } EXPORT_SYMBOL_GPL(rtl8366_set_pvid); -int rtl8366_enable_vlan4k(struct realtek_smi *smi, bool enable) +int rtl8366_enable_vlan4k(struct realtek_priv *priv, bool enable) { int ret; @@ -229,52 +229,52 @@ int rtl8366_enable_vlan4k(struct realtek_smi *smi, bool enable) */ if (enable) { /* Make sure VLAN is ON */ - ret = smi->ops->enable_vlan(smi, true); + ret = priv->ops->enable_vlan(priv, true); if (ret) return ret; - smi->vlan_enabled = true; + priv->vlan_enabled = true; } - ret = smi->ops->enable_vlan4k(smi, enable); + ret = priv->ops->enable_vlan4k(priv, enable); if (ret) return ret; - smi->vlan4k_enabled = enable; + priv->vlan4k_enabled = enable; return 0; } EXPORT_SYMBOL_GPL(rtl8366_enable_vlan4k); -int rtl8366_enable_vlan(struct realtek_smi *smi, bool enable) +int rtl8366_enable_vlan(struct realtek_priv *priv, bool enable) { int ret; - ret = smi->ops->enable_vlan(smi, enable); + ret = priv->ops->enable_vlan(priv, enable); if (ret) return ret; - smi->vlan_enabled = enable; + priv->vlan_enabled = enable; /* If we turn VLAN off, make sure that we turn off * 4k VLAN as well, if that happened to be on. */ if (!enable) { - smi->vlan4k_enabled = false; - ret = smi->ops->enable_vlan4k(smi, false); + priv->vlan4k_enabled = false; + ret = priv->ops->enable_vlan4k(priv, false); } return ret; } EXPORT_SYMBOL_GPL(rtl8366_enable_vlan); -int rtl8366_reset_vlan(struct realtek_smi *smi) +int rtl8366_reset_vlan(struct realtek_priv *priv) { struct rtl8366_vlan_mc vlanmc; int ret; int i; - rtl8366_enable_vlan(smi, false); - rtl8366_enable_vlan4k(smi, false); + rtl8366_enable_vlan(priv, false); + rtl8366_enable_vlan4k(priv, false); /* Clear the 16 VLAN member configurations */ vlanmc.vid = 0; @@ -282,8 +282,8 @@ int rtl8366_reset_vlan(struct realtek_smi *smi) vlanmc.member = 0; vlanmc.untag = 0; vlanmc.fid = 0; - for (i = 0; i < smi->num_vlan_mc; i++) { - ret = smi->ops->set_vlan_mc(smi, i, &vlanmc); + for (i = 0; i < priv->num_vlan_mc; i++) { + ret = priv->ops->set_vlan_mc(priv, i, &vlanmc); if (ret) return ret; } @@ -298,12 +298,12 @@ int rtl8366_vlan_add(struct dsa_switch *ds, int port, { bool untagged = !!(vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED); bool pvid = !!(vlan->flags & BRIDGE_VLAN_INFO_PVID); - struct realtek_smi *smi = ds->priv; + struct realtek_priv *priv = ds->priv; u32 member = 0; u32 untag = 0; int ret; - if (!smi->ops->is_vlan_valid(smi, vlan->vid)) { + if (!priv->ops->is_vlan_valid(priv, vlan->vid)) { NL_SET_ERR_MSG_MOD(extack, "VLAN ID not valid"); return -EINVAL; } @@ -312,13 +312,13 @@ int rtl8366_vlan_add(struct dsa_switch *ds, int port, * FIXME: what's with this 4k business? * Just rtl8366_enable_vlan() seems inconclusive. */ - ret = rtl8366_enable_vlan4k(smi, true); + ret = rtl8366_enable_vlan4k(priv, true); if (ret) { NL_SET_ERR_MSG_MOD(extack, "Failed to enable VLAN 4K"); return ret; } - dev_dbg(smi->dev, "add VLAN %d on port %d, %s, %s\n", + dev_dbg(priv->dev, "add VLAN %d on port %d, %s, %s\n", vlan->vid, port, untagged ? "untagged" : "tagged", pvid ? "PVID" : "no PVID"); @@ -327,18 +327,18 @@ int rtl8366_vlan_add(struct dsa_switch *ds, int port, if (untagged) untag |= BIT(port); - ret = rtl8366_set_vlan(smi, vlan->vid, member, untag, 0); + ret = rtl8366_set_vlan(priv, vlan->vid, member, untag, 0); if (ret) { - dev_err(smi->dev, "failed to set up VLAN %04x", vlan->vid); + dev_err(priv->dev, "failed to set up VLAN %04x", vlan->vid); return ret; } if (!pvid) return 0; - ret = rtl8366_set_pvid(smi, port, vlan->vid); + ret = rtl8366_set_pvid(priv, port, vlan->vid); if (ret) { - dev_err(smi->dev, "failed to set PVID on port %d to VLAN %04x", + dev_err(priv->dev, "failed to set PVID on port %d to VLAN %04x", port, vlan->vid); return ret; } @@ -350,15 +350,15 @@ EXPORT_SYMBOL_GPL(rtl8366_vlan_add); int rtl8366_vlan_del(struct dsa_switch *ds, int port, const struct switchdev_obj_port_vlan *vlan) { - struct realtek_smi *smi = ds->priv; + struct realtek_priv *priv = ds->priv; int ret, i; - dev_dbg(smi->dev, "del VLAN %d on port %d\n", vlan->vid, port); + dev_dbg(priv->dev, "del VLAN %d on port %d\n", vlan->vid, port); - for (i = 0; i < smi->num_vlan_mc; i++) { + for (i = 0; i < priv->num_vlan_mc; i++) { struct rtl8366_vlan_mc vlanmc; - ret = smi->ops->get_vlan_mc(smi, i, &vlanmc); + ret = priv->ops->get_vlan_mc(priv, i, &vlanmc); if (ret) return ret; @@ -376,9 +376,9 @@ int rtl8366_vlan_del(struct dsa_switch *ds, int port, vlanmc.priority = 0; vlanmc.fid = 0; } - ret = smi->ops->set_vlan_mc(smi, i, &vlanmc); + ret = priv->ops->set_vlan_mc(priv, i, &vlanmc); if (ret) { - dev_err(smi->dev, + dev_err(priv->dev, "failed to remove VLAN %04x\n", vlan->vid); return ret; @@ -394,15 +394,15 @@ EXPORT_SYMBOL_GPL(rtl8366_vlan_del); void rtl8366_get_strings(struct dsa_switch *ds, int port, u32 stringset, uint8_t *data) { - struct realtek_smi *smi = ds->priv; + struct realtek_priv *priv = ds->priv; struct rtl8366_mib_counter *mib; int i; - if (port >= smi->num_ports) + if (port >= priv->num_ports) return; - for (i = 0; i < smi->num_mib_counters; i++) { - mib = &smi->mib_counters[i]; + for (i = 0; i < priv->num_mib_counters; i++) { + mib = &priv->mib_counters[i]; strncpy(data + i * ETH_GSTRING_LEN, mib->name, ETH_GSTRING_LEN); } @@ -411,35 +411,35 @@ EXPORT_SYMBOL_GPL(rtl8366_get_strings); int rtl8366_get_sset_count(struct dsa_switch *ds, int port, int sset) { - struct realtek_smi *smi = ds->priv; + struct realtek_priv *priv = ds->priv; /* We only support SS_STATS */ if (sset != ETH_SS_STATS) return 0; - if (port >= smi->num_ports) + if (port >= priv->num_ports) return -EINVAL; - return smi->num_mib_counters; + return priv->num_mib_counters; } EXPORT_SYMBOL_GPL(rtl8366_get_sset_count); void rtl8366_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data) { - struct realtek_smi *smi = ds->priv; + struct realtek_priv *priv = ds->priv; int i; int ret; - if (port >= smi->num_ports) + if (port >= priv->num_ports) return; - for (i = 0; i < smi->num_mib_counters; i++) { + for (i = 0; i < priv->num_mib_counters; i++) { struct rtl8366_mib_counter *mib; u64 mibvalue = 0; - mib = &smi->mib_counters[i]; - ret = smi->ops->get_mib_counter(smi, port, mib, &mibvalue); + mib = &priv->mib_counters[i]; + ret = priv->ops->get_mib_counter(priv, port, mib, &mibvalue); if (ret) { - dev_err(smi->dev, "error reading MIB counter %s\n", + dev_err(priv->dev, "error reading MIB counter %s\n", mib->name); } data[i] = mibvalue; diff --git a/drivers/net/dsa/realtek/rtl8366rb.c b/drivers/net/dsa/realtek/rtl8366rb.c index ecc19bd5115f..b1635c20276b 100644 --- a/drivers/net/dsa/realtek/rtl8366rb.c +++ b/drivers/net/dsa/realtek/rtl8366rb.c @@ -21,7 +21,7 @@ #include #include -#include "realtek-smi-core.h" +#include "realtek.h" #define RTL8366RB_PORT_NUM_CPU 5 #define RTL8366RB_NUM_PORTS 6 @@ -396,7 +396,7 @@ static struct rtl8366_mib_counter rtl8366rb_mib_counters[] = { { 0, 70, 2, "IfOutBroadcastPkts" }, }; -static int rtl8366rb_get_mib_counter(struct realtek_smi *smi, +static int rtl8366rb_get_mib_counter(struct realtek_priv *priv, int port, struct rtl8366_mib_counter *mib, u64 *mibvalue) @@ -412,12 +412,12 @@ static int rtl8366rb_get_mib_counter(struct realtek_smi *smi, /* Writing access counter address first * then ASIC will prepare 64bits counter wait for being retrived */ - ret = regmap_write(smi->map, addr, 0); /* Write whatever */ + ret = regmap_write(priv->map, addr, 0); /* Write whatever */ if (ret) return ret; /* Read MIB control register */ - ret = regmap_read(smi->map, RTL8366RB_MIB_CTRL_REG, &val); + ret = regmap_read(priv->map, RTL8366RB_MIB_CTRL_REG, &val); if (ret) return -EIO; @@ -430,7 +430,7 @@ static int rtl8366rb_get_mib_counter(struct realtek_smi *smi, /* Read each individual MIB 16 bits at the time */ *mibvalue = 0; for (i = mib->length; i > 0; i--) { - ret = regmap_read(smi->map, addr + (i - 1), &val); + ret = regmap_read(priv->map, addr + (i - 1), &val); if (ret) return ret; *mibvalue = (*mibvalue << 16) | (val & 0xFFFF); @@ -455,38 +455,38 @@ static u32 rtl8366rb_get_irqmask(struct irq_data *d) static void rtl8366rb_mask_irq(struct irq_data *d) { - struct realtek_smi *smi = irq_data_get_irq_chip_data(d); + struct realtek_priv *priv = irq_data_get_irq_chip_data(d); int ret; - ret = regmap_update_bits(smi->map, RTL8366RB_INTERRUPT_MASK_REG, + ret = regmap_update_bits(priv->map, RTL8366RB_INTERRUPT_MASK_REG, rtl8366rb_get_irqmask(d), 0); if (ret) - dev_err(smi->dev, "could not mask IRQ\n"); + dev_err(priv->dev, "could not mask IRQ\n"); } static void rtl8366rb_unmask_irq(struct irq_data *d) { - struct realtek_smi *smi = irq_data_get_irq_chip_data(d); + struct realtek_priv *priv = irq_data_get_irq_chip_data(d); int ret; - ret = regmap_update_bits(smi->map, RTL8366RB_INTERRUPT_MASK_REG, + ret = regmap_update_bits(priv->map, RTL8366RB_INTERRUPT_MASK_REG, rtl8366rb_get_irqmask(d), rtl8366rb_get_irqmask(d)); if (ret) - dev_err(smi->dev, "could not unmask IRQ\n"); + dev_err(priv->dev, "could not unmask IRQ\n"); } static irqreturn_t rtl8366rb_irq(int irq, void *data) { - struct realtek_smi *smi = data; + struct realtek_priv *priv = data; u32 stat; int ret; /* This clears the IRQ status register */ - ret = regmap_read(smi->map, RTL8366RB_INTERRUPT_STATUS_REG, + ret = regmap_read(priv->map, RTL8366RB_INTERRUPT_STATUS_REG, &stat); if (ret) { - dev_err(smi->dev, "can't read interrupt status\n"); + dev_err(priv->dev, "can't read interrupt status\n"); return IRQ_NONE; } stat &= RTL8366RB_INTERRUPT_VALID; @@ -502,7 +502,7 @@ static irqreturn_t rtl8366rb_irq(int irq, void *data) */ if (line < 12 && line > 5) line -= 5; - child_irq = irq_find_mapping(smi->irqdomain, line); + child_irq = irq_find_mapping(priv->irqdomain, line); handle_nested_irq(child_irq); } return IRQ_HANDLED; @@ -538,7 +538,7 @@ static const struct irq_domain_ops rtl8366rb_irqdomain_ops = { .xlate = irq_domain_xlate_onecell, }; -static int rtl8366rb_setup_cascaded_irq(struct realtek_smi *smi) +static int rtl8366rb_setup_cascaded_irq(struct realtek_priv *priv) { struct device_node *intc; unsigned long irq_trig; @@ -547,24 +547,24 @@ static int rtl8366rb_setup_cascaded_irq(struct realtek_smi *smi) u32 val; int i; - intc = of_get_child_by_name(smi->dev->of_node, "interrupt-controller"); + intc = of_get_child_by_name(priv->dev->of_node, "interrupt-controller"); if (!intc) { - dev_err(smi->dev, "missing child interrupt-controller node\n"); + dev_err(priv->dev, "missing child interrupt-controller node\n"); return -EINVAL; } /* RB8366RB IRQs cascade off this one */ irq = of_irq_get(intc, 0); if (irq <= 0) { - dev_err(smi->dev, "failed to get parent IRQ\n"); + dev_err(priv->dev, "failed to get parent IRQ\n"); ret = irq ? irq : -EINVAL; goto out_put_node; } /* This clears the IRQ status register */ - ret = regmap_read(smi->map, RTL8366RB_INTERRUPT_STATUS_REG, + ret = regmap_read(priv->map, RTL8366RB_INTERRUPT_STATUS_REG, &val); if (ret) { - dev_err(smi->dev, "can't read interrupt status\n"); + dev_err(priv->dev, "can't read interrupt status\n"); goto out_put_node; } @@ -573,48 +573,48 @@ static int rtl8366rb_setup_cascaded_irq(struct realtek_smi *smi) switch (irq_trig) { case IRQF_TRIGGER_RISING: case IRQF_TRIGGER_HIGH: - dev_info(smi->dev, "active high/rising IRQ\n"); + dev_info(priv->dev, "active high/rising IRQ\n"); val = 0; break; case IRQF_TRIGGER_FALLING: case IRQF_TRIGGER_LOW: - dev_info(smi->dev, "active low/falling IRQ\n"); + dev_info(priv->dev, "active low/falling IRQ\n"); val = RTL8366RB_INTERRUPT_POLARITY; break; } - ret = regmap_update_bits(smi->map, RTL8366RB_INTERRUPT_CONTROL_REG, + ret = regmap_update_bits(priv->map, RTL8366RB_INTERRUPT_CONTROL_REG, RTL8366RB_INTERRUPT_POLARITY, val); if (ret) { - dev_err(smi->dev, "could not configure IRQ polarity\n"); + dev_err(priv->dev, "could not configure IRQ polarity\n"); goto out_put_node; } - ret = devm_request_threaded_irq(smi->dev, irq, NULL, + ret = devm_request_threaded_irq(priv->dev, irq, NULL, rtl8366rb_irq, IRQF_ONESHOT, - "RTL8366RB", smi); + "RTL8366RB", priv); if (ret) { - dev_err(smi->dev, "unable to request irq: %d\n", ret); + dev_err(priv->dev, "unable to request irq: %d\n", ret); goto out_put_node; } - smi->irqdomain = irq_domain_add_linear(intc, + priv->irqdomain = irq_domain_add_linear(intc, RTL8366RB_NUM_INTERRUPT, &rtl8366rb_irqdomain_ops, - smi); - if (!smi->irqdomain) { - dev_err(smi->dev, "failed to create IRQ domain\n"); + priv); + if (!priv->irqdomain) { + dev_err(priv->dev, "failed to create IRQ domain\n"); ret = -EINVAL; goto out_put_node; } - for (i = 0; i < smi->num_ports; i++) - irq_set_parent(irq_create_mapping(smi->irqdomain, i), irq); + for (i = 0; i < priv->num_ports; i++) + irq_set_parent(irq_create_mapping(priv->irqdomain, i), irq); out_put_node: of_node_put(intc); return ret; } -static int rtl8366rb_set_addr(struct realtek_smi *smi) +static int rtl8366rb_set_addr(struct realtek_priv *priv) { u8 addr[ETH_ALEN]; u16 val; @@ -622,18 +622,18 @@ static int rtl8366rb_set_addr(struct realtek_smi *smi) eth_random_addr(addr); - dev_info(smi->dev, "set MAC: %02X:%02X:%02X:%02X:%02X:%02X\n", + dev_info(priv->dev, "set MAC: %02X:%02X:%02X:%02X:%02X:%02X\n", addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); val = addr[0] << 8 | addr[1]; - ret = regmap_write(smi->map, RTL8366RB_SMAR0, val); + ret = regmap_write(priv->map, RTL8366RB_SMAR0, val); if (ret) return ret; val = addr[2] << 8 | addr[3]; - ret = regmap_write(smi->map, RTL8366RB_SMAR1, val); + ret = regmap_write(priv->map, RTL8366RB_SMAR1, val); if (ret) return ret; val = addr[4] << 8 | addr[5]; - ret = regmap_write(smi->map, RTL8366RB_SMAR2, val); + ret = regmap_write(priv->map, RTL8366RB_SMAR2, val); if (ret) return ret; @@ -765,7 +765,7 @@ static const struct rtl8366rb_jam_tbl_entry rtl8366rb_green_jam[] = { /* Function that jams the tables in the proper registers */ static int rtl8366rb_jam_table(const struct rtl8366rb_jam_tbl_entry *jam_table, - int jam_size, struct realtek_smi *smi, + int jam_size, struct realtek_priv *priv, bool write_dbg) { u32 val; @@ -774,13 +774,13 @@ static int rtl8366rb_jam_table(const struct rtl8366rb_jam_tbl_entry *jam_table, for (i = 0; i < jam_size; i++) { if ((jam_table[i].reg & 0xBE00) == 0xBE00) { - ret = regmap_read(smi->map, + ret = regmap_read(priv->map, RTL8366RB_PHY_ACCESS_BUSY_REG, &val); if (ret) return ret; if (!(val & RTL8366RB_PHY_INT_BUSY)) { - ret = regmap_write(smi->map, + ret = regmap_write(priv->map, RTL8366RB_PHY_ACCESS_CTRL_REG, RTL8366RB_PHY_CTRL_WRITE); if (ret) @@ -788,10 +788,10 @@ static int rtl8366rb_jam_table(const struct rtl8366rb_jam_tbl_entry *jam_table, } } if (write_dbg) - dev_dbg(smi->dev, "jam %04x into register %04x\n", + dev_dbg(priv->dev, "jam %04x into register %04x\n", jam_table[i].val, jam_table[i].reg); - ret = regmap_write(smi->map, + ret = regmap_write(priv->map, jam_table[i].reg, jam_table[i].val); if (ret) @@ -802,7 +802,7 @@ static int rtl8366rb_jam_table(const struct rtl8366rb_jam_tbl_entry *jam_table, static int rtl8366rb_setup(struct dsa_switch *ds) { - struct realtek_smi *smi = ds->priv; + struct realtek_priv *priv = ds->priv; const struct rtl8366rb_jam_tbl_entry *jam_table; struct rtl8366rb *rb; u32 chip_ver = 0; @@ -812,11 +812,11 @@ static int rtl8366rb_setup(struct dsa_switch *ds) int ret; int i; - rb = smi->chip_data; + rb = priv->chip_data; - ret = regmap_read(smi->map, RTL8366RB_CHIP_ID_REG, &chip_id); + ret = regmap_read(priv->map, RTL8366RB_CHIP_ID_REG, &chip_id); if (ret) { - dev_err(smi->dev, "unable to read chip id\n"); + dev_err(priv->dev, "unable to read chip id\n"); return ret; } @@ -824,18 +824,18 @@ static int rtl8366rb_setup(struct dsa_switch *ds) case RTL8366RB_CHIP_ID_8366: break; default: - dev_err(smi->dev, "unknown chip id (%04x)\n", chip_id); + dev_err(priv->dev, "unknown chip id (%04x)\n", chip_id); return -ENODEV; } - ret = regmap_read(smi->map, RTL8366RB_CHIP_VERSION_CTRL_REG, + ret = regmap_read(priv->map, RTL8366RB_CHIP_VERSION_CTRL_REG, &chip_ver); if (ret) { - dev_err(smi->dev, "unable to read chip version\n"); + dev_err(priv->dev, "unable to read chip version\n"); return ret; } - dev_info(smi->dev, "RTL%04x ver %u chip found\n", + dev_info(priv->dev, "RTL%04x ver %u chip found\n", chip_id, chip_ver & RTL8366RB_CHIP_VERSION_MASK); /* Do the init dance using the right jam table */ @@ -872,20 +872,20 @@ static int rtl8366rb_setup(struct dsa_switch *ds) jam_size = ARRAY_SIZE(rtl8366rb_init_jam_dgn3500); } - ret = rtl8366rb_jam_table(jam_table, jam_size, smi, true); + ret = rtl8366rb_jam_table(jam_table, jam_size, priv, true); if (ret) return ret; /* Isolate all user ports so they can only send packets to itself and the CPU port */ for (i = 0; i < RTL8366RB_PORT_NUM_CPU; i++) { - ret = regmap_write(smi->map, RTL8366RB_PORT_ISO(i), + ret = regmap_write(priv->map, RTL8366RB_PORT_ISO(i), RTL8366RB_PORT_ISO_PORTS(BIT(RTL8366RB_PORT_NUM_CPU)) | RTL8366RB_PORT_ISO_EN); if (ret) return ret; } /* CPU port can send packets to all ports */ - ret = regmap_write(smi->map, RTL8366RB_PORT_ISO(RTL8366RB_PORT_NUM_CPU), + ret = regmap_write(priv->map, RTL8366RB_PORT_ISO(RTL8366RB_PORT_NUM_CPU), RTL8366RB_PORT_ISO_PORTS(dsa_user_ports(ds)) | RTL8366RB_PORT_ISO_EN); if (ret) @@ -893,26 +893,26 @@ static int rtl8366rb_setup(struct dsa_switch *ds) /* Set up the "green ethernet" feature */ ret = rtl8366rb_jam_table(rtl8366rb_green_jam, - ARRAY_SIZE(rtl8366rb_green_jam), smi, false); + ARRAY_SIZE(rtl8366rb_green_jam), priv, false); if (ret) return ret; - ret = regmap_write(smi->map, + ret = regmap_write(priv->map, RTL8366RB_GREEN_FEATURE_REG, (chip_ver == 1) ? 0x0007 : 0x0003); if (ret) return ret; /* Vendor driver sets 0x240 in registers 0xc and 0xd (undocumented) */ - ret = regmap_write(smi->map, 0x0c, 0x240); + ret = regmap_write(priv->map, 0x0c, 0x240); if (ret) return ret; - ret = regmap_write(smi->map, 0x0d, 0x240); + ret = regmap_write(priv->map, 0x0d, 0x240); if (ret) return ret; /* Set some random MAC address */ - ret = rtl8366rb_set_addr(smi); + ret = rtl8366rb_set_addr(priv); if (ret) return ret; @@ -921,21 +921,21 @@ static int rtl8366rb_setup(struct dsa_switch *ds) * If you set RTL8368RB_CPU_NO_TAG (bit 15) in this registers * the custom tag is turned off. */ - ret = regmap_update_bits(smi->map, RTL8368RB_CPU_CTRL_REG, + ret = regmap_update_bits(priv->map, RTL8368RB_CPU_CTRL_REG, 0xFFFF, - BIT(smi->cpu_port)); + BIT(priv->cpu_port)); if (ret) return ret; /* Make sure we default-enable the fixed CPU port */ - ret = regmap_update_bits(smi->map, RTL8366RB_PECR, - BIT(smi->cpu_port), + ret = regmap_update_bits(priv->map, RTL8366RB_PECR, + BIT(priv->cpu_port), 0); if (ret) return ret; /* Set maximum packet length to 1536 bytes */ - ret = regmap_update_bits(smi->map, RTL8366RB_SGCR, + ret = regmap_update_bits(priv->map, RTL8366RB_SGCR, RTL8366RB_SGCR_MAX_LENGTH_MASK, RTL8366RB_SGCR_MAX_LENGTH_1536); if (ret) @@ -945,13 +945,13 @@ static int rtl8366rb_setup(struct dsa_switch *ds) rb->max_mtu[i] = 1532; /* Disable learning for all ports */ - ret = regmap_write(smi->map, RTL8366RB_PORT_LEARNDIS_CTRL, + ret = regmap_write(priv->map, RTL8366RB_PORT_LEARNDIS_CTRL, RTL8366RB_PORT_ALL); if (ret) return ret; /* Enable auto ageing for all ports */ - ret = regmap_write(smi->map, RTL8366RB_SECURITY_CTRL, 0); + ret = regmap_write(priv->map, RTL8366RB_SECURITY_CTRL, 0); if (ret) return ret; @@ -962,30 +962,30 @@ static int rtl8366rb_setup(struct dsa_switch *ds) * connected to something exotic such as fiber, then this might * be worth experimenting with. */ - ret = regmap_update_bits(smi->map, RTL8366RB_PMC0, + ret = regmap_update_bits(priv->map, RTL8366RB_PMC0, RTL8366RB_PMC0_P4_IOMODE_MASK, 0 << RTL8366RB_PMC0_P4_IOMODE_SHIFT); if (ret) return ret; /* Accept all packets by default, we enable filtering on-demand */ - ret = regmap_write(smi->map, RTL8366RB_VLAN_INGRESS_CTRL1_REG, + ret = regmap_write(priv->map, RTL8366RB_VLAN_INGRESS_CTRL1_REG, 0); if (ret) return ret; - ret = regmap_write(smi->map, RTL8366RB_VLAN_INGRESS_CTRL2_REG, + ret = regmap_write(priv->map, RTL8366RB_VLAN_INGRESS_CTRL2_REG, 0); if (ret) return ret; /* Don't drop packets whose DA has not been learned */ - ret = regmap_update_bits(smi->map, RTL8366RB_SSCR2, + ret = regmap_update_bits(priv->map, RTL8366RB_SSCR2, RTL8366RB_SSCR2_DROP_UNKNOWN_DA, 0); if (ret) return ret; /* Set blinking, TODO: make this configurable */ - ret = regmap_update_bits(smi->map, RTL8366RB_LED_BLINKRATE_REG, + ret = regmap_update_bits(priv->map, RTL8366RB_LED_BLINKRATE_REG, RTL8366RB_LED_BLINKRATE_MASK, RTL8366RB_LED_BLINKRATE_56MS); if (ret) @@ -996,15 +996,15 @@ static int rtl8366rb_setup(struct dsa_switch *ds) * behaviour (no individual config) but we can set up each * LED separately. */ - if (smi->leds_disabled) { + if (priv->leds_disabled) { /* Turn everything off */ - regmap_update_bits(smi->map, + regmap_update_bits(priv->map, RTL8366RB_LED_0_1_CTRL_REG, 0x0FFF, 0); - regmap_update_bits(smi->map, + regmap_update_bits(priv->map, RTL8366RB_LED_2_3_CTRL_REG, 0x0FFF, 0); - regmap_update_bits(smi->map, + regmap_update_bits(priv->map, RTL8366RB_INTERRUPT_CONTROL_REG, RTL8366RB_P4_RGMII_LED, 0); @@ -1014,7 +1014,7 @@ static int rtl8366rb_setup(struct dsa_switch *ds) val = RTL8366RB_LED_FORCE; } for (i = 0; i < 4; i++) { - ret = regmap_update_bits(smi->map, + ret = regmap_update_bits(priv->map, RTL8366RB_LED_CTRL_REG, 0xf << (i * 4), val << (i * 4)); @@ -1022,17 +1022,17 @@ static int rtl8366rb_setup(struct dsa_switch *ds) return ret; } - ret = rtl8366_reset_vlan(smi); + ret = rtl8366_reset_vlan(priv); if (ret) return ret; - ret = rtl8366rb_setup_cascaded_irq(smi); + ret = rtl8366rb_setup_cascaded_irq(priv); if (ret) - dev_info(smi->dev, "no interrupt support\n"); + dev_info(priv->dev, "no interrupt support\n"); - ret = realtek_smi_setup_mdio(smi); + ret = priv->setup_interface(ds); if (ret) { - dev_info(smi->dev, "could not set up MDIO bus\n"); + dev_info(priv->dev, "could not set up MDIO bus\n"); return -ENODEV; } @@ -1052,35 +1052,35 @@ rtl8366rb_mac_link_up(struct dsa_switch *ds, int port, unsigned int mode, phy_interface_t interface, struct phy_device *phydev, int speed, int duplex, bool tx_pause, bool rx_pause) { - struct realtek_smi *smi = ds->priv; + struct realtek_priv *priv = ds->priv; int ret; - if (port != smi->cpu_port) + if (port != priv->cpu_port) return; - dev_dbg(smi->dev, "MAC link up on CPU port (%d)\n", port); + dev_dbg(priv->dev, "MAC link up on CPU port (%d)\n", port); /* Force the fixed CPU port into 1Gbit mode, no autonegotiation */ - ret = regmap_update_bits(smi->map, RTL8366RB_MAC_FORCE_CTRL_REG, + ret = regmap_update_bits(priv->map, RTL8366RB_MAC_FORCE_CTRL_REG, BIT(port), BIT(port)); if (ret) { - dev_err(smi->dev, "failed to force 1Gbit on CPU port\n"); + dev_err(priv->dev, "failed to force 1Gbit on CPU port\n"); return; } - ret = regmap_update_bits(smi->map, RTL8366RB_PAACR2, + ret = regmap_update_bits(priv->map, RTL8366RB_PAACR2, 0xFF00U, RTL8366RB_PAACR_CPU_PORT << 8); if (ret) { - dev_err(smi->dev, "failed to set PAACR on CPU port\n"); + dev_err(priv->dev, "failed to set PAACR on CPU port\n"); return; } /* Enable the CPU port */ - ret = regmap_update_bits(smi->map, RTL8366RB_PECR, BIT(port), + ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port), 0); if (ret) { - dev_err(smi->dev, "failed to enable the CPU port\n"); + dev_err(priv->dev, "failed to enable the CPU port\n"); return; } } @@ -1089,99 +1089,99 @@ static void rtl8366rb_mac_link_down(struct dsa_switch *ds, int port, unsigned int mode, phy_interface_t interface) { - struct realtek_smi *smi = ds->priv; + struct realtek_priv *priv = ds->priv; int ret; - if (port != smi->cpu_port) + if (port != priv->cpu_port) return; - dev_dbg(smi->dev, "MAC link down on CPU port (%d)\n", port); + dev_dbg(priv->dev, "MAC link down on CPU port (%d)\n", port); /* Disable the CPU port */ - ret = regmap_update_bits(smi->map, RTL8366RB_PECR, BIT(port), + ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port), BIT(port)); if (ret) { - dev_err(smi->dev, "failed to disable the CPU port\n"); + dev_err(priv->dev, "failed to disable the CPU port\n"); return; } } -static void rb8366rb_set_port_led(struct realtek_smi *smi, +static void rb8366rb_set_port_led(struct realtek_priv *priv, int port, bool enable) { u16 val = enable ? 0x3f : 0; int ret; - if (smi->leds_disabled) + if (priv->leds_disabled) return; switch (port) { case 0: - ret = regmap_update_bits(smi->map, + ret = regmap_update_bits(priv->map, RTL8366RB_LED_0_1_CTRL_REG, 0x3F, val); break; case 1: - ret = regmap_update_bits(smi->map, + ret = regmap_update_bits(priv->map, RTL8366RB_LED_0_1_CTRL_REG, 0x3F << RTL8366RB_LED_1_OFFSET, val << RTL8366RB_LED_1_OFFSET); break; case 2: - ret = regmap_update_bits(smi->map, + ret = regmap_update_bits(priv->map, RTL8366RB_LED_2_3_CTRL_REG, 0x3F, val); break; case 3: - ret = regmap_update_bits(smi->map, + ret = regmap_update_bits(priv->map, RTL8366RB_LED_2_3_CTRL_REG, 0x3F << RTL8366RB_LED_3_OFFSET, val << RTL8366RB_LED_3_OFFSET); break; case 4: - ret = regmap_update_bits(smi->map, + ret = regmap_update_bits(priv->map, RTL8366RB_INTERRUPT_CONTROL_REG, RTL8366RB_P4_RGMII_LED, enable ? RTL8366RB_P4_RGMII_LED : 0); break; default: - dev_err(smi->dev, "no LED for port %d\n", port); + dev_err(priv->dev, "no LED for port %d\n", port); return; } if (ret) - dev_err(smi->dev, "error updating LED on port %d\n", port); + dev_err(priv->dev, "error updating LED on port %d\n", port); } static int rtl8366rb_port_enable(struct dsa_switch *ds, int port, struct phy_device *phy) { - struct realtek_smi *smi = ds->priv; + struct realtek_priv *priv = ds->priv; int ret; - dev_dbg(smi->dev, "enable port %d\n", port); - ret = regmap_update_bits(smi->map, RTL8366RB_PECR, BIT(port), + dev_dbg(priv->dev, "enable port %d\n", port); + ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port), 0); if (ret) return ret; - rb8366rb_set_port_led(smi, port, true); + rb8366rb_set_port_led(priv, port, true); return 0; } static void rtl8366rb_port_disable(struct dsa_switch *ds, int port) { - struct realtek_smi *smi = ds->priv; + struct realtek_priv *priv = ds->priv; int ret; - dev_dbg(smi->dev, "disable port %d\n", port); - ret = regmap_update_bits(smi->map, RTL8366RB_PECR, BIT(port), + dev_dbg(priv->dev, "disable port %d\n", port); + ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port), BIT(port)); if (ret) return; - rb8366rb_set_port_led(smi, port, false); + rb8366rb_set_port_led(priv, port, false); } static int @@ -1189,7 +1189,7 @@ rtl8366rb_port_bridge_join(struct dsa_switch *ds, int port, struct dsa_bridge bridge, bool *tx_fwd_offload) { - struct realtek_smi *smi = ds->priv; + struct realtek_priv *priv = ds->priv; unsigned int port_bitmap = 0; int ret, i; @@ -1202,17 +1202,17 @@ rtl8366rb_port_bridge_join(struct dsa_switch *ds, int port, if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge)) continue; /* Join this port to each other port on the bridge */ - ret = regmap_update_bits(smi->map, RTL8366RB_PORT_ISO(i), + ret = regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(i), RTL8366RB_PORT_ISO_PORTS(BIT(port)), RTL8366RB_PORT_ISO_PORTS(BIT(port))); if (ret) - dev_err(smi->dev, "failed to join port %d\n", port); + dev_err(priv->dev, "failed to join port %d\n", port); port_bitmap |= BIT(i); } /* Set the bits for the ports we can access */ - return regmap_update_bits(smi->map, RTL8366RB_PORT_ISO(port), + return regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(port), RTL8366RB_PORT_ISO_PORTS(port_bitmap), RTL8366RB_PORT_ISO_PORTS(port_bitmap)); } @@ -1221,7 +1221,7 @@ static void rtl8366rb_port_bridge_leave(struct dsa_switch *ds, int port, struct dsa_bridge bridge) { - struct realtek_smi *smi = ds->priv; + struct realtek_priv *priv = ds->priv; unsigned int port_bitmap = 0; int ret, i; @@ -1234,28 +1234,28 @@ rtl8366rb_port_bridge_leave(struct dsa_switch *ds, int port, if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge)) continue; /* Remove this port from any other port on the bridge */ - ret = regmap_update_bits(smi->map, RTL8366RB_PORT_ISO(i), + ret = regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(i), RTL8366RB_PORT_ISO_PORTS(BIT(port)), 0); if (ret) - dev_err(smi->dev, "failed to leave port %d\n", port); + dev_err(priv->dev, "failed to leave port %d\n", port); port_bitmap |= BIT(i); } /* Clear the bits for the ports we can not access, leave ourselves */ - regmap_update_bits(smi->map, RTL8366RB_PORT_ISO(port), + regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(port), RTL8366RB_PORT_ISO_PORTS(port_bitmap), 0); } /** * rtl8366rb_drop_untagged() - make the switch drop untagged and C-tagged frames - * @smi: SMI state container + * @priv: SMI state container * @port: the port to drop untagged and C-tagged frames on * @drop: whether to drop or pass untagged and C-tagged frames */ -static int rtl8366rb_drop_untagged(struct realtek_smi *smi, int port, bool drop) +static int rtl8366rb_drop_untagged(struct realtek_priv *priv, int port, bool drop) { - return regmap_update_bits(smi->map, RTL8366RB_VLAN_INGRESS_CTRL1_REG, + return regmap_update_bits(priv->map, RTL8366RB_VLAN_INGRESS_CTRL1_REG, RTL8366RB_VLAN_INGRESS_CTRL1_DROP(port), drop ? RTL8366RB_VLAN_INGRESS_CTRL1_DROP(port) : 0); } @@ -1264,17 +1264,17 @@ static int rtl8366rb_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, struct netlink_ext_ack *extack) { - struct realtek_smi *smi = ds->priv; + struct realtek_priv *priv = ds->priv; struct rtl8366rb *rb; int ret; - rb = smi->chip_data; + rb = priv->chip_data; - dev_dbg(smi->dev, "port %d: %s VLAN filtering\n", port, + dev_dbg(priv->dev, "port %d: %s VLAN filtering\n", port, vlan_filtering ? "enable" : "disable"); /* If the port is not in the member set, the frame will be dropped */ - ret = regmap_update_bits(smi->map, RTL8366RB_VLAN_INGRESS_CTRL2_REG, + ret = regmap_update_bits(priv->map, RTL8366RB_VLAN_INGRESS_CTRL2_REG, BIT(port), vlan_filtering ? BIT(port) : 0); if (ret) return ret; @@ -1284,9 +1284,9 @@ static int rtl8366rb_vlan_filtering(struct dsa_switch *ds, int port, * filtering on a port, we need to accept any frames. */ if (vlan_filtering) - ret = rtl8366rb_drop_untagged(smi, port, !rb->pvid_enabled[port]); + ret = rtl8366rb_drop_untagged(priv, port, !rb->pvid_enabled[port]); else - ret = rtl8366rb_drop_untagged(smi, port, false); + ret = rtl8366rb_drop_untagged(priv, port, false); return ret; } @@ -1308,11 +1308,11 @@ rtl8366rb_port_bridge_flags(struct dsa_switch *ds, int port, struct switchdev_brport_flags flags, struct netlink_ext_ack *extack) { - struct realtek_smi *smi = ds->priv; + struct realtek_priv *priv = ds->priv; int ret; if (flags.mask & BR_LEARNING) { - ret = regmap_update_bits(smi->map, RTL8366RB_PORT_LEARNDIS_CTRL, + ret = regmap_update_bits(priv->map, RTL8366RB_PORT_LEARNDIS_CTRL, BIT(port), (flags.val & BR_LEARNING) ? 0 : BIT(port)); if (ret) @@ -1325,7 +1325,7 @@ rtl8366rb_port_bridge_flags(struct dsa_switch *ds, int port, static void rtl8366rb_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) { - struct realtek_smi *smi = ds->priv; + struct realtek_priv *priv = ds->priv; u32 val; int i; @@ -1344,13 +1344,13 @@ rtl8366rb_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) val = RTL8366RB_STP_STATE_FORWARDING; break; default: - dev_err(smi->dev, "unknown bridge state requested\n"); + dev_err(priv->dev, "unknown bridge state requested\n"); return; } /* Set the same status for the port on all the FIDs */ for (i = 0; i < RTL8366RB_NUM_FIDS; i++) { - regmap_update_bits(smi->map, RTL8366RB_STP_STATE_BASE + i, + regmap_update_bits(priv->map, RTL8366RB_STP_STATE_BASE + i, RTL8366RB_STP_STATE_MASK(port), RTL8366RB_STP_STATE(port, val)); } @@ -1359,26 +1359,26 @@ rtl8366rb_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) static void rtl8366rb_port_fast_age(struct dsa_switch *ds, int port) { - struct realtek_smi *smi = ds->priv; + struct realtek_priv *priv = ds->priv; /* This will age out any learned L2 entries */ - regmap_update_bits(smi->map, RTL8366RB_SECURITY_CTRL, + regmap_update_bits(priv->map, RTL8366RB_SECURITY_CTRL, BIT(port), BIT(port)); /* Restore the normal state of things */ - regmap_update_bits(smi->map, RTL8366RB_SECURITY_CTRL, + regmap_update_bits(priv->map, RTL8366RB_SECURITY_CTRL, BIT(port), 0); } static int rtl8366rb_change_mtu(struct dsa_switch *ds, int port, int new_mtu) { - struct realtek_smi *smi = ds->priv; + struct realtek_priv *priv = ds->priv; struct rtl8366rb *rb; unsigned int max_mtu; u32 len; int i; /* Cache the per-port MTU setting */ - rb = smi->chip_data; + rb = priv->chip_data; rb->max_mtu[port] = new_mtu; /* Roof out the MTU for the entire switch to the greatest @@ -1406,7 +1406,7 @@ static int rtl8366rb_change_mtu(struct dsa_switch *ds, int port, int new_mtu) else len = RTL8366RB_SGCR_MAX_LENGTH_16000; - return regmap_update_bits(smi->map, RTL8366RB_SGCR, + return regmap_update_bits(priv->map, RTL8366RB_SGCR, RTL8366RB_SGCR_MAX_LENGTH_MASK, len); } @@ -1419,7 +1419,7 @@ static int rtl8366rb_max_mtu(struct dsa_switch *ds, int port) return 15996; } -static int rtl8366rb_get_vlan_4k(struct realtek_smi *smi, u32 vid, +static int rtl8366rb_get_vlan_4k(struct realtek_priv *priv, u32 vid, struct rtl8366_vlan_4k *vlan4k) { u32 data[3]; @@ -1432,19 +1432,19 @@ static int rtl8366rb_get_vlan_4k(struct realtek_smi *smi, u32 vid, return -EINVAL; /* write VID */ - ret = regmap_write(smi->map, RTL8366RB_VLAN_TABLE_WRITE_BASE, + ret = regmap_write(priv->map, RTL8366RB_VLAN_TABLE_WRITE_BASE, vid & RTL8366RB_VLAN_VID_MASK); if (ret) return ret; /* write table access control word */ - ret = regmap_write(smi->map, RTL8366RB_TABLE_ACCESS_CTRL_REG, + ret = regmap_write(priv->map, RTL8366RB_TABLE_ACCESS_CTRL_REG, RTL8366RB_TABLE_VLAN_READ_CTRL); if (ret) return ret; for (i = 0; i < 3; i++) { - ret = regmap_read(smi->map, + ret = regmap_read(priv->map, RTL8366RB_VLAN_TABLE_READ_BASE + i, &data[i]); if (ret) @@ -1460,7 +1460,7 @@ static int rtl8366rb_get_vlan_4k(struct realtek_smi *smi, u32 vid, return 0; } -static int rtl8366rb_set_vlan_4k(struct realtek_smi *smi, +static int rtl8366rb_set_vlan_4k(struct realtek_priv *priv, const struct rtl8366_vlan_4k *vlan4k) { u32 data[3]; @@ -1480,7 +1480,7 @@ static int rtl8366rb_set_vlan_4k(struct realtek_smi *smi, data[2] = vlan4k->fid & RTL8366RB_VLAN_FID_MASK; for (i = 0; i < 3; i++) { - ret = regmap_write(smi->map, + ret = regmap_write(priv->map, RTL8366RB_VLAN_TABLE_WRITE_BASE + i, data[i]); if (ret) @@ -1488,13 +1488,13 @@ static int rtl8366rb_set_vlan_4k(struct realtek_smi *smi, } /* write table access control word */ - ret = regmap_write(smi->map, RTL8366RB_TABLE_ACCESS_CTRL_REG, + ret = regmap_write(priv->map, RTL8366RB_TABLE_ACCESS_CTRL_REG, RTL8366RB_TABLE_VLAN_WRITE_CTRL); return ret; } -static int rtl8366rb_get_vlan_mc(struct realtek_smi *smi, u32 index, +static int rtl8366rb_get_vlan_mc(struct realtek_priv *priv, u32 index, struct rtl8366_vlan_mc *vlanmc) { u32 data[3]; @@ -1507,7 +1507,7 @@ static int rtl8366rb_get_vlan_mc(struct realtek_smi *smi, u32 index, return -EINVAL; for (i = 0; i < 3; i++) { - ret = regmap_read(smi->map, + ret = regmap_read(priv->map, RTL8366RB_VLAN_MC_BASE(index) + i, &data[i]); if (ret) @@ -1525,7 +1525,7 @@ static int rtl8366rb_get_vlan_mc(struct realtek_smi *smi, u32 index, return 0; } -static int rtl8366rb_set_vlan_mc(struct realtek_smi *smi, u32 index, +static int rtl8366rb_set_vlan_mc(struct realtek_priv *priv, u32 index, const struct rtl8366_vlan_mc *vlanmc) { u32 data[3]; @@ -1549,7 +1549,7 @@ static int rtl8366rb_set_vlan_mc(struct realtek_smi *smi, u32 index, data[2] = vlanmc->fid & RTL8366RB_VLAN_FID_MASK; for (i = 0; i < 3; i++) { - ret = regmap_write(smi->map, + ret = regmap_write(priv->map, RTL8366RB_VLAN_MC_BASE(index) + i, data[i]); if (ret) @@ -1559,15 +1559,15 @@ static int rtl8366rb_set_vlan_mc(struct realtek_smi *smi, u32 index, return 0; } -static int rtl8366rb_get_mc_index(struct realtek_smi *smi, int port, int *val) +static int rtl8366rb_get_mc_index(struct realtek_priv *priv, int port, int *val) { u32 data; int ret; - if (port >= smi->num_ports) + if (port >= priv->num_ports) return -EINVAL; - ret = regmap_read(smi->map, RTL8366RB_PORT_VLAN_CTRL_REG(port), + ret = regmap_read(priv->map, RTL8366RB_PORT_VLAN_CTRL_REG(port), &data); if (ret) return ret; @@ -1578,19 +1578,19 @@ static int rtl8366rb_get_mc_index(struct realtek_smi *smi, int port, int *val) return 0; } -static int rtl8366rb_set_mc_index(struct realtek_smi *smi, int port, int index) +static int rtl8366rb_set_mc_index(struct realtek_priv *priv, int port, int index) { struct rtl8366rb *rb; bool pvid_enabled; int ret; - rb = smi->chip_data; + rb = priv->chip_data; pvid_enabled = !!index; - if (port >= smi->num_ports || index >= RTL8366RB_NUM_VLANS) + if (port >= priv->num_ports || index >= RTL8366RB_NUM_VLANS) return -EINVAL; - ret = regmap_update_bits(smi->map, RTL8366RB_PORT_VLAN_CTRL_REG(port), + ret = regmap_update_bits(priv->map, RTL8366RB_PORT_VLAN_CTRL_REG(port), RTL8366RB_PORT_VLAN_CTRL_MASK << RTL8366RB_PORT_VLAN_CTRL_SHIFT(port), (index & RTL8366RB_PORT_VLAN_CTRL_MASK) << @@ -1604,17 +1604,17 @@ static int rtl8366rb_set_mc_index(struct realtek_smi *smi, int port, int index) * not drop any untagged or C-tagged frames. Make sure to update the * filtering setting. */ - if (dsa_port_is_vlan_filtering(dsa_to_port(smi->ds, port))) - ret = rtl8366rb_drop_untagged(smi, port, !pvid_enabled); + if (dsa_port_is_vlan_filtering(dsa_to_port(priv->ds, port))) + ret = rtl8366rb_drop_untagged(priv, port, !pvid_enabled); return ret; } -static bool rtl8366rb_is_vlan_valid(struct realtek_smi *smi, unsigned int vlan) +static bool rtl8366rb_is_vlan_valid(struct realtek_priv *priv, unsigned int vlan) { unsigned int max = RTL8366RB_NUM_VLANS - 1; - if (smi->vlan4k_enabled) + if (priv->vlan4k_enabled) max = RTL8366RB_NUM_VIDS - 1; if (vlan > max) @@ -1623,23 +1623,23 @@ static bool rtl8366rb_is_vlan_valid(struct realtek_smi *smi, unsigned int vlan) return true; } -static int rtl8366rb_enable_vlan(struct realtek_smi *smi, bool enable) +static int rtl8366rb_enable_vlan(struct realtek_priv *priv, bool enable) { - dev_dbg(smi->dev, "%s VLAN\n", enable ? "enable" : "disable"); - return regmap_update_bits(smi->map, + dev_dbg(priv->dev, "%s VLAN\n", enable ? "enable" : "disable"); + return regmap_update_bits(priv->map, RTL8366RB_SGCR, RTL8366RB_SGCR_EN_VLAN, enable ? RTL8366RB_SGCR_EN_VLAN : 0); } -static int rtl8366rb_enable_vlan4k(struct realtek_smi *smi, bool enable) +static int rtl8366rb_enable_vlan4k(struct realtek_priv *priv, bool enable) { - dev_dbg(smi->dev, "%s VLAN 4k\n", enable ? "enable" : "disable"); - return regmap_update_bits(smi->map, RTL8366RB_SGCR, + dev_dbg(priv->dev, "%s VLAN 4k\n", enable ? "enable" : "disable"); + return regmap_update_bits(priv->map, RTL8366RB_SGCR, RTL8366RB_SGCR_EN_VLAN_4KTB, enable ? RTL8366RB_SGCR_EN_VLAN_4KTB : 0); } -static int rtl8366rb_phy_read(struct realtek_smi *smi, int phy, int regnum) +static int rtl8366rb_phy_read(struct realtek_priv *priv, int phy, int regnum) { u32 val; u32 reg; @@ -1648,32 +1648,32 @@ static int rtl8366rb_phy_read(struct realtek_smi *smi, int phy, int regnum) if (phy > RTL8366RB_PHY_NO_MAX) return -EINVAL; - ret = regmap_write(smi->map, RTL8366RB_PHY_ACCESS_CTRL_REG, + ret = regmap_write(priv->map, RTL8366RB_PHY_ACCESS_CTRL_REG, RTL8366RB_PHY_CTRL_READ); if (ret) return ret; reg = 0x8000 | (1 << (phy + RTL8366RB_PHY_NO_OFFSET)) | regnum; - ret = regmap_write(smi->map, reg, 0); + ret = regmap_write(priv->map, reg, 0); if (ret) { - dev_err(smi->dev, + dev_err(priv->dev, "failed to write PHY%d reg %04x @ %04x, ret %d\n", phy, regnum, reg, ret); return ret; } - ret = regmap_read(smi->map, RTL8366RB_PHY_ACCESS_DATA_REG, &val); + ret = regmap_read(priv->map, RTL8366RB_PHY_ACCESS_DATA_REG, &val); if (ret) return ret; - dev_dbg(smi->dev, "read PHY%d register 0x%04x @ %08x, val <- %04x\n", + dev_dbg(priv->dev, "read PHY%d register 0x%04x @ %08x, val <- %04x\n", phy, regnum, reg, val); return val; } -static int rtl8366rb_phy_write(struct realtek_smi *smi, int phy, int regnum, +static int rtl8366rb_phy_write(struct realtek_priv *priv, int phy, int regnum, u16 val) { u32 reg; @@ -1682,34 +1682,34 @@ static int rtl8366rb_phy_write(struct realtek_smi *smi, int phy, int regnum, if (phy > RTL8366RB_PHY_NO_MAX) return -EINVAL; - ret = regmap_write(smi->map, RTL8366RB_PHY_ACCESS_CTRL_REG, + ret = regmap_write(priv->map, RTL8366RB_PHY_ACCESS_CTRL_REG, RTL8366RB_PHY_CTRL_WRITE); if (ret) return ret; reg = 0x8000 | (1 << (phy + RTL8366RB_PHY_NO_OFFSET)) | regnum; - dev_dbg(smi->dev, "write PHY%d register 0x%04x @ %04x, val -> %04x\n", + dev_dbg(priv->dev, "write PHY%d register 0x%04x @ %04x, val -> %04x\n", phy, regnum, reg, val); - ret = regmap_write(smi->map, reg, val); + ret = regmap_write(priv->map, reg, val); if (ret) return ret; return 0; } -static int rtl8366rb_reset_chip(struct realtek_smi *smi) +static int rtl8366rb_reset_chip(struct realtek_priv *priv) { int timeout = 10; u32 val; int ret; - realtek_smi_write_reg_noack(smi, RTL8366RB_RESET_CTRL_REG, + priv->write_reg_noack(priv, RTL8366RB_RESET_CTRL_REG, RTL8366RB_CHIP_CTRL_RESET_HW); do { usleep_range(20000, 25000); - ret = regmap_read(smi->map, RTL8366RB_RESET_CTRL_REG, &val); + ret = regmap_read(priv->map, RTL8366RB_RESET_CTRL_REG, &val); if (ret) return ret; @@ -1718,21 +1718,21 @@ static int rtl8366rb_reset_chip(struct realtek_smi *smi) } while (--timeout); if (!timeout) { - dev_err(smi->dev, "timeout waiting for the switch to reset\n"); + dev_err(priv->dev, "timeout waiting for the switch to reset\n"); return -EIO; } return 0; } -static int rtl8366rb_detect(struct realtek_smi *smi) +static int rtl8366rb_detect(struct realtek_priv *priv) { - struct device *dev = smi->dev; + struct device *dev = priv->dev; int ret; u32 val; /* Detect device */ - ret = regmap_read(smi->map, 0x5c, &val); + ret = regmap_read(priv->map, 0x5c, &val); if (ret) { dev_err(dev, "can't get chip ID (%d)\n", ret); return ret; @@ -1745,11 +1745,11 @@ static int rtl8366rb_detect(struct realtek_smi *smi) return -ENODEV; case 0x5937: dev_info(dev, "found an RTL8366RB switch\n"); - smi->cpu_port = RTL8366RB_PORT_NUM_CPU; - smi->num_ports = RTL8366RB_NUM_PORTS; - smi->num_vlan_mc = RTL8366RB_NUM_VLANS; - smi->mib_counters = rtl8366rb_mib_counters; - smi->num_mib_counters = ARRAY_SIZE(rtl8366rb_mib_counters); + priv->cpu_port = RTL8366RB_PORT_NUM_CPU; + priv->num_ports = RTL8366RB_NUM_PORTS; + priv->num_vlan_mc = RTL8366RB_NUM_VLANS; + priv->mib_counters = rtl8366rb_mib_counters; + priv->num_mib_counters = ARRAY_SIZE(rtl8366rb_mib_counters); break; default: dev_info(dev, "found an Unknown Realtek switch (id=0x%04x)\n", @@ -1757,7 +1757,7 @@ static int rtl8366rb_detect(struct realtek_smi *smi) break; } - ret = rtl8366rb_reset_chip(smi); + ret = rtl8366rb_reset_chip(priv); if (ret) return ret; @@ -1787,7 +1787,7 @@ static const struct dsa_switch_ops rtl8366rb_switch_ops = { .port_max_mtu = rtl8366rb_max_mtu, }; -static const struct realtek_smi_ops rtl8366rb_smi_ops = { +static const struct realtek_ops rtl8366rb_ops = { .detect = rtl8366rb_detect, .get_vlan_mc = rtl8366rb_get_vlan_mc, .set_vlan_mc = rtl8366rb_set_vlan_mc, @@ -1803,9 +1803,9 @@ static const struct realtek_smi_ops rtl8366rb_smi_ops = { .phy_write = rtl8366rb_phy_write, }; -const struct realtek_smi_variant rtl8366rb_variant = { +const struct realtek_variant rtl8366rb_variant = { .ds_ops = &rtl8366rb_switch_ops, - .ops = &rtl8366rb_smi_ops, + .ops = &rtl8366rb_ops, .clk_delay = 10, .cmd_read = 0xa9, .cmd_write = 0xa8, From patchwork Thu Dec 16 20:13:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Luiz Angelo Daros de Luca X-Patchwork-Id: 12682443 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 66082C433FE for ; Thu, 16 Dec 2021 20:14:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241242AbhLPUOZ (ORCPT ); Thu, 16 Dec 2021 15:14:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41418 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241228AbhLPUOY (ORCPT ); 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[187.49.235.234]) by smtp.gmail.com with ESMTPSA id a15sm5110266qtb.5.2021.12.16.12.14.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Dec 2021 12:14:22 -0800 (PST) From: luizluca@gmail.com To: netdev@vger.kernel.org Cc: linus.walleij@linaro.org, andrew@lunn.ch, vivien.didelot@gmail.com, f.fainelli@gmail.com, olteanv@gmail.com, alsi@bang-olufsen.dk, arinc.unal@arinc9.com, Luiz Angelo Daros de Luca Subject: [PATCH net-next 04/13] net: dsa: realtek: convert subdrivers into modules Date: Thu, 16 Dec 2021 17:13:33 -0300 Message-Id: <20211216201342.25587-5-luizluca@gmail.com> X-Mailer: git-send-email 2.34.0 In-Reply-To: <20211216201342.25587-1-luizluca@gmail.com> References: <20211216201342.25587-1-luizluca@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Luiz Angelo Daros de Luca Preparing for multiple interfaces support, the drivers must be independent of realtek-smi. Tested-by: Arınç ÜNAL Signed-off-by: Luiz Angelo Daros de Luca Reported-by: kernel test robot --- drivers/net/dsa/realtek/Kconfig | 20 +++++++++++++++++-- drivers/net/dsa/realtek/Makefile | 4 +++- .../{realtek-smi-core.c => realtek-smi.c} | 15 ++++++++++---- drivers/net/dsa/realtek/rtl8365mb.c | 2 ++ .../dsa/realtek/{rtl8366.c => rtl8366-core.c} | 0 drivers/net/dsa/realtek/rtl8366rb.c | 2 ++ 6 files changed, 36 insertions(+), 7 deletions(-) rename drivers/net/dsa/realtek/{realtek-smi-core.c => realtek-smi.c} (96%) rename drivers/net/dsa/realtek/{rtl8366.c => rtl8366-core.c} (100%) diff --git a/drivers/net/dsa/realtek/Kconfig b/drivers/net/dsa/realtek/Kconfig index bbc6e918baa6..c002a84a00f5 100644 --- a/drivers/net/dsa/realtek/Kconfig +++ b/drivers/net/dsa/realtek/Kconfig @@ -2,8 +2,6 @@ menuconfig NET_DSA_REALTEK tristate "Realtek Ethernet switch family support" depends on NET_DSA - select NET_DSA_TAG_RTL4_A - select NET_DSA_TAG_RTL8_4 select FIXED_PHY select IRQ_DOMAIN select REALTEK_PHY @@ -17,3 +15,21 @@ config NET_DSA_REALTEK_SMI default y help Select to enable support for registering switches connected through SMI. + +config NET_DSA_REALTEK_RTL8365MB + tristate "Realtek RTL8365MB switch subdriver" + default y + depends on NET_DSA_REALTEK + depends on NET_DSA_REALTEK_SMI + select NET_DSA_TAG_RTL8_4 + help + Select to enable support for Realtek RTL8365MB + +config NET_DSA_REALTEK_RTL8366RB + tristate "Realtek RTL8366RB switch subdriver" + default y + depends on NET_DSA_REALTEK + depends on NET_DSA_REALTEK_SMI + select NET_DSA_TAG_RTL4_A + help + Select to enable support for Realtek RTL8366RB diff --git a/drivers/net/dsa/realtek/Makefile b/drivers/net/dsa/realtek/Makefile index 323b921bfce0..8b5a4abcedd3 100644 --- a/drivers/net/dsa/realtek/Makefile +++ b/drivers/net/dsa/realtek/Makefile @@ -1,3 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_NET_DSA_REALTEK_SMI) += realtek-smi.o -realtek-smi-objs := realtek-smi-core.o rtl8366.o rtl8366rb.o rtl8365mb.o +obj-$(CONFIG_NET_DSA_REALTEK_RTL8366RB) += rtl8366.o +rtl8366-objs := rtl8366-core.o rtl8366rb.o +obj-$(CONFIG_NET_DSA_REALTEK_RTL8365MB) += rtl8365mb.o diff --git a/drivers/net/dsa/realtek/realtek-smi-core.c b/drivers/net/dsa/realtek/realtek-smi.c similarity index 96% rename from drivers/net/dsa/realtek/realtek-smi-core.c rename to drivers/net/dsa/realtek/realtek-smi.c index 2c78eb5c0bdc..11447096c8dc 100644 --- a/drivers/net/dsa/realtek/realtek-smi-core.c +++ b/drivers/net/dsa/realtek/realtek-smi.c @@ -297,7 +297,6 @@ int realtek_smi_write_reg_noack(struct realtek_priv *priv, u32 addr, { return realtek_smi_write_reg(priv, addr, data, false); } -EXPORT_SYMBOL_GPL(realtek_smi_write_reg_noack); /* Regmap accessors */ @@ -342,8 +341,9 @@ static int realtek_smi_mdio_write(struct mii_bus *bus, int addr, int regnum, return priv->ops->phy_write(priv, addr, regnum, val); } -int realtek_smi_setup_mdio(struct realtek_priv *priv) +int realtek_smi_setup_mdio(struct dsa_switch *ds) { + struct realtek_priv *priv = (struct realtek_priv *)ds->priv; struct device_node *mdio_np; int ret; @@ -363,10 +363,10 @@ int realtek_smi_setup_mdio(struct realtek_priv *priv) priv->slave_mii_bus->read = realtek_smi_mdio_read; priv->slave_mii_bus->write = realtek_smi_mdio_write; snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "SMI-%d", - priv->ds->index); + ds->index); priv->slave_mii_bus->dev.of_node = mdio_np; priv->slave_mii_bus->parent = priv->dev; - priv->ds->slave_mii_bus = priv->slave_mii_bus; + ds->slave_mii_bus = priv->slave_mii_bus; ret = devm_of_mdiobus_register(priv->dev, priv->slave_mii_bus, mdio_np); if (ret) { @@ -413,6 +413,9 @@ static int realtek_smi_probe(struct platform_device *pdev) priv->cmd_write = var->cmd_write; priv->ops = var->ops; + priv->setup_interface=realtek_smi_setup_mdio; + priv->write_reg_noack=realtek_smi_write_reg_noack; + dev_set_drvdata(dev, priv); spin_lock_init(&priv->lock); @@ -492,19 +495,23 @@ static void realtek_smi_shutdown(struct platform_device *pdev) } static const struct of_device_id realtek_smi_of_match[] = { +#if IS_ENABLED(CONFIG_NET_DSA_REALTEK_RTL8366RB) { .compatible = "realtek,rtl8366rb", .data = &rtl8366rb_variant, }, +#endif { /* FIXME: add support for RTL8366S and more */ .compatible = "realtek,rtl8366s", .data = NULL, }, +#if IS_ENABLED(CONFIG_NET_DSA_REALTEK_RTL8365MB) { .compatible = "realtek,rtl8365mb", .data = &rtl8365mb_variant, }, +#endif { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, realtek_smi_of_match); diff --git a/drivers/net/dsa/realtek/rtl8365mb.c b/drivers/net/dsa/realtek/rtl8365mb.c index f562a6efb574..d6054f63f204 100644 --- a/drivers/net/dsa/realtek/rtl8365mb.c +++ b/drivers/net/dsa/realtek/rtl8365mb.c @@ -1987,3 +1987,5 @@ const struct realtek_variant rtl8365mb_variant = { .chip_data_sz = sizeof(struct rtl8365mb), }; EXPORT_SYMBOL_GPL(rtl8365mb_variant); + +MODULE_LICENSE("GPL"); diff --git a/drivers/net/dsa/realtek/rtl8366.c b/drivers/net/dsa/realtek/rtl8366-core.c similarity index 100% rename from drivers/net/dsa/realtek/rtl8366.c rename to drivers/net/dsa/realtek/rtl8366-core.c diff --git a/drivers/net/dsa/realtek/rtl8366rb.c b/drivers/net/dsa/realtek/rtl8366rb.c index b1635c20276b..31f1a949c8e7 100644 --- a/drivers/net/dsa/realtek/rtl8366rb.c +++ b/drivers/net/dsa/realtek/rtl8366rb.c @@ -1812,3 +1812,5 @@ const struct realtek_variant rtl8366rb_variant = { .chip_data_sz = sizeof(struct rtl8366rb), }; EXPORT_SYMBOL_GPL(rtl8366rb_variant); + +MODULE_LICENSE("GPL"); From patchwork Thu Dec 16 20:13:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Luiz Angelo Daros de Luca X-Patchwork-Id: 12682447 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1FEF6C4332F for ; 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[187.49.235.234]) by smtp.gmail.com with ESMTPSA id a15sm5110266qtb.5.2021.12.16.12.14.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Dec 2021 12:14:25 -0800 (PST) From: luizluca@gmail.com To: netdev@vger.kernel.org Cc: linus.walleij@linaro.org, andrew@lunn.ch, vivien.didelot@gmail.com, f.fainelli@gmail.com, olteanv@gmail.com, alsi@bang-olufsen.dk, arinc.unal@arinc9.com, Luiz Angelo Daros de Luca Subject: [PATCH net-next 05/13] net: dsa: realtek: use phy_read in ds->ops Date: Thu, 16 Dec 2021 17:13:34 -0300 Message-Id: <20211216201342.25587-6-luizluca@gmail.com> X-Mailer: git-send-email 2.34.0 In-Reply-To: <20211216201342.25587-1-luizluca@gmail.com> References: <20211216201342.25587-1-luizluca@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Luiz Angelo Daros de Luca The ds->ops->phy_read will only be used if the ds->slave_mii_bus was not initialized. Calling realtek_smi_setup_mdio will create a ds->slave_mii_bus, making ds->ops->phy_read dormant. Using ds->ops->phy_read will allow switches connected through non-SMI interfaces (like mdio) to let ds allocate slave_mii_bus and reuse the same code. Tested-by: Arınç ÜNAL Signed-off-by: Luiz Angelo Daros de Luca Reviewed-by: Linus Walleij --- drivers/net/dsa/realtek/realtek-smi.c | 8 ++++---- drivers/net/dsa/realtek/realtek.h | 3 --- drivers/net/dsa/realtek/rtl8365mb.c | 10 ++++++---- drivers/net/dsa/realtek/rtl8366rb.c | 10 ++++++---- 4 files changed, 16 insertions(+), 15 deletions(-) diff --git a/drivers/net/dsa/realtek/realtek-smi.c b/drivers/net/dsa/realtek/realtek-smi.c index 11447096c8dc..f10acd7d3636 100644 --- a/drivers/net/dsa/realtek/realtek-smi.c +++ b/drivers/net/dsa/realtek/realtek-smi.c @@ -328,17 +328,17 @@ static const struct regmap_config realtek_smi_mdio_regmap_config = { static int realtek_smi_mdio_read(struct mii_bus *bus, int addr, int regnum) { - struct realtek_priv *priv = bus->priv; + struct dsa_switch *ds = ((struct realtek_priv *)bus->priv)->ds; - return priv->ops->phy_read(priv, addr, regnum); + return ds->ops->phy_read(ds, addr, regnum); } static int realtek_smi_mdio_write(struct mii_bus *bus, int addr, int regnum, u16 val) { - struct realtek_priv *priv = bus->priv; + struct dsa_switch *ds = ((struct realtek_priv *)bus->priv)->ds; - return priv->ops->phy_write(priv, addr, regnum, val); + return ds->ops->phy_write(ds, addr, regnum, val); } int realtek_smi_setup_mdio(struct dsa_switch *ds) diff --git a/drivers/net/dsa/realtek/realtek.h b/drivers/net/dsa/realtek/realtek.h index 766e79151a6c..daca0c0b7ea2 100644 --- a/drivers/net/dsa/realtek/realtek.h +++ b/drivers/net/dsa/realtek/realtek.h @@ -103,9 +103,6 @@ struct realtek_ops { int (*enable_vlan)(struct realtek_priv *priv, bool enable); int (*enable_vlan4k)(struct realtek_priv *priv, bool enable); int (*enable_port)(struct realtek_priv *priv, int port, bool enable); - int (*phy_read)(struct realtek_priv *priv, int phy, int regnum); - int (*phy_write)(struct realtek_priv *priv, int phy, int regnum, - u16 val); }; struct realtek_variant { diff --git a/drivers/net/dsa/realtek/rtl8365mb.c b/drivers/net/dsa/realtek/rtl8365mb.c index d6054f63f204..488b17a68226 100644 --- a/drivers/net/dsa/realtek/rtl8365mb.c +++ b/drivers/net/dsa/realtek/rtl8365mb.c @@ -674,11 +674,12 @@ static int rtl8365mb_phy_ocp_write(struct realtek_priv *priv, int phy, return 0; } -static int rtl8365mb_phy_read(struct realtek_priv *priv, int phy, int regnum) +static int rtl8365mb_phy_read(struct dsa_switch *ds, int phy, int regnum) { u32 ocp_addr; u16 val; int ret; + struct realtek_priv *priv = ds->priv; if (phy > RTL8365MB_PHYADDRMAX) return -EINVAL; @@ -702,11 +703,12 @@ static int rtl8365mb_phy_read(struct realtek_priv *priv, int phy, int regnum) return val; } -static int rtl8365mb_phy_write(struct realtek_priv *priv, int phy, int regnum, +static int rtl8365mb_phy_write(struct dsa_switch *ds, int phy, int regnum, u16 val) { u32 ocp_addr; int ret; + struct realtek_priv *priv = (struct realtek_priv *)ds->priv; if (phy > RTL8365MB_PHYADDRMAX) return -EINVAL; @@ -1958,6 +1960,8 @@ static const struct dsa_switch_ops rtl8365mb_switch_ops = { .get_tag_protocol = rtl8365mb_get_tag_protocol, .setup = rtl8365mb_setup, .teardown = rtl8365mb_teardown, + .phy_read = rtl8365mb_phy_read, + .phy_write = rtl8365mb_phy_write, .phylink_validate = rtl8365mb_phylink_validate, .phylink_mac_config = rtl8365mb_phylink_mac_config, .phylink_mac_link_down = rtl8365mb_phylink_mac_link_down, @@ -1974,8 +1978,6 @@ static const struct dsa_switch_ops rtl8365mb_switch_ops = { static const struct realtek_ops rtl8365mb_ops = { .detect = rtl8365mb_detect, - .phy_read = rtl8365mb_phy_read, - .phy_write = rtl8365mb_phy_write, }; const struct realtek_variant rtl8365mb_variant = { diff --git a/drivers/net/dsa/realtek/rtl8366rb.c b/drivers/net/dsa/realtek/rtl8366rb.c index 31f1a949c8e7..27f08a5f53d4 100644 --- a/drivers/net/dsa/realtek/rtl8366rb.c +++ b/drivers/net/dsa/realtek/rtl8366rb.c @@ -1639,11 +1639,12 @@ static int rtl8366rb_enable_vlan4k(struct realtek_priv *priv, bool enable) enable ? RTL8366RB_SGCR_EN_VLAN_4KTB : 0); } -static int rtl8366rb_phy_read(struct realtek_priv *priv, int phy, int regnum) +static int rtl8366rb_phy_read(struct dsa_switch *ds, int phy, int regnum) { u32 val; u32 reg; int ret; + struct realtek_priv *priv = ds->priv; if (phy > RTL8366RB_PHY_NO_MAX) return -EINVAL; @@ -1673,11 +1674,12 @@ static int rtl8366rb_phy_read(struct realtek_priv *priv, int phy, int regnum) return val; } -static int rtl8366rb_phy_write(struct realtek_priv *priv, int phy, int regnum, +static int rtl8366rb_phy_write(struct dsa_switch *ds, int phy, int regnum, u16 val) { u32 reg; int ret; + struct realtek_priv *priv = ds->priv; if (phy > RTL8366RB_PHY_NO_MAX) return -EINVAL; @@ -1767,6 +1769,8 @@ static int rtl8366rb_detect(struct realtek_priv *priv) static const struct dsa_switch_ops rtl8366rb_switch_ops = { .get_tag_protocol = rtl8366_get_tag_protocol, .setup = rtl8366rb_setup, + .phy_read = rtl8366rb_phy_read, + .phy_write = rtl8366rb_phy_write, .phylink_mac_link_up = rtl8366rb_mac_link_up, .phylink_mac_link_down = rtl8366rb_mac_link_down, .get_strings = rtl8366_get_strings, @@ -1799,8 +1803,6 @@ static const struct realtek_ops rtl8366rb_ops = { .is_vlan_valid = rtl8366rb_is_vlan_valid, .enable_vlan = rtl8366rb_enable_vlan, .enable_vlan4k = rtl8366rb_enable_vlan4k, - .phy_read = rtl8366rb_phy_read, - .phy_write = rtl8366rb_phy_write, }; const struct realtek_variant rtl8366rb_variant = { From patchwork Thu Dec 16 20:13:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Luiz Angelo Daros de Luca X-Patchwork-Id: 12682449 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23011C433FE for ; Thu, 16 Dec 2021 20:14:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241251AbhLPUOc (ORCPT ); Thu, 16 Dec 2021 15:14:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41444 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241245AbhLPUOb (ORCPT ); Thu, 16 Dec 2021 15:14:31 -0500 Received: from mail-qk1-x735.google.com (mail-qk1-x735.google.com [IPv6:2607:f8b0:4864:20::735]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1D614C061574 for ; Thu, 16 Dec 2021 12:14:30 -0800 (PST) Received: by mail-qk1-x735.google.com with SMTP id t6so118543qkg.1 for ; Thu, 16 Dec 2021 12:14:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eeDZMZzzCvStXE/DrJdNcGT+efRMXCq58T1ud4iM/V8=; b=fbTcFElYBRmLEh19fd0qYWSn954xk5c/UwLnDDAwplg9VilPXhtQJgSExyDhEl/tjt 9rIpyGKFM2B+fGk/lckYbe1tgxLua6OcHtXFcnFxtZMj+EY50rhrUeVMK3UxPzHgE3v5 VxoF8+O8eHwRnB7JTb4rYuKMKj3COizXvAQFhFr0OITK1kxvzI6l0npwIVTeSpQdqY3d ezeudw3rpuQIYEzzNCimqXvH0hc8tN484dtq2hz+LDey95hz9UXcKdNU8HppzYrVyfW8 n7fw5RMX9oj0gJ1t8qy9+wuXMIbTyGRJ1vrxjHMkka0AADfJWw+aUX5iqbEVRkM0N+5c r+JA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eeDZMZzzCvStXE/DrJdNcGT+efRMXCq58T1ud4iM/V8=; b=iG/YucrZEfNiof8ykVZoGtkZEoG/bR+oRLZhIXh3hNc3IYmAJDkNoYWOg8PMwr+DwT bc5u8IO38HF68rJMhP1n3QGz5umx/hQ3eQfpnU6iW029o752HXcyGOjN8Tv1DHLG2Xek P5kTTya+/4rdHhslcFc/2IjBoS80WWFbp2o88TVsLIA5l/FnCbtF5khGcIb4zuCRdfZj eYIcCICLnMKGq/baEVwkp1bRg9vtNYU3wP8wLwgR3azpqn3asXW+sq0DqZjT9bDttTF+ YwQujvePpuEnSLpD/kcScszTCR0KepWzt3niPTDPb8ogOt2z//e5Jyvj9DPLL8S40Hdg I6cg== X-Gm-Message-State: AOAM5330pLZ5OpACLKs1zKzCYuvR+DmiI4433BwuKJ4FZVEJAcr05Xad xKNO5zHIoD9heywhlBQ+DmC4jf+5II07qA== X-Google-Smtp-Source: ABdhPJyZs0Ay7ZIn7a/xB3tY2YQMXIrMFUNYncygHB0uHLcTz92piax+Gz/u3uSJEcSLbEr55Llntw== X-Received: by 2002:a05:620a:318d:: with SMTP id bi13mr13282306qkb.279.1639685669013; Thu, 16 Dec 2021 12:14:29 -0800 (PST) Received: from tresc043793.tre-sc.gov.br (187-049-235-234.floripa.net.br. [187.49.235.234]) by smtp.gmail.com with ESMTPSA id a15sm5110266qtb.5.2021.12.16.12.14.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Dec 2021 12:14:28 -0800 (PST) From: luizluca@gmail.com To: netdev@vger.kernel.org Cc: linus.walleij@linaro.org, andrew@lunn.ch, vivien.didelot@gmail.com, f.fainelli@gmail.com, olteanv@gmail.com, alsi@bang-olufsen.dk, arinc.unal@arinc9.com, Luiz Angelo Daros de Luca Subject: [PATCH net-next 06/13] net: dsa: rtl8365mb: move rtl8365mb.c to rtl8367c.c Date: Thu, 16 Dec 2021 17:13:35 -0300 Message-Id: <20211216201342.25587-7-luizluca@gmail.com> X-Mailer: git-send-email 2.34.0 In-Reply-To: <20211216201342.25587-1-luizluca@gmail.com> References: <20211216201342.25587-1-luizluca@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Luiz Angelo Daros de Luca Tested-by: Arınç ÜNAL Signed-off-by: Luiz Angelo Daros de Luca Acked-by: Linus Walleij --- drivers/net/dsa/realtek/Makefile | 2 +- drivers/net/dsa/realtek/{rtl8365mb.c => rtl8367c.c} | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename drivers/net/dsa/realtek/{rtl8365mb.c => rtl8367c.c} (100%) diff --git a/drivers/net/dsa/realtek/Makefile b/drivers/net/dsa/realtek/Makefile index 8b5a4abcedd3..efb9568077f5 100644 --- a/drivers/net/dsa/realtek/Makefile +++ b/drivers/net/dsa/realtek/Makefile @@ -2,4 +2,4 @@ obj-$(CONFIG_NET_DSA_REALTEK_SMI) += realtek-smi.o obj-$(CONFIG_NET_DSA_REALTEK_RTL8366RB) += rtl8366.o rtl8366-objs := rtl8366-core.o rtl8366rb.o -obj-$(CONFIG_NET_DSA_REALTEK_RTL8365MB) += rtl8365mb.o +obj-$(CONFIG_NET_DSA_REALTEK_RTL8365MB) += rtl8367c.o diff --git a/drivers/net/dsa/realtek/rtl8365mb.c b/drivers/net/dsa/realtek/rtl8367c.c similarity index 100% rename from drivers/net/dsa/realtek/rtl8365mb.c rename to drivers/net/dsa/realtek/rtl8367c.c From patchwork Thu Dec 16 20:13:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Luiz Angelo Daros de Luca X-Patchwork-Id: 12682451 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12C6FC433EF for ; Thu, 16 Dec 2021 20:14:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241250AbhLPUOg (ORCPT ); Thu, 16 Dec 2021 15:14:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41468 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241244AbhLPUOf (ORCPT ); Thu, 16 Dec 2021 15:14:35 -0500 Received: from mail-qt1-x82e.google.com (mail-qt1-x82e.google.com [IPv6:2607:f8b0:4864:20::82e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BD0CBC061574 for ; Thu, 16 Dec 2021 12:14:34 -0800 (PST) Received: by mail-qt1-x82e.google.com with SMTP id j17so454221qtx.2 for ; Thu, 16 Dec 2021 12:14:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ExjjKO3DOVJ4Cp9V/RQVwG+nld3rr/GkJJrIzBSNsN0=; b=dRWX0Si6nP6Irb+fbzQg5eYpc/1zZxtr19bjcfXMyDKcGsaxWv78IrlNIgVI2K3Rvg 6eVwSvnhdAPLsFFVhFT9eC40WKyIzT/BKFKWyZvrgA9Hm8uG838IqXsFdVmzDES68usn XKl7q36vsw8tiH/hr9kHeh/eTzEz9JUOgzKZ1hslL56lNlgXG00+/ByUBoeed1MZEtad tMcns5A4vGSd8FTAFhKjkE/dAMk86ibIdXhMpF1JnD0JaXOaBx5CQnSLOHeXXoweqUDZ 7PGUlgTL5HNpOY4807Znnt889+uaDmQwxOPRSgTYLXPjHf8qqv/byTiNwRQl0fvrKpb6 HuzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ExjjKO3DOVJ4Cp9V/RQVwG+nld3rr/GkJJrIzBSNsN0=; b=FqnBGf997RiHXNHLyanuVHWsXshZuZJAYN0gXq+aR+zTwa1hgwu8G0WFEvczdfnS2e u0H5prsuaf80suRpYgXhpkvg07vSRqYufCfLCirYk754/BPIy9skBirQ8D+VfbBgkjwC ckSNgh5Ho2C4mHgQ6hVsjFchpu30LBU2BGVPkkaYV6DK9IDz9xqYQ8XFpZZZvmzuahyZ dHBhQQAfwmcMrfIbCDPgOhw7zmbihqflQAyT7xKwdwCrH72UkjVGdV+Q+QuuNIAQinKK MQpO4Nq5hFFNTyz2ZJcGC9+U2QdpF4S29I7muC7wxyI0Zrrq5wMd/IluaWhXZqmM+SSG fqaw== X-Gm-Message-State: AOAM530mGsmAT1lwnAEnARig8uxI3Y1Vi0ExH9tKt2RMAmr/HeDFuh5y wwS855qURyBETMlq1ckAEVzApT0o5oLxcQ== X-Google-Smtp-Source: ABdhPJylgKV5rFl70J4zImbrPBCzW9jCJfdF7FEiAFXrHSR3EFYt0jKnX4+XHk1WuIblky84DBgolg== X-Received: by 2002:ac8:5c54:: with SMTP id j20mr18582512qtj.121.1639685672480; Thu, 16 Dec 2021 12:14:32 -0800 (PST) Received: from tresc043793.tre-sc.gov.br (187-049-235-234.floripa.net.br. [187.49.235.234]) by smtp.gmail.com with ESMTPSA id a15sm5110266qtb.5.2021.12.16.12.14.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Dec 2021 12:14:31 -0800 (PST) From: luizluca@gmail.com To: netdev@vger.kernel.org Cc: linus.walleij@linaro.org, andrew@lunn.ch, vivien.didelot@gmail.com, f.fainelli@gmail.com, olteanv@gmail.com, alsi@bang-olufsen.dk, arinc.unal@arinc9.com, Luiz Angelo Daros de Luca Subject: [PATCH net-next 07/13] net: dsa: rtl8365mb: rename rtl8365mb to rtl8367c Date: Thu, 16 Dec 2021 17:13:36 -0300 Message-Id: <20211216201342.25587-8-luizluca@gmail.com> X-Mailer: git-send-email 2.34.0 In-Reply-To: <20211216201342.25587-1-luizluca@gmail.com> References: <20211216201342.25587-1-luizluca@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Luiz Angelo Daros de Luca rtl8365mb refers to a single device supported by the driver. The rtl8367c does not refer to any real device, but it is the driver version name used by Realtek. Tested-by: Arınç ÜNAL Signed-off-by: Luiz Angelo Daros de Luca --- drivers/net/dsa/realtek/Kconfig | 9 +- drivers/net/dsa/realtek/Makefile | 2 +- drivers/net/dsa/realtek/realtek-smi.c | 4 +- drivers/net/dsa/realtek/realtek.h | 2 +- drivers/net/dsa/realtek/rtl8367c.c | 1321 ++++++++++++------------- drivers/net/phy/realtek.c | 2 +- 6 files changed, 666 insertions(+), 674 deletions(-) diff --git a/drivers/net/dsa/realtek/Kconfig b/drivers/net/dsa/realtek/Kconfig index c002a84a00f5..874574db9177 100644 --- a/drivers/net/dsa/realtek/Kconfig +++ b/drivers/net/dsa/realtek/Kconfig @@ -16,14 +16,17 @@ config NET_DSA_REALTEK_SMI help Select to enable support for registering switches connected through SMI. -config NET_DSA_REALTEK_RTL8365MB - tristate "Realtek RTL8365MB switch subdriver" +config NET_DSA_REALTEK_RTL8367C + tristate "Realtek RTL8367C switch subdriver" default y depends on NET_DSA_REALTEK depends on NET_DSA_REALTEK_SMI select NET_DSA_TAG_RTL8_4 help - Select to enable support for Realtek RTL8365MB + Select to enable support for Realtek RTL8365MB-VC. This subdriver + might also support RTL8363NB, RTL8363NB-VB, RTL8363SC, RTL8363SC-VB, RTL8364NB, + RTL8364NB-VB, RTL8366SC, RTL8367RB-VB, RTL8367S, RTL8367SB, RTL8370MB, RTL8310SR + in the future. config NET_DSA_REALTEK_RTL8366RB tristate "Realtek RTL8366RB switch subdriver" diff --git a/drivers/net/dsa/realtek/Makefile b/drivers/net/dsa/realtek/Makefile index efb9568077f5..84d5ab062c89 100644 --- a/drivers/net/dsa/realtek/Makefile +++ b/drivers/net/dsa/realtek/Makefile @@ -2,4 +2,4 @@ obj-$(CONFIG_NET_DSA_REALTEK_SMI) += realtek-smi.o obj-$(CONFIG_NET_DSA_REALTEK_RTL8366RB) += rtl8366.o rtl8366-objs := rtl8366-core.o rtl8366rb.o -obj-$(CONFIG_NET_DSA_REALTEK_RTL8365MB) += rtl8367c.o +obj-$(CONFIG_NET_DSA_REALTEK_RTL8367C) += rtl8367c.o diff --git a/drivers/net/dsa/realtek/realtek-smi.c b/drivers/net/dsa/realtek/realtek-smi.c index f10acd7d3636..258f90956cec 100644 --- a/drivers/net/dsa/realtek/realtek-smi.c +++ b/drivers/net/dsa/realtek/realtek-smi.c @@ -506,10 +506,10 @@ static const struct of_device_id realtek_smi_of_match[] = { .compatible = "realtek,rtl8366s", .data = NULL, }, -#if IS_ENABLED(CONFIG_NET_DSA_REALTEK_RTL8365MB) +#if IS_ENABLED(CONFIG_NET_DSA_REALTEK_RTL8367C) { .compatible = "realtek,rtl8365mb", - .data = &rtl8365mb_variant, + .data = &rtl8367c_variant, }, #endif { /* sentinel */ }, diff --git a/drivers/net/dsa/realtek/realtek.h b/drivers/net/dsa/realtek/realtek.h index daca0c0b7ea2..976cb7823c92 100644 --- a/drivers/net/dsa/realtek/realtek.h +++ b/drivers/net/dsa/realtek/realtek.h @@ -134,6 +134,6 @@ int rtl8366_get_sset_count(struct dsa_switch *ds, int port, int sset); void rtl8366_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data); extern const struct realtek_variant rtl8366rb_variant; -extern const struct realtek_variant rtl8365mb_variant; +extern const struct realtek_variant rtl8367c_variant; #endif /* _REALTEK_SMI_H */ diff --git a/drivers/net/dsa/realtek/rtl8367c.c b/drivers/net/dsa/realtek/rtl8367c.c index 488b17a68226..98ec793a82bc 100644 --- a/drivers/net/dsa/realtek/rtl8367c.c +++ b/drivers/net/dsa/realtek/rtl8367c.c @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 -/* Realtek SMI subdriver for the Realtek RTL8365MB-VC ethernet switch. +/* Realtek SMI subdriver for the Realtek RTL8367C ethernet switches. * * Copyright (C) 2021 Alvin Šipraga * Copyright (C) 2021 Michael Rasmussen @@ -52,19 +52,7 @@ * the driver will manually reprogram some registers using jam tables to reach * an initial state defined by the vendor driver. * - * This Linux driver is written based on an OS-agnostic vendor driver from - * Realtek. The reference GPL-licensed sources can be found in the OpenWrt - * source tree under the name rtl8367c. The vendor driver claims to support a - * number of similar switch controllers from Realtek, but the only hardware we - * have is the RTL8365MB-VC. Moreover, there does not seem to be any chip under - * the name RTL8367C. Although one wishes that the 'C' stood for some kind of - * common hardware revision, there exist examples of chips with the suffix -VC - * which are explicitly not supported by the rtl8367c driver and which instead - * require the rtl8367d vendor driver. With all this uncertainty, the driver has - * been modestly named rtl8365mb. Future implementors may wish to rename things - * accordingly. - * - * In the same family of chips, some carry up to 8 user ports and up to 2 + * In this family of chips, some carry up to 8 user ports and up to 2 * extension ports. Where possible this driver tries to make things generic, but * more work must be done to support these configurations. According to * documentation from Realtek, the family should include the following chips: @@ -102,202 +90,203 @@ #include "realtek.h" /* Chip-specific data and limits */ -#define RTL8365MB_CHIP_ID_8365MB_VC 0x6367 -#define RTL8365MB_CPU_PORT_NUM_8365MB_VC 6 -#define RTL8365MB_LEARN_LIMIT_MAX_8365MB_VC 2112 +#define RTL8367C_CHIP_ID_8365MB_VC 0x6367 +#define RTL8367C_CPU_PORT_NUM_8365MB_VC 6 + +#define RTL8367C_LEARN_LIMIT_MAX 2112 /* Family-specific data and limits */ -#define RTL8365MB_PHYADDRMAX 7 -#define RTL8365MB_NUM_PHYREGS 32 -#define RTL8365MB_PHYREGMAX (RTL8365MB_NUM_PHYREGS - 1) -#define RTL8365MB_MAX_NUM_PORTS (RTL8365MB_CPU_PORT_NUM_8365MB_VC + 1) +#define RTL8367C_PHYADDRMAX 7 +#define RTL8367C_NUM_PHYREGS 32 +#define RTL8367C_PHYREGMAX (RTL8367C_NUM_PHYREGS - 1) +#define RTL8367C_MAX_NUM_PORTS (RTL8367C_CPU_PORT_NUM_8365MB_VC + 1) /* Chip identification registers */ -#define RTL8365MB_CHIP_ID_REG 0x1300 +#define RTL8367C_CHIP_ID_REG 0x1300 -#define RTL8365MB_CHIP_VER_REG 0x1301 +#define RTL8367C_CHIP_VER_REG 0x1301 -#define RTL8365MB_MAGIC_REG 0x13C2 -#define RTL8365MB_MAGIC_VALUE 0x0249 +#define RTL8367C_MAGIC_REG 0x13C2 +#define RTL8367C_MAGIC_VALUE 0x0249 /* Chip reset register */ -#define RTL8365MB_CHIP_RESET_REG 0x1322 -#define RTL8365MB_CHIP_RESET_SW_MASK 0x0002 -#define RTL8365MB_CHIP_RESET_HW_MASK 0x0001 +#define RTL8367C_CHIP_RESET_REG 0x1322 +#define RTL8367C_CHIP_RESET_SW_MASK 0x0002 +#define RTL8367C_CHIP_RESET_HW_MASK 0x0001 /* Interrupt polarity register */ -#define RTL8365MB_INTR_POLARITY_REG 0x1100 -#define RTL8365MB_INTR_POLARITY_MASK 0x0001 -#define RTL8365MB_INTR_POLARITY_HIGH 0 -#define RTL8365MB_INTR_POLARITY_LOW 1 +#define RTL8367C_INTR_POLARITY_REG 0x1100 +#define RTL8367C_INTR_POLARITY_MASK 0x0001 +#define RTL8367C_INTR_POLARITY_HIGH 0 +#define RTL8367C_INTR_POLARITY_LOW 1 /* Interrupt control/status register - enable/check specific interrupt types */ -#define RTL8365MB_INTR_CTRL_REG 0x1101 -#define RTL8365MB_INTR_STATUS_REG 0x1102 -#define RTL8365MB_INTR_SLIENT_START_2_MASK 0x1000 -#define RTL8365MB_INTR_SLIENT_START_MASK 0x0800 -#define RTL8365MB_INTR_ACL_ACTION_MASK 0x0200 -#define RTL8365MB_INTR_CABLE_DIAG_FIN_MASK 0x0100 -#define RTL8365MB_INTR_INTERRUPT_8051_MASK 0x0080 -#define RTL8365MB_INTR_LOOP_DETECTION_MASK 0x0040 -#define RTL8365MB_INTR_GREEN_TIMER_MASK 0x0020 -#define RTL8365MB_INTR_SPECIAL_CONGEST_MASK 0x0010 -#define RTL8365MB_INTR_SPEED_CHANGE_MASK 0x0008 -#define RTL8365MB_INTR_LEARN_OVER_MASK 0x0004 -#define RTL8365MB_INTR_METER_EXCEEDED_MASK 0x0002 -#define RTL8365MB_INTR_LINK_CHANGE_MASK 0x0001 -#define RTL8365MB_INTR_ALL_MASK \ - (RTL8365MB_INTR_SLIENT_START_2_MASK | \ - RTL8365MB_INTR_SLIENT_START_MASK | \ - RTL8365MB_INTR_ACL_ACTION_MASK | \ - RTL8365MB_INTR_CABLE_DIAG_FIN_MASK | \ - RTL8365MB_INTR_INTERRUPT_8051_MASK | \ - RTL8365MB_INTR_LOOP_DETECTION_MASK | \ - RTL8365MB_INTR_GREEN_TIMER_MASK | \ - RTL8365MB_INTR_SPECIAL_CONGEST_MASK | \ - RTL8365MB_INTR_SPEED_CHANGE_MASK | \ - RTL8365MB_INTR_LEARN_OVER_MASK | \ - RTL8365MB_INTR_METER_EXCEEDED_MASK | \ - RTL8365MB_INTR_LINK_CHANGE_MASK) +#define RTL8367C_INTR_CTRL_REG 0x1101 +#define RTL8367C_INTR_STATUS_REG 0x1102 +#define RTL8367C_INTR_SLIENT_START_2_MASK 0x1000 +#define RTL8367C_INTR_SLIENT_START_MASK 0x0800 +#define RTL8367C_INTR_ACL_ACTION_MASK 0x0200 +#define RTL8367C_INTR_CABLE_DIAG_FIN_MASK 0x0100 +#define RTL8367C_INTR_INTERRUPT_8051_MASK 0x0080 +#define RTL8367C_INTR_LOOP_DETECTION_MASK 0x0040 +#define RTL8367C_INTR_GREEN_TIMER_MASK 0x0020 +#define RTL8367C_INTR_SPECIAL_CONGEST_MASK 0x0010 +#define RTL8367C_INTR_SPEED_CHANGE_MASK 0x0008 +#define RTL8367C_INTR_LEARN_OVER_MASK 0x0004 +#define RTL8367C_INTR_METER_EXCEEDED_MASK 0x0002 +#define RTL8367C_INTR_LINK_CHANGE_MASK 0x0001 +#define RTL8367C_INTR_ALL_MASK \ + (RTL8367C_INTR_SLIENT_START_2_MASK | \ + RTL8367C_INTR_SLIENT_START_MASK | \ + RTL8367C_INTR_ACL_ACTION_MASK | \ + RTL8367C_INTR_CABLE_DIAG_FIN_MASK | \ + RTL8367C_INTR_INTERRUPT_8051_MASK | \ + RTL8367C_INTR_LOOP_DETECTION_MASK | \ + RTL8367C_INTR_GREEN_TIMER_MASK | \ + RTL8367C_INTR_SPECIAL_CONGEST_MASK | \ + RTL8367C_INTR_SPEED_CHANGE_MASK | \ + RTL8367C_INTR_LEARN_OVER_MASK | \ + RTL8367C_INTR_METER_EXCEEDED_MASK | \ + RTL8367C_INTR_LINK_CHANGE_MASK) /* Per-port interrupt type status registers */ -#define RTL8365MB_PORT_LINKDOWN_IND_REG 0x1106 -#define RTL8365MB_PORT_LINKDOWN_IND_MASK 0x07FF +#define RTL8367C_PORT_LINKDOWN_IND_REG 0x1106 +#define RTL8367C_PORT_LINKDOWN_IND_MASK 0x07FF -#define RTL8365MB_PORT_LINKUP_IND_REG 0x1107 -#define RTL8365MB_PORT_LINKUP_IND_MASK 0x07FF +#define RTL8367C_PORT_LINKUP_IND_REG 0x1107 +#define RTL8367C_PORT_LINKUP_IND_MASK 0x07FF /* PHY indirect access registers */ -#define RTL8365MB_INDIRECT_ACCESS_CTRL_REG 0x1F00 -#define RTL8365MB_INDIRECT_ACCESS_CTRL_RW_MASK 0x0002 -#define RTL8365MB_INDIRECT_ACCESS_CTRL_RW_READ 0 -#define RTL8365MB_INDIRECT_ACCESS_CTRL_RW_WRITE 1 -#define RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_MASK 0x0001 -#define RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_VALUE 1 -#define RTL8365MB_INDIRECT_ACCESS_STATUS_REG 0x1F01 -#define RTL8365MB_INDIRECT_ACCESS_ADDRESS_REG 0x1F02 -#define RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_5_1_MASK GENMASK(4, 0) -#define RTL8365MB_INDIRECT_ACCESS_ADDRESS_PHYNUM_MASK GENMASK(7, 5) -#define RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_9_6_MASK GENMASK(11, 8) -#define RTL8365MB_PHY_BASE 0x2000 -#define RTL8365MB_INDIRECT_ACCESS_WRITE_DATA_REG 0x1F03 -#define RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG 0x1F04 +#define RTL8367C_INDIRECT_ACCESS_CTRL_REG 0x1F00 +#define RTL8367C_INDIRECT_ACCESS_CTRL_RW_MASK 0x0002 +#define RTL8367C_INDIRECT_ACCESS_CTRL_RW_READ 0 +#define RTL8367C_INDIRECT_ACCESS_CTRL_RW_WRITE 1 +#define RTL8367C_INDIRECT_ACCESS_CTRL_CMD_MASK 0x0001 +#define RTL8367C_INDIRECT_ACCESS_CTRL_CMD_VALUE 1 +#define RTL8367C_INDIRECT_ACCESS_STATUS_REG 0x1F01 +#define RTL8367C_INDIRECT_ACCESS_ADDRESS_REG 0x1F02 +#define RTL8367C_INDIRECT_ACCESS_ADDRESS_OCPADR_5_1_MASK GENMASK(4, 0) +#define RTL8367C_INDIRECT_ACCESS_ADDRESS_PHYNUM_MASK GENMASK(7, 5) +#define RTL8367C_INDIRECT_ACCESS_ADDRESS_OCPADR_9_6_MASK GENMASK(11, 8) +#define RTL8367C_PHY_BASE 0x2000 +#define RTL8367C_INDIRECT_ACCESS_WRITE_DATA_REG 0x1F03 +#define RTL8367C_INDIRECT_ACCESS_READ_DATA_REG 0x1F04 /* PHY OCP address prefix register */ -#define RTL8365MB_GPHY_OCP_MSB_0_REG 0x1D15 -#define RTL8365MB_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK 0x0FC0 -#define RTL8365MB_PHY_OCP_ADDR_PREFIX_MASK 0xFC00 +#define RTL8367C_GPHY_OCP_MSB_0_REG 0x1D15 +#define RTL8367C_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK 0x0FC0 +#define RTL8367C_PHY_OCP_ADDR_PREFIX_MASK 0xFC00 /* The PHY OCP addresses of PHY registers 0~31 start here */ -#define RTL8365MB_PHY_OCP_ADDR_PHYREG_BASE 0xA400 +#define RTL8367C_PHY_OCP_ADDR_PHYREG_BASE 0xA400 /* EXT port interface mode values - used in DIGITAL_INTERFACE_SELECT */ -#define RTL8365MB_EXT_PORT_MODE_DISABLE 0 -#define RTL8365MB_EXT_PORT_MODE_RGMII 1 -#define RTL8365MB_EXT_PORT_MODE_MII_MAC 2 -#define RTL8365MB_EXT_PORT_MODE_MII_PHY 3 -#define RTL8365MB_EXT_PORT_MODE_TMII_MAC 4 -#define RTL8365MB_EXT_PORT_MODE_TMII_PHY 5 -#define RTL8365MB_EXT_PORT_MODE_GMII 6 -#define RTL8365MB_EXT_PORT_MODE_RMII_MAC 7 -#define RTL8365MB_EXT_PORT_MODE_RMII_PHY 8 -#define RTL8365MB_EXT_PORT_MODE_SGMII 9 -#define RTL8365MB_EXT_PORT_MODE_HSGMII 10 -#define RTL8365MB_EXT_PORT_MODE_1000X_100FX 11 -#define RTL8365MB_EXT_PORT_MODE_1000X 12 -#define RTL8365MB_EXT_PORT_MODE_100FX 13 +#define RTL8367C_EXT_PORT_MODE_DISABLE 0 +#define RTL8367C_EXT_PORT_MODE_RGMII 1 +#define RTL8367C_EXT_PORT_MODE_MII_MAC 2 +#define RTL8367C_EXT_PORT_MODE_MII_PHY 3 +#define RTL8367C_EXT_PORT_MODE_TMII_MAC 4 +#define RTL8367C_EXT_PORT_MODE_TMII_PHY 5 +#define RTL8367C_EXT_PORT_MODE_GMII 6 +#define RTL8367C_EXT_PORT_MODE_RMII_MAC 7 +#define RTL8367C_EXT_PORT_MODE_RMII_PHY 8 +#define RTL8367C_EXT_PORT_MODE_SGMII 9 +#define RTL8367C_EXT_PORT_MODE_HSGMII 10 +#define RTL8367C_EXT_PORT_MODE_1000X_100FX 11 +#define RTL8367C_EXT_PORT_MODE_1000X 12 +#define RTL8367C_EXT_PORT_MODE_100FX 13 /* EXT port interface mode configuration registers 0~1 */ -#define RTL8365MB_DIGITAL_INTERFACE_SELECT_REG0 0x1305 -#define RTL8365MB_DIGITAL_INTERFACE_SELECT_REG1 0x13C3 -#define RTL8365MB_DIGITAL_INTERFACE_SELECT_REG(_extport) \ - (RTL8365MB_DIGITAL_INTERFACE_SELECT_REG0 + \ +#define RTL8367C_DIGITAL_INTERFACE_SELECT_REG0 0x1305 +#define RTL8367C_DIGITAL_INTERFACE_SELECT_REG1 0x13C3 +#define RTL8367C_DIGITAL_INTERFACE_SELECT_REG(_extport) \ + (RTL8367C_DIGITAL_INTERFACE_SELECT_REG0 + \ ((_extport) >> 1) * (0x13C3 - 0x1305)) -#define RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_MASK(_extport) \ +#define RTL8367C_DIGITAL_INTERFACE_SELECT_MODE_MASK(_extport) \ (0xF << (((_extport) % 2))) -#define RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_OFFSET(_extport) \ +#define RTL8367C_DIGITAL_INTERFACE_SELECT_MODE_OFFSET(_extport) \ (((_extport) % 2) * 4) /* EXT port RGMII TX/RX delay configuration registers 1~2 */ -#define RTL8365MB_EXT_RGMXF_REG1 0x1307 -#define RTL8365MB_EXT_RGMXF_REG2 0x13C5 -#define RTL8365MB_EXT_RGMXF_REG(_extport) \ - (RTL8365MB_EXT_RGMXF_REG1 + \ +#define RTL8367C_EXT_RGMXF_REG1 0x1307 +#define RTL8367C_EXT_RGMXF_REG2 0x13C5 +#define RTL8367C_EXT_RGMXF_REG(_extport) \ + (RTL8367C_EXT_RGMXF_REG1 + \ (((_extport) >> 1) * (0x13C5 - 0x1307))) -#define RTL8365MB_EXT_RGMXF_RXDELAY_MASK 0x0007 -#define RTL8365MB_EXT_RGMXF_TXDELAY_MASK 0x0008 +#define RTL8367C_EXT_RGMXF_RXDELAY_MASK 0x0007 +#define RTL8367C_EXT_RGMXF_TXDELAY_MASK 0x0008 /* External port speed values - used in DIGITAL_INTERFACE_FORCE */ -#define RTL8365MB_PORT_SPEED_10M 0 -#define RTL8365MB_PORT_SPEED_100M 1 -#define RTL8365MB_PORT_SPEED_1000M 2 +#define RTL8367C_PORT_SPEED_10M 0 +#define RTL8367C_PORT_SPEED_100M 1 +#define RTL8367C_PORT_SPEED_1000M 2 /* EXT port force configuration registers 0~2 */ -#define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG0 0x1310 -#define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG1 0x1311 -#define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG2 0x13C4 -#define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG(_extport) \ - (RTL8365MB_DIGITAL_INTERFACE_FORCE_REG0 + \ +#define RTL8367C_DIGITAL_INTERFACE_FORCE_REG0 0x1310 +#define RTL8367C_DIGITAL_INTERFACE_FORCE_REG1 0x1311 +#define RTL8367C_DIGITAL_INTERFACE_FORCE_REG2 0x13C4 +#define RTL8367C_DIGITAL_INTERFACE_FORCE_REG(_extport) \ + (RTL8367C_DIGITAL_INTERFACE_FORCE_REG0 + \ ((_extport) & 0x1) + \ ((((_extport) >> 1) & 0x1) * (0x13C4 - 0x1310))) -#define RTL8365MB_DIGITAL_INTERFACE_FORCE_EN_MASK 0x1000 -#define RTL8365MB_DIGITAL_INTERFACE_FORCE_NWAY_MASK 0x0080 -#define RTL8365MB_DIGITAL_INTERFACE_FORCE_TXPAUSE_MASK 0x0040 -#define RTL8365MB_DIGITAL_INTERFACE_FORCE_RXPAUSE_MASK 0x0020 -#define RTL8365MB_DIGITAL_INTERFACE_FORCE_LINK_MASK 0x0010 -#define RTL8365MB_DIGITAL_INTERFACE_FORCE_DUPLEX_MASK 0x0004 -#define RTL8365MB_DIGITAL_INTERFACE_FORCE_SPEED_MASK 0x0003 +#define RTL8367C_DIGITAL_INTERFACE_FORCE_EN_MASK 0x1000 +#define RTL8367C_DIGITAL_INTERFACE_FORCE_NWAY_MASK 0x0080 +#define RTL8367C_DIGITAL_INTERFACE_FORCE_TXPAUSE_MASK 0x0040 +#define RTL8367C_DIGITAL_INTERFACE_FORCE_RXPAUSE_MASK 0x0020 +#define RTL8367C_DIGITAL_INTERFACE_FORCE_LINK_MASK 0x0010 +#define RTL8367C_DIGITAL_INTERFACE_FORCE_DUPLEX_MASK 0x0004 +#define RTL8367C_DIGITAL_INTERFACE_FORCE_SPEED_MASK 0x0003 /* CPU port mask register - controls which ports are treated as CPU ports */ -#define RTL8365MB_CPU_PORT_MASK_REG 0x1219 -#define RTL8365MB_CPU_PORT_MASK_MASK 0x07FF +#define RTL8367C_CPU_PORT_MASK_REG 0x1219 +#define RTL8367C_CPU_PORT_MASK_MASK 0x07FF /* CPU control register */ -#define RTL8365MB_CPU_CTRL_REG 0x121A -#define RTL8365MB_CPU_CTRL_TRAP_PORT_EXT_MASK 0x0400 -#define RTL8365MB_CPU_CTRL_TAG_FORMAT_MASK 0x0200 -#define RTL8365MB_CPU_CTRL_RXBYTECOUNT_MASK 0x0080 -#define RTL8365MB_CPU_CTRL_TAG_POSITION_MASK 0x0040 -#define RTL8365MB_CPU_CTRL_TRAP_PORT_MASK 0x0038 -#define RTL8365MB_CPU_CTRL_INSERTMODE_MASK 0x0006 -#define RTL8365MB_CPU_CTRL_EN_MASK 0x0001 +#define RTL8367C_CPU_CTRL_REG 0x121A +#define RTL8367C_CPU_CTRL_TRAP_PORT_EXT_MASK 0x0400 +#define RTL8367C_CPU_CTRL_TAG_FORMAT_MASK 0x0200 +#define RTL8367C_CPU_CTRL_RXBYTECOUNT_MASK 0x0080 +#define RTL8367C_CPU_CTRL_TAG_POSITION_MASK 0x0040 +#define RTL8367C_CPU_CTRL_TRAP_PORT_MASK 0x0038 +#define RTL8367C_CPU_CTRL_INSERTMODE_MASK 0x0006 +#define RTL8367C_CPU_CTRL_EN_MASK 0x0001 /* Maximum packet length register */ -#define RTL8365MB_CFG0_MAX_LEN_REG 0x088C -#define RTL8365MB_CFG0_MAX_LEN_MASK 0x3FFF +#define RTL8367C_CFG0_MAX_LEN_REG 0x088C +#define RTL8367C_CFG0_MAX_LEN_MASK 0x3FFF /* Port learning limit registers */ -#define RTL8365MB_LUT_PORT_LEARN_LIMIT_BASE 0x0A20 -#define RTL8365MB_LUT_PORT_LEARN_LIMIT_REG(_physport) \ - (RTL8365MB_LUT_PORT_LEARN_LIMIT_BASE + (_physport)) +#define RTL8367C_LUT_PORT_LEARN_LIMIT_BASE 0x0A20 +#define RTL8367C_LUT_PORT_LEARN_LIMIT_REG(_physport) \ + (RTL8367C_LUT_PORT_LEARN_LIMIT_BASE + (_physport)) /* Port isolation (forwarding mask) registers */ -#define RTL8365MB_PORT_ISOLATION_REG_BASE 0x08A2 -#define RTL8365MB_PORT_ISOLATION_REG(_physport) \ - (RTL8365MB_PORT_ISOLATION_REG_BASE + (_physport)) -#define RTL8365MB_PORT_ISOLATION_MASK 0x07FF +#define RTL8367C_PORT_ISOLATION_REG_BASE 0x08A2 +#define RTL8367C_PORT_ISOLATION_REG(_physport) \ + (RTL8367C_PORT_ISOLATION_REG_BASE + (_physport)) +#define RTL8367C_PORT_ISOLATION_MASK 0x07FF /* MSTP port state registers - indexed by tree instance */ -#define RTL8365MB_MSTI_CTRL_BASE 0x0A00 -#define RTL8365MB_MSTI_CTRL_REG(_msti, _physport) \ - (RTL8365MB_MSTI_CTRL_BASE + ((_msti) << 1) + ((_physport) >> 3)) -#define RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET(_physport) ((_physport) << 1) -#define RTL8365MB_MSTI_CTRL_PORT_STATE_MASK(_physport) \ - (0x3 << RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET((_physport))) +#define RTL8367C_MSTI_CTRL_BASE 0x0A00 +#define RTL8367C_MSTI_CTRL_REG(_msti, _physport) \ + (RTL8367C_MSTI_CTRL_BASE + ((_msti) << 1) + ((_physport) >> 3)) +#define RTL8367C_MSTI_CTRL_PORT_STATE_OFFSET(_physport) ((_physport) << 1) +#define RTL8367C_MSTI_CTRL_PORT_STATE_MASK(_physport) \ + (0x3 << RTL8367C_MSTI_CTRL_PORT_STATE_OFFSET((_physport))) /* MIB counter value registers */ -#define RTL8365MB_MIB_COUNTER_BASE 0x1000 -#define RTL8365MB_MIB_COUNTER_REG(_x) (RTL8365MB_MIB_COUNTER_BASE + (_x)) +#define RTL8367C_MIB_COUNTER_BASE 0x1000 +#define RTL8367C_MIB_COUNTER_REG(_x) (RTL8367C_MIB_COUNTER_BASE + (_x)) /* MIB counter address register */ -#define RTL8365MB_MIB_ADDRESS_REG 0x1004 -#define RTL8365MB_MIB_ADDRESS_PORT_OFFSET 0x007C -#define RTL8365MB_MIB_ADDRESS(_p, _x) \ - (((RTL8365MB_MIB_ADDRESS_PORT_OFFSET) * (_p) + (_x)) >> 2) +#define RTL8367C_MIB_ADDRESS_REG 0x1004 +#define RTL8367C_MIB_ADDRESS_PORT_OFFSET 0x007C +#define RTL8367C_MIB_ADDRESS(_p, _x) \ + (((RTL8367C_MIB_ADDRESS_PORT_OFFSET) * (_p) + (_x)) >> 2) -#define RTL8365MB_MIB_CTRL0_REG 0x1005 -#define RTL8365MB_MIB_CTRL0_RESET_MASK 0x0002 -#define RTL8365MB_MIB_CTRL0_BUSY_MASK 0x0001 +#define RTL8367C_MIB_CTRL0_REG 0x1005 +#define RTL8367C_MIB_CTRL0_RESET_MASK 0x0002 +#define RTL8367C_MIB_CTRL0_BUSY_MASK 0x0001 /* The DSA callback .get_stats64 runs in atomic context, so we are not allowed * to block. On the other hand, accessing MIB counters absolutely requires us to @@ -305,149 +294,149 @@ * asynchronously and updates some private data, which the callback can then * fetch atomically. Three seconds should be a good enough polling interval. */ -#define RTL8365MB_STATS_INTERVAL_JIFFIES (3 * HZ) - -enum rtl8365mb_mib_counter_index { - RTL8365MB_MIB_ifInOctets, - RTL8365MB_MIB_dot3StatsFCSErrors, - RTL8365MB_MIB_dot3StatsSymbolErrors, - RTL8365MB_MIB_dot3InPauseFrames, - RTL8365MB_MIB_dot3ControlInUnknownOpcodes, - RTL8365MB_MIB_etherStatsFragments, - RTL8365MB_MIB_etherStatsJabbers, - RTL8365MB_MIB_ifInUcastPkts, - RTL8365MB_MIB_etherStatsDropEvents, - RTL8365MB_MIB_ifInMulticastPkts, - RTL8365MB_MIB_ifInBroadcastPkts, - RTL8365MB_MIB_inMldChecksumError, - RTL8365MB_MIB_inIgmpChecksumError, - RTL8365MB_MIB_inMldSpecificQuery, - RTL8365MB_MIB_inMldGeneralQuery, - RTL8365MB_MIB_inIgmpSpecificQuery, - RTL8365MB_MIB_inIgmpGeneralQuery, - RTL8365MB_MIB_inMldLeaves, - RTL8365MB_MIB_inIgmpLeaves, - RTL8365MB_MIB_etherStatsOctets, - RTL8365MB_MIB_etherStatsUnderSizePkts, - RTL8365MB_MIB_etherOversizeStats, - RTL8365MB_MIB_etherStatsPkts64Octets, - RTL8365MB_MIB_etherStatsPkts65to127Octets, - RTL8365MB_MIB_etherStatsPkts128to255Octets, - RTL8365MB_MIB_etherStatsPkts256to511Octets, - RTL8365MB_MIB_etherStatsPkts512to1023Octets, - RTL8365MB_MIB_etherStatsPkts1024to1518Octets, - RTL8365MB_MIB_ifOutOctets, - RTL8365MB_MIB_dot3StatsSingleCollisionFrames, - RTL8365MB_MIB_dot3StatsMultipleCollisionFrames, - RTL8365MB_MIB_dot3StatsDeferredTransmissions, - RTL8365MB_MIB_dot3StatsLateCollisions, - RTL8365MB_MIB_etherStatsCollisions, - RTL8365MB_MIB_dot3StatsExcessiveCollisions, - RTL8365MB_MIB_dot3OutPauseFrames, - RTL8365MB_MIB_ifOutDiscards, - RTL8365MB_MIB_dot1dTpPortInDiscards, - RTL8365MB_MIB_ifOutUcastPkts, - RTL8365MB_MIB_ifOutMulticastPkts, - RTL8365MB_MIB_ifOutBroadcastPkts, - RTL8365MB_MIB_outOampduPkts, - RTL8365MB_MIB_inOampduPkts, - RTL8365MB_MIB_inIgmpJoinsSuccess, - RTL8365MB_MIB_inIgmpJoinsFail, - RTL8365MB_MIB_inMldJoinsSuccess, - RTL8365MB_MIB_inMldJoinsFail, - RTL8365MB_MIB_inReportSuppressionDrop, - RTL8365MB_MIB_inLeaveSuppressionDrop, - RTL8365MB_MIB_outIgmpReports, - RTL8365MB_MIB_outIgmpLeaves, - RTL8365MB_MIB_outIgmpGeneralQuery, - RTL8365MB_MIB_outIgmpSpecificQuery, - RTL8365MB_MIB_outMldReports, - RTL8365MB_MIB_outMldLeaves, - RTL8365MB_MIB_outMldGeneralQuery, - RTL8365MB_MIB_outMldSpecificQuery, - RTL8365MB_MIB_inKnownMulticastPkts, - RTL8365MB_MIB_END, +#define RTL8367C_STATS_INTERVAL_JIFFIES (3 * HZ) + +enum rtl8367c_mib_counter_index { + RTL8367C_MIB_ifInOctets, + RTL8367C_MIB_dot3StatsFCSErrors, + RTL8367C_MIB_dot3StatsSymbolErrors, + RTL8367C_MIB_dot3InPauseFrames, + RTL8367C_MIB_dot3ControlInUnknownOpcodes, + RTL8367C_MIB_etherStatsFragments, + RTL8367C_MIB_etherStatsJabbers, + RTL8367C_MIB_ifInUcastPkts, + RTL8367C_MIB_etherStatsDropEvents, + RTL8367C_MIB_ifInMulticastPkts, + RTL8367C_MIB_ifInBroadcastPkts, + RTL8367C_MIB_inMldChecksumError, + RTL8367C_MIB_inIgmpChecksumError, + RTL8367C_MIB_inMldSpecificQuery, + RTL8367C_MIB_inMldGeneralQuery, + RTL8367C_MIB_inIgmpSpecificQuery, + RTL8367C_MIB_inIgmpGeneralQuery, + RTL8367C_MIB_inMldLeaves, + RTL8367C_MIB_inIgmpLeaves, + RTL8367C_MIB_etherStatsOctets, + RTL8367C_MIB_etherStatsUnderSizePkts, + RTL8367C_MIB_etherOversizeStats, + RTL8367C_MIB_etherStatsPkts64Octets, + RTL8367C_MIB_etherStatsPkts65to127Octets, + RTL8367C_MIB_etherStatsPkts128to255Octets, + RTL8367C_MIB_etherStatsPkts256to511Octets, + RTL8367C_MIB_etherStatsPkts512to1023Octets, + RTL8367C_MIB_etherStatsPkts1024to1518Octets, + RTL8367C_MIB_ifOutOctets, + RTL8367C_MIB_dot3StatsSingleCollisionFrames, + RTL8367C_MIB_dot3StatsMultipleCollisionFrames, + RTL8367C_MIB_dot3StatsDeferredTransmissions, + RTL8367C_MIB_dot3StatsLateCollisions, + RTL8367C_MIB_etherStatsCollisions, + RTL8367C_MIB_dot3StatsExcessiveCollisions, + RTL8367C_MIB_dot3OutPauseFrames, + RTL8367C_MIB_ifOutDiscards, + RTL8367C_MIB_dot1dTpPortInDiscards, + RTL8367C_MIB_ifOutUcastPkts, + RTL8367C_MIB_ifOutMulticastPkts, + RTL8367C_MIB_ifOutBroadcastPkts, + RTL8367C_MIB_outOampduPkts, + RTL8367C_MIB_inOampduPkts, + RTL8367C_MIB_inIgmpJoinsSuccess, + RTL8367C_MIB_inIgmpJoinsFail, + RTL8367C_MIB_inMldJoinsSuccess, + RTL8367C_MIB_inMldJoinsFail, + RTL8367C_MIB_inReportSuppressionDrop, + RTL8367C_MIB_inLeaveSuppressionDrop, + RTL8367C_MIB_outIgmpReports, + RTL8367C_MIB_outIgmpLeaves, + RTL8367C_MIB_outIgmpGeneralQuery, + RTL8367C_MIB_outIgmpSpecificQuery, + RTL8367C_MIB_outMldReports, + RTL8367C_MIB_outMldLeaves, + RTL8367C_MIB_outMldGeneralQuery, + RTL8367C_MIB_outMldSpecificQuery, + RTL8367C_MIB_inKnownMulticastPkts, + RTL8367C_MIB_END, }; -struct rtl8365mb_mib_counter { +struct rtl8367c_mib_counter { u32 offset; u32 length; const char *name; }; -#define RTL8365MB_MAKE_MIB_COUNTER(_offset, _length, _name) \ - [RTL8365MB_MIB_ ## _name] = { _offset, _length, #_name } - -static struct rtl8365mb_mib_counter rtl8365mb_mib_counters[] = { - RTL8365MB_MAKE_MIB_COUNTER(0, 4, ifInOctets), - RTL8365MB_MAKE_MIB_COUNTER(4, 2, dot3StatsFCSErrors), - RTL8365MB_MAKE_MIB_COUNTER(6, 2, dot3StatsSymbolErrors), - RTL8365MB_MAKE_MIB_COUNTER(8, 2, dot3InPauseFrames), - RTL8365MB_MAKE_MIB_COUNTER(10, 2, dot3ControlInUnknownOpcodes), - RTL8365MB_MAKE_MIB_COUNTER(12, 2, etherStatsFragments), - RTL8365MB_MAKE_MIB_COUNTER(14, 2, etherStatsJabbers), - RTL8365MB_MAKE_MIB_COUNTER(16, 2, ifInUcastPkts), - RTL8365MB_MAKE_MIB_COUNTER(18, 2, etherStatsDropEvents), - RTL8365MB_MAKE_MIB_COUNTER(20, 2, ifInMulticastPkts), - RTL8365MB_MAKE_MIB_COUNTER(22, 2, ifInBroadcastPkts), - RTL8365MB_MAKE_MIB_COUNTER(24, 2, inMldChecksumError), - RTL8365MB_MAKE_MIB_COUNTER(26, 2, inIgmpChecksumError), - RTL8365MB_MAKE_MIB_COUNTER(28, 2, inMldSpecificQuery), - RTL8365MB_MAKE_MIB_COUNTER(30, 2, inMldGeneralQuery), - RTL8365MB_MAKE_MIB_COUNTER(32, 2, inIgmpSpecificQuery), - RTL8365MB_MAKE_MIB_COUNTER(34, 2, inIgmpGeneralQuery), - RTL8365MB_MAKE_MIB_COUNTER(36, 2, inMldLeaves), - RTL8365MB_MAKE_MIB_COUNTER(38, 2, inIgmpLeaves), - RTL8365MB_MAKE_MIB_COUNTER(40, 4, etherStatsOctets), - RTL8365MB_MAKE_MIB_COUNTER(44, 2, etherStatsUnderSizePkts), - RTL8365MB_MAKE_MIB_COUNTER(46, 2, etherOversizeStats), - RTL8365MB_MAKE_MIB_COUNTER(48, 2, etherStatsPkts64Octets), - RTL8365MB_MAKE_MIB_COUNTER(50, 2, etherStatsPkts65to127Octets), - RTL8365MB_MAKE_MIB_COUNTER(52, 2, etherStatsPkts128to255Octets), - RTL8365MB_MAKE_MIB_COUNTER(54, 2, etherStatsPkts256to511Octets), - RTL8365MB_MAKE_MIB_COUNTER(56, 2, etherStatsPkts512to1023Octets), - RTL8365MB_MAKE_MIB_COUNTER(58, 2, etherStatsPkts1024to1518Octets), - RTL8365MB_MAKE_MIB_COUNTER(60, 4, ifOutOctets), - RTL8365MB_MAKE_MIB_COUNTER(64, 2, dot3StatsSingleCollisionFrames), - RTL8365MB_MAKE_MIB_COUNTER(66, 2, dot3StatsMultipleCollisionFrames), - RTL8365MB_MAKE_MIB_COUNTER(68, 2, dot3StatsDeferredTransmissions), - RTL8365MB_MAKE_MIB_COUNTER(70, 2, dot3StatsLateCollisions), - RTL8365MB_MAKE_MIB_COUNTER(72, 2, etherStatsCollisions), - RTL8365MB_MAKE_MIB_COUNTER(74, 2, dot3StatsExcessiveCollisions), - RTL8365MB_MAKE_MIB_COUNTER(76, 2, dot3OutPauseFrames), - RTL8365MB_MAKE_MIB_COUNTER(78, 2, ifOutDiscards), - RTL8365MB_MAKE_MIB_COUNTER(80, 2, dot1dTpPortInDiscards), - RTL8365MB_MAKE_MIB_COUNTER(82, 2, ifOutUcastPkts), - RTL8365MB_MAKE_MIB_COUNTER(84, 2, ifOutMulticastPkts), - RTL8365MB_MAKE_MIB_COUNTER(86, 2, ifOutBroadcastPkts), - RTL8365MB_MAKE_MIB_COUNTER(88, 2, outOampduPkts), - RTL8365MB_MAKE_MIB_COUNTER(90, 2, inOampduPkts), - RTL8365MB_MAKE_MIB_COUNTER(92, 4, inIgmpJoinsSuccess), - RTL8365MB_MAKE_MIB_COUNTER(96, 2, inIgmpJoinsFail), - RTL8365MB_MAKE_MIB_COUNTER(98, 2, inMldJoinsSuccess), - RTL8365MB_MAKE_MIB_COUNTER(100, 2, inMldJoinsFail), - RTL8365MB_MAKE_MIB_COUNTER(102, 2, inReportSuppressionDrop), - RTL8365MB_MAKE_MIB_COUNTER(104, 2, inLeaveSuppressionDrop), - RTL8365MB_MAKE_MIB_COUNTER(106, 2, outIgmpReports), - RTL8365MB_MAKE_MIB_COUNTER(108, 2, outIgmpLeaves), - RTL8365MB_MAKE_MIB_COUNTER(110, 2, outIgmpGeneralQuery), - RTL8365MB_MAKE_MIB_COUNTER(112, 2, outIgmpSpecificQuery), - RTL8365MB_MAKE_MIB_COUNTER(114, 2, outMldReports), - RTL8365MB_MAKE_MIB_COUNTER(116, 2, outMldLeaves), - RTL8365MB_MAKE_MIB_COUNTER(118, 2, outMldGeneralQuery), - RTL8365MB_MAKE_MIB_COUNTER(120, 2, outMldSpecificQuery), - RTL8365MB_MAKE_MIB_COUNTER(122, 2, inKnownMulticastPkts), +#define RTL8367C_MAKE_MIB_COUNTER(_offset, _length, _name) \ + [RTL8367C_MIB_ ## _name] = { _offset, _length, #_name } + +static struct rtl8367c_mib_counter rtl8367c_mib_counters[] = { + RTL8367C_MAKE_MIB_COUNTER(0, 4, ifInOctets), + RTL8367C_MAKE_MIB_COUNTER(4, 2, dot3StatsFCSErrors), + RTL8367C_MAKE_MIB_COUNTER(6, 2, dot3StatsSymbolErrors), + RTL8367C_MAKE_MIB_COUNTER(8, 2, dot3InPauseFrames), + RTL8367C_MAKE_MIB_COUNTER(10, 2, dot3ControlInUnknownOpcodes), + RTL8367C_MAKE_MIB_COUNTER(12, 2, etherStatsFragments), + RTL8367C_MAKE_MIB_COUNTER(14, 2, etherStatsJabbers), + RTL8367C_MAKE_MIB_COUNTER(16, 2, ifInUcastPkts), + RTL8367C_MAKE_MIB_COUNTER(18, 2, etherStatsDropEvents), + RTL8367C_MAKE_MIB_COUNTER(20, 2, ifInMulticastPkts), + RTL8367C_MAKE_MIB_COUNTER(22, 2, ifInBroadcastPkts), + RTL8367C_MAKE_MIB_COUNTER(24, 2, inMldChecksumError), + RTL8367C_MAKE_MIB_COUNTER(26, 2, inIgmpChecksumError), + RTL8367C_MAKE_MIB_COUNTER(28, 2, inMldSpecificQuery), + RTL8367C_MAKE_MIB_COUNTER(30, 2, inMldGeneralQuery), + RTL8367C_MAKE_MIB_COUNTER(32, 2, inIgmpSpecificQuery), + RTL8367C_MAKE_MIB_COUNTER(34, 2, inIgmpGeneralQuery), + RTL8367C_MAKE_MIB_COUNTER(36, 2, inMldLeaves), + RTL8367C_MAKE_MIB_COUNTER(38, 2, inIgmpLeaves), + RTL8367C_MAKE_MIB_COUNTER(40, 4, etherStatsOctets), + RTL8367C_MAKE_MIB_COUNTER(44, 2, etherStatsUnderSizePkts), + RTL8367C_MAKE_MIB_COUNTER(46, 2, etherOversizeStats), + RTL8367C_MAKE_MIB_COUNTER(48, 2, etherStatsPkts64Octets), + RTL8367C_MAKE_MIB_COUNTER(50, 2, etherStatsPkts65to127Octets), + RTL8367C_MAKE_MIB_COUNTER(52, 2, etherStatsPkts128to255Octets), + RTL8367C_MAKE_MIB_COUNTER(54, 2, etherStatsPkts256to511Octets), + RTL8367C_MAKE_MIB_COUNTER(56, 2, etherStatsPkts512to1023Octets), + RTL8367C_MAKE_MIB_COUNTER(58, 2, etherStatsPkts1024to1518Octets), + RTL8367C_MAKE_MIB_COUNTER(60, 4, ifOutOctets), + RTL8367C_MAKE_MIB_COUNTER(64, 2, dot3StatsSingleCollisionFrames), + RTL8367C_MAKE_MIB_COUNTER(66, 2, dot3StatsMultipleCollisionFrames), + RTL8367C_MAKE_MIB_COUNTER(68, 2, dot3StatsDeferredTransmissions), + RTL8367C_MAKE_MIB_COUNTER(70, 2, dot3StatsLateCollisions), + RTL8367C_MAKE_MIB_COUNTER(72, 2, etherStatsCollisions), + RTL8367C_MAKE_MIB_COUNTER(74, 2, dot3StatsExcessiveCollisions), + RTL8367C_MAKE_MIB_COUNTER(76, 2, dot3OutPauseFrames), + RTL8367C_MAKE_MIB_COUNTER(78, 2, ifOutDiscards), + RTL8367C_MAKE_MIB_COUNTER(80, 2, dot1dTpPortInDiscards), + RTL8367C_MAKE_MIB_COUNTER(82, 2, ifOutUcastPkts), + RTL8367C_MAKE_MIB_COUNTER(84, 2, ifOutMulticastPkts), + RTL8367C_MAKE_MIB_COUNTER(86, 2, ifOutBroadcastPkts), + RTL8367C_MAKE_MIB_COUNTER(88, 2, outOampduPkts), + RTL8367C_MAKE_MIB_COUNTER(90, 2, inOampduPkts), + RTL8367C_MAKE_MIB_COUNTER(92, 4, inIgmpJoinsSuccess), + RTL8367C_MAKE_MIB_COUNTER(96, 2, inIgmpJoinsFail), + RTL8367C_MAKE_MIB_COUNTER(98, 2, inMldJoinsSuccess), + RTL8367C_MAKE_MIB_COUNTER(100, 2, inMldJoinsFail), + RTL8367C_MAKE_MIB_COUNTER(102, 2, inReportSuppressionDrop), + RTL8367C_MAKE_MIB_COUNTER(104, 2, inLeaveSuppressionDrop), + RTL8367C_MAKE_MIB_COUNTER(106, 2, outIgmpReports), + RTL8367C_MAKE_MIB_COUNTER(108, 2, outIgmpLeaves), + RTL8367C_MAKE_MIB_COUNTER(110, 2, outIgmpGeneralQuery), + RTL8367C_MAKE_MIB_COUNTER(112, 2, outIgmpSpecificQuery), + RTL8367C_MAKE_MIB_COUNTER(114, 2, outMldReports), + RTL8367C_MAKE_MIB_COUNTER(116, 2, outMldLeaves), + RTL8367C_MAKE_MIB_COUNTER(118, 2, outMldGeneralQuery), + RTL8367C_MAKE_MIB_COUNTER(120, 2, outMldSpecificQuery), + RTL8367C_MAKE_MIB_COUNTER(122, 2, inKnownMulticastPkts), }; -static_assert(ARRAY_SIZE(rtl8365mb_mib_counters) == RTL8365MB_MIB_END); +static_assert(ARRAY_SIZE(rtl8367c_mib_counters) == RTL8367C_MIB_END); -struct rtl8365mb_jam_tbl_entry { +struct rtl8367c_jam_tbl_entry { u16 reg; u16 val; }; /* Lifted from the vendor driver sources */ -static const struct rtl8365mb_jam_tbl_entry rtl8365mb_init_jam_8365mb_vc[] = { +static const struct rtl8367c_jam_tbl_entry rtl8367c_init_jam_8367c[] = { { 0x13EB, 0x15BB }, { 0x1303, 0x06D6 }, { 0x1304, 0x0700 }, { 0x13E2, 0x003F }, { 0x13F9, 0x0090 }, { 0x121E, 0x03CA }, { 0x1233, 0x0352 }, { 0x1237, 0x00A0 }, { 0x123A, 0x0030 }, @@ -456,43 +445,43 @@ static const struct rtl8365mb_jam_tbl_entry rtl8365mb_init_jam_8365mb_vc[] = { { 0x13F0, 0x0000 }, }; -static const struct rtl8365mb_jam_tbl_entry rtl8365mb_init_jam_common[] = { +static const struct rtl8367c_jam_tbl_entry rtl8367c_init_jam_common[] = { { 0x1200, 0x7FCB }, { 0x0884, 0x0003 }, { 0x06EB, 0x0001 }, { 0x03Fa, 0x0007 }, { 0x08C8, 0x00C0 }, { 0x0A30, 0x020E }, { 0x0800, 0x0000 }, { 0x0802, 0x0000 }, { 0x09DA, 0x0013 }, { 0x1D32, 0x0002 }, }; -enum rtl8365mb_stp_state { - RTL8365MB_STP_STATE_DISABLED = 0, - RTL8365MB_STP_STATE_BLOCKING = 1, - RTL8365MB_STP_STATE_LEARNING = 2, - RTL8365MB_STP_STATE_FORWARDING = 3, +enum rtl8367c_stp_state { + RTL8367C_STP_STATE_DISABLED = 0, + RTL8367C_STP_STATE_BLOCKING = 1, + RTL8367C_STP_STATE_LEARNING = 2, + RTL8367C_STP_STATE_FORWARDING = 3, }; -enum rtl8365mb_cpu_insert { - RTL8365MB_CPU_INSERT_TO_ALL = 0, - RTL8365MB_CPU_INSERT_TO_TRAPPING = 1, - RTL8365MB_CPU_INSERT_TO_NONE = 2, +enum rtl8367c_cpu_insert { + RTL8367C_CPU_INSERT_TO_ALL = 0, + RTL8367C_CPU_INSERT_TO_TRAPPING = 1, + RTL8367C_CPU_INSERT_TO_NONE = 2, }; -enum rtl8365mb_cpu_position { - RTL8365MB_CPU_POS_AFTER_SA = 0, - RTL8365MB_CPU_POS_BEFORE_CRC = 1, +enum rtl8367c_cpu_position { + RTL8367C_CPU_POS_AFTER_SA = 0, + RTL8367C_CPU_POS_BEFORE_CRC = 1, }; -enum rtl8365mb_cpu_format { - RTL8365MB_CPU_FORMAT_8BYTES = 0, - RTL8365MB_CPU_FORMAT_4BYTES = 1, +enum rtl8367c_cpu_format { + RTL8367C_CPU_FORMAT_8BYTES = 0, + RTL8367C_CPU_FORMAT_4BYTES = 1, }; -enum rtl8365mb_cpu_rxlen { - RTL8365MB_CPU_RXLEN_72BYTES = 0, - RTL8365MB_CPU_RXLEN_64BYTES = 1, +enum rtl8367c_cpu_rxlen { + RTL8367C_CPU_RXLEN_72BYTES = 0, + RTL8367C_CPU_RXLEN_64BYTES = 1, }; /** - * struct rtl8365mb_cpu - CPU port configuration + * struct rtl8367c_cpu - CPU port configuration * @enable: enable/disable hardware insertion of CPU tag in switch->CPU frames * @mask: port mask of ports that parse should parse CPU tags * @trap_port: forward trapped frames to this port @@ -504,26 +493,26 @@ enum rtl8365mb_cpu_rxlen { * Represents the CPU tagging and CPU port configuration of the switch. These * settings are configurable at runtime. */ -struct rtl8365mb_cpu { +struct rtl8367c_cpu { bool enable; u32 mask; u32 trap_port; - enum rtl8365mb_cpu_insert insert; - enum rtl8365mb_cpu_position position; - enum rtl8365mb_cpu_rxlen rx_length; - enum rtl8365mb_cpu_format format; + enum rtl8367c_cpu_insert insert; + enum rtl8367c_cpu_position position; + enum rtl8367c_cpu_rxlen rx_length; + enum rtl8367c_cpu_format format; }; /** - * struct rtl8365mb_port - private per-port data + * struct rtl8367c_port - private per-port data * @priv: pointer to parent realtek_priv data * @index: DSA port index, same as dsa_port::index - * @stats: link statistics populated by rtl8365mb_stats_poll, ready for atomic - * access via rtl8365mb_get_stats64 + * @stats: link statistics populated by rtl8367c_stats_poll, ready for atomic + * access via rtl8367c_get_stats64 * @stats_lock: protect the stats structure during read/update * @mib_work: delayed work for polling MIB counters */ -struct rtl8365mb_port { +struct rtl8367c_port { struct realtek_priv *priv; unsigned int index; struct rtnl_link_stats64 stats; @@ -532,7 +521,7 @@ struct rtl8365mb_port { }; /** - * struct rtl8365mb - private chip-specific driver data + * struct rtl8367c - private chip-specific driver data * @priv: pointer to parent realtek_priv data * @irq: registered IRQ or zero * @chip_id: chip identifier @@ -547,52 +536,52 @@ struct rtl8365mb_port { * * Private data for this driver. */ -struct rtl8365mb { +struct rtl8367c { struct realtek_priv *priv; int irq; u32 chip_id; u32 chip_ver; u32 port_mask; u32 learn_limit_max; - struct rtl8365mb_cpu cpu; + struct rtl8367c_cpu cpu; struct mutex mib_lock; - struct rtl8365mb_port ports[RTL8365MB_MAX_NUM_PORTS]; - const struct rtl8365mb_jam_tbl_entry *jam_table; + struct rtl8367c_port ports[RTL8367C_MAX_NUM_PORTS]; + const struct rtl8367c_jam_tbl_entry *jam_table; size_t jam_size; }; -static int rtl8365mb_phy_poll_busy(struct realtek_priv *priv) +static int rtl8367c_phy_poll_busy(struct realtek_priv *priv) { u32 val; return regmap_read_poll_timeout(priv->map, - RTL8365MB_INDIRECT_ACCESS_STATUS_REG, + RTL8367C_INDIRECT_ACCESS_STATUS_REG, val, !val, 10, 100); } -static int rtl8365mb_phy_ocp_prepare(struct realtek_priv *priv, int phy, +static int rtl8367c_phy_ocp_prepare(struct realtek_priv *priv, int phy, u32 ocp_addr) { u32 val; int ret; /* Set OCP prefix */ - val = FIELD_GET(RTL8365MB_PHY_OCP_ADDR_PREFIX_MASK, ocp_addr); + val = FIELD_GET(RTL8367C_PHY_OCP_ADDR_PREFIX_MASK, ocp_addr); ret = regmap_update_bits( - priv->map, RTL8365MB_GPHY_OCP_MSB_0_REG, - RTL8365MB_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK, - FIELD_PREP(RTL8365MB_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK, val)); + priv->map, RTL8367C_GPHY_OCP_MSB_0_REG, + RTL8367C_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK, + FIELD_PREP(RTL8367C_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK, val)); if (ret) return ret; /* Set PHY register address */ - val = RTL8365MB_PHY_BASE; - val |= FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_ADDRESS_PHYNUM_MASK, phy); - val |= FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_5_1_MASK, + val = RTL8367C_PHY_BASE; + val |= FIELD_PREP(RTL8367C_INDIRECT_ACCESS_ADDRESS_PHYNUM_MASK, phy); + val |= FIELD_PREP(RTL8367C_INDIRECT_ACCESS_ADDRESS_OCPADR_5_1_MASK, ocp_addr >> 1); - val |= FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_9_6_MASK, + val |= FIELD_PREP(RTL8367C_INDIRECT_ACCESS_ADDRESS_OCPADR_9_6_MASK, ocp_addr >> 6); - ret = regmap_write(priv->map, RTL8365MB_INDIRECT_ACCESS_ADDRESS_REG, + ret = regmap_write(priv->map, RTL8367C_INDIRECT_ACCESS_ADDRESS_REG, val); if (ret) return ret; @@ -600,35 +589,35 @@ static int rtl8365mb_phy_ocp_prepare(struct realtek_priv *priv, int phy, return 0; } -static int rtl8365mb_phy_ocp_read(struct realtek_priv *priv, int phy, +static int rtl8367c_phy_ocp_read(struct realtek_priv *priv, int phy, u32 ocp_addr, u16 *data) { u32 val; int ret; - ret = rtl8365mb_phy_poll_busy(priv); + ret = rtl8367c_phy_poll_busy(priv); if (ret) return ret; - ret = rtl8365mb_phy_ocp_prepare(priv, phy, ocp_addr); + ret = rtl8367c_phy_ocp_prepare(priv, phy, ocp_addr); if (ret) return ret; /* Execute read operation */ - val = FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_MASK, - RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_VALUE) | - FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_RW_MASK, - RTL8365MB_INDIRECT_ACCESS_CTRL_RW_READ); - ret = regmap_write(priv->map, RTL8365MB_INDIRECT_ACCESS_CTRL_REG, val); + val = FIELD_PREP(RTL8367C_INDIRECT_ACCESS_CTRL_CMD_MASK, + RTL8367C_INDIRECT_ACCESS_CTRL_CMD_VALUE) | + FIELD_PREP(RTL8367C_INDIRECT_ACCESS_CTRL_RW_MASK, + RTL8367C_INDIRECT_ACCESS_CTRL_RW_READ); + ret = regmap_write(priv->map, RTL8367C_INDIRECT_ACCESS_CTRL_REG, val); if (ret) return ret; - ret = rtl8365mb_phy_poll_busy(priv); + ret = rtl8367c_phy_poll_busy(priv); if (ret) return ret; /* Get PHY register data */ - ret = regmap_read(priv->map, RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG, + ret = regmap_read(priv->map, RTL8367C_INDIRECT_ACCESS_READ_DATA_REG, &val); if (ret) return ret; @@ -638,58 +627,58 @@ static int rtl8365mb_phy_ocp_read(struct realtek_priv *priv, int phy, return 0; } -static int rtl8365mb_phy_ocp_write(struct realtek_priv *priv, int phy, +static int rtl8367c_phy_ocp_write(struct realtek_priv *priv, int phy, u32 ocp_addr, u16 data) { u32 val; int ret; - ret = rtl8365mb_phy_poll_busy(priv); + ret = rtl8367c_phy_poll_busy(priv); if (ret) return ret; - ret = rtl8365mb_phy_ocp_prepare(priv, phy, ocp_addr); + ret = rtl8367c_phy_ocp_prepare(priv, phy, ocp_addr); if (ret) return ret; /* Set PHY register data */ - ret = regmap_write(priv->map, RTL8365MB_INDIRECT_ACCESS_WRITE_DATA_REG, + ret = regmap_write(priv->map, RTL8367C_INDIRECT_ACCESS_WRITE_DATA_REG, data); if (ret) return ret; /* Execute write operation */ - val = FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_MASK, - RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_VALUE) | - FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_RW_MASK, - RTL8365MB_INDIRECT_ACCESS_CTRL_RW_WRITE); - ret = regmap_write(priv->map, RTL8365MB_INDIRECT_ACCESS_CTRL_REG, val); + val = FIELD_PREP(RTL8367C_INDIRECT_ACCESS_CTRL_CMD_MASK, + RTL8367C_INDIRECT_ACCESS_CTRL_CMD_VALUE) | + FIELD_PREP(RTL8367C_INDIRECT_ACCESS_CTRL_RW_MASK, + RTL8367C_INDIRECT_ACCESS_CTRL_RW_WRITE); + ret = regmap_write(priv->map, RTL8367C_INDIRECT_ACCESS_CTRL_REG, val); if (ret) return ret; - ret = rtl8365mb_phy_poll_busy(priv); + ret = rtl8367c_phy_poll_busy(priv); if (ret) return ret; return 0; } -static int rtl8365mb_phy_read(struct dsa_switch *ds, int phy, int regnum) +static int rtl8367c_phy_read(struct dsa_switch *ds, int phy, int regnum) { u32 ocp_addr; u16 val; int ret; struct realtek_priv *priv = ds->priv; - if (phy > RTL8365MB_PHYADDRMAX) + if (phy > RTL8367C_PHYADDRMAX) return -EINVAL; - if (regnum > RTL8365MB_PHYREGMAX) + if (regnum > RTL8367C_PHYREGMAX) return -EINVAL; - ocp_addr = RTL8365MB_PHY_OCP_ADDR_PHYREG_BASE + regnum * 2; + ocp_addr = RTL8367C_PHY_OCP_ADDR_PHYREG_BASE + regnum * 2; - ret = rtl8365mb_phy_ocp_read(priv, phy, ocp_addr, &val); + ret = rtl8367c_phy_ocp_read(priv, phy, ocp_addr, &val); if (ret) { dev_err(priv->dev, "failed to read PHY%d reg %02x @ %04x, ret %d\n", phy, @@ -703,22 +692,22 @@ static int rtl8365mb_phy_read(struct dsa_switch *ds, int phy, int regnum) return val; } -static int rtl8365mb_phy_write(struct dsa_switch *ds, int phy, int regnum, +static int rtl8367c_phy_write(struct dsa_switch *ds, int phy, int regnum, u16 val) { u32 ocp_addr; int ret; struct realtek_priv *priv = (struct realtek_priv *)ds->priv; - if (phy > RTL8365MB_PHYADDRMAX) + if (phy > RTL8367C_PHYADDRMAX) return -EINVAL; - if (regnum > RTL8365MB_PHYREGMAX) + if (regnum > RTL8367C_PHYREGMAX) return -EINVAL; - ocp_addr = RTL8365MB_PHY_OCP_ADDR_PHYREG_BASE + regnum * 2; + ocp_addr = RTL8367C_PHY_OCP_ADDR_PHYREG_BASE + regnum * 2; - ret = rtl8365mb_phy_ocp_write(priv, phy, ocp_addr, val); + ret = rtl8367c_phy_ocp_write(priv, phy, ocp_addr, val); if (ret) { dev_err(priv->dev, "failed to write PHY%d reg %02x @ %04x, ret %d\n", phy, @@ -733,13 +722,13 @@ static int rtl8365mb_phy_write(struct dsa_switch *ds, int phy, int regnum, } static enum dsa_tag_protocol -rtl8365mb_get_tag_protocol(struct dsa_switch *ds, int port, +rtl8367c_get_tag_protocol(struct dsa_switch *ds, int port, enum dsa_tag_protocol mp) { return DSA_TAG_PROTO_RTL8_4; } -static int rtl8365mb_ext_config_rgmii(struct realtek_priv *priv, int port, +static int rtl8367c_ext_config_rgmii(struct realtek_priv *priv, int port, phy_interface_t interface) { struct device_node *dn; @@ -774,7 +763,7 @@ static int rtl8365mb_ext_config_rgmii(struct realtek_priv *priv, int port, * * The vendor driver also states that this must be configured *before* * forcing the external interface into a particular mode, which is done - * in the rtl8365mb_phylink_mac_link_{up,down} functions. + * in the rtl8367c_phylink_mac_link_{up,down} functions. * * Only configure an RGMII TX (resp. RX) delay if the * tx-internal-delay-ps (resp. rx-internal-delay-ps) OF property is @@ -803,19 +792,19 @@ static int rtl8365mb_ext_config_rgmii(struct realtek_priv *priv, int port, } ret = regmap_update_bits( - priv->map, RTL8365MB_EXT_RGMXF_REG(ext_port), - RTL8365MB_EXT_RGMXF_TXDELAY_MASK | - RTL8365MB_EXT_RGMXF_RXDELAY_MASK, - FIELD_PREP(RTL8365MB_EXT_RGMXF_TXDELAY_MASK, tx_delay) | - FIELD_PREP(RTL8365MB_EXT_RGMXF_RXDELAY_MASK, rx_delay)); + priv->map, RTL8367C_EXT_RGMXF_REG(ext_port), + RTL8367C_EXT_RGMXF_TXDELAY_MASK | + RTL8367C_EXT_RGMXF_RXDELAY_MASK, + FIELD_PREP(RTL8367C_EXT_RGMXF_TXDELAY_MASK, tx_delay) | + FIELD_PREP(RTL8367C_EXT_RGMXF_RXDELAY_MASK, rx_delay)); if (ret) return ret; ret = regmap_update_bits( - priv->map, RTL8365MB_DIGITAL_INTERFACE_SELECT_REG(ext_port), - RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_MASK(ext_port), - RTL8365MB_EXT_PORT_MODE_RGMII - << RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_OFFSET( + priv->map, RTL8367C_DIGITAL_INTERFACE_SELECT_REG(ext_port), + RTL8367C_DIGITAL_INTERFACE_SELECT_MODE_MASK(ext_port), + RTL8367C_EXT_PORT_MODE_RGMII + << RTL8367C_DIGITAL_INTERFACE_SELECT_MODE_OFFSET( ext_port)); if (ret) return ret; @@ -823,7 +812,7 @@ static int rtl8365mb_ext_config_rgmii(struct realtek_priv *priv, int port, return 0; } -static int rtl8365mb_ext_config_forcemode(struct realtek_priv *priv, int port, +static int rtl8367c_ext_config_forcemode(struct realtek_priv *priv, int port, bool link, int speed, int duplex, bool tx_pause, bool rx_pause) { @@ -850,11 +839,11 @@ static int rtl8365mb_ext_config_forcemode(struct realtek_priv *priv, int port, r_tx_pause = tx_pause ? 1 : 0; if (speed == SPEED_1000) { - r_speed = RTL8365MB_PORT_SPEED_1000M; + r_speed = RTL8367C_PORT_SPEED_1000M; } else if (speed == SPEED_100) { - r_speed = RTL8365MB_PORT_SPEED_100M; + r_speed = RTL8367C_PORT_SPEED_100M; } else if (speed == SPEED_10) { - r_speed = RTL8365MB_PORT_SPEED_10M; + r_speed = RTL8367C_PORT_SPEED_10M; } else { dev_err(priv->dev, "unsupported port speed %s\n", phy_speed_to_str(speed)); @@ -879,17 +868,17 @@ static int rtl8365mb_ext_config_forcemode(struct realtek_priv *priv, int port, r_duplex = 0; } - val = FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_EN_MASK, 1) | - FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_TXPAUSE_MASK, + val = FIELD_PREP(RTL8367C_DIGITAL_INTERFACE_FORCE_EN_MASK, 1) | + FIELD_PREP(RTL8367C_DIGITAL_INTERFACE_FORCE_TXPAUSE_MASK, r_tx_pause) | - FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_RXPAUSE_MASK, + FIELD_PREP(RTL8367C_DIGITAL_INTERFACE_FORCE_RXPAUSE_MASK, r_rx_pause) | - FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_LINK_MASK, r_link) | - FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_DUPLEX_MASK, + FIELD_PREP(RTL8367C_DIGITAL_INTERFACE_FORCE_LINK_MASK, r_link) | + FIELD_PREP(RTL8367C_DIGITAL_INTERFACE_FORCE_DUPLEX_MASK, r_duplex) | - FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_SPEED_MASK, r_speed); + FIELD_PREP(RTL8367C_DIGITAL_INTERFACE_FORCE_SPEED_MASK, r_speed); ret = regmap_write(priv->map, - RTL8365MB_DIGITAL_INTERFACE_FORCE_REG(ext_port), + RTL8367C_DIGITAL_INTERFACE_FORCE_REG(ext_port), val); if (ret) return ret; @@ -897,7 +886,7 @@ static int rtl8365mb_ext_config_forcemode(struct realtek_priv *priv, int port, return 0; } -static bool rtl8365mb_phy_mode_supported(struct dsa_switch *ds, int port, +static bool rtl8367c_phy_mode_supported(struct dsa_switch *ds, int port, phy_interface_t interface) { if (dsa_is_user_port(ds, port) && @@ -914,7 +903,7 @@ static bool rtl8365mb_phy_mode_supported(struct dsa_switch *ds, int port, return false; } -static void rtl8365mb_phylink_validate(struct dsa_switch *ds, int port, +static void rtl8367c_phylink_validate(struct dsa_switch *ds, int port, unsigned long *supported, struct phylink_link_state *state) { @@ -926,7 +915,7 @@ static void rtl8365mb_phylink_validate(struct dsa_switch *ds, int port, * expects the MAC driver to return all supported link modes. */ if (state->interface != PHY_INTERFACE_MODE_NA && - !rtl8365mb_phy_mode_supported(ds, port, state->interface)) { + !rtl8367c_phy_mode_supported(ds, port, state->interface)) { dev_err(priv->dev, "phy mode %s is unsupported on port %d\n", phy_modes(state->interface), port); linkmode_zero(supported); @@ -949,14 +938,14 @@ static void rtl8365mb_phylink_validate(struct dsa_switch *ds, int port, linkmode_and(state->advertising, state->advertising, mask); } -static void rtl8365mb_phylink_mac_config(struct dsa_switch *ds, int port, +static void rtl8367c_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, const struct phylink_link_state *state) { struct realtek_priv *priv = ds->priv; int ret; - if (!rtl8365mb_phy_mode_supported(ds, port, state->interface)) { + if (!rtl8367c_phy_mode_supported(ds, port, state->interface)) { dev_err(priv->dev, "phy mode %s is unsupported on port %d\n", phy_modes(state->interface), port); return; @@ -970,7 +959,7 @@ static void rtl8365mb_phylink_mac_config(struct dsa_switch *ds, int port, } if (phy_interface_mode_is_rgmii(state->interface)) { - ret = rtl8365mb_ext_config_rgmii(priv, port, state->interface); + ret = rtl8367c_ext_config_rgmii(priv, port, state->interface); if (ret) dev_err(priv->dev, "failed to configure RGMII mode on port %d: %d\n", @@ -983,13 +972,13 @@ static void rtl8365mb_phylink_mac_config(struct dsa_switch *ds, int port, */ } -static void rtl8365mb_phylink_mac_link_down(struct dsa_switch *ds, int port, +static void rtl8367c_phylink_mac_link_down(struct dsa_switch *ds, int port, unsigned int mode, phy_interface_t interface) { struct realtek_priv *priv = ds->priv; - struct rtl8365mb_port *p; - struct rtl8365mb *mb; + struct rtl8367c_port *p; + struct rtl8367c *mb; int ret; mb = priv->chip_data; @@ -997,7 +986,7 @@ static void rtl8365mb_phylink_mac_link_down(struct dsa_switch *ds, int port, cancel_delayed_work_sync(&p->mib_work); if (phy_interface_mode_is_rgmii(interface)) { - ret = rtl8365mb_ext_config_forcemode(priv, port, false, 0, 0, + ret = rtl8367c_ext_config_forcemode(priv, port, false, 0, 0, false, false); if (ret) dev_err(priv->dev, @@ -1008,7 +997,7 @@ static void rtl8365mb_phylink_mac_link_down(struct dsa_switch *ds, int port, } } -static void rtl8365mb_phylink_mac_link_up(struct dsa_switch *ds, int port, +static void rtl8367c_phylink_mac_link_up(struct dsa_switch *ds, int port, unsigned int mode, phy_interface_t interface, struct phy_device *phydev, int speed, @@ -1016,8 +1005,8 @@ static void rtl8365mb_phylink_mac_link_up(struct dsa_switch *ds, int port, bool rx_pause) { struct realtek_priv *priv = ds->priv; - struct rtl8365mb_port *p; - struct rtl8365mb *mb; + struct rtl8367c_port *p; + struct rtl8367c *mb; int ret; mb = priv->chip_data; @@ -1025,7 +1014,7 @@ static void rtl8365mb_phylink_mac_link_up(struct dsa_switch *ds, int port, schedule_delayed_work(&p->mib_work, 0); if (phy_interface_mode_is_rgmii(interface)) { - ret = rtl8365mb_ext_config_forcemode(priv, port, true, speed, + ret = rtl8367c_ext_config_forcemode(priv, port, true, speed, duplex, tx_pause, rx_pause); if (ret) @@ -1037,58 +1026,58 @@ static void rtl8365mb_phylink_mac_link_up(struct dsa_switch *ds, int port, } } -static void rtl8365mb_port_stp_state_set(struct dsa_switch *ds, int port, +static void rtl8367c_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) { struct realtek_priv *priv = ds->priv; - enum rtl8365mb_stp_state val; + enum rtl8367c_stp_state val; int msti = 0; switch (state) { case BR_STATE_DISABLED: - val = RTL8365MB_STP_STATE_DISABLED; + val = RTL8367C_STP_STATE_DISABLED; break; case BR_STATE_BLOCKING: case BR_STATE_LISTENING: - val = RTL8365MB_STP_STATE_BLOCKING; + val = RTL8367C_STP_STATE_BLOCKING; break; case BR_STATE_LEARNING: - val = RTL8365MB_STP_STATE_LEARNING; + val = RTL8367C_STP_STATE_LEARNING; break; case BR_STATE_FORWARDING: - val = RTL8365MB_STP_STATE_FORWARDING; + val = RTL8367C_STP_STATE_FORWARDING; break; default: dev_err(priv->dev, "invalid STP state: %u\n", state); return; } - regmap_update_bits(priv->map, RTL8365MB_MSTI_CTRL_REG(msti, port), - RTL8365MB_MSTI_CTRL_PORT_STATE_MASK(port), - val << RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET(port)); + regmap_update_bits(priv->map, RTL8367C_MSTI_CTRL_REG(msti, port), + RTL8367C_MSTI_CTRL_PORT_STATE_MASK(port), + val << RTL8367C_MSTI_CTRL_PORT_STATE_OFFSET(port)); } -static int rtl8365mb_port_set_learning(struct realtek_priv *priv, int port, +static int rtl8367c_port_set_learning(struct realtek_priv *priv, int port, bool enable) { - struct rtl8365mb *mb = priv->chip_data; + struct rtl8367c *mb = priv->chip_data; /* Enable/disable learning by limiting the number of L2 addresses the * port can learn. Realtek documentation states that a limit of zero * disables learning. When enabling learning, set it to the chip's * maximum. */ - return regmap_write(priv->map, RTL8365MB_LUT_PORT_LEARN_LIMIT_REG(port), + return regmap_write(priv->map, RTL8367C_LUT_PORT_LEARN_LIMIT_REG(port), enable ? mb->learn_limit_max : 0); } -static int rtl8365mb_port_set_isolation(struct realtek_priv *priv, int port, +static int rtl8367c_port_set_isolation(struct realtek_priv *priv, int port, u32 mask) { - return regmap_write(priv->map, RTL8365MB_PORT_ISOLATION_REG(port), mask); + return regmap_write(priv->map, RTL8367C_PORT_ISOLATION_REG(port), mask); } -static int rtl8365mb_mib_counter_read(struct realtek_priv *priv, int port, +static int rtl8367c_mib_counter_read(struct realtek_priv *priv, int port, u32 offset, u32 length, u64 *mibvalue) { u64 tmpvalue = 0; @@ -1100,20 +1089,20 @@ static int rtl8365mb_mib_counter_read(struct realtek_priv *priv, int port, * and then poll the control register before reading the value from some * counter registers. */ - ret = regmap_write(priv->map, RTL8365MB_MIB_ADDRESS_REG, - RTL8365MB_MIB_ADDRESS(port, offset)); + ret = regmap_write(priv->map, RTL8367C_MIB_ADDRESS_REG, + RTL8367C_MIB_ADDRESS(port, offset)); if (ret) return ret; /* Poll for completion */ - ret = regmap_read_poll_timeout(priv->map, RTL8365MB_MIB_CTRL0_REG, val, - !(val & RTL8365MB_MIB_CTRL0_BUSY_MASK), + ret = regmap_read_poll_timeout(priv->map, RTL8367C_MIB_CTRL0_REG, val, + !(val & RTL8367C_MIB_CTRL0_BUSY_MASK), 10, 100); if (ret) return ret; /* Presumably this indicates a MIB counter read failure */ - if (val & RTL8365MB_MIB_CTRL0_RESET_MASK) + if (val & RTL8367C_MIB_CTRL0_RESET_MASK) return -EIO; /* There are four MIB counter registers each holding a 16 bit word of a @@ -1129,7 +1118,7 @@ static int rtl8365mb_mib_counter_read(struct realtek_priv *priv, int port, /* Read the MIB counter 16 bits at a time */ for (i = 0; i < length; i++) { ret = regmap_read(priv->map, - RTL8365MB_MIB_COUNTER_REG(offset - i), &val); + RTL8367C_MIB_COUNTER_REG(offset - i), &val); if (ret) return ret; @@ -1142,20 +1131,20 @@ static int rtl8365mb_mib_counter_read(struct realtek_priv *priv, int port, return 0; } -static void rtl8365mb_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *data) +static void rtl8367c_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *data) { struct realtek_priv *priv = ds->priv; - struct rtl8365mb *mb; + struct rtl8367c *mb; int ret; int i; mb = priv->chip_data; mutex_lock(&mb->mib_lock); - for (i = 0; i < RTL8365MB_MIB_END; i++) { - struct rtl8365mb_mib_counter *mib = &rtl8365mb_mib_counters[i]; + for (i = 0; i < RTL8367C_MIB_END; i++) { + struct rtl8367c_mib_counter *mib = &rtl8367c_mib_counters[i]; - ret = rtl8365mb_mib_counter_read(priv, port, mib->offset, + ret = rtl8367c_mib_counter_read(priv, port, mib->offset, mib->length, &data[i]); if (ret) { dev_err(priv->dev, @@ -1167,83 +1156,83 @@ static void rtl8365mb_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *da mutex_unlock(&mb->mib_lock); } -static void rtl8365mb_get_strings(struct dsa_switch *ds, int port, u32 stringset, u8 *data) +static void rtl8367c_get_strings(struct dsa_switch *ds, int port, u32 stringset, u8 *data) { int i; if (stringset != ETH_SS_STATS) return; - for (i = 0; i < RTL8365MB_MIB_END; i++) { - struct rtl8365mb_mib_counter *mib = &rtl8365mb_mib_counters[i]; + for (i = 0; i < RTL8367C_MIB_END; i++) { + struct rtl8367c_mib_counter *mib = &rtl8367c_mib_counters[i]; strncpy(data + i * ETH_GSTRING_LEN, mib->name, ETH_GSTRING_LEN); } } -static int rtl8365mb_get_sset_count(struct dsa_switch *ds, int port, int sset) +static int rtl8367c_get_sset_count(struct dsa_switch *ds, int port, int sset) { if (sset != ETH_SS_STATS) return -EOPNOTSUPP; - return RTL8365MB_MIB_END; + return RTL8367C_MIB_END; } -static void rtl8365mb_get_phy_stats(struct dsa_switch *ds, int port, +static void rtl8367c_get_phy_stats(struct dsa_switch *ds, int port, struct ethtool_eth_phy_stats *phy_stats) { struct realtek_priv *priv = ds->priv; - struct rtl8365mb_mib_counter *mib; - struct rtl8365mb *mb; + struct rtl8367c_mib_counter *mib; + struct rtl8367c *mb; mb = priv->chip_data; - mib = &rtl8365mb_mib_counters[RTL8365MB_MIB_dot3StatsSymbolErrors]; + mib = &rtl8367c_mib_counters[RTL8367C_MIB_dot3StatsSymbolErrors]; mutex_lock(&mb->mib_lock); - rtl8365mb_mib_counter_read(priv, port, mib->offset, mib->length, + rtl8367c_mib_counter_read(priv, port, mib->offset, mib->length, &phy_stats->SymbolErrorDuringCarrier); mutex_unlock(&mb->mib_lock); } -static void rtl8365mb_get_mac_stats(struct dsa_switch *ds, int port, +static void rtl8367c_get_mac_stats(struct dsa_switch *ds, int port, struct ethtool_eth_mac_stats *mac_stats) { - u64 cnt[RTL8365MB_MIB_END] = { - [RTL8365MB_MIB_ifOutOctets] = 1, - [RTL8365MB_MIB_ifOutUcastPkts] = 1, - [RTL8365MB_MIB_ifOutMulticastPkts] = 1, - [RTL8365MB_MIB_ifOutBroadcastPkts] = 1, - [RTL8365MB_MIB_dot3OutPauseFrames] = 1, - [RTL8365MB_MIB_ifOutDiscards] = 1, - [RTL8365MB_MIB_ifInOctets] = 1, - [RTL8365MB_MIB_ifInUcastPkts] = 1, - [RTL8365MB_MIB_ifInMulticastPkts] = 1, - [RTL8365MB_MIB_ifInBroadcastPkts] = 1, - [RTL8365MB_MIB_dot3InPauseFrames] = 1, - [RTL8365MB_MIB_dot3StatsSingleCollisionFrames] = 1, - [RTL8365MB_MIB_dot3StatsMultipleCollisionFrames] = 1, - [RTL8365MB_MIB_dot3StatsFCSErrors] = 1, - [RTL8365MB_MIB_dot3StatsDeferredTransmissions] = 1, - [RTL8365MB_MIB_dot3StatsLateCollisions] = 1, - [RTL8365MB_MIB_dot3StatsExcessiveCollisions] = 1, + u64 cnt[RTL8367C_MIB_END] = { + [RTL8367C_MIB_ifOutOctets] = 1, + [RTL8367C_MIB_ifOutUcastPkts] = 1, + [RTL8367C_MIB_ifOutMulticastPkts] = 1, + [RTL8367C_MIB_ifOutBroadcastPkts] = 1, + [RTL8367C_MIB_dot3OutPauseFrames] = 1, + [RTL8367C_MIB_ifOutDiscards] = 1, + [RTL8367C_MIB_ifInOctets] = 1, + [RTL8367C_MIB_ifInUcastPkts] = 1, + [RTL8367C_MIB_ifInMulticastPkts] = 1, + [RTL8367C_MIB_ifInBroadcastPkts] = 1, + [RTL8367C_MIB_dot3InPauseFrames] = 1, + [RTL8367C_MIB_dot3StatsSingleCollisionFrames] = 1, + [RTL8367C_MIB_dot3StatsMultipleCollisionFrames] = 1, + [RTL8367C_MIB_dot3StatsFCSErrors] = 1, + [RTL8367C_MIB_dot3StatsDeferredTransmissions] = 1, + [RTL8367C_MIB_dot3StatsLateCollisions] = 1, + [RTL8367C_MIB_dot3StatsExcessiveCollisions] = 1, }; struct realtek_priv *priv = ds->priv; - struct rtl8365mb *mb; + struct rtl8367c *mb; int ret; int i; mb = priv->chip_data; mutex_lock(&mb->mib_lock); - for (i = 0; i < RTL8365MB_MIB_END; i++) { - struct rtl8365mb_mib_counter *mib = &rtl8365mb_mib_counters[i]; + for (i = 0; i < RTL8367C_MIB_END; i++) { + struct rtl8367c_mib_counter *mib = &rtl8367c_mib_counters[i]; /* Only fetch required MIB counters (marked = 1 above) */ if (!cnt[i]) continue; - ret = rtl8365mb_mib_counter_read(priv, port, mib->offset, + ret = rtl8367c_mib_counter_read(priv, port, mib->offset, mib->length, &cnt[i]); if (ret) break; @@ -1256,76 +1245,76 @@ static void rtl8365mb_get_mac_stats(struct dsa_switch *ds, int port, * subject. */ - mac_stats->FramesTransmittedOK = cnt[RTL8365MB_MIB_ifOutUcastPkts] + - cnt[RTL8365MB_MIB_ifOutMulticastPkts] + - cnt[RTL8365MB_MIB_ifOutBroadcastPkts] + - cnt[RTL8365MB_MIB_dot3OutPauseFrames] - - cnt[RTL8365MB_MIB_ifOutDiscards]; + mac_stats->FramesTransmittedOK = cnt[RTL8367C_MIB_ifOutUcastPkts] + + cnt[RTL8367C_MIB_ifOutMulticastPkts] + + cnt[RTL8367C_MIB_ifOutBroadcastPkts] + + cnt[RTL8367C_MIB_dot3OutPauseFrames] - + cnt[RTL8367C_MIB_ifOutDiscards]; mac_stats->SingleCollisionFrames = - cnt[RTL8365MB_MIB_dot3StatsSingleCollisionFrames]; + cnt[RTL8367C_MIB_dot3StatsSingleCollisionFrames]; mac_stats->MultipleCollisionFrames = - cnt[RTL8365MB_MIB_dot3StatsMultipleCollisionFrames]; - mac_stats->FramesReceivedOK = cnt[RTL8365MB_MIB_ifInUcastPkts] + - cnt[RTL8365MB_MIB_ifInMulticastPkts] + - cnt[RTL8365MB_MIB_ifInBroadcastPkts] + - cnt[RTL8365MB_MIB_dot3InPauseFrames]; + cnt[RTL8367C_MIB_dot3StatsMultipleCollisionFrames]; + mac_stats->FramesReceivedOK = cnt[RTL8367C_MIB_ifInUcastPkts] + + cnt[RTL8367C_MIB_ifInMulticastPkts] + + cnt[RTL8367C_MIB_ifInBroadcastPkts] + + cnt[RTL8367C_MIB_dot3InPauseFrames]; mac_stats->FrameCheckSequenceErrors = - cnt[RTL8365MB_MIB_dot3StatsFCSErrors]; - mac_stats->OctetsTransmittedOK = cnt[RTL8365MB_MIB_ifOutOctets] - + cnt[RTL8367C_MIB_dot3StatsFCSErrors]; + mac_stats->OctetsTransmittedOK = cnt[RTL8367C_MIB_ifOutOctets] - 18 * mac_stats->FramesTransmittedOK; mac_stats->FramesWithDeferredXmissions = - cnt[RTL8365MB_MIB_dot3StatsDeferredTransmissions]; - mac_stats->LateCollisions = cnt[RTL8365MB_MIB_dot3StatsLateCollisions]; + cnt[RTL8367C_MIB_dot3StatsDeferredTransmissions]; + mac_stats->LateCollisions = cnt[RTL8367C_MIB_dot3StatsLateCollisions]; mac_stats->FramesAbortedDueToXSColls = - cnt[RTL8365MB_MIB_dot3StatsExcessiveCollisions]; - mac_stats->OctetsReceivedOK = cnt[RTL8365MB_MIB_ifInOctets] - + cnt[RTL8367C_MIB_dot3StatsExcessiveCollisions]; + mac_stats->OctetsReceivedOK = cnt[RTL8367C_MIB_ifInOctets] - 18 * mac_stats->FramesReceivedOK; mac_stats->MulticastFramesXmittedOK = - cnt[RTL8365MB_MIB_ifOutMulticastPkts]; + cnt[RTL8367C_MIB_ifOutMulticastPkts]; mac_stats->BroadcastFramesXmittedOK = - cnt[RTL8365MB_MIB_ifOutBroadcastPkts]; + cnt[RTL8367C_MIB_ifOutBroadcastPkts]; mac_stats->MulticastFramesReceivedOK = - cnt[RTL8365MB_MIB_ifInMulticastPkts]; + cnt[RTL8367C_MIB_ifInMulticastPkts]; mac_stats->BroadcastFramesReceivedOK = - cnt[RTL8365MB_MIB_ifInBroadcastPkts]; + cnt[RTL8367C_MIB_ifInBroadcastPkts]; } -static void rtl8365mb_get_ctrl_stats(struct dsa_switch *ds, int port, +static void rtl8367c_get_ctrl_stats(struct dsa_switch *ds, int port, struct ethtool_eth_ctrl_stats *ctrl_stats) { struct realtek_priv *priv = ds->priv; - struct rtl8365mb_mib_counter *mib; - struct rtl8365mb *mb; + struct rtl8367c_mib_counter *mib; + struct rtl8367c *mb; mb = priv->chip_data; - mib = &rtl8365mb_mib_counters[RTL8365MB_MIB_dot3ControlInUnknownOpcodes]; + mib = &rtl8367c_mib_counters[RTL8367C_MIB_dot3ControlInUnknownOpcodes]; mutex_lock(&mb->mib_lock); - rtl8365mb_mib_counter_read(priv, port, mib->offset, mib->length, + rtl8367c_mib_counter_read(priv, port, mib->offset, mib->length, &ctrl_stats->UnsupportedOpcodesReceived); mutex_unlock(&mb->mib_lock); } -static void rtl8365mb_stats_update(struct realtek_priv *priv, int port) +static void rtl8367c_stats_update(struct realtek_priv *priv, int port) { - u64 cnt[RTL8365MB_MIB_END] = { - [RTL8365MB_MIB_ifOutOctets] = 1, - [RTL8365MB_MIB_ifOutUcastPkts] = 1, - [RTL8365MB_MIB_ifOutMulticastPkts] = 1, - [RTL8365MB_MIB_ifOutBroadcastPkts] = 1, - [RTL8365MB_MIB_ifOutDiscards] = 1, - [RTL8365MB_MIB_ifInOctets] = 1, - [RTL8365MB_MIB_ifInUcastPkts] = 1, - [RTL8365MB_MIB_ifInMulticastPkts] = 1, - [RTL8365MB_MIB_ifInBroadcastPkts] = 1, - [RTL8365MB_MIB_etherStatsDropEvents] = 1, - [RTL8365MB_MIB_etherStatsCollisions] = 1, - [RTL8365MB_MIB_etherStatsFragments] = 1, - [RTL8365MB_MIB_etherStatsJabbers] = 1, - [RTL8365MB_MIB_dot3StatsFCSErrors] = 1, - [RTL8365MB_MIB_dot3StatsLateCollisions] = 1, + u64 cnt[RTL8367C_MIB_END] = { + [RTL8367C_MIB_ifOutOctets] = 1, + [RTL8367C_MIB_ifOutUcastPkts] = 1, + [RTL8367C_MIB_ifOutMulticastPkts] = 1, + [RTL8367C_MIB_ifOutBroadcastPkts] = 1, + [RTL8367C_MIB_ifOutDiscards] = 1, + [RTL8367C_MIB_ifInOctets] = 1, + [RTL8367C_MIB_ifInUcastPkts] = 1, + [RTL8367C_MIB_ifInMulticastPkts] = 1, + [RTL8367C_MIB_ifInBroadcastPkts] = 1, + [RTL8367C_MIB_etherStatsDropEvents] = 1, + [RTL8367C_MIB_etherStatsCollisions] = 1, + [RTL8367C_MIB_etherStatsFragments] = 1, + [RTL8367C_MIB_etherStatsJabbers] = 1, + [RTL8367C_MIB_dot3StatsFCSErrors] = 1, + [RTL8367C_MIB_dot3StatsLateCollisions] = 1, }; - struct rtl8365mb *mb = priv->chip_data; + struct rtl8367c *mb = priv->chip_data; struct rtnl_link_stats64 *stats; int ret; int i; @@ -1333,14 +1322,14 @@ static void rtl8365mb_stats_update(struct realtek_priv *priv, int port) stats = &mb->ports[port].stats; mutex_lock(&mb->mib_lock); - for (i = 0; i < RTL8365MB_MIB_END; i++) { - struct rtl8365mb_mib_counter *c = &rtl8365mb_mib_counters[i]; + for (i = 0; i < RTL8367C_MIB_END; i++) { + struct rtl8367c_mib_counter *c = &rtl8367c_mib_counters[i]; /* Only fetch required MIB counters (marked = 1 above) */ if (!cnt[i]) continue; - ret = rtl8365mb_mib_counter_read(priv, port, c->offset, + ret = rtl8367c_mib_counter_read(priv, port, c->offset, c->length, &cnt[i]); if (ret) break; @@ -1353,56 +1342,56 @@ static void rtl8365mb_stats_update(struct realtek_priv *priv, int port) spin_lock(&mb->ports[port].stats_lock); - stats->rx_packets = cnt[RTL8365MB_MIB_ifInUcastPkts] + - cnt[RTL8365MB_MIB_ifInMulticastPkts] + - cnt[RTL8365MB_MIB_ifInBroadcastPkts] - - cnt[RTL8365MB_MIB_ifOutDiscards]; + stats->rx_packets = cnt[RTL8367C_MIB_ifInUcastPkts] + + cnt[RTL8367C_MIB_ifInMulticastPkts] + + cnt[RTL8367C_MIB_ifInBroadcastPkts] - + cnt[RTL8367C_MIB_ifOutDiscards]; - stats->tx_packets = cnt[RTL8365MB_MIB_ifOutUcastPkts] + - cnt[RTL8365MB_MIB_ifOutMulticastPkts] + - cnt[RTL8365MB_MIB_ifOutBroadcastPkts]; + stats->tx_packets = cnt[RTL8367C_MIB_ifOutUcastPkts] + + cnt[RTL8367C_MIB_ifOutMulticastPkts] + + cnt[RTL8367C_MIB_ifOutBroadcastPkts]; /* if{In,Out}Octets includes FCS - remove it */ - stats->rx_bytes = cnt[RTL8365MB_MIB_ifInOctets] - 4 * stats->rx_packets; + stats->rx_bytes = cnt[RTL8367C_MIB_ifInOctets] - 4 * stats->rx_packets; stats->tx_bytes = - cnt[RTL8365MB_MIB_ifOutOctets] - 4 * stats->tx_packets; + cnt[RTL8367C_MIB_ifOutOctets] - 4 * stats->tx_packets; - stats->rx_dropped = cnt[RTL8365MB_MIB_etherStatsDropEvents]; - stats->tx_dropped = cnt[RTL8365MB_MIB_ifOutDiscards]; + stats->rx_dropped = cnt[RTL8367C_MIB_etherStatsDropEvents]; + stats->tx_dropped = cnt[RTL8367C_MIB_ifOutDiscards]; - stats->multicast = cnt[RTL8365MB_MIB_ifInMulticastPkts]; - stats->collisions = cnt[RTL8365MB_MIB_etherStatsCollisions]; + stats->multicast = cnt[RTL8367C_MIB_ifInMulticastPkts]; + stats->collisions = cnt[RTL8367C_MIB_etherStatsCollisions]; - stats->rx_length_errors = cnt[RTL8365MB_MIB_etherStatsFragments] + - cnt[RTL8365MB_MIB_etherStatsJabbers]; - stats->rx_crc_errors = cnt[RTL8365MB_MIB_dot3StatsFCSErrors]; + stats->rx_length_errors = cnt[RTL8367C_MIB_etherStatsFragments] + + cnt[RTL8367C_MIB_etherStatsJabbers]; + stats->rx_crc_errors = cnt[RTL8367C_MIB_dot3StatsFCSErrors]; stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors; - stats->tx_aborted_errors = cnt[RTL8365MB_MIB_ifOutDiscards]; - stats->tx_window_errors = cnt[RTL8365MB_MIB_dot3StatsLateCollisions]; + stats->tx_aborted_errors = cnt[RTL8367C_MIB_ifOutDiscards]; + stats->tx_window_errors = cnt[RTL8367C_MIB_dot3StatsLateCollisions]; stats->tx_errors = stats->tx_aborted_errors + stats->tx_window_errors; spin_unlock(&mb->ports[port].stats_lock); } -static void rtl8365mb_stats_poll(struct work_struct *work) +static void rtl8367c_stats_poll(struct work_struct *work) { - struct rtl8365mb_port *p = container_of(to_delayed_work(work), - struct rtl8365mb_port, + struct rtl8367c_port *p = container_of(to_delayed_work(work), + struct rtl8367c_port, mib_work); struct realtek_priv *priv = p->priv; - rtl8365mb_stats_update(priv, p->index); + rtl8367c_stats_update(priv, p->index); - schedule_delayed_work(&p->mib_work, RTL8365MB_STATS_INTERVAL_JIFFIES); + schedule_delayed_work(&p->mib_work, RTL8367C_STATS_INTERVAL_JIFFIES); } -static void rtl8365mb_get_stats64(struct dsa_switch *ds, int port, +static void rtl8367c_get_stats64(struct dsa_switch *ds, int port, struct rtnl_link_stats64 *s) { struct realtek_priv *priv = ds->priv; - struct rtl8365mb_port *p; - struct rtl8365mb *mb; + struct rtl8367c_port *p; + struct rtl8367c *mb; mb = priv->chip_data; p = &mb->ports[port]; @@ -1412,9 +1401,9 @@ static void rtl8365mb_get_stats64(struct dsa_switch *ds, int port, spin_unlock(&p->stats_lock); } -static void rtl8365mb_stats_setup(struct realtek_priv *priv) +static void rtl8367c_stats_setup(struct realtek_priv *priv) { - struct rtl8365mb *mb = priv->chip_data; + struct rtl8367c *mb = priv->chip_data; int i; /* Per-chip global mutex to protect MIB counter access, since doing @@ -1423,7 +1412,7 @@ static void rtl8365mb_stats_setup(struct realtek_priv *priv) mutex_init(&mb->mib_lock); for (i = 0; i < priv->num_ports; i++) { - struct rtl8365mb_port *p = &mb->ports[i]; + struct rtl8367c_port *p = &mb->ports[i]; if (dsa_is_unused_port(priv->ds, i)) continue; @@ -1434,17 +1423,17 @@ static void rtl8365mb_stats_setup(struct realtek_priv *priv) /* This work polls the MIB counters and keeps the stats64 data * up-to-date. */ - INIT_DELAYED_WORK(&p->mib_work, rtl8365mb_stats_poll); + INIT_DELAYED_WORK(&p->mib_work, rtl8367c_stats_poll); } } -static void rtl8365mb_stats_teardown(struct realtek_priv *priv) +static void rtl8367c_stats_teardown(struct realtek_priv *priv) { - struct rtl8365mb *mb = priv->chip_data; + struct rtl8367c *mb = priv->chip_data; int i; for (i = 0; i < priv->num_ports; i++) { - struct rtl8365mb_port *p = &mb->ports[i]; + struct rtl8367c_port *p = &mb->ports[i]; if (dsa_is_unused_port(priv->ds, i)) continue; @@ -1453,7 +1442,7 @@ static void rtl8365mb_stats_teardown(struct realtek_priv *priv) } } -static int rtl8365mb_get_and_clear_status_reg(struct realtek_priv *priv, u32 reg, +static int rtl8367c_get_and_clear_status_reg(struct realtek_priv *priv, u32 reg, u32 *val) { int ret; @@ -1465,40 +1454,40 @@ static int rtl8365mb_get_and_clear_status_reg(struct realtek_priv *priv, u32 reg return regmap_write(priv->map, reg, *val); } -static irqreturn_t rtl8365mb_irq(int irq, void *data) +static irqreturn_t rtl8367c_irq(int irq, void *data) { struct realtek_priv *priv = data; unsigned long line_changes = 0; - struct rtl8365mb *mb; + struct rtl8367c *mb; u32 stat; int line; int ret; mb = priv->chip_data; - ret = rtl8365mb_get_and_clear_status_reg(priv, RTL8365MB_INTR_STATUS_REG, + ret = rtl8367c_get_and_clear_status_reg(priv, RTL8367C_INTR_STATUS_REG, &stat); if (ret) goto out_error; - if (stat & RTL8365MB_INTR_LINK_CHANGE_MASK) { + if (stat & RTL8367C_INTR_LINK_CHANGE_MASK) { u32 linkdown_ind; u32 linkup_ind; u32 val; - ret = rtl8365mb_get_and_clear_status_reg( - priv, RTL8365MB_PORT_LINKUP_IND_REG, &val); + ret = rtl8367c_get_and_clear_status_reg( + priv, RTL8367C_PORT_LINKUP_IND_REG, &val); if (ret) goto out_error; - linkup_ind = FIELD_GET(RTL8365MB_PORT_LINKUP_IND_MASK, val); + linkup_ind = FIELD_GET(RTL8367C_PORT_LINKUP_IND_MASK, val); - ret = rtl8365mb_get_and_clear_status_reg( - priv, RTL8365MB_PORT_LINKDOWN_IND_REG, &val); + ret = rtl8367c_get_and_clear_status_reg( + priv, RTL8367C_PORT_LINKDOWN_IND_REG, &val); if (ret) goto out_error; - linkdown_ind = FIELD_GET(RTL8365MB_PORT_LINKDOWN_IND_MASK, val); + linkdown_ind = FIELD_GET(RTL8367C_PORT_LINKDOWN_IND_MASK, val); line_changes = (linkup_ind | linkdown_ind) & mb->port_mask; } @@ -1521,56 +1510,56 @@ static irqreturn_t rtl8365mb_irq(int irq, void *data) return IRQ_NONE; } -static struct irq_chip rtl8365mb_irq_chip = { - .name = "rtl8365mb", +static struct irq_chip rtl8367c_irq_chip = { + .name = "rtl8367c", /* The hardware doesn't support masking IRQs on a per-port basis */ }; -static int rtl8365mb_irq_map(struct irq_domain *domain, unsigned int irq, +static int rtl8367c_irq_map(struct irq_domain *domain, unsigned int irq, irq_hw_number_t hwirq) { irq_set_chip_data(irq, domain->host_data); - irq_set_chip_and_handler(irq, &rtl8365mb_irq_chip, handle_simple_irq); + irq_set_chip_and_handler(irq, &rtl8367c_irq_chip, handle_simple_irq); irq_set_nested_thread(irq, 1); irq_set_noprobe(irq); return 0; } -static void rtl8365mb_irq_unmap(struct irq_domain *d, unsigned int irq) +static void rtl8367c_irq_unmap(struct irq_domain *d, unsigned int irq) { irq_set_nested_thread(irq, 0); irq_set_chip_and_handler(irq, NULL, NULL); irq_set_chip_data(irq, NULL); } -static const struct irq_domain_ops rtl8365mb_irqdomain_ops = { - .map = rtl8365mb_irq_map, - .unmap = rtl8365mb_irq_unmap, +static const struct irq_domain_ops rtl8367c_irqdomain_ops = { + .map = rtl8367c_irq_map, + .unmap = rtl8367c_irq_unmap, .xlate = irq_domain_xlate_onecell, }; -static int rtl8365mb_set_irq_enable(struct realtek_priv *priv, bool enable) +static int rtl8367c_set_irq_enable(struct realtek_priv *priv, bool enable) { - return regmap_update_bits(priv->map, RTL8365MB_INTR_CTRL_REG, - RTL8365MB_INTR_LINK_CHANGE_MASK, - FIELD_PREP(RTL8365MB_INTR_LINK_CHANGE_MASK, + return regmap_update_bits(priv->map, RTL8367C_INTR_CTRL_REG, + RTL8367C_INTR_LINK_CHANGE_MASK, + FIELD_PREP(RTL8367C_INTR_LINK_CHANGE_MASK, enable ? 1 : 0)); } -static int rtl8365mb_irq_enable(struct realtek_priv *priv) +static int rtl8367c_irq_enable(struct realtek_priv *priv) { - return rtl8365mb_set_irq_enable(priv, true); + return rtl8367c_set_irq_enable(priv, true); } -static int rtl8365mb_irq_disable(struct realtek_priv *priv) +static int rtl8367c_irq_disable(struct realtek_priv *priv) { - return rtl8365mb_set_irq_enable(priv, false); + return rtl8367c_set_irq_enable(priv, false); } -static int rtl8365mb_irq_setup(struct realtek_priv *priv) +static int rtl8367c_irq_setup(struct realtek_priv *priv) { - struct rtl8365mb *mb = priv->chip_data; + struct rtl8367c *mb = priv->chip_data; struct device_node *intc; u32 irq_trig; int virq; @@ -1585,7 +1574,7 @@ static int rtl8365mb_irq_setup(struct realtek_priv *priv) return -EINVAL; } - /* rtl8365mb IRQs cascade off this one */ + /* rtl8367c IRQs cascade off this one */ irq = of_irq_get(intc, 0); if (irq <= 0) { if (irq != -EPROBE_DEFER) @@ -1596,7 +1585,7 @@ static int rtl8365mb_irq_setup(struct realtek_priv *priv) } priv->irqdomain = irq_domain_add_linear(intc, priv->num_ports, - &rtl8365mb_irqdomain_ops, priv); + &rtl8367c_irqdomain_ops, priv); if (!priv->irqdomain) { dev_err(priv->dev, "failed to add irq domain\n"); ret = -ENOMEM; @@ -1620,11 +1609,11 @@ static int rtl8365mb_irq_setup(struct realtek_priv *priv) switch (irq_trig) { case IRQF_TRIGGER_RISING: case IRQF_TRIGGER_HIGH: - val = RTL8365MB_INTR_POLARITY_HIGH; + val = RTL8367C_INTR_POLARITY_HIGH; break; case IRQF_TRIGGER_FALLING: case IRQF_TRIGGER_LOW: - val = RTL8365MB_INTR_POLARITY_LOW; + val = RTL8367C_INTR_POLARITY_LOW; break; default: dev_err(priv->dev, "unsupported irq trigger type %u\n", @@ -1633,25 +1622,25 @@ static int rtl8365mb_irq_setup(struct realtek_priv *priv) goto out_remove_irqdomain; } - ret = regmap_update_bits(priv->map, RTL8365MB_INTR_POLARITY_REG, - RTL8365MB_INTR_POLARITY_MASK, - FIELD_PREP(RTL8365MB_INTR_POLARITY_MASK, val)); + ret = regmap_update_bits(priv->map, RTL8367C_INTR_POLARITY_REG, + RTL8367C_INTR_POLARITY_MASK, + FIELD_PREP(RTL8367C_INTR_POLARITY_MASK, val)); if (ret) goto out_remove_irqdomain; /* Disable the interrupt in case the chip has it enabled on reset */ - ret = rtl8365mb_irq_disable(priv); + ret = rtl8367c_irq_disable(priv); if (ret) goto out_remove_irqdomain; /* Clear the interrupt status register */ - ret = regmap_write(priv->map, RTL8365MB_INTR_STATUS_REG, - RTL8365MB_INTR_ALL_MASK); + ret = regmap_write(priv->map, RTL8367C_INTR_STATUS_REG, + RTL8367C_INTR_ALL_MASK); if (ret) goto out_remove_irqdomain; - ret = request_threaded_irq(irq, NULL, rtl8365mb_irq, IRQF_ONESHOT, - "rtl8365mb", priv); + ret = request_threaded_irq(irq, NULL, rtl8367c_irq, IRQF_ONESHOT, + "rtl8367c", priv); if (ret) { dev_err(priv->dev, "failed to request irq: %d\n", ret); goto out_remove_irqdomain; @@ -1660,7 +1649,7 @@ static int rtl8365mb_irq_setup(struct realtek_priv *priv) /* Store the irq so that we know to free it during teardown */ mb->irq = irq; - ret = rtl8365mb_irq_enable(priv); + ret = rtl8367c_irq_enable(priv); if (ret) goto out_free_irq; @@ -1687,9 +1676,9 @@ static int rtl8365mb_irq_setup(struct realtek_priv *priv) return ret; } -static void rtl8365mb_irq_teardown(struct realtek_priv *priv) +static void rtl8367c_irq_teardown(struct realtek_priv *priv) { - struct rtl8365mb *mb = priv->chip_data; + struct rtl8367c *mb = priv->chip_data; int virq; int i; @@ -1709,38 +1698,38 @@ static void rtl8365mb_irq_teardown(struct realtek_priv *priv) } } -static int rtl8365mb_cpu_config(struct realtek_priv *priv) +static int rtl8367c_cpu_config(struct realtek_priv *priv) { - struct rtl8365mb *mb = priv->chip_data; - struct rtl8365mb_cpu *cpu = &mb->cpu; + struct rtl8367c *mb = priv->chip_data; + struct rtl8367c_cpu *cpu = &mb->cpu; u32 val; int ret; - ret = regmap_update_bits(priv->map, RTL8365MB_CPU_PORT_MASK_REG, - RTL8365MB_CPU_PORT_MASK_MASK, - FIELD_PREP(RTL8365MB_CPU_PORT_MASK_MASK, + ret = regmap_update_bits(priv->map, RTL8367C_CPU_PORT_MASK_REG, + RTL8367C_CPU_PORT_MASK_MASK, + FIELD_PREP(RTL8367C_CPU_PORT_MASK_MASK, cpu->mask)); if (ret) return ret; - val = FIELD_PREP(RTL8365MB_CPU_CTRL_EN_MASK, cpu->enable ? 1 : 0) | - FIELD_PREP(RTL8365MB_CPU_CTRL_INSERTMODE_MASK, cpu->insert) | - FIELD_PREP(RTL8365MB_CPU_CTRL_TAG_POSITION_MASK, cpu->position) | - FIELD_PREP(RTL8365MB_CPU_CTRL_RXBYTECOUNT_MASK, cpu->rx_length) | - FIELD_PREP(RTL8365MB_CPU_CTRL_TAG_FORMAT_MASK, cpu->format) | - FIELD_PREP(RTL8365MB_CPU_CTRL_TRAP_PORT_MASK, cpu->trap_port) | - FIELD_PREP(RTL8365MB_CPU_CTRL_TRAP_PORT_EXT_MASK, + val = FIELD_PREP(RTL8367C_CPU_CTRL_EN_MASK, cpu->enable ? 1 : 0) | + FIELD_PREP(RTL8367C_CPU_CTRL_INSERTMODE_MASK, cpu->insert) | + FIELD_PREP(RTL8367C_CPU_CTRL_TAG_POSITION_MASK, cpu->position) | + FIELD_PREP(RTL8367C_CPU_CTRL_RXBYTECOUNT_MASK, cpu->rx_length) | + FIELD_PREP(RTL8367C_CPU_CTRL_TAG_FORMAT_MASK, cpu->format) | + FIELD_PREP(RTL8367C_CPU_CTRL_TRAP_PORT_MASK, cpu->trap_port) | + FIELD_PREP(RTL8367C_CPU_CTRL_TRAP_PORT_EXT_MASK, cpu->trap_port >> 3); - ret = regmap_write(priv->map, RTL8365MB_CPU_CTRL_REG, val); + ret = regmap_write(priv->map, RTL8367C_CPU_CTRL_REG, val); if (ret) return ret; return 0; } -static int rtl8365mb_switch_init(struct realtek_priv *priv) +static int rtl8367c_switch_init(struct realtek_priv *priv) { - struct rtl8365mb *mb = priv->chip_data; + struct rtl8367c *mb = priv->chip_data; int ret; int i; @@ -1755,9 +1744,9 @@ static int rtl8365mb_switch_init(struct realtek_priv *priv) } /* Common init jam */ - for (i = 0; i < ARRAY_SIZE(rtl8365mb_init_jam_common); i++) { - ret = regmap_write(priv->map, rtl8365mb_init_jam_common[i].reg, - rtl8365mb_init_jam_common[i].val); + for (i = 0; i < ARRAY_SIZE(rtl8367c_init_jam_common); i++) { + ret = regmap_write(priv->map, rtl8367c_init_jam_common[i].reg, + rtl8367c_init_jam_common[i].val); if (ret) return ret; } @@ -1765,60 +1754,60 @@ static int rtl8365mb_switch_init(struct realtek_priv *priv) return 0; } -static int rtl8365mb_reset_chip(struct realtek_priv *priv) +static int rtl8367c_reset_chip(struct realtek_priv *priv) { u32 val; - priv->write_reg_noack(priv, RTL8365MB_CHIP_RESET_REG, - FIELD_PREP(RTL8365MB_CHIP_RESET_HW_MASK, + priv->write_reg_noack(priv, RTL8367C_CHIP_RESET_REG, + FIELD_PREP(RTL8367C_CHIP_RESET_HW_MASK, 1)); /* Realtek documentation says the chip needs 1 second to reset. Sleep * for 100 ms before accessing any registers to prevent ACK timeouts. */ msleep(100); - return regmap_read_poll_timeout(priv->map, RTL8365MB_CHIP_RESET_REG, val, - !(val & RTL8365MB_CHIP_RESET_HW_MASK), + return regmap_read_poll_timeout(priv->map, RTL8367C_CHIP_RESET_REG, val, + !(val & RTL8367C_CHIP_RESET_HW_MASK), 20000, 1e6); } -static int rtl8365mb_setup(struct dsa_switch *ds) +static int rtl8367c_setup(struct dsa_switch *ds) { struct realtek_priv *priv = ds->priv; - struct rtl8365mb *mb; + struct rtl8367c *mb; int ret; int i; mb = priv->chip_data; - ret = rtl8365mb_reset_chip(priv); + ret = rtl8367c_reset_chip(priv); if (ret) { dev_err(priv->dev, "failed to reset chip: %d\n", ret); goto out_error; } /* Configure switch to vendor-defined initial state */ - ret = rtl8365mb_switch_init(priv); + ret = rtl8367c_switch_init(priv); if (ret) { dev_err(priv->dev, "failed to initialize switch: %d\n", ret); goto out_error; } /* Set up cascading IRQs */ - ret = rtl8365mb_irq_setup(priv); + ret = rtl8367c_irq_setup(priv); if (ret == -EPROBE_DEFER) return ret; else if (ret) dev_info(priv->dev, "no interrupt support\n"); /* Configure CPU tagging */ - ret = rtl8365mb_cpu_config(priv); + ret = rtl8367c_cpu_config(priv); if (ret) goto out_teardown_irq; /* Configure ports */ for (i = 0; i < priv->num_ports; i++) { - struct rtl8365mb_port *p = &mb->ports[i]; + struct rtl8367c_port *p = &mb->ports[i]; if (dsa_is_unused_port(priv->ds, i)) continue; @@ -1828,12 +1817,12 @@ static int rtl8365mb_setup(struct dsa_switch *ds) p->index = i; /* Forward only to the CPU */ - ret = rtl8365mb_port_set_isolation(priv, i, BIT(priv->cpu_port)); + ret = rtl8367c_port_set_isolation(priv, i, BIT(priv->cpu_port)); if (ret) goto out_teardown_irq; /* Disable learning */ - ret = rtl8365mb_port_set_learning(priv, i, false); + ret = rtl8367c_port_set_learning(priv, i, false); if (ret) goto out_teardown_irq; @@ -1841,13 +1830,13 @@ static int rtl8365mb_setup(struct dsa_switch *ds) * ports will still forward frames to the CPU despite being * administratively down by default. */ - rtl8365mb_port_stp_state_set(priv->ds, i, BR_STATE_DISABLED); + rtl8367c_port_stp_state_set(priv->ds, i, BR_STATE_DISABLED); } /* Set maximum packet length to 1536 bytes */ - ret = regmap_update_bits(priv->map, RTL8365MB_CFG0_MAX_LEN_REG, - RTL8365MB_CFG0_MAX_LEN_MASK, - FIELD_PREP(RTL8365MB_CFG0_MAX_LEN_MASK, 1536)); + ret = regmap_update_bits(priv->map, RTL8367C_CFG0_MAX_LEN_REG, + RTL8367C_CFG0_MAX_LEN_MASK, + FIELD_PREP(RTL8367C_CFG0_MAX_LEN_MASK, 1536)); if (ret) goto out_teardown_irq; @@ -1860,60 +1849,60 @@ static int rtl8365mb_setup(struct dsa_switch *ds) } /* Start statistics counter polling */ - rtl8365mb_stats_setup(priv); + rtl8367c_stats_setup(priv); return 0; out_teardown_irq: - rtl8365mb_irq_teardown(priv); + rtl8367c_irq_teardown(priv); out_error: return ret; } -static void rtl8365mb_teardown(struct dsa_switch *ds) +static void rtl8367c_teardown(struct dsa_switch *ds) { struct realtek_priv *priv = ds->priv; - rtl8365mb_stats_teardown(priv); - rtl8365mb_irq_teardown(priv); + rtl8367c_stats_teardown(priv); + rtl8367c_irq_teardown(priv); } -static int rtl8365mb_get_chip_id_and_ver(struct regmap *map, u32 *id, u32 *ver) +static int rtl8367c_get_chip_id_and_ver(struct regmap *map, u32 *id, u32 *ver) { int ret; /* For some reason we have to write a magic value to an arbitrary * register whenever accessing the chip ID/version registers. */ - ret = regmap_write(map, RTL8365MB_MAGIC_REG, RTL8365MB_MAGIC_VALUE); + ret = regmap_write(map, RTL8367C_MAGIC_REG, RTL8367C_MAGIC_VALUE); if (ret) return ret; - ret = regmap_read(map, RTL8365MB_CHIP_ID_REG, id); + ret = regmap_read(map, RTL8367C_CHIP_ID_REG, id); if (ret) return ret; - ret = regmap_read(map, RTL8365MB_CHIP_VER_REG, ver); + ret = regmap_read(map, RTL8367C_CHIP_VER_REG, ver); if (ret) return ret; /* Reset magic register */ - ret = regmap_write(map, RTL8365MB_MAGIC_REG, 0); + ret = regmap_write(map, RTL8367C_MAGIC_REG, 0); if (ret) return ret; return 0; } -static int rtl8365mb_detect(struct realtek_priv *priv) +static int rtl8367c_detect(struct realtek_priv *priv) { - struct rtl8365mb *mb = priv->chip_data; + struct rtl8367c *mb = priv->chip_data; u32 chip_id; u32 chip_ver; int ret; - ret = rtl8365mb_get_chip_id_and_ver(priv->map, &chip_id, &chip_ver); + ret = rtl8367c_get_chip_id_and_ver(priv->map, &chip_id, &chip_ver); if (ret) { dev_err(priv->dev, "failed to read chip id and version: %d\n", ret); @@ -1921,29 +1910,29 @@ static int rtl8365mb_detect(struct realtek_priv *priv) } switch (chip_id) { - case RTL8365MB_CHIP_ID_8365MB_VC: + case RTL8367C_CHIP_ID_8365MB_VC: dev_info(priv->dev, - "found an RTL8365MB-VC switch (ver=0x%04x)\n", - chip_ver); + "found an RTL8365MB-VC switch (ver=0x%04x)\n", + chip_ver); - priv->cpu_port = RTL8365MB_CPU_PORT_NUM_8365MB_VC; + priv->cpu_port = RTL8367C_CPU_PORT_NUM_8365MB_VC; priv->num_ports = priv->cpu_port + 1; mb->priv = priv; mb->chip_id = chip_id; mb->chip_ver = chip_ver; mb->port_mask = BIT(priv->num_ports) - 1; - mb->learn_limit_max = RTL8365MB_LEARN_LIMIT_MAX_8365MB_VC; - mb->jam_table = rtl8365mb_init_jam_8365mb_vc; - mb->jam_size = ARRAY_SIZE(rtl8365mb_init_jam_8365mb_vc); + mb->learn_limit_max = RTL8367C_LEARN_LIMIT_MAX; + mb->jam_table = rtl8367c_init_jam_8367c; + mb->jam_size = ARRAY_SIZE(rtl8367c_init_jam_8367c); mb->cpu.enable = 1; mb->cpu.mask = BIT(priv->cpu_port); mb->cpu.trap_port = priv->cpu_port; - mb->cpu.insert = RTL8365MB_CPU_INSERT_TO_ALL; - mb->cpu.position = RTL8365MB_CPU_POS_AFTER_SA; - mb->cpu.rx_length = RTL8365MB_CPU_RXLEN_64BYTES; - mb->cpu.format = RTL8365MB_CPU_FORMAT_8BYTES; + mb->cpu.insert = RTL8367C_CPU_INSERT_TO_ALL; + mb->cpu.position = RTL8367C_CPU_POS_AFTER_SA; + mb->cpu.rx_length = RTL8367C_CPU_RXLEN_64BYTES; + mb->cpu.format = RTL8367C_CPU_FORMAT_8BYTES; break; default: @@ -1956,38 +1945,38 @@ static int rtl8365mb_detect(struct realtek_priv *priv) return 0; } -static const struct dsa_switch_ops rtl8365mb_switch_ops = { - .get_tag_protocol = rtl8365mb_get_tag_protocol, - .setup = rtl8365mb_setup, - .teardown = rtl8365mb_teardown, - .phy_read = rtl8365mb_phy_read, - .phy_write = rtl8365mb_phy_write, - .phylink_validate = rtl8365mb_phylink_validate, - .phylink_mac_config = rtl8365mb_phylink_mac_config, - .phylink_mac_link_down = rtl8365mb_phylink_mac_link_down, - .phylink_mac_link_up = rtl8365mb_phylink_mac_link_up, - .port_stp_state_set = rtl8365mb_port_stp_state_set, - .get_strings = rtl8365mb_get_strings, - .get_ethtool_stats = rtl8365mb_get_ethtool_stats, - .get_sset_count = rtl8365mb_get_sset_count, - .get_eth_phy_stats = rtl8365mb_get_phy_stats, - .get_eth_mac_stats = rtl8365mb_get_mac_stats, - .get_eth_ctrl_stats = rtl8365mb_get_ctrl_stats, - .get_stats64 = rtl8365mb_get_stats64, +static const struct dsa_switch_ops rtl8367c_switch_ops = { + .get_tag_protocol = rtl8367c_get_tag_protocol, + .setup = rtl8367c_setup, + .teardown = rtl8367c_teardown, + .phy_read = rtl8367c_phy_read, + .phy_write = rtl8367c_phy_write, + .phylink_validate = rtl8367c_phylink_validate, + .phylink_mac_config = rtl8367c_phylink_mac_config, + .phylink_mac_link_down = rtl8367c_phylink_mac_link_down, + .phylink_mac_link_up = rtl8367c_phylink_mac_link_up, + .port_stp_state_set = rtl8367c_port_stp_state_set, + .get_strings = rtl8367c_get_strings, + .get_ethtool_stats = rtl8367c_get_ethtool_stats, + .get_sset_count = rtl8367c_get_sset_count, + .get_eth_phy_stats = rtl8367c_get_phy_stats, + .get_eth_mac_stats = rtl8367c_get_mac_stats, + .get_eth_ctrl_stats = rtl8367c_get_ctrl_stats, + .get_stats64 = rtl8367c_get_stats64, }; -static const struct realtek_ops rtl8365mb_ops = { - .detect = rtl8365mb_detect, +static const struct realtek_ops rtl8367c_ops = { + .detect = rtl8367c_detect, }; -const struct realtek_variant rtl8365mb_variant = { - .ds_ops = &rtl8365mb_switch_ops, - .ops = &rtl8365mb_ops, +const struct realtek_variant rtl8367c_variant = { + .ds_ops = &rtl8367c_switch_ops, + .ops = &rtl8367c_ops, .clk_delay = 10, .cmd_read = 0xb9, .cmd_write = 0xb8, - .chip_data_sz = sizeof(struct rtl8365mb), + .chip_data_sz = sizeof(struct rtl8367c), }; -EXPORT_SYMBOL_GPL(rtl8365mb_variant); +EXPORT_SYMBOL_GPL(rtl8367c_variant); MODULE_LICENSE("GPL"); diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c index a5671ab896b3..4574782ae52e 100644 --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c @@ -1025,7 +1025,7 @@ static struct phy_driver realtek_drvs[] = { .write_page = rtl821x_write_page, }, { PHY_ID_MATCH_EXACT(0x001cc942), - .name = "RTL8365MB-VC Gigabit Ethernet", + .name = "RTL8367C Gigabit Ethernet", /* Interrupt handling analogous to RTL8366RB */ .config_intr = genphy_no_config_intr, .handle_interrupt = genphy_handle_interrupt_no_ack, From patchwork Thu Dec 16 20:13:37 2021 Content-Type: text/plain; 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[187.49.235.234]) by smtp.gmail.com with ESMTPSA id a15sm5110266qtb.5.2021.12.16.12.14.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Dec 2021 12:14:35 -0800 (PST) From: luizluca@gmail.com To: netdev@vger.kernel.org Cc: linus.walleij@linaro.org, andrew@lunn.ch, vivien.didelot@gmail.com, f.fainelli@gmail.com, olteanv@gmail.com, alsi@bang-olufsen.dk, arinc.unal@arinc9.com, Luiz Angelo Daros de Luca Subject: [PATCH net-next 08/13] net: dsa: realtek: add new mdio interface for drivers Date: Thu, 16 Dec 2021 17:13:37 -0300 Message-Id: <20211216201342.25587-9-luizluca@gmail.com> X-Mailer: git-send-email 2.34.0 In-Reply-To: <20211216201342.25587-1-luizluca@gmail.com> References: <20211216201342.25587-1-luizluca@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Luiz Angelo Daros de Luca This driver is a mdio_driver instead of a platform driver (like realtek-smi). Tested-by: Arınç ÜNAL Signed-off-by: Luiz Angelo Daros de Luca Reported-by: kernel test robot --- drivers/net/dsa/realtek/Kconfig | 11 +- drivers/net/dsa/realtek/Makefile | 1 + drivers/net/dsa/realtek/realtek-mdio.c | 284 +++++++++++++++++++++++++ drivers/net/dsa/realtek/realtek.h | 3 + 4 files changed, 297 insertions(+), 2 deletions(-) create mode 100644 drivers/net/dsa/realtek/realtek-mdio.c diff --git a/drivers/net/dsa/realtek/Kconfig b/drivers/net/dsa/realtek/Kconfig index 874574db9177..48194d0dd51f 100644 --- a/drivers/net/dsa/realtek/Kconfig +++ b/drivers/net/dsa/realtek/Kconfig @@ -9,6 +9,13 @@ menuconfig NET_DSA_REALTEK help Select to enable support for Realtek Ethernet switch chips. +config NET_DSA_REALTEK_MDIO + tristate "Realtek MDIO connected switch driver" + depends on NET_DSA_REALTEK + default y + help + Select to enable support for registering switches configured through MDIO. + config NET_DSA_REALTEK_SMI tristate "Realtek SMI connected switch driver" depends on NET_DSA_REALTEK @@ -20,7 +27,7 @@ config NET_DSA_REALTEK_RTL8367C tristate "Realtek RTL8367C switch subdriver" default y depends on NET_DSA_REALTEK - depends on NET_DSA_REALTEK_SMI + depends on NET_DSA_REALTEK_SMI || NET_DSA_REALTEK_MDIO select NET_DSA_TAG_RTL8_4 help Select to enable support for Realtek RTL8365MB-VC. This subdriver @@ -32,7 +39,7 @@ config NET_DSA_REALTEK_RTL8366RB tristate "Realtek RTL8366RB switch subdriver" default y depends on NET_DSA_REALTEK - depends on NET_DSA_REALTEK_SMI + depends on NET_DSA_REALTEK_SMI || NET_DSA_REALTEK_MDIO select NET_DSA_TAG_RTL4_A help Select to enable support for Realtek RTL8366RB diff --git a/drivers/net/dsa/realtek/Makefile b/drivers/net/dsa/realtek/Makefile index 84d5ab062c89..01df2ccbb77f 100644 --- a/drivers/net/dsa/realtek/Makefile +++ b/drivers/net/dsa/realtek/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_NET_DSA_REALTEK_MDIO) += realtek-mdio.o obj-$(CONFIG_NET_DSA_REALTEK_SMI) += realtek-smi.o obj-$(CONFIG_NET_DSA_REALTEK_RTL8366RB) += rtl8366.o rtl8366-objs := rtl8366-core.o rtl8366rb.o diff --git a/drivers/net/dsa/realtek/realtek-mdio.c b/drivers/net/dsa/realtek/realtek-mdio.c new file mode 100644 index 000000000000..b7febd63e04f --- /dev/null +++ b/drivers/net/dsa/realtek/realtek-mdio.c @@ -0,0 +1,284 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* Realtek MDIO interface driver + * + * + * ASICs we intend to support with this driver: + * + * RTL8366 - The original version, apparently + * RTL8369 - Similar enough to have the same datsheet as RTL8366 + * RTL8366RB - Probably reads out "RTL8366 revision B", has a quite + * different register layout from the other two + * RTL8366S - Is this "RTL8366 super"? + * RTL8367 - Has an OpenWRT driver as well + * RTL8368S - Seems to be an alternative name for RTL8366RB + * RTL8370 - Also uses SMI + * + * Copyright (C) 2017 Linus Walleij + * Copyright (C) 2010 Antti Seppälä + * Copyright (C) 2010 Roman Yeryomin + * Copyright (C) 2011 Colin Leitner + * Copyright (C) 2009-2010 Gabor Juhos + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "realtek.h" + +/* Read/write via mdiobus */ +#define MDC_MDIO_CTRL0_REG 31 +#define MDC_MDIO_START_REG 29 +#define MDC_MDIO_CTRL1_REG 21 +#define MDC_MDIO_ADDRESS_REG 23 +#define MDC_MDIO_DATA_WRITE_REG 24 +#define MDC_MDIO_DATA_READ_REG 25 + +#define MDC_MDIO_START_OP 0xFFFF +#define MDC_MDIO_ADDR_OP 0x000E +#define MDC_MDIO_READ_OP 0x0001 +#define MDC_MDIO_WRITE_OP 0x0003 +#define MDC_REALTEK_DEFAULT_PHY_ADDR 0x0 + +int realtek_mdio_read_reg(struct realtek_priv *priv, u32 addr, u32 *data) +{ + u32 phy_id = priv->phy_id; + struct mii_bus *bus = priv->bus; + + BUG_ON(in_interrupt()); + + mutex_lock(&bus->mdio_lock); + /* Write Start command to register 29 */ + bus->write(bus, phy_id, MDC_MDIO_START_REG, MDC_MDIO_START_OP); + + /* Write address control code to register 31 */ + bus->write(bus, phy_id, MDC_MDIO_CTRL0_REG, MDC_MDIO_ADDR_OP); + + /* Write Start command to register 29 */ + bus->write(bus, phy_id, MDC_MDIO_START_REG, MDC_MDIO_START_OP); + + /* Write address to register 23 */ + bus->write(bus, phy_id, MDC_MDIO_ADDRESS_REG, addr); + + /* Write Start command to register 29 */ + bus->write(bus, phy_id, MDC_MDIO_START_REG, MDC_MDIO_START_OP); + + /* Write read control code to register 21 */ + bus->write(bus, phy_id, MDC_MDIO_CTRL1_REG, MDC_MDIO_READ_OP); + + /* Write Start command to register 29 */ + bus->write(bus, phy_id, MDC_MDIO_START_REG, MDC_MDIO_START_OP); + + /* Read data from register 25 */ + *data = bus->read(bus, phy_id, MDC_MDIO_DATA_READ_REG); + + mutex_unlock(&bus->mdio_lock); + + return 0; +} + +static int realtek_mdio_write_reg(struct realtek_priv *priv, u32 addr, u32 data) +{ + u32 phy_id = priv->phy_id; + struct mii_bus *bus = priv->bus; + + BUG_ON(in_interrupt()); + + mutex_lock(&bus->mdio_lock); + + /* Write Start command to register 29 */ + bus->write(bus, phy_id, MDC_MDIO_START_REG, MDC_MDIO_START_OP); + + /* Write address control code to register 31 */ + bus->write(bus, phy_id, MDC_MDIO_CTRL0_REG, MDC_MDIO_ADDR_OP); + + /* Write Start command to register 29 */ + bus->write(bus, phy_id, MDC_MDIO_START_REG, MDC_MDIO_START_OP); + + /* Write address to register 23 */ + bus->write(bus, phy_id, MDC_MDIO_ADDRESS_REG, addr); + + /* Write Start command to register 29 */ + bus->write(bus, phy_id, MDC_MDIO_START_REG, MDC_MDIO_START_OP); + + /* Write data to register 24 */ + bus->write(bus, phy_id, MDC_MDIO_DATA_WRITE_REG, data); + + /* Write Start command to register 29 */ + bus->write(bus, phy_id, MDC_MDIO_START_REG, MDC_MDIO_START_OP); + + /* Write data control code to register 21 */ + bus->write(bus, phy_id, MDC_MDIO_CTRL1_REG, MDC_MDIO_WRITE_OP); + + mutex_unlock(&bus->mdio_lock); + return 0; +} + + +/* Regmap accessors */ + +static int realtek_mdio_write(void *ctx, u32 reg, u32 val) +{ + struct realtek_priv *priv = ctx; + + return realtek_mdio_write_reg(priv, reg, val); +} + +static int realtek_mdio_read(void *ctx, u32 reg, u32 *val) +{ + struct realtek_priv *priv = ctx; + + return realtek_mdio_read_reg(priv, reg, val); +} + +static const struct regmap_config realtek_mdio_regmap_config = { + .reg_bits = 10, /* A4..A0 R4..R0 */ + .val_bits = 16, + .reg_stride = 1, + /* PHY regs are at 0x8000 */ + .max_register = 0xffff, + .reg_format_endian = REGMAP_ENDIAN_BIG, + .reg_read = realtek_mdio_read, + .reg_write = realtek_mdio_write, + .cache_type = REGCACHE_NONE, +}; + +static int realtek_mdio_probe(struct mdio_device *mdiodev) +{ + struct realtek_priv *priv; + struct device *dev = &mdiodev->dev; + const struct realtek_variant *var; + int ret; + struct device_node *np; + + var = of_device_get_match_data(dev); + priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->phy_id = mdiodev->addr; + + // Start by setting up the register mapping + priv->map = devm_regmap_init(dev, NULL, priv, &realtek_mdio_regmap_config); + + priv->bus = mdiodev->bus; + priv->dev = &mdiodev->dev; + priv->chip_data = (void *)priv + sizeof(*priv); + + priv->clk_delay = var->clk_delay; + priv->cmd_read = var->cmd_read; + priv->cmd_write = var->cmd_write; + priv->ops = var->ops; + + if (IS_ERR(priv->map)) + dev_warn(dev, "regmap initialization failed"); + + priv->write_reg_noack=realtek_mdio_write_reg; + + np = dev->of_node; + + dev_set_drvdata(dev, priv); + spin_lock_init(&priv->lock); + + /* TODO: if power is software controlled, set up any regulators here */ + + /* FIXME: maybe skip if no gpio but reset after the switch was detected */ + /* Assert then deassert RESET */ + /* + priv->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(priv->reset)) { + dev_err(dev, "failed to get RESET GPIO\n"); + return PTR_ERR(priv->reset); + } + msleep(REALTEK_SMI_HW_STOP_DELAY); + gpiod_set_value(priv->reset, 0); + msleep(REALTEK_SMI_HW_START_DELAY); + dev_info(dev, "deasserted RESET\n"); + */ + + priv->leds_disabled = of_property_read_bool(np, "realtek,disable-leds"); + + ret = priv->ops->detect(priv); + if (ret) { + dev_err(dev, "unable to detect switch\n"); + return ret; + } + + priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL); + if (!priv->ds) + return -ENOMEM; + + priv->ds->dev = dev; + priv->ds->num_ports = priv->num_ports; + priv->ds->priv = priv; + priv->ds->ops = var->ds_ops; + + ret = dsa_register_switch(priv->ds); + if (ret) { + dev_err(priv->dev, "unable to register switch ret = %d\n", ret); + return ret; + } + + return 0; +} + +static void realtek_mdio_remove(struct mdio_device *mdiodev) +{ + struct realtek_priv *priv = dev_get_drvdata(&mdiodev->dev); + + if (!priv) + return; + + dsa_unregister_switch(priv->ds); + //gpiod_set_value(smi->reset, 1); + dev_set_drvdata(&mdiodev->dev, NULL); +} + +static void realtek_mdio_shutdown(struct mdio_device *mdiodev) +{ + struct realtek_priv *priv = dev_get_drvdata(&mdiodev->dev); + + if (!priv) + return; + + dsa_switch_shutdown(priv->ds); + + dev_set_drvdata(&mdiodev->dev, NULL); +} + +static const struct of_device_id realtek_mdio_of_match[] = { +#if IS_ENABLED(CONFIG_NET_DSA_REALTEK_RTL8366RB) + { .compatible = "realtek,rtl8366rb", .data = &rtl8366rb_variant, }, +#endif + /* FIXME: add support for RTL8366S and more */ + { .compatible = "realtek,rtl8366s", .data = NULL, }, +#if IS_ENABLED(CONFIG_NET_DSA_REALTEK_RTL8367C) + { .compatible = "realtek,rtl8365mb", .data = &rtl8367c_variant, }, +#endif + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, realtek_mdio_of_match); + +static struct mdio_driver realtek_mdio_driver = { + .mdiodrv.driver = { + .name = "realtek-mdio", + .of_match_table = of_match_ptr(realtek_mdio_of_match), + }, + .probe = realtek_mdio_probe, + .remove = realtek_mdio_remove, + .shutdown = realtek_mdio_shutdown, +}; +mdio_module_driver(realtek_mdio_driver); + +MODULE_LICENSE("GPL"); diff --git a/drivers/net/dsa/realtek/realtek.h b/drivers/net/dsa/realtek/realtek.h index 976cb7823c92..c1f20a23ab9e 100644 --- a/drivers/net/dsa/realtek/realtek.h +++ b/drivers/net/dsa/realtek/realtek.h @@ -50,6 +50,8 @@ struct realtek_priv { struct gpio_desc *mdio; struct regmap *map; struct mii_bus *slave_mii_bus; + struct mii_bus *bus; + int phy_id; unsigned int clk_delay; u8 cmd_read; @@ -66,6 +68,7 @@ struct realtek_priv { struct rtl8366_mib_counter *mib_counters; const struct realtek_ops *ops; + int (*setup)(struct dsa_switch *ds); int (*setup_interface)(struct dsa_switch *ds); int (*write_reg_noack)(struct realtek_priv *priv, u32 addr, u32 data); From patchwork Thu Dec 16 20:13:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Luiz Angelo Daros de Luca X-Patchwork-Id: 12682455 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C5D0AC433EF for ; Thu, 16 Dec 2021 20:14:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241253AbhLPUOq (ORCPT ); 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[187.49.235.234]) by smtp.gmail.com with ESMTPSA id a15sm5110266qtb.5.2021.12.16.12.14.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Dec 2021 12:14:37 -0800 (PST) From: luizluca@gmail.com To: netdev@vger.kernel.org Cc: linus.walleij@linaro.org, andrew@lunn.ch, vivien.didelot@gmail.com, f.fainelli@gmail.com, olteanv@gmail.com, alsi@bang-olufsen.dk, arinc.unal@arinc9.com, Luiz Angelo Daros de Luca Subject: [PATCH net-next 09/13] dt-bindings: net: dsa: realtek-mdio: document new interface Date: Thu, 16 Dec 2021 17:13:38 -0300 Message-Id: <20211216201342.25587-10-luizluca@gmail.com> X-Mailer: git-send-email 2.34.0 In-Reply-To: <20211216201342.25587-1-luizluca@gmail.com> References: <20211216201342.25587-1-luizluca@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Luiz Angelo Daros de Luca realtek-mdio is a new mdio driver for realtek switches that use mdio (instead of SMI) interface. Reviewed-by: Arınç ÜNAL Signed-off-by: Luiz Angelo Daros de Luca --- .../bindings/net/dsa/realtek-mdio.txt | 85 +++++++++++++++++++ MAINTAINERS | 2 +- 2 files changed, 86 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/net/dsa/realtek-mdio.txt diff --git a/Documentation/devicetree/bindings/net/dsa/realtek-mdio.txt b/Documentation/devicetree/bindings/net/dsa/realtek-mdio.txt new file mode 100644 index 000000000000..01b0463b808f --- /dev/null +++ b/Documentation/devicetree/bindings/net/dsa/realtek-mdio.txt @@ -0,0 +1,85 @@ +Realtek MDIO-based Switches +========================== + +Realtek MDIO-based Switches uses MDIO protocol as opposed to realtek +SMI-based switches. The realtek-mdio driver is an mdio driver and it must +be inserted inside an mdio node. + +Required properties: + +- compatible: must be exactly one of (same as realtek-smi): + "realtek,rtl8365mb" (4+1 ports) + "realtek,rtl8366rb" (4+1 ports) + "realtek,rtl8366s" (4+1 ports) + +Required properties: +- reg: MDIO PHY ID to access the switch + +Optional properties: +- realtek,disable-leds: if the LED drivers are not used in the + hardware design this will disable them so they are not turned on + and wasting power. + +See net/dsa/dsa.txt for a list of additional required and optional properties +and subnodes of DSA switches. + +Optional properties of dsa port: + +- realtek,ext-int: defines the external interface number (0, 1, 2). By default, 1. + +Examples: + +An example for the RTL8367S: + +&mdio0 { + switch { + compatible = "realtek,rtl8367s"; + reg = <29>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + port@0 { + reg = <0>; + label = "lan4"; + }; + + port@1 { + reg = <1>; + label = "lan3"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan1"; + }; + + port@4 { + reg = <4>; + label = "wan"; + }; + + port@7 { + reg = <7>; + ethernet = <ðernet>; + phy-mode = "rgmii"; + realtek,ext-int = <2>; + tx-internal-delay-ps = <2000>; + rx-internal-delay-ps = <0>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; +}; + diff --git a/MAINTAINERS b/MAINTAINERS index a8f949b368a8..750f5c68c5fa 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -16152,7 +16152,7 @@ F: sound/soc/codecs/rt* REALTEK RTL83xx SMI DSA ROUTER CHIPS M: Linus Walleij S: Maintained -F: Documentation/devicetree/bindings/net/dsa/realtek-smi.txt +F: Documentation/devicetree/bindings/net/dsa/realtek-*.txt F: drivers/net/dsa/realtek/* REALTEK WIRELESS DRIVER (rtlwifi family) From patchwork Thu Dec 16 20:13:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Luiz Angelo Daros de Luca X-Patchwork-Id: 12682459 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA10CC4332F for ; Thu, 16 Dec 2021 20:14:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241261AbhLPUOr (ORCPT ); Thu, 16 Dec 2021 15:14:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41502 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241260AbhLPUOm (ORCPT ); Thu, 16 Dec 2021 15:14:42 -0500 Received: from mail-qk1-x730.google.com (mail-qk1-x730.google.com [IPv6:2607:f8b0:4864:20::730]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 52CDFC06173F for ; Thu, 16 Dec 2021 12:14:42 -0800 (PST) Received: by mail-qk1-x730.google.com with SMTP id t6so119080qkg.1 for ; Thu, 16 Dec 2021 12:14:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0LmjyK+2zVn20q1+6xXaTvbtM6sOZn2sG53WToXfZ4c=; b=kk1oE63Y6bFdcwviI88NY1pEfgZaBWxlbVC2RCqqKiK9ce9B0aWX1Etf+YcfNPjCNf W5BHoRZdtc/JTopi/ss8w7/xlli8zONdzyvDMOyGMEF5oBVPkC1MZTgoK2fSnGoMgj6y eQh5H4+UO+7aknWOGwynAgIYZTg7s/t9yWAcbyZUn55weL+mFeOzNCTCr17eUEdHynoj seCgS1QJPb81B/NINsKVuDDTU/zJc0t6HNyLdi1PYKBgAtAynZ7mZ9VV8R39n1s9V5i3 KKEhPr4dcVnOfAAzsOY5vGbSg5clDvBINpm+m21MKyzZ8MXLPJgxSIub+TZfivg8ckyk 4Ocw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0LmjyK+2zVn20q1+6xXaTvbtM6sOZn2sG53WToXfZ4c=; b=jNL5hy/SgUTsnvhC8mHbfJc5QFOwkK2blPVYBdu1/+ExZLHkTs8vCy2/KOmBUbJoBZ FPlwooGwoIvB+Y9jd90B4PJqrpnyn85xdDHIsiuNb+MMXJIg6886AnEbmtBVDiyIMZh6 hPR7s078V/WuTmE2mWhl2jYpqGdgV2cEio6Id5YRIZYtZm31xFjk88PYmMgL3F6hGcTp a6xJiUkHT1Zl0GFoJ3sjRuE5URvNubu2iEshyVFiciPJNx58uE2G8Zw6/oRSEKfTo0ur 2W5iKA8RZwJkm1z3dJUTufLtX8IGLLqovGnrgV1Eyz0AjH5JMjFSZIFLQDU66o+Cfdsc XcIg== X-Gm-Message-State: AOAM530xUxKaOqej0dbs/Btr4rPP2wxDPZRcUqfZIZcqH1bprkfOHGx5 +gKdHsSr2lW9Xg657JvkR6UYFzvuNej1lQ== X-Google-Smtp-Source: ABdhPJxHuFD/XuxGF4Tu2uIwW4LhNk+ywoNiPBh7b2uoqRcnC8pebKPDoYGuB9nOMmmfo+qCi25V8w== X-Received: by 2002:a05:620a:4507:: with SMTP id t7mr13504498qkp.582.1639685681171; Thu, 16 Dec 2021 12:14:41 -0800 (PST) Received: from tresc043793.tre-sc.gov.br (187-049-235-234.floripa.net.br. [187.49.235.234]) by smtp.gmail.com with ESMTPSA id a15sm5110266qtb.5.2021.12.16.12.14.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Dec 2021 12:14:40 -0800 (PST) From: luizluca@gmail.com To: netdev@vger.kernel.org Cc: linus.walleij@linaro.org, andrew@lunn.ch, vivien.didelot@gmail.com, f.fainelli@gmail.com, olteanv@gmail.com, alsi@bang-olufsen.dk, arinc.unal@arinc9.com, Luiz Angelo Daros de Luca Subject: [PATCH net-next 10/13] net: dsa: realtek: rtl8367c: rename extport to extint, add "realtek,ext-int" Date: Thu, 16 Dec 2021 17:13:39 -0300 Message-Id: <20211216201342.25587-11-luizluca@gmail.com> X-Mailer: git-send-email 2.34.0 In-Reply-To: <20211216201342.25587-1-luizluca@gmail.com> References: <20211216201342.25587-1-luizluca@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Luiz Angelo Daros de Luca "extport" 0, 1, 2 was used to reference external ports (ext0, ext1, ext2). Meanwhile, port 0..9 is used as switch ports, including external ports. "extport" was renamed to extint to make it clear it does not mean the port number but the external interface number. The macros that map extint numbers to registers addresses now use inline ifs instead of binary arithmetic. "extint" was hardcoded to 1. Now it can be defined with a device-tree port property "realtek,ext-int"; Tested-by: Arınç ÜNAL Signed-off-by: Luiz Angelo Daros de Luca --- .../bindings/net/dsa/realtek-smi.txt | 4 + drivers/net/dsa/realtek/rtl8367c.c | 106 ++++++++++++------ 2 files changed, 74 insertions(+), 36 deletions(-) diff --git a/Documentation/devicetree/bindings/net/dsa/realtek-smi.txt b/Documentation/devicetree/bindings/net/dsa/realtek-smi.txt index 3a60e77ceed4..acdb026e5307 100644 --- a/Documentation/devicetree/bindings/net/dsa/realtek-smi.txt +++ b/Documentation/devicetree/bindings/net/dsa/realtek-smi.txt @@ -56,6 +56,10 @@ See net/mdio.txt for additional MDIO bus properties. See net/dsa/dsa.txt for a list of additional required and optional properties and subnodes of DSA switches. +Optional properties of dsa port: + +- realtek,ext-int: defines the external interface number (0, 1, 2). By default, 1. + Examples: An example for the RTL8366RB: diff --git a/drivers/net/dsa/realtek/rtl8367c.c b/drivers/net/dsa/realtek/rtl8367c.c index 98ec793a82bc..6aca48165d1f 100644 --- a/drivers/net/dsa/realtek/rtl8367c.c +++ b/drivers/net/dsa/realtek/rtl8367c.c @@ -197,22 +197,26 @@ #define RTL8367C_EXT_PORT_MODE_100FX 13 /* EXT port interface mode configuration registers 0~1 */ -#define RTL8367C_DIGITAL_INTERFACE_SELECT_REG0 0x1305 -#define RTL8367C_DIGITAL_INTERFACE_SELECT_REG1 0x13C3 -#define RTL8367C_DIGITAL_INTERFACE_SELECT_REG(_extport) \ - (RTL8367C_DIGITAL_INTERFACE_SELECT_REG0 + \ - ((_extport) >> 1) * (0x13C3 - 0x1305)) -#define RTL8367C_DIGITAL_INTERFACE_SELECT_MODE_MASK(_extport) \ - (0xF << (((_extport) % 2))) -#define RTL8367C_DIGITAL_INTERFACE_SELECT_MODE_OFFSET(_extport) \ - (((_extport) % 2) * 4) - -/* EXT port RGMII TX/RX delay configuration registers 1~2 */ -#define RTL8367C_EXT_RGMXF_REG1 0x1307 -#define RTL8367C_EXT_RGMXF_REG2 0x13C5 -#define RTL8367C_EXT_RGMXF_REG(_extport) \ - (RTL8367C_EXT_RGMXF_REG1 + \ - (((_extport) >> 1) * (0x13C5 - 0x1307))) +#define RTL8367C_DIGITAL_INTERFACE_SELECT_REG0 0x1305 /*EXT1*/ +#define RTL8367C_DIGITAL_INTERFACE_SELECT_REG1 0x13C3 /*EXT2*/ +#define RTL8367C_DIGITAL_INTERFACE_SELECT_REG(_extint) \ + (_extint==1 ? RTL8367C_DIGITAL_INTERFACE_SELECT_REG0 : \ + _extint==2 ? RTL8367C_DIGITAL_INTERFACE_SELECT_REG1 : \ + 0x0) +#define RTL8367C_DIGITAL_INTERFACE_SELECT_MODE_MASK(_extint) \ + (0xF << (((_extint) % 2))) +#define RTL8367C_DIGITAL_INTERFACE_SELECT_MODE_OFFSET(_extint) \ + (((_extint) % 2) * 4) + +/* EXT port RGMII TX/RX delay configuration registers 0~2 */ +#define RTL8367C_EXT_RGMXF_REG0 0x1306 /*EXT0*/ +#define RTL8367C_EXT_RGMXF_REG1 0x1307 /*EXT1*/ +#define RTL8367C_EXT_RGMXF_REG2 0x13C5 /*EXT2*/ +#define RTL8367C_EXT_RGMXF_REG(_extint) \ + (_extint==0 ? RTL8367C_EXT_RGMXF_REG0 : \ + _extint==1 ? RTL8367C_EXT_RGMXF_REG1 : \ + _extint==2 ? RTL8367C_EXT_RGMXF_REG2 : \ + 0x0) #define RTL8367C_EXT_RGMXF_RXDELAY_MASK 0x0007 #define RTL8367C_EXT_RGMXF_TXDELAY_MASK 0x0008 @@ -222,13 +226,14 @@ #define RTL8367C_PORT_SPEED_1000M 2 /* EXT port force configuration registers 0~2 */ -#define RTL8367C_DIGITAL_INTERFACE_FORCE_REG0 0x1310 -#define RTL8367C_DIGITAL_INTERFACE_FORCE_REG1 0x1311 -#define RTL8367C_DIGITAL_INTERFACE_FORCE_REG2 0x13C4 -#define RTL8367C_DIGITAL_INTERFACE_FORCE_REG(_extport) \ - (RTL8367C_DIGITAL_INTERFACE_FORCE_REG0 + \ - ((_extport) & 0x1) + \ - ((((_extport) >> 1) & 0x1) * (0x13C4 - 0x1310))) +#define RTL8367C_DIGITAL_INTERFACE_FORCE_REG0 0x1310 /*EXT0*/ +#define RTL8367C_DIGITAL_INTERFACE_FORCE_REG1 0x1311 /*EXT1*/ +#define RTL8367C_DIGITAL_INTERFACE_FORCE_REG2 0x13C4 /*EXT2*/ +#define RTL8367C_DIGITAL_INTERFACE_FORCE_REG(_extint) \ + (_extint==0 ? RTL8367C_DIGITAL_INTERFACE_FORCE_REG0 : \ + _extint==1 ? RTL8367C_DIGITAL_INTERFACE_FORCE_REG1 : \ + _extint==2 ? RTL8367C_DIGITAL_INTERFACE_FORCE_REG2 : \ + 0x0) #define RTL8367C_DIGITAL_INTERFACE_FORCE_EN_MASK 0x1000 #define RTL8367C_DIGITAL_INTERFACE_FORCE_NWAY_MASK 0x0080 #define RTL8367C_DIGITAL_INTERFACE_FORCE_TXPAUSE_MASK 0x0040 @@ -511,6 +516,7 @@ struct rtl8367c_cpu { * access via rtl8367c_get_stats64 * @stats_lock: protect the stats structure during read/update * @mib_work: delayed work for polling MIB counters + * @ext_int: the external interface related to this port (-1 to none) */ struct rtl8367c_port { struct realtek_priv *priv; @@ -518,6 +524,7 @@ struct rtl8367c_port { struct rtnl_link_stats64 stats; spinlock_t stats_lock; struct delayed_work mib_work; + int ext_int; }; /** @@ -733,15 +740,15 @@ static int rtl8367c_ext_config_rgmii(struct realtek_priv *priv, int port, { struct device_node *dn; struct dsa_port *dp; + struct rtl8367c_port *p; + struct rtl8367c *mb; int tx_delay = 0; int rx_delay = 0; - int ext_port; + int ext_int; u32 val; int ret; - if (port == priv->cpu_port) { - ext_port = 1; - } else { + if (port != priv->cpu_port) { dev_err(priv->dev, "only one EXT port is currently supported\n"); return -EINVAL; } @@ -749,6 +756,10 @@ static int rtl8367c_ext_config_rgmii(struct realtek_priv *priv, int port, dp = dsa_to_port(priv->ds, port); dn = dp->dn; + mb = priv->chip_data; + p = &mb->ports[port]; + ext_int = p->ext_int; + /* Set the RGMII TX/RX delay * * The Realtek vendor driver indicates the following possible @@ -792,7 +803,7 @@ static int rtl8367c_ext_config_rgmii(struct realtek_priv *priv, int port, } ret = regmap_update_bits( - priv->map, RTL8367C_EXT_RGMXF_REG(ext_port), + priv->map, RTL8367C_EXT_RGMXF_REG(ext_int), RTL8367C_EXT_RGMXF_TXDELAY_MASK | RTL8367C_EXT_RGMXF_RXDELAY_MASK, FIELD_PREP(RTL8367C_EXT_RGMXF_TXDELAY_MASK, tx_delay) | @@ -801,11 +812,11 @@ static int rtl8367c_ext_config_rgmii(struct realtek_priv *priv, int port, return ret; ret = regmap_update_bits( - priv->map, RTL8367C_DIGITAL_INTERFACE_SELECT_REG(ext_port), - RTL8367C_DIGITAL_INTERFACE_SELECT_MODE_MASK(ext_port), + priv->map, RTL8367C_DIGITAL_INTERFACE_SELECT_REG(ext_int), + RTL8367C_DIGITAL_INTERFACE_SELECT_MODE_MASK(ext_int), RTL8367C_EXT_PORT_MODE_RGMII << RTL8367C_DIGITAL_INTERFACE_SELECT_MODE_OFFSET( - ext_port)); + ext_int)); if (ret) return ret; @@ -816,22 +827,26 @@ static int rtl8367c_ext_config_forcemode(struct realtek_priv *priv, int port, bool link, int speed, int duplex, bool tx_pause, bool rx_pause) { + struct rtl8367c_port *p; + struct rtl8367c *mb; u32 r_tx_pause; u32 r_rx_pause; u32 r_duplex; u32 r_speed; u32 r_link; - int ext_port; + int ext_int; int val; int ret; - if (port == priv->cpu_port) { - ext_port = 1; - } else { + if (port != priv->cpu_port) { dev_err(priv->dev, "only one EXT port is currently supported\n"); return -EINVAL; } + mb = priv->chip_data; + p = &mb->ports[port]; + ext_int = p->ext_int; + if (link) { /* Force the link up with the desired configuration */ r_link = 1; @@ -878,7 +893,7 @@ static int rtl8367c_ext_config_forcemode(struct realtek_priv *priv, int port, r_duplex) | FIELD_PREP(RTL8367C_DIGITAL_INTERFACE_FORCE_SPEED_MASK, r_speed); ret = regmap_write(priv->map, - RTL8367C_DIGITAL_INTERFACE_FORCE_REG(ext_port), + RTL8367C_DIGITAL_INTERFACE_FORCE_REG(ext_int), val); if (ret) return ret; @@ -1807,7 +1822,9 @@ static int rtl8367c_setup(struct dsa_switch *ds) /* Configure ports */ for (i = 0; i < priv->num_ports; i++) { + struct device_node *dn; struct rtl8367c_port *p = &mb->ports[i]; + u32 val; if (dsa_is_unused_port(priv->ds, i)) continue; @@ -1831,6 +1848,23 @@ static int rtl8367c_setup(struct dsa_switch *ds) * administratively down by default. */ rtl8367c_port_stp_state_set(priv->ds, i, BR_STATE_DISABLED); + + dn = dsa_to_port(priv->ds, i)->dn; + + if (!of_property_read_u32(dn, "realtek,ext-int", &val)) { + if (val < 0 || val > 2) { + dev_err(priv->dev, + "realtek,ext-int must be between 0 and 2 \n"); + return -EINVAL; + } + p->ext_int = val; + } else { + if (dsa_is_cpu_port(priv->ds, i)) + /* existing default */ + p->ext_int = 1; + else + p->ext_int = -1; + } } /* Set maximum packet length to 1536 bytes */ From patchwork Thu Dec 16 20:13:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Luiz Angelo Daros de Luca X-Patchwork-Id: 12682457 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7168DC433FE for ; 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[187.49.235.234]) by smtp.gmail.com with ESMTPSA id a15sm5110266qtb.5.2021.12.16.12.14.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Dec 2021 12:14:43 -0800 (PST) From: luizluca@gmail.com To: netdev@vger.kernel.org Cc: linus.walleij@linaro.org, andrew@lunn.ch, vivien.didelot@gmail.com, f.fainelli@gmail.com, olteanv@gmail.com, alsi@bang-olufsen.dk, arinc.unal@arinc9.com, Luiz Angelo Daros de Luca Subject: [PATCH net-next 11/13] net: dsa: realtek: rtl8367c: use GENMASK(n-1,0) instead of BIT(n)-1 Date: Thu, 16 Dec 2021 17:13:40 -0300 Message-Id: <20211216201342.25587-12-luizluca@gmail.com> X-Mailer: git-send-email 2.34.0 In-Reply-To: <20211216201342.25587-1-luizluca@gmail.com> References: <20211216201342.25587-1-luizluca@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Luiz Angelo Daros de Luca Tested-by: Arınç ÜNAL Signed-off-by: Luiz Angelo Daros de Luca Reviewed-by: Linus Walleij --- drivers/net/dsa/realtek/rtl8367c.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/dsa/realtek/rtl8367c.c b/drivers/net/dsa/realtek/rtl8367c.c index 6aca48165d1f..f370ea948c59 100644 --- a/drivers/net/dsa/realtek/rtl8367c.c +++ b/drivers/net/dsa/realtek/rtl8367c.c @@ -1955,7 +1955,7 @@ static int rtl8367c_detect(struct realtek_priv *priv) mb->priv = priv; mb->chip_id = chip_id; mb->chip_ver = chip_ver; - mb->port_mask = BIT(priv->num_ports) - 1; + mb->port_mask = GENMASK(priv->num_ports-1,0); mb->learn_limit_max = RTL8367C_LEARN_LIMIT_MAX; mb->jam_table = rtl8367c_init_jam_8367c; mb->jam_size = ARRAY_SIZE(rtl8367c_init_jam_8367c); From patchwork Thu Dec 16 20:13:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Luiz Angelo Daros de Luca X-Patchwork-Id: 12682461 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20F00C433EF for ; Thu, 16 Dec 2021 20:14:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241263AbhLPUOu (ORCPT ); Thu, 16 Dec 2021 15:14:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41526 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241257AbhLPUOs (ORCPT ); Thu, 16 Dec 2021 15:14:48 -0500 Received: from mail-qt1-x835.google.com (mail-qt1-x835.google.com [IPv6:2607:f8b0:4864:20::835]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D20AEC061574 for ; Thu, 16 Dec 2021 12:14:47 -0800 (PST) Received: by mail-qt1-x835.google.com with SMTP id t11so444369qtw.3 for ; Thu, 16 Dec 2021 12:14:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VyqmtVk4BF4S8fw2AGDQkytFyYmjt7Tp2U4twupOWd8=; b=d+esC13fmBAhrtGjf1SL/QxhNFK6qaC3kZs1snhkm9kFx7jw4mPKgd4OZ7Rx+1Nmi3 aka/pU32kIiKrqNMkacNdJeS5ENn2V1yb1YUNoGs0OtFp2T4R9q28sHX50nrmNCvlkSN 3aqWZsXPd878YEsqVPrMkolzWx/zc0HYQOOOGdThQaYSMpUqmD9e4swQkMA9j3+lqDj2 d2+A9TDAyHSbpIcQ27AknkPtqvY9mGkO28u5xzfVnXJNDNnwXKApqe+s9bZqNki+24CS LxrVQmrmk+aFhBkmMwF8qUPO/N+vXdtysfjLV6UhTErVDcfcIizL2UW2OCPvURn+Waju KbfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VyqmtVk4BF4S8fw2AGDQkytFyYmjt7Tp2U4twupOWd8=; b=7uGBdQlSl9nQ5GRgQpWm6D9fTQ4wkCAM20ogRGcyaNAZbGtfBEz9vhTG8ewwOhNM6M bUGx9bnspACpWjdBLUOj09NPXG1GZ4Db/bXsDbTCmB9WKm0taXpNTG/+ydoymfwzCicI f1q5OdjlfdLW6AFoKcmT4l3WVsCzkuYAX0M6I3H/lziAwU+YAQ6+IdeNcF0/8CY0ohBF hvCc34YF954epqrh7fbGXttQyUQD5N01uipBLFZDqSdLHCIYw14u047OzJSYS6vqPE77 2zdrS71qZdSQFyLbNlI8Sebd0/1msvuLjNE1noowLb3NP1tBszQS4qzhV8kIAvlT5cTe DaJA== X-Gm-Message-State: AOAM531F5MQfO6gx7wQkhsBOtWT/5oOBpk9sv0vzpJ1Rtl8OIa8ObzjZ lM8Zi7cOyoGOavmwpx2h0oBbw/pDICC9Mw== X-Google-Smtp-Source: ABdhPJwjnQjXHtaOazOrXspyv3eU/xCQk2CscIVycej92bWLcTAZACFZYv4yuFDyiZPB3cN8FBW1yA== X-Received: by 2002:a05:622a:42:: with SMTP id y2mr19048449qtw.250.1639685686832; Thu, 16 Dec 2021 12:14:46 -0800 (PST) Received: from tresc043793.tre-sc.gov.br (187-049-235-234.floripa.net.br. [187.49.235.234]) by smtp.gmail.com with ESMTPSA id a15sm5110266qtb.5.2021.12.16.12.14.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Dec 2021 12:14:46 -0800 (PST) From: luizluca@gmail.com To: netdev@vger.kernel.org Cc: linus.walleij@linaro.org, andrew@lunn.ch, vivien.didelot@gmail.com, f.fainelli@gmail.com, olteanv@gmail.com, alsi@bang-olufsen.dk, arinc.unal@arinc9.com, Luiz Angelo Daros de Luca Subject: [PATCH net-next 12/13] net: dsa: realtek: rtl8367c: use DSA CPU port Date: Thu, 16 Dec 2021 17:13:41 -0300 Message-Id: <20211216201342.25587-13-luizluca@gmail.com> X-Mailer: git-send-email 2.34.0 In-Reply-To: <20211216201342.25587-1-luizluca@gmail.com> References: <20211216201342.25587-1-luizluca@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Luiz Angelo Daros de Luca Instead of a fixed CPU port, assume that DSA is correct. Tested-by: Arınç ÜNAL Signed-off-by: Luiz Angelo Daros de Luca --- drivers/net/dsa/realtek/rtl8367c.c | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/drivers/net/dsa/realtek/rtl8367c.c b/drivers/net/dsa/realtek/rtl8367c.c index f370ea948c59..a478ddc33a9e 100644 --- a/drivers/net/dsa/realtek/rtl8367c.c +++ b/drivers/net/dsa/realtek/rtl8367c.c @@ -91,7 +91,6 @@ /* Chip-specific data and limits */ #define RTL8367C_CHIP_ID_8365MB_VC 0x6367 -#define RTL8367C_CPU_PORT_NUM_8365MB_VC 6 #define RTL8367C_LEARN_LIMIT_MAX 2112 @@ -99,7 +98,7 @@ #define RTL8367C_PHYADDRMAX 7 #define RTL8367C_NUM_PHYREGS 32 #define RTL8367C_PHYREGMAX (RTL8367C_NUM_PHYREGS - 1) -#define RTL8367C_MAX_NUM_PORTS (RTL8367C_CPU_PORT_NUM_8365MB_VC + 1) +#define RTL8367C_MAX_NUM_PORTS 7 /* Chip identification registers */ #define RTL8367C_CHIP_ID_REG 0x1300 @@ -1816,9 +1815,18 @@ static int rtl8367c_setup(struct dsa_switch *ds) dev_info(priv->dev, "no interrupt support\n"); /* Configure CPU tagging */ - ret = rtl8367c_cpu_config(priv); - if (ret) - goto out_teardown_irq; + for (i = 0; i < priv->num_ports; i++) { + if (!(dsa_is_cpu_port(priv->ds, i))) + continue; + priv->cpu_port = i; + mb->cpu.mask = BIT(priv->cpu_port); + mb->cpu.trap_port = priv->cpu_port; + ret = rtl8367c_cpu_config(priv); + if (ret) + goto out_teardown_irq; + + break; + } /* Configure ports */ for (i = 0; i < priv->num_ports; i++) { @@ -1949,8 +1957,7 @@ static int rtl8367c_detect(struct realtek_priv *priv) "found an RTL8365MB-VC switch (ver=0x%04x)\n", chip_ver); - priv->cpu_port = RTL8367C_CPU_PORT_NUM_8365MB_VC; - priv->num_ports = priv->cpu_port + 1; + priv->num_ports = RTL8367C_MAX_NUM_PORTS; mb->priv = priv; mb->chip_id = chip_id; @@ -1961,8 +1968,6 @@ static int rtl8367c_detect(struct realtek_priv *priv) mb->jam_size = ARRAY_SIZE(rtl8367c_init_jam_8367c); mb->cpu.enable = 1; - mb->cpu.mask = BIT(priv->cpu_port); - mb->cpu.trap_port = priv->cpu_port; mb->cpu.insert = RTL8367C_CPU_INSERT_TO_ALL; mb->cpu.position = RTL8367C_CPU_POS_AFTER_SA; mb->cpu.rx_length = RTL8367C_CPU_RXLEN_64BYTES; From patchwork Thu Dec 16 20:13:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Luiz Angelo Daros de Luca X-Patchwork-Id: 12682463 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 966C6C433F5 for ; Thu, 16 Dec 2021 20:14:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241260AbhLPUOw (ORCPT ); Thu, 16 Dec 2021 15:14:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41544 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241257AbhLPUOv (ORCPT ); Thu, 16 Dec 2021 15:14:51 -0500 Received: from mail-qt1-x82f.google.com (mail-qt1-x82f.google.com [IPv6:2607:f8b0:4864:20::82f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AE146C061574 for ; Thu, 16 Dec 2021 12:14:50 -0800 (PST) Received: by mail-qt1-x82f.google.com with SMTP id z9so413202qtj.9 for ; Thu, 16 Dec 2021 12:14:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VWH94Un8GoGwi66okxuXS0MUBHEQhsgaWrtRKfs2Cww=; b=hI4mwviVo52wlMYPCWDgH/jcLk2nVPzOg73klVYYbbhZweYjcBn3Ni/S2BC/Fp+j16 qDGj99aubU6thWW/9nXjYwDMifuZBrK5mTdfSSnwP8nKsf6k3lX6sW6ZUxBpCX3/HUyS wFcaLtd/ZTr3JkvdP+r0NZKXAxLmGyMf15TdZC1bUE9fScQ5g2G+9O5Ft+MYPAxfh1Xu cHaPZmziWV3B5QLxQlUnfNH1QHRrULfeM9NdYai/NT92Y/omBmHl9YTBTsGbuDHcWzab TtFsunw9XJCwDVWVo4dqf1Bf/Fpx90oSq6RGgNFJN4snXwEzPurh7mhCPTz9IvC+MMtr 8sVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VWH94Un8GoGwi66okxuXS0MUBHEQhsgaWrtRKfs2Cww=; b=JoOGuCQ+/9mqw8GjNJOVFQFifOV/j6FtW4oRu8EVd/fcTv7nn3b2OS2IZ8ATCuPuAI ipUx2ppuYneiOCxnnuf6It2udfyGiBgWXR30BHcu6iTO/N1rtH/7SsKC8ZMMmn9wFZbK 9tN0kFtcIBtVbBxpkCWzdplLbr4sqP0S3oI5dpGFSwU/LNllWHTvgpfuF//Jo7myE8YV JePo3ujUj7JjN0zirDDnwLIlt7VwWjVS56SCqSAKIoAJ+vKGzzrZLAgBWxldlVoUEbJN 0jHQrmAWpactAZRCh7wwfJj7QzRNtLI0m2bwdNUT4FOqpU9HAQzymCtNvQpWwz5HXuCK 8Otg== X-Gm-Message-State: AOAM530zgBxCcrYWInB8bj1ohwT1frF+/8v5WDW+mZ/xxV/hnk2EGQis 6X6UfK48UrD3t0AIUN8TYh+AENPXdwCGmA== X-Google-Smtp-Source: ABdhPJxqmxNBfzZzegHExPEh3nAhNAmwm393wQlMVw5v6FozXIM8TSHrDvcZnOChkdBfyIjpPRh7jQ== X-Received: by 2002:a05:622a:1a9b:: with SMTP id s27mr18748536qtc.417.1639685689665; Thu, 16 Dec 2021 12:14:49 -0800 (PST) Received: from tresc043793.tre-sc.gov.br (187-049-235-234.floripa.net.br. [187.49.235.234]) by smtp.gmail.com with ESMTPSA id a15sm5110266qtb.5.2021.12.16.12.14.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Dec 2021 12:14:49 -0800 (PST) From: luizluca@gmail.com To: netdev@vger.kernel.org Cc: linus.walleij@linaro.org, andrew@lunn.ch, vivien.didelot@gmail.com, f.fainelli@gmail.com, olteanv@gmail.com, alsi@bang-olufsen.dk, arinc.unal@arinc9.com, Luiz Angelo Daros de Luca Subject: [PATCH net-next 13/13] net: dsa: realtek: rtl8367c: add RTL8367S support Date: Thu, 16 Dec 2021 17:13:42 -0300 Message-Id: <20211216201342.25587-14-luizluca@gmail.com> X-Mailer: git-send-email 2.34.0 In-Reply-To: <20211216201342.25587-1-luizluca@gmail.com> References: <20211216201342.25587-1-luizluca@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Luiz Angelo Daros de Luca Realtek's RTL8367S, a 5+2 port 10/100/1000M Ethernet switch. It shares the same driver family (RTL8367C) with other models as the RTL8365MB-VC. Its compatible string is "realtek,rtl8367s". It was tested only with MDIO interface (realtek-mdio), although it might work out-of-the-box with SMI interface (using realtek-smi). This patch was based on an unpublished patch from Alvin Šipraga . Tested-by: Arınç ÜNAL Signed-off-by: Luiz Angelo Daros de Luca --- .../bindings/net/dsa/realtek-mdio.txt | 1 + .../bindings/net/dsa/realtek-smi.txt | 1 + drivers/net/dsa/realtek/Kconfig | 4 +-- drivers/net/dsa/realtek/realtek-mdio.c | 1 + drivers/net/dsa/realtek/realtek-smi.c | 4 +++ drivers/net/dsa/realtek/rtl8367c.c | 33 +++++++++++++++---- 6 files changed, 35 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/net/dsa/realtek-mdio.txt b/Documentation/devicetree/bindings/net/dsa/realtek-mdio.txt index 01b0463b808f..48aa263792ac 100644 --- a/Documentation/devicetree/bindings/net/dsa/realtek-mdio.txt +++ b/Documentation/devicetree/bindings/net/dsa/realtek-mdio.txt @@ -11,6 +11,7 @@ Required properties: "realtek,rtl8365mb" (4+1 ports) "realtek,rtl8366rb" (4+1 ports) "realtek,rtl8366s" (4+1 ports) + "realtek,rtl8367s" (5+2 ports) Required properties: - reg: MDIO PHY ID to access the switch diff --git a/Documentation/devicetree/bindings/net/dsa/realtek-smi.txt b/Documentation/devicetree/bindings/net/dsa/realtek-smi.txt index acdb026e5307..b295b8c0d5fc 100644 --- a/Documentation/devicetree/bindings/net/dsa/realtek-smi.txt +++ b/Documentation/devicetree/bindings/net/dsa/realtek-smi.txt @@ -13,6 +13,7 @@ Required properties: "realtek,rtl8365mb" (4+1 ports) "realtek,rtl8366rb" (4+1 ports) "realtek,rtl8366s" (4+1 ports) + "realtek,rtl8367s" (5+2 ports) Required properties: - mdc-gpios: GPIO line for the MDC clock line. diff --git a/drivers/net/dsa/realtek/Kconfig b/drivers/net/dsa/realtek/Kconfig index 48194d0dd51f..25de1107732d 100644 --- a/drivers/net/dsa/realtek/Kconfig +++ b/drivers/net/dsa/realtek/Kconfig @@ -30,9 +30,9 @@ config NET_DSA_REALTEK_RTL8367C depends on NET_DSA_REALTEK_SMI || NET_DSA_REALTEK_MDIO select NET_DSA_TAG_RTL8_4 help - Select to enable support for Realtek RTL8365MB-VC. This subdriver + Select to enable support for Realtek RTL8365MB-VC and RTL8367S. This subdriver might also support RTL8363NB, RTL8363NB-VB, RTL8363SC, RTL8363SC-VB, RTL8364NB, - RTL8364NB-VB, RTL8366SC, RTL8367RB-VB, RTL8367S, RTL8367SB, RTL8370MB, RTL8310SR + RTL8364NB-VB, RTL8366SC, RTL8367RB-VB, RTL8367SB, RTL8370MB, RTL8310SR in the future. config NET_DSA_REALTEK_RTL8366RB diff --git a/drivers/net/dsa/realtek/realtek-mdio.c b/drivers/net/dsa/realtek/realtek-mdio.c index b7febd63e04f..1f80b6bdbe5b 100644 --- a/drivers/net/dsa/realtek/realtek-mdio.c +++ b/drivers/net/dsa/realtek/realtek-mdio.c @@ -265,6 +265,7 @@ static const struct of_device_id realtek_mdio_of_match[] = { { .compatible = "realtek,rtl8366s", .data = NULL, }, #if IS_ENABLED(CONFIG_NET_DSA_REALTEK_RTL8367C) { .compatible = "realtek,rtl8365mb", .data = &rtl8367c_variant, }, + { .compatible = "realtek,rtl8367s", .data = &rtl8367c_variant, }, #endif { /* sentinel */ }, }; diff --git a/drivers/net/dsa/realtek/realtek-smi.c b/drivers/net/dsa/realtek/realtek-smi.c index 258f90956cec..ecb68a216595 100644 --- a/drivers/net/dsa/realtek/realtek-smi.c +++ b/drivers/net/dsa/realtek/realtek-smi.c @@ -511,6 +511,10 @@ static const struct of_device_id realtek_smi_of_match[] = { .compatible = "realtek,rtl8365mb", .data = &rtl8367c_variant, }, + { + .compatible = "realtek,rtl8367s", + .data = &rtl8367c_variant, + }, #endif { /* sentinel */ }, }; diff --git a/drivers/net/dsa/realtek/rtl8367c.c b/drivers/net/dsa/realtek/rtl8367c.c index a478ddc33a9e..c192ede6ca88 100644 --- a/drivers/net/dsa/realtek/rtl8367c.c +++ b/drivers/net/dsa/realtek/rtl8367c.c @@ -90,15 +90,23 @@ #include "realtek.h" /* Chip-specific data and limits */ -#define RTL8367C_CHIP_ID_8365MB_VC 0x6367 +#define RTL8367C_CHIP_ID_8367C 0x6367 +/* 0x0276 and 0x0597 as well */ -#define RTL8367C_LEARN_LIMIT_MAX 2112 +#define RTL8367C_CHIP_ID_8365MB_VC RTL8367C_CHIP_ID_8367C +#define RTL8367C_CHIP_VER_8365MB_VC 0x0040 + +#define RTL8367C_CHIP_ID_8367S RTL8367C_CHIP_ID_8367C +#define RTL8367C_CHIP_VER_8367S 0x00A0 + +#define RTL8367C_LEARN_LIMIT_MAX 2112 /* Family-specific data and limits */ #define RTL8367C_PHYADDRMAX 7 #define RTL8367C_NUM_PHYREGS 32 #define RTL8367C_PHYREGMAX (RTL8367C_NUM_PHYREGS - 1) -#define RTL8367C_MAX_NUM_PORTS 7 +// RTL8370MB and RTL8310SR, possibly suportable by this driver, have 10 ports +#define RTL8367C_MAX_NUM_PORTS 10 /* Chip identification registers */ #define RTL8367C_CHIP_ID_REG 0x1300 @@ -1952,10 +1960,21 @@ static int rtl8367c_detect(struct realtek_priv *priv) } switch (chip_id) { - case RTL8367C_CHIP_ID_8365MB_VC: - dev_info(priv->dev, - "found an RTL8365MB-VC switch (ver=0x%04x)\n", - chip_ver); + case RTL8367C_CHIP_ID_8367C: + if (chip_ver == RTL8367C_CHIP_VER_8365MB_VC) { + dev_info(priv->dev, + "found an RTL8365MB-VC switch (ver=0x%04x)\n", + chip_ver); + } else if (chip_ver == RTL8367C_CHIP_VER_8367S) { + dev_info(priv->dev, + "found an RTL8367S switch (ver=0x%04x)\n", + chip_ver); + } else { + dev_err(priv->dev, "found an RTL8367C switch with " + "unrecognized chip version (ver=0x%04x)\n", + chip_ver); + return -ENODEV; + } priv->num_ports = RTL8367C_MAX_NUM_PORTS;