From patchwork Fri Dec 17 04:19:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 12683617 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 66513C433FE for ; Fri, 17 Dec 2021 04:20:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232700AbhLQEUO (ORCPT ); Thu, 16 Dec 2021 23:20:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44700 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232690AbhLQEUM (ORCPT ); Thu, 16 Dec 2021 23:20:12 -0500 Received: from mail-pg1-x52d.google.com (mail-pg1-x52d.google.com [IPv6:2607:f8b0:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B6157C061574; Thu, 16 Dec 2021 20:20:12 -0800 (PST) Received: by mail-pg1-x52d.google.com with SMTP id 133so940527pgc.12; Thu, 16 Dec 2021 20:20:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=t6iJOC5DPpuDKIOK7ECu/vvBO8ICNaPQRjhnRSWrI2g=; b=eh/ImVhg76S3I6ACNB7gF6t12Fi2/UhZL9hne6rMpoarNjMkiUj12v+uI0rPqCzyhU +9NvcDbul19TktjGZNW5nz3H3stj9pinILehEDljA9wWXVrOvvzXqlv8+NePLPBRrATQ rXeX74BM5pcmV06Mjr4TtqdGtSY4OFUAOfMcDjwliAtIcgn04XkLiWymlBy4+Pgzvmgp BhpMFjCl/gLqBKCxkKL6D4wJh+oPkdrV2awdV+tlyH9yscaRwkcDRF3UkxnUsuzVnM0W 6W7UeGvNqEbVPuUWmKFKdebdiM7e+XKrzvaK6PANYSQ2oNjfb13PXwHbevs5Q3gSSQK/ 9GDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=t6iJOC5DPpuDKIOK7ECu/vvBO8ICNaPQRjhnRSWrI2g=; b=UDneTA5pdRvwMmBoKB65WNUvGMeK239VKKD3su8QQG9VX3sw9QjOZ9c6N3jEPNN1DY tWnrYc7u9+EPLBkTqmuW8urayprvXOcrDvn4PNpnv+LOoNSj9XF6r5Yzpdg+ZR9P+RWL 8Rv0qGKn/uJKKI7QyT1PW31z+UonHFBQsddE8JHonZFjygi+72T2O2nYSASJyJlffhl+ Lv1Gwd0wwTZ7CEgG1wBOw0cUTNcnZKK8kL4SYdY2qsMnl5wbuhfu1tfbH3K7O94wDDRL r2oMN8bBza81QzCYHO5MJgaWUoJKrA0FrunVmFM5nawZsswfLul0zzzKjEwoqsoH6jml 644w== X-Gm-Message-State: AOAM533mJQL+NuX6SDZJxE4sJjKdVK4zksNvD0cc/KwxdHU34grySpfg R1HcLHLk++FocpcRjKAVFdE5JAN9kfE= X-Google-Smtp-Source: ABdhPJw4xYAzWHY8vlcb1RcDXHF6isTLeI+gjmgauvYO12IB4YpHoHrjptTPaxNMSKDmqT1xUIn1vg== X-Received: by 2002:a62:3888:0:b0:4a9:5e0e:8b99 with SMTP id f130-20020a623888000000b004a95e0e8b99mr1248155pfa.30.1639714811708; Thu, 16 Dec 2021 20:20:11 -0800 (PST) Received: from fainelli-desktop.igp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id mq10sm7553496pjb.3.2021.12.16.20.20.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Dec 2021 20:20:11 -0800 (PST) From: Florian Fainelli To: devicetree@vger.kernel.org Cc: Florian Fainelli , Damien Le Moal , Rob Herring , Thomas Gleixner , Marc Zyngier , bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE), Greg Kroah-Hartman , Al Cooper , Ray Jui , Scott Branden , linux-ide@vger.kernel.org (open list:LIBATA SUBSYSTEM (Serial and Parallel ATA drivers)), linux-kernel@vger.kernel.org (open list), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE), linux-usb@vger.kernel.org (open list:USB SUBSYSTEM) Subject: [PATCH v4 1/6] dt-bindings: interrupt-controller: Convert BCM7120 L2 to YAML Date: Thu, 16 Dec 2021 20:19:56 -0800 Message-Id: <20211217042001.479577-2-f.fainelli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211217042001.479577-1-f.fainelli@gmail.com> References: <20211217042001.479577-1-f.fainelli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Convert the Broadcom BCM7120 Level 2 interrupt controller Device Tree binding to YAML to help with validation. Signed-off-by: Florian Fainelli --- .../brcm,bcm7120-l2-intc.txt | 88 ------------- .../brcm,bcm7120-l2-intc.yaml | 124 ++++++++++++++++++ 2 files changed, 124 insertions(+), 88 deletions(-) delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt deleted file mode 100644 index addd86b6ca2f..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt +++ /dev/null @@ -1,88 +0,0 @@ -Broadcom BCM7120-style Level 2 interrupt controller - -This interrupt controller hardware is a second level interrupt controller that -is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based -platforms. It can be found on BCM7xxx products starting with BCM7120. - -Such an interrupt controller has the following hardware design: - -- outputs multiple interrupts signals towards its interrupt controller parent - -- controls how some of the interrupts will be flowing, whether they will - directly output an interrupt signal towards the interrupt controller parent, - or if they will output an interrupt signal at this 2nd level interrupt - controller, in particular for UARTs - -- has one 32-bit enable word and one 32-bit status word - -- no atomic set/clear operations - -- not all bits within the interrupt controller actually map to an interrupt - -The typical hardware layout for this controller is represented below: - -2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC) - -0 -----[ MUX ] ------------|==========> GIC interrupt 75 - \-----------\ - | -1 -----[ MUX ] --------)---|==========> GIC interrupt 76 - \------------| - | -2 -----[ MUX ] --------)---|==========> GIC interrupt 77 - \------------| - | -3 ---------------------| -4 ---------------------| -5 ---------------------| -7 ---------------------|---|===========> GIC interrupt 66 -9 ---------------------| -10 --------------------| -11 --------------------/ - -6 ------------------------\ - |===========> GIC interrupt 64 -8 ------------------------/ - -12 ........................ X -13 ........................ X (not connected) -.. -31 ........................ X - -Required properties: - -- compatible: should be "brcm,bcm7120-l2-intc" -- reg: specifies the base physical address and size of the registers -- interrupt-controller: identifies the node as an interrupt controller -- #interrupt-cells: specifies the number of cells needed to encode an interrupt - source, should be 1. -- interrupts: specifies the interrupt line(s) in the interrupt-parent controller - node, valid values depend on the type of parent interrupt controller -- brcm,int-map-mask: 32-bits bit mask describing how many and which interrupts - are wired to this 2nd level interrupt controller, and how they match their - respective interrupt parents. Should match exactly the number of interrupts - specified in the 'interrupts' property. - -Optional properties: - -- brcm,irq-can-wake: if present, this means the L2 controller can be used as a - wakeup source for system suspend/resume. - -- brcm,int-fwd-mask: if present, a bit mask to configure the interrupts which - have a mux gate, typically UARTs. Setting these bits will make their - respective interrupt outputs bypass this 2nd level interrupt controller - completely; it is completely transparent for the interrupt controller - parent. This should have one 32-bit word per enable/status pair. - -Example: - -irq0_intc: interrupt-controller@f0406800 { - compatible = "brcm,bcm7120-l2-intc"; - interrupt-parent = <&intc>; - #interrupt-cells = <1>; - reg = <0xf0406800 0x8>; - interrupt-controller; - interrupts = <0x0 0x42 0x0>, <0x0 0x40 0x0>; - brcm,int-map-mask = <0xeb8>, <0x140>; - brcm,int-fwd-mask = <0x7>; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml new file mode 100644 index 000000000000..e10c9879f3f8 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7120-l2-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM7120-style Level 2 interrupt controller + +maintainers: + - Florian Fainelli + +description: > + This interrupt controller hardware is a second level interrupt controller that + is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based + platforms. It can be found on BCM7xxx products starting with BCM7120. + + Such an interrupt controller has the following hardware design: + + - outputs multiple interrupts signals towards its interrupt controller parent + + - controls how some of the interrupts will be flowing, whether they will + directly output an interrupt signal towards the interrupt controller parent, + or if they will output an interrupt signal at this 2nd level interrupt + controller, in particular for UARTs + + - has one 32-bit enable word and one 32-bit status word + + - no atomic set/clear operations + + - not all bits within the interrupt controller actually map to an interrupt + + The typical hardware layout for this controller is represented below: + + 2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC) + + 0 -----[ MUX ] ------------|==========> GIC interrupt 75 + \-----------\ + | + 1 -----[ MUX ] --------)---|==========> GIC interrupt 76 + \------------| + | + 2 -----[ MUX ] --------)---|==========> GIC interrupt 77 + \------------| + | + 3 ---------------------| + 4 ---------------------| + 5 ---------------------| + 7 ---------------------|---|===========> GIC interrupt 66 + 9 ---------------------| + 10 --------------------| + 11 --------------------/ + + 6 ------------------------\ + |===========> GIC interrupt 64 + 8 ------------------------/ + + 12 ........................ X + 13 ........................ X (not connected) + .. + 31 ........................ X + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +properties: + compatible: + const: brcm,bcm7120-l2-intc + + reg: + maxItems: 1 + description: > + Specifies the base physical address and size of the registers + + interrupt-controller: true + + "#interrupt-cells": + const: 1 + + interrupts: true + + brcm,int-map-mask: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: > + 32-bits bit mask describing how many and which interrupts are wired to + this 2nd level interrupt controller, and how they match their respective + interrupt parents. Should match exactly the number of interrupts + specified in the 'interrupts' property. + + brcm,irq-can-wake: + type: boolean + description: > + If present, this means the L2 controller can be used as a wakeup source + for system suspend/resume. + + brcm,int-fwd-mask: + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + if present, a bit mask to configure the interrupts which have a mux gate, + typically UARTs. Setting these bits will make their respective interrupt + outputs bypass this 2nd level interrupt controller completely; it is + completely transparent for the interrupt controller parent. This should + have one 32-bit word per enable/status pair. + +additionalProperties: false + +required: + - compatible + - reg + - interrupt-controller + - "#interrupt-cells" + - interrupts + +examples: + - | + irq0_intc: interrupt-controller@f0406800 { + compatible = "brcm,bcm7120-l2-intc"; + interrupt-parent = <&intc>; + #interrupt-cells = <1>; + reg = <0xf0406800 0x8>; + interrupt-controller; + interrupts = <0x0 0x42 0x0>, <0x0 0x40 0x0>; + brcm,int-map-mask = <0xeb8>, <0x140>; + brcm,int-fwd-mask = <0x7>; + }; From patchwork Fri Dec 17 04:19:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 12683615 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B8A63C43219 for ; Fri, 17 Dec 2021 04:20:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232724AbhLQEUP (ORCPT ); Thu, 16 Dec 2021 23:20:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44710 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232655AbhLQEUO (ORCPT ); Thu, 16 Dec 2021 23:20:14 -0500 Received: from mail-pg1-x531.google.com (mail-pg1-x531.google.com [IPv6:2607:f8b0:4864:20::531]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6EC1BC061574; Thu, 16 Dec 2021 20:20:14 -0800 (PST) Received: by mail-pg1-x531.google.com with SMTP id j11so978079pgs.2; Thu, 16 Dec 2021 20:20:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zmWmnK0WKuVDlmt6wZDvsvjiu/QeAOZ/HlwwvclxrtM=; b=Ybhk1b4BaJOqomxkyCHZ4XMGvXqjydFRoks6iuNTckp2o2xUXKgGPdJWS4SFNIPncq coTDZqjmo3oOw4TLb0vcIxQEwMk6fAj8aJOVcHEv5kvQwVN4KZCBmfr4YWpxTBKB6vPT YLYTb/z/cD38fc3QmAlpmbGsX3O7/degx0sSEkWgD5Nqgv1z2AVZG6ZMWaGBJjcgCkBl Q39FcdOIjh93plaqRvZmCg7Tqa258GK+RQSa9rnkm81IDQd6s3A5MZW/aTjlzDeR0z5N wYySbv05CRf3KfRP+zZAnWST/a/L6GnrucUC97F3gEbRr55fP+Y2HzriPVJ8MblpPMdt J76w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zmWmnK0WKuVDlmt6wZDvsvjiu/QeAOZ/HlwwvclxrtM=; b=UNW2oXibRnGzWTw6jW4vC/+A/ZoYjOkUeA/rY7/EvAh431DXWH6eV2VHECzw2L1opd Wp7FEMmCwH5nSiyX0x5qXwHU2jq4yu2Eph731X4lTA+bWsXkLeCH/UjnB0X937UPSVlo zNyjd7vUlgYT7GpZ0SqiqxdcX4ZncV9uGUNRaEKEa97Ha9snGTcaPqX/DJbvojtnuk24 r1TbQ8nmV/R2741w+jLvTNf7r8fQdvgJgDMhT3niwj//QflJ/H9fp/OjfM8YBPJH9bu2 yxy9ogxR/ah746766SN4yiQRZ05ZwQfo4gjhsj6YM+/7WufXOeucnZ1umzqJUIdyIVPj O2kA== X-Gm-Message-State: AOAM532gQfj40UwmS7cEOHXUJWLCYCCi5SxH4/e/zJlenMsv31ANZ4OR wzE4cethT+ECwDFtWczlkqHEvSucd9I= X-Google-Smtp-Source: ABdhPJwRc0wxumUjAqE7UXbvEOVWjFwqAsMctaFrs3Y1yy1SZWrTHc5v1rt+2HJdjTJQREQaitwdmA== X-Received: by 2002:a65:4889:: with SMTP id n9mr1279475pgs.303.1639714813569; Thu, 16 Dec 2021 20:20:13 -0800 (PST) Received: from fainelli-desktop.igp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id mq10sm7553496pjb.3.2021.12.16.20.20.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Dec 2021 20:20:13 -0800 (PST) From: Florian Fainelli To: devicetree@vger.kernel.org Cc: Florian Fainelli , Damien Le Moal , Rob Herring , Thomas Gleixner , Marc Zyngier , bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE), Greg Kroah-Hartman , Al Cooper , Ray Jui , Scott Branden , linux-ide@vger.kernel.org (open list:LIBATA SUBSYSTEM (Serial and Parallel ATA drivers)), linux-kernel@vger.kernel.org (open list), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE), linux-usb@vger.kernel.org (open list:USB SUBSYSTEM) Subject: [PATCH v4 2/6] dt-bindings: interrupt-controller: Merge BCM3380 with BCM7120 Date: Thu, 16 Dec 2021 20:19:57 -0800 Message-Id: <20211217042001.479577-3-f.fainelli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211217042001.479577-1-f.fainelli@gmail.com> References: <20211217042001.479577-1-f.fainelli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org The two bindings are very similar and should be covered by the same document, do that so we can get rid of an additional binding file. Signed-off-by: Florian Fainelli --- .../brcm,bcm3380-l2-intc.txt | 39 ------------------- .../brcm,bcm7120-l2-intc.yaml | 31 +++++++++++++-- 2 files changed, 28 insertions(+), 42 deletions(-) delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm3380-l2-intc.txt diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm3380-l2-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm3380-l2-intc.txt deleted file mode 100644 index 37aea40d5430..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm3380-l2-intc.txt +++ /dev/null @@ -1,39 +0,0 @@ -Broadcom BCM3380-style Level 1 / Level 2 interrupt controller - -This interrupt controller shows up in various forms on many BCM338x/BCM63xx -chipsets. It has the following properties: - -- outputs a single interrupt signal to its interrupt controller parent - -- contains one or more enable/status word pairs, which often appear at - different offsets in different blocks - -- no atomic set/clear operations - -Required properties: - -- compatible: should be "brcm,bcm3380-l2-intc" -- reg: specifies one or more enable/status pairs, in the following format: - ... -- interrupt-controller: identifies the node as an interrupt controller -- #interrupt-cells: specifies the number of cells needed to encode an interrupt - source, should be 1. -- interrupts: specifies the interrupt line in the interrupt-parent controller - node, valid values depend on the type of parent interrupt controller - -Optional properties: - -- brcm,irq-can-wake: if present, this means the L2 controller can be used as a - wakeup source for system suspend/resume. - -Example: - -irq0_intc: interrupt-controller@10000020 { - compatible = "brcm,bcm3380-l2-intc"; - reg = <0x10000024 0x4 0x1000002c 0x4>, - <0x10000020 0x4 0x10000028 0x4>; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&cpu_intc>; - interrupts = <2>; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml index e10c9879f3f8..d24493fe246c 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7120-l2-intc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Broadcom BCM7120-style Level 2 interrupt controller +title: Broadcom BCM7120-style Level 2 and Broadcom BCM3380 Level 1 / Level 2 maintainers: - Florian Fainelli @@ -59,15 +59,29 @@ description: > .. 31 ........................ X + The BCM3380 Level 1 / Level 2 interrrupt controller shows up in various forms + on many BCM338x/BCM63xx chipsets. It has the following properties: + + - outputs a single interrupt signal to its interrupt controller parent + + - contains one or more enable/status word pairs, which often appear at + different offsets in different blocks + + - no atomic set/clear operations + allOf: - $ref: /schemas/interrupt-controller.yaml# properties: compatible: - const: brcm,bcm7120-l2-intc + items: + - enum: + - brcm,bcm7120-l2-intc + - brcm,bcm3380-l2-intc reg: - maxItems: 1 + minItems: 1 + maxItems: 4 description: > Specifies the base physical address and size of the registers @@ -122,3 +136,14 @@ examples: brcm,int-map-mask = <0xeb8>, <0x140>; brcm,int-fwd-mask = <0x7>; }; + + - | + irq1_intc: interrupt-controller@10000020 { + compatible = "brcm,bcm3380-l2-intc"; + reg = <0x10000024 0x4>, <0x1000002c 0x4>, + <0x10000020 0x4>, <0x10000028 0x4>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&cpu_intc>; + interrupts = <2>; + }; From patchwork Fri Dec 17 04:19:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 12683619 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6EACAC433EF for ; Fri, 17 Dec 2021 04:20:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232789AbhLQEUW (ORCPT ); Thu, 16 Dec 2021 23:20:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44720 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232728AbhLQEUQ (ORCPT ); Thu, 16 Dec 2021 23:20:16 -0500 Received: from mail-pg1-x533.google.com (mail-pg1-x533.google.com [IPv6:2607:f8b0:4864:20::533]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5F03CC06173E; Thu, 16 Dec 2021 20:20:16 -0800 (PST) Received: by mail-pg1-x533.google.com with SMTP id 200so972437pgg.3; Thu, 16 Dec 2021 20:20:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hvQSZSJjmQDhoVNAws8o0GpYR+Fym5ONsESevW2QHHo=; b=VCLMgUs3P2HRhSbZzwxM1P5j9NYLF+tWlrBYBKuNZQV0ComR8SANLymGpQtIksO75I p/BNZf/3NNAplUfm34AXrjqvIGkh+pwNeolLwI7hnxom+j8LpEJklqNVAP71AKDW+IQr HvWF+0f1ikF3zI4+puJ9zMcA5ObqPp2Q90a1RcuaL7NEC31UrWEIorFJYyrClhbelmR/ g2/WOES0f/Hz/dA0RFpsePJKwpxOgLGnFRYjDNnGAKSienFFR21Fjx9CSaDFxwtP6khr W7lEmY+t8JqM3aPcvEXk24lpgGeUE+wt6WMmfzwQa2XOtV3r+IxPJUuOcCwJotRaace4 JxKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hvQSZSJjmQDhoVNAws8o0GpYR+Fym5ONsESevW2QHHo=; b=Mxh9bKymEPKIFXvUHBQuVWzH6871giBiDnmYulktvzbGFT5J+RTJ7kZGCka1OWCKP8 HtvYUxAt/6i5kwkefRycn9eQW1Gt3q4BXUCyek3z8EGxqT377y1KR5BCSIlH+M57djBq VU3LSZzJWp2JxRx8HNR58SsjgB6lLYIwtTswfy3M1jBOG7QDQF4qjH0tyFgFhrE5fPZo OaE1JgXAwkEewSGpHiVIjnZiNhqPFBL3v+BDt0Ium7iGEGizg8R6L15OcGgEzamCoedw HJcPfHFxsRywWng/+KdRgyYhTo2OzfnXZ/Qa7Ey3kWrbYSjJd0E88XmpbVBmwVidyjTx WjlA== X-Gm-Message-State: AOAM532dhklfIQ5+Xml9c5Qiw1PwcwT6xBLE9cC/7Wx3hWQrg/H/CoyN oIB6Jox15drI4ObQCczaEh3S2YaxaF8= X-Google-Smtp-Source: ABdhPJwkisUtzEda3tzD4bYdOMoMHn17gkOvTZhkm5bs9qxmGRaGjO45sdXG/2Elh4jamoSMvLNGcA== X-Received: by 2002:a63:8bc4:: with SMTP id j187mr1281031pge.189.1639714815537; Thu, 16 Dec 2021 20:20:15 -0800 (PST) Received: from fainelli-desktop.igp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id mq10sm7553496pjb.3.2021.12.16.20.20.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Dec 2021 20:20:15 -0800 (PST) From: Florian Fainelli To: devicetree@vger.kernel.org Cc: Florian Fainelli , Damien Le Moal , Rob Herring , Thomas Gleixner , Marc Zyngier , bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE), Greg Kroah-Hartman , Al Cooper , Ray Jui , Scott Branden , linux-ide@vger.kernel.org (open list:LIBATA SUBSYSTEM (Serial and Parallel ATA drivers)), linux-kernel@vger.kernel.org (open list), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE), linux-usb@vger.kernel.org (open list:USB SUBSYSTEM) Subject: [PATCH v4 3/6] ARM: dts: NSP: Rename SATA unit name Date: Thu, 16 Dec 2021 20:19:58 -0800 Message-Id: <20211217042001.479577-4-f.fainelli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211217042001.479577-1-f.fainelli@gmail.com> References: <20211217042001.479577-1-f.fainelli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Rename the SATA controller unit name from ahci to sata in preparation for adding the Broadcom SATA3 controller YAML binding which will bring validation. Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-nsp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index 1c08daa18858..ded5a59e0679 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -534,7 +534,7 @@ sata_phy1: sata-phy@1 { }; }; - sata: ahci@41000 { + sata: sata@41000 { compatible = "brcm,bcm-nsp-ahci"; reg-names = "ahci", "top-ctrl"; reg = <0x41000 0x1000>, <0x40020 0x1c>; From patchwork Fri Dec 17 04:19:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 12683621 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 04B7FC43217 for ; Fri, 17 Dec 2021 04:20:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232797AbhLQEUY (ORCPT ); Thu, 16 Dec 2021 23:20:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44744 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232747AbhLQEUU (ORCPT ); Thu, 16 Dec 2021 23:20:20 -0500 Received: from mail-pj1-x1032.google.com (mail-pj1-x1032.google.com [IPv6:2607:f8b0:4864:20::1032]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3FFB7C061747; Thu, 16 Dec 2021 20:20:18 -0800 (PST) Received: by mail-pj1-x1032.google.com with SMTP id v13-20020a17090a088d00b001b0e3a74cf7so3397396pjc.1; Thu, 16 Dec 2021 20:20:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LopG2br+9EBkgFCWCvvz7i5E0kmkV07MyNs9kSUl6Qs=; b=dVRGlh5gdS7+FzRPuTDAREASjyY9nZx8ZRYPkvBlroQQYhPbfY0Vs7AUHRBnAPG6FR QCAIkn7lI8re6rCaK1o7EmMr37N+HiMZrn8tDHEL+QMX2EfKafaQZu7yzTL2UcXLfu0r q3OE91miOxpj5qYMKttufbFiZRtIzDocyUVQl2bKbtHGzPsbMtlfqq4fqhlAt6iKkHOD O+0nx1vF9vjaAuN9ULYJBCpwPTKuGgT1+moLTE1gbcApWIOqkNmXEojWI2C3Om2CV1MX DirJhH+0JzDD64QyZ5ezX7FjBI8sIDbMQ9ZEIidgh8+FWBqc7ImZpNk4kb5XkcYWuyst bcdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LopG2br+9EBkgFCWCvvz7i5E0kmkV07MyNs9kSUl6Qs=; b=bW6KwYownt32jEF4xWkTXNJug01vDAxMx6fuUkWss/8N/LCWguD7Npbut4e2Nww+gk SajZUbi+J0RJ8Yr7gW7DtCgRFbA8KjckwNeawI35bgF0wprtPH5xrS5Tfos580DZw9Bm HNNcq+Y0LN18F2TXKplDyWDMB4MZ+5PdQAHNd7l+HWtdIe2F4MsR/+sV/8czSyaj1gkt NAm14st0TJ8PHCJEZAztJgYgkRpwG4wZASxFlYdyW4F9/Oc9rRE/gSKkeXI6Q6tFvej3 Fs+8r/e+YiyjuExdLw9Rsr7ydHys0Z4N8oWx4DRzSJSrKB9QDwogQRn+D+Wq3kWpe57f 3CKw== X-Gm-Message-State: AOAM5325dd0sKbfiE0UVDtuREMyoiqgAhQ3FrTbOKbrqdp3y3pL6iW9P AjAdVBcL887R3DFjRewu3XKOsawp/u0= X-Google-Smtp-Source: ABdhPJzF4eI6Lj2lVooltyfuOQeuC75yPK4VP5B07vClQbXFNYg1RVkN3gJhf1zKOlrbvGmeQ4czvA== X-Received: by 2002:a17:90b:3758:: with SMTP id ne24mr1664848pjb.59.1639714817399; Thu, 16 Dec 2021 20:20:17 -0800 (PST) Received: from fainelli-desktop.igp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id mq10sm7553496pjb.3.2021.12.16.20.20.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Dec 2021 20:20:16 -0800 (PST) From: Florian Fainelli To: devicetree@vger.kernel.org Cc: Florian Fainelli , Damien Le Moal , Rob Herring , Thomas Gleixner , Marc Zyngier , bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE), Greg Kroah-Hartman , Al Cooper , Ray Jui , Scott Branden , linux-ide@vger.kernel.org (open list:LIBATA SUBSYSTEM (Serial and Parallel ATA drivers)), linux-kernel@vger.kernel.org (open list), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE), linux-usb@vger.kernel.org (open list:USB SUBSYSTEM) Subject: [PATCH v4 4/6] dt-bindings: ata: Convert Broadcom SATA to YAML Date: Thu, 16 Dec 2021 20:19:59 -0800 Message-Id: <20211217042001.479577-5-f.fainelli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211217042001.479577-1-f.fainelli@gmail.com> References: <20211217042001.479577-1-f.fainelli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Convert the Broadcom SATA3 AHCI controller Device Tree binding to YAML to help with validation. Acked-by: Damien Le Moal Signed-off-by: Florian Fainelli --- .../bindings/ata/brcm,sata-brcm.txt | 45 ---------- .../bindings/ata/brcm,sata-brcm.yaml | 90 +++++++++++++++++++ 2 files changed, 90 insertions(+), 45 deletions(-) delete mode 100644 Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt create mode 100644 Documentation/devicetree/bindings/ata/brcm,sata-brcm.yaml diff --git a/Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt b/Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt deleted file mode 100644 index b9ae4ce4a0a0..000000000000 --- a/Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt +++ /dev/null @@ -1,45 +0,0 @@ -* Broadcom SATA3 AHCI Controller - -SATA nodes are defined to describe on-chip Serial ATA controllers. -Each SATA controller should have its own node. - -Required properties: -- compatible : should be one or more of - "brcm,bcm7216-ahci" - "brcm,bcm7425-ahci" - "brcm,bcm7445-ahci" - "brcm,bcm-nsp-ahci" - "brcm,sata3-ahci" - "brcm,bcm63138-ahci" -- reg : register mappings for AHCI and SATA_TOP_CTRL -- reg-names : "ahci" and "top-ctrl" -- interrupts : interrupt mapping for SATA IRQ - -Optional properties: - -- reset: for "brcm,bcm7216-ahci" must be a valid reset phandle - pointing to the RESCAL reset controller provider node. -- reset-names: for "brcm,bcm7216-ahci", must be "rescal". - -Also see ahci-platform.txt. - -Example: - - sata@f045a000 { - compatible = "brcm,bcm7445-ahci", "brcm,sata3-ahci"; - reg = <0xf045a000 0xa9c>, <0xf0458040 0x24>; - reg-names = "ahci", "top-ctrl"; - interrupts = <0 30 0>; - #address-cells = <1>; - #size-cells = <0>; - - sata0: sata-port@0 { - reg = <0>; - phys = <&sata_phy 0>; - }; - - sata1: sata-port@1 { - reg = <1>; - phys = <&sata_phy 1>; - }; - }; diff --git a/Documentation/devicetree/bindings/ata/brcm,sata-brcm.yaml b/Documentation/devicetree/bindings/ata/brcm,sata-brcm.yaml new file mode 100644 index 000000000000..235a93ac86b0 --- /dev/null +++ b/Documentation/devicetree/bindings/ata/brcm,sata-brcm.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ata/brcm,sata-brcm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom SATA3 AHCI Controller + +description: + SATA nodes are defined to describe on-chip Serial ATA controllers. + Each SATA controller should have its own node. + +maintainers: + - Florian Fainelli + +allOf: + - $ref: sata-common.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - brcm,bcm7216-ahci + - brcm,bcm7445-ahci + - brcm,bcm7425-ahci + - brcm,bcm63138-ahci + - const: brcm,sata3-ahci + - items: + - const: brcm,bcm-nsp-ahci + + reg: + minItems: 2 + maxItems: 2 + + reg-names: + items: + - const: ahci + - const: top-ctrl + + interrupts: + maxItems: 1 + + dma-coherent: true + +if: + properties: + compatible: + contains: + enum: + - brcm,bcm7216-ahci + - brcm,bcm63138-ahci +then: + properties: + resets: + maxItems: 1 + reset-names: + enum: + - rescal + - ahci + +required: + - compatible + - reg + - interrupts + - "#address-cells" + - "#size-cells" + +unevaluatedProperties: false + +examples: + - | + sata@f045a000 { + compatible = "brcm,bcm7445-ahci", "brcm,sata3-ahci"; + reg = <0xf045a000 0xa9c>, <0xf0458040 0x24>; + reg-names = "ahci", "top-ctrl"; + interrupts = <0 30 0>; + #address-cells = <1>; + #size-cells = <0>; + + sata0: sata-port@0 { + reg = <0>; + phys = <&sata_phy 0>; + }; + + sata1: sata-port@1 { + reg = <1>; + phys = <&sata_phy 1>; + }; + }; From patchwork Fri Dec 17 04:20:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 12683623 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B14CBC433F5 for ; Fri, 17 Dec 2021 04:20:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232753AbhLQEUZ (ORCPT ); Thu, 16 Dec 2021 23:20:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44758 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232756AbhLQEUV (ORCPT ); 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Thu, 16 Dec 2021 20:20:18 -0800 (PST) From: Florian Fainelli To: devicetree@vger.kernel.org Cc: Florian Fainelli , Damien Le Moal , Rob Herring , Thomas Gleixner , Marc Zyngier , bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE), Greg Kroah-Hartman , Al Cooper , Ray Jui , Scott Branden , linux-ide@vger.kernel.org (open list:LIBATA SUBSYSTEM (Serial and Parallel ATA drivers)), linux-kernel@vger.kernel.org (open list), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE), linux-usb@vger.kernel.org (open list:USB SUBSYSTEM) Subject: [PATCH v4 5/6] dt-bindings: bus: Convert GISB arbiter to YAML Date: Thu, 16 Dec 2021 20:20:00 -0800 Message-Id: <20211217042001.479577-6-f.fainelli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211217042001.479577-1-f.fainelli@gmail.com> References: <20211217042001.479577-1-f.fainelli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Convert the Broadcom STB GISB bus arbiter to YAML to help with validation. Signed-off-by: Florian Fainelli --- .../devicetree/bindings/bus/brcm,gisb-arb.txt | 34 ---------- .../bindings/bus/brcm,gisb-arb.yaml | 66 +++++++++++++++++++ 2 files changed, 66 insertions(+), 34 deletions(-) delete mode 100644 Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt create mode 100644 Documentation/devicetree/bindings/bus/brcm,gisb-arb.yaml diff --git a/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt b/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt deleted file mode 100644 index 10f6d0a8159d..000000000000 --- a/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt +++ /dev/null @@ -1,34 +0,0 @@ -Broadcom GISB bus Arbiter controller - -Required properties: - -- compatible: - "brcm,bcm7278-gisb-arb" for V7 28nm chips - "brcm,gisb-arb" or "brcm,bcm7445-gisb-arb" for other 28nm chips - "brcm,bcm7435-gisb-arb" for newer 40nm chips - "brcm,bcm7400-gisb-arb" for older 40nm chips and all 65nm chips - "brcm,bcm7038-gisb-arb" for 130nm chips -- reg: specifies the base physical address and size of the registers -- interrupts: specifies the two interrupts (timeout and TEA) to be used from - the parent interrupt controller. A third optional interrupt may be specified - for breakpoints. - -Optional properties: - -- brcm,gisb-arb-master-mask: 32-bits wide bitmask used to specify which GISB - masters are valid at the system level -- brcm,gisb-arb-master-names: string list of the litteral name of the GISB - masters. Should match the number of bits set in brcm,gisb-master-mask and - the order in which they appear - -Example: - -gisb-arb@f0400000 { - compatible = "brcm,gisb-arb"; - reg = <0xf0400000 0x800>; - interrupts = <0>, <2>; - interrupt-parent = <&sun_l2_intc>; - - brcm,gisb-arb-master-mask = <0x7>; - brcm,gisb-arb-master-names = "bsp_0", "scpu_0", "cpu_0"; -}; diff --git a/Documentation/devicetree/bindings/bus/brcm,gisb-arb.yaml b/Documentation/devicetree/bindings/bus/brcm,gisb-arb.yaml new file mode 100644 index 000000000000..b23c3001991e --- /dev/null +++ b/Documentation/devicetree/bindings/bus/brcm,gisb-arb.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/brcm,gisb-arb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom GISB bus Arbiter controller + +maintainers: + - Florian Fainelli + +properties: + compatible: + oneOf: + - items: + - enum: + - brcm,bcm7445-gisb-arb # for other 28nm chips + - const: brcm,gisb-arb + - items: + - enum: + - brcm,bcm7278-gisb-arb # for V7 28nm chips + - brcm,bcm7435-gisb-arb # for newer 40nm chips + - brcm,bcm7400-gisb-arb # for older 40nm chips and all 65nm chips + - brcm,bcm7038-gisb-arb # for 130nm chips + - brcm,gisb-arb # fallback compatible + + reg: + maxItems: 1 + + interrupts: + minItems: 2 + items: + - description: timeout interrupt line + - description: target abort interrupt line + - description: breakpoint interrupt line + + brcm,gisb-arb-master-mask: + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + 32-bits wide bitmask used to specify which GISB masters are valid at the + system level + + brcm,gisb-arb-master-names: + $ref: /schemas/types.yaml#/definitions/string-array + description: > + String list of the litteral name of the GISB masters. Should match the + number of bits set in brcm,gisb-master-mask and the order in which they + appear from MSB to LSB. + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + gisb-arb@f0400000 { + compatible = "brcm,gisb-arb"; + reg = <0xf0400000 0x800>; + interrupts = <0>, <2>; + interrupt-parent = <&sun_l2_intc>; + brcm,gisb-arb-master-mask = <0x7>; + brcm,gisb-arb-master-names = "bsp_0", "scpu_0", "cpu_0"; + }; From patchwork Fri Dec 17 04:20:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 12683625 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9B13CC4332F for ; Fri, 17 Dec 2021 04:20:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232762AbhLQEUb (ORCPT ); Thu, 16 Dec 2021 23:20:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44752 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232782AbhLQEUW (ORCPT ); Thu, 16 Dec 2021 23:20:22 -0500 Received: from mail-pg1-x52e.google.com (mail-pg1-x52e.google.com [IPv6:2607:f8b0:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F379AC06173E; Thu, 16 Dec 2021 20:20:21 -0800 (PST) Received: by mail-pg1-x52e.google.com with SMTP id a23so969489pgm.4; Thu, 16 Dec 2021 20:20:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ieSmX+5TUTroa8wpdRCdIiNWCBAnggfwpKp3Xk+VqbI=; b=F/po5oCu+WsIqbYhXeVZ/xLt7WIGKIk+eW+tUokvAvPAOMyyqFdtvIiU3sMkF051tz 1KudGZ2tchYF7H5aEgcte1CHuMVLQPvSDj0bY6VBfOrA/crk7e0TOh7EZDCfP7n6D+e5 JRHrctv0ZAsVGwumNjZRSE+fCPfybe6tikYYbzB0GiC2okkLCSvpXq1wBYSJcMFZyhS5 hSI1IVGQEORmoGMiiqo/Nm14rjWtkUgd4C6CsoPWrHetIW2E4UpR8o2N59MWdEEVbPbf PtG5Erep4wOF+ngnr/7aU5YVyw2CeqL/8pZh20zkY2/f7w7FprylB+O7B/jNf57BgIh0 H4Ng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ieSmX+5TUTroa8wpdRCdIiNWCBAnggfwpKp3Xk+VqbI=; b=Dt0A6sYnoKvGPRy3okxzxfi490PaseWCzBkhC4B8dfeJTY1BCOIi0Ly7xU7hVwgh1P 0jNbSAiwaKRqZPmvKKAoTmRkjONgQtidcf/CWvdZ5di1C2P/lV+JXJ3HcUuud2nj8fr7 BT3SJjf13LSfDA8q+MmD2cA4n0GJ/Tf4c/H0hEEPXv9HTjr7uA5V3t3J4phTv1RAVXwG CGITXs6VRVC7EPSC2BsODrFrSMK3oy3EK7HJ7xxByyrt0CIjNX5dlLPlA2/JGdcHzIZW BWhU+260HK9annx2WSjPzYlDel9O4S+zdyu0l72G95BZ7rHKB+zt8n6kWk1k3QWamI3Z zS4w== X-Gm-Message-State: AOAM530CHZyRXdx9gwAAC5PVUVB+abtZtPqMHexHSKvB4PZMlfaro9z5 L0zbeASvNsFPEp67z8vCfvT8RXK8mGU= X-Google-Smtp-Source: ABdhPJyu0yis2GMSgTTY1EHcgCTH9yVzZcUbaIQtRNg7Fci35upHl+yrbt7ETwj85/2S0TfFTG/Edw== X-Received: by 2002:a65:5bc4:: with SMTP id o4mr1238841pgr.489.1639714821151; Thu, 16 Dec 2021 20:20:21 -0800 (PST) Received: from fainelli-desktop.igp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id mq10sm7553496pjb.3.2021.12.16.20.20.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Dec 2021 20:20:20 -0800 (PST) From: Florian Fainelli To: devicetree@vger.kernel.org Cc: Florian Fainelli , Damien Le Moal , Rob Herring , Thomas Gleixner , Marc Zyngier , bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE), Greg Kroah-Hartman , Al Cooper , Ray Jui , Scott Branden , linux-ide@vger.kernel.org (open list:LIBATA SUBSYSTEM (Serial and Parallel ATA drivers)), linux-kernel@vger.kernel.org (open list), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE), linux-usb@vger.kernel.org (open list:USB SUBSYSTEM) Subject: [PATCH v4 6/6] dt-bindings: usb: Convert BDC to YAML Date: Thu, 16 Dec 2021 20:20:01 -0800 Message-Id: <20211217042001.479577-7-f.fainelli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211217042001.479577-1-f.fainelli@gmail.com> References: <20211217042001.479577-1-f.fainelli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Convert the Broadcom BDC device controller Device Tree binding to YAML to help with validation. Signed-off-by: Florian Fainelli --- .../devicetree/bindings/usb/brcm,bdc.txt | 29 ----------- .../devicetree/bindings/usb/brcm,bdc.yaml | 49 +++++++++++++++++++ MAINTAINERS | 2 +- 3 files changed, 50 insertions(+), 30 deletions(-) delete mode 100644 Documentation/devicetree/bindings/usb/brcm,bdc.txt create mode 100644 Documentation/devicetree/bindings/usb/brcm,bdc.yaml diff --git a/Documentation/devicetree/bindings/usb/brcm,bdc.txt b/Documentation/devicetree/bindings/usb/brcm,bdc.txt deleted file mode 100644 index c9f52b97cef1..000000000000 --- a/Documentation/devicetree/bindings/usb/brcm,bdc.txt +++ /dev/null @@ -1,29 +0,0 @@ -Broadcom USB Device Controller (BDC) -==================================== - -Required properties: - -- compatible: must be one of: - "brcm,bdc-udc-v2" - "brcm,bdc" -- reg: the base register address and length -- interrupts: the interrupt line for this controller - -Optional properties: - -On Broadcom STB platforms, these properties are required: - -- phys: phandle to one or two USB PHY blocks - NOTE: Some SoC's have a single phy and some have - USB 2.0 and USB 3.0 phys -- clocks: phandle to the functional clock of this block - -Example: - - bdc@f0b02000 { - compatible = "brcm,bdc-udc-v2"; - reg = <0xf0b02000 0xfc4>; - interrupts = <0x0 0x60 0x0>; - phys = <&usbphy_0 0x0>; - clocks = <&sw_usbd>; - }; diff --git a/Documentation/devicetree/bindings/usb/brcm,bdc.yaml b/Documentation/devicetree/bindings/usb/brcm,bdc.yaml new file mode 100644 index 000000000000..f72dc65d4919 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/brcm,bdc.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/brcm,bdc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom USB Device Controller (BDC) + +maintainers: + - Al Cooper + - Florian Fainelli + +properties: + compatible: + items: + - enum: + - brcm,bdc-udc-v2 + - brcm,bdc + + reg: + maxItems: 1 + + interrupts: true + + phys: + minItems: 1 + items: + - description: USB 2.0 or 3.0 PHY + - description: USB 3.0 PHY if there is a dedicated 2.0 PHY + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + usb@f0b02000 { + compatible = "brcm,bdc-udc-v2"; + reg = <0xf0b02000 0xfc4>; + interrupts = <0x0 0x60 0x0>; + phys = <&usbphy_0 0x0>; + clocks = <&sw_usbd>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index b5b7dcaba8b6..4a8356add1c9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3679,7 +3679,7 @@ M: Al Cooper L: linux-usb@vger.kernel.org L: bcm-kernel-feedback-list@broadcom.com S: Maintained -F: Documentation/devicetree/bindings/usb/brcm,bdc.txt +F: Documentation/devicetree/bindings/usb/brcm,bdc.yaml F: drivers/usb/gadget/udc/bdc/ BROADCOM BMIPS CPUFREQ DRIVER