From patchwork Fri Dec 17 12:49:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 12684551 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6298CC433F5 for ; Fri, 17 Dec 2021 12:50:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=DPvsRWzEXyaOvKHzhjedADFNBNejX+DNTPND79cO8oo=; b=Fdl0lkJwFOkM45 ew33AQBO+t5YbbeEYHDbCskUVVhNU6ywnSzj20sw1hz4WKWm7EODfbTKY4Zh9hD1Z8dmLZvAd6pfg I6Tqp7wmCP8+U1Rorit257KGw2EgkHv/MNETIwPhKw2pF+MTcq1jrXrf48pOdixcnP6qjc6wxcjAQ 6/ZpB8oYTOfZtGKUEVmkM5sx+0Nb1xMZ4XjQDHfrCvuS11LuG8tUbzdYtflj8lZ4jRaEJ42/qGxrn wfKF+UywWl/bM10Ht0qzz3bjQP+ryLuWjLXp+lE191pCn3is1xqCyGpF2vKBHtkMDgbscdi6nmWdL ffRwc0N2IUso9uki3/8Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1myCgU-00AEOh-8c; Fri, 17 Dec 2021 12:50:02 +0000 Received: from michel.telenet-ops.be ([2a02:1800:110:4::f00:18]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1myCgI-00AEFG-8D for linux-riscv@lists.infradead.org; Fri, 17 Dec 2021 12:49:52 +0000 Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed20:d13f:527c:5504:a743]) by michel.telenet-ops.be with bizsmtp id XQpm26001250X3006QpmHA; Fri, 17 Dec 2021 13:49:48 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1myCgD-005YxL-C3; Fri, 17 Dec 2021 13:49:45 +0100 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1myCgC-00ASqj-Ev; Fri, 17 Dec 2021 13:49:44 +0100 From: Geert Uytterhoeven To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Rob Herring , Damien Le Moal , Lewis Hanly , Krzysztof Kozlowski , Conor Dooley , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Geert Uytterhoeven , Damien Le Moal Subject: [PATCH v3 01/11] riscv: dts: canaan: Fix SPI FLASH node names Date: Fri, 17 Dec 2021 13:49:22 +0100 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211217_044950_609058_3160F823 X-CRM114-Status: UNSURE ( 8.66 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org "make dtbs_check": arch/riscv/boot/dts/canaan/sipeed_maix_bit.dt.yaml: spi-flash@0: $nodename:0: 'spi-flash@0' does not match '^flash(@.*)?$' From schema: Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml Fix this by renaming all SPI FLASH nodes to "flash". Signed-off-by: Geert Uytterhoeven Reviewed-by: Damien Le Moal Reviewed-by: Krzysztof Kozlowski Tested-by: Damien Le Moal --- v3: - No changes, v2: - Add Reviewed-by, Tested-by. --- arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts | 2 +- arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts | 2 +- arch/riscv/boot/dts/canaan/sipeed_maix_go.dts | 2 +- arch/riscv/boot/dts/canaan/sipeed_maixduino.dts | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts b/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts index 0bcaf35045e795ed..984872f3d3a9b9ea 100644 --- a/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts +++ b/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts @@ -199,7 +199,7 @@ slot@0 { }; &spi3 { - spi-flash@0 { + flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <50000000>; diff --git a/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts b/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts index ac8a03f5867adbd0..7ba99b4da304218e 100644 --- a/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts +++ b/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts @@ -201,7 +201,7 @@ slot@0 { }; &spi3 { - spi-flash@0 { + flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <50000000>; diff --git a/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts b/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts index 623998194bc18aab..be9b12c9b374acb3 100644 --- a/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts +++ b/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts @@ -209,7 +209,7 @@ slot@0 { }; &spi3 { - spi-flash@0 { + flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <50000000>; diff --git a/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts b/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts index cf605ba0d67e43cd..031c0c28f8195777 100644 --- a/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts +++ b/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts @@ -174,7 +174,7 @@ slot@0 { }; &spi3 { - spi-flash@0 { + flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <50000000>; From patchwork Fri Dec 17 12:49:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 12684553 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DEB98C433EF for ; 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Fri, 17 Dec 2021 12:50:04 +0000 Received: from michel.telenet-ops.be ([2a02:1800:110:4::f00:18]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1myCgI-00AEFH-86 for linux-riscv@lists.infradead.org; Fri, 17 Dec 2021 12:49:52 +0000 Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed20:d13f:527c:5504:a743]) by michel.telenet-ops.be with bizsmtp id XQpl2600i250X3006QplH8; Fri, 17 Dec 2021 13:49:48 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1myCgD-005YxM-7J; Fri, 17 Dec 2021 13:49:45 +0100 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1myCgC-00ASqq-GJ; Fri, 17 Dec 2021 13:49:44 +0100 From: Geert Uytterhoeven To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Rob Herring , Damien Le Moal , Lewis Hanly , Krzysztof Kozlowski , Conor Dooley , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Geert Uytterhoeven , Damien Le Moal Subject: [PATCH v3 02/11] riscv: dts: canaan: Group tuples in interrupt properties Date: Fri, 17 Dec 2021 13:49:23 +0100 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211217_044950_524362_BECB9744 X-CRM114-Status: UNSURE ( 7.56 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org To improve human readability and enable automatic validation, the tuples in the various properties containing interrupt specifiers should be grouped. Fix this by grouping the tuples of "interrupts" and "interrupts-extended" properties using angle brackets. Signed-off-by: Geert Uytterhoeven Reviewed-by: Damien Le Moal Reviewed-by: Krzysztof Kozlowski Tested-by: Damien Le Moal --- v3: - No changes, v2: - Add Reviewed-by, Tested-by. --- arch/riscv/boot/dts/canaan/k210.dtsi | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi index 5e8ca8142482153b..56f57118c633b91a 100644 --- a/arch/riscv/boot/dts/canaan/k210.dtsi +++ b/arch/riscv/boot/dts/canaan/k210.dtsi @@ -103,8 +103,8 @@ rom0: nvmem@1000 { clint0: timer@2000000 { compatible = "canaan,k210-clint", "sifive,clint0"; reg = <0x2000000 0xC000>; - interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 - &cpu1_intc 3 &cpu1_intc 7>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>; }; plic0: interrupt-controller@c000000 { @@ -113,7 +113,7 @@ plic0: interrupt-controller@c000000 { compatible = "canaan,k210-plic", "sifive,plic-1.0.0"; reg = <0xC000000 0x4000000>; interrupt-controller; - interrupts-extended = <&cpu0_intc 11 &cpu1_intc 11>; + interrupts-extended = <&cpu0_intc 11>, <&cpu1_intc 11>; riscv,ndev = <65>; }; @@ -130,10 +130,11 @@ gpio0: gpio-controller@38001000 { compatible = "canaan,k210-gpiohs", "sifive,gpio0"; reg = <0x38001000 0x1000>; interrupt-controller; - interrupts = <34 35 36 37 38 39 40 41 - 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 - 58 59 60 61 62 63 64 65>; + interrupts = <34>, <35>, <36>, <37>, <38>, <39>, <40>, + <41>, <42>, <43>, <44>, <45>, <46>, <47>, + <48>, <49>, <50>, <51>, <52>, <53>, <54>, + <55>, <56>, <57>, <58>, <59>, <60>, <61>, + <62>, <63>, <64>, <65>; gpio-controller; ngpios = <32>; }; @@ -141,7 +142,7 @@ gpio0: gpio-controller@38001000 { dmac0: dma-controller@50000000 { compatible = "snps,axi-dma-1.01a"; reg = <0x50000000 0x1000>; - interrupts = <27 28 29 30 31 32>; + interrupts = <27>, <28>, <29>, <30>, <31>, <32>; #dma-cells = <1>; clocks = <&sysclk K210_CLK_DMA>, <&sysclk K210_CLK_DMA>; clock-names = "core-clk", "cfgr-clk"; @@ -316,7 +317,7 @@ fpioa: pinmux@502b0000 { timer0: timer@502d0000 { compatible = "snps,dw-apb-timer"; reg = <0x502D0000 0x100>; - interrupts = <14 15>; + interrupts = <14>, <15>; clocks = <&sysclk K210_CLK_TIMER0>, <&sysclk K210_CLK_APB0>; clock-names = "timer", "pclk"; @@ -326,7 +327,7 @@ timer0: timer@502d0000 { timer1: timer@502e0000 { compatible = "snps,dw-apb-timer"; reg = <0x502E0000 0x100>; - interrupts = <16 17>; + interrupts = <16>, <17>; clocks = <&sysclk K210_CLK_TIMER1>, <&sysclk K210_CLK_APB0>; clock-names = "timer", "pclk"; @@ -336,7 +337,7 @@ timer1: timer@502e0000 { timer2: timer@502f0000 { compatible = "snps,dw-apb-timer"; reg = <0x502F0000 0x100>; - interrupts = <18 19>; + interrupts = <18>, <19>; clocks = <&sysclk K210_CLK_TIMER2>, <&sysclk K210_CLK_APB0>; clock-names = "timer", "pclk"; From patchwork Fri Dec 17 12:49:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 12684549 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6BA6DC433EF for ; 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Fri, 17 Dec 2021 12:49:59 +0000 Received: from michel.telenet-ops.be ([2a02:1800:110:4::f00:18]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1myCgI-00AEEq-8C for linux-riscv@lists.infradead.org; Fri, 17 Dec 2021 12:49:52 +0000 Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed20:d13f:527c:5504:a743]) by michel.telenet-ops.be with bizsmtp id XQpl2600b250X3006QplH5; Fri, 17 Dec 2021 13:49:47 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1myCgD-005YxN-21; Fri, 17 Dec 2021 13:49:45 +0100 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1myCgC-00ASqx-HF; Fri, 17 Dec 2021 13:49:44 +0100 From: Geert Uytterhoeven To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Rob Herring , Damien Le Moal , Lewis Hanly , Krzysztof Kozlowski , Conor Dooley , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v3 03/11] riscv: dts: microchip: mpfs: Drop empty chosen node Date: Fri, 17 Dec 2021 13:49:24 +0100 Message-Id: <53c36082ffa612ebe7ec53ebcc0dc29f11a083a6.1639744905.git.geert@linux-m68k.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211217_044950_577290_8E0FDFEA X-CRM114-Status: UNSURE ( 7.32 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org It does not make sense to have an (empty) chosen node in an SoC-specific .dtsi, as chosen is meant for system-specific configuration. It is already provided in microchip-mpfs-icicle-kit.dts anyway. Fixes: 0fa6107eca4186ad ("RISC-V: Initial DTS for Microchip ICICLE board") Signed-off-by: Geert Uytterhoeven Reviewed-by: Conor Dooley Tested-by: Conor Dooley Reviewed-by: Krzysztof Kozlowski --- v3: - Add Tested-by, v2: - Add Reviewed-by. --- arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi index c9f6d205d2ba1a5e..794da883acb19256 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi @@ -9,9 +9,6 @@ / { model = "Microchip PolarFire SoC"; compatible = "microchip,mpfs"; - chosen { - }; - cpus { #address-cells = <1>; #size-cells = <0>; From patchwork Fri Dec 17 12:49:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 12684563 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E900CC433F5 for ; Fri, 17 Dec 2021 12:50:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=KMecX1Gm31oq/yH85okzRolmuHRruZQTanafK+E2GV4=; b=w1H/Lib6eF1A1k oVzVR5cHlc3ZEtT+IAXzkTe+3eg+J8rOaZXWzIqqPvBS22cyledPk7IXJjD43NPZe7SL0mR4BY0UG qWriBtmon8nfi48vI9amCirqsclbKxydU1sgHfijwvA7hVJ5C8cBMg+qB4L4udyyF3L1QKaEVO9MI MFSldtG3tNKkd7UtxxECFzwqNqUX0rCG9ke69jXWALXifhJbJKgNnya66BoUdjoGcgQE6MRmtC7hz 2G2fsrC4yfK16ZiXUWgn26igEkY+dfzYBT3nKLv83hZIgAXajmltLccYd5/c5tAzpqOe09K1XoDD1 R5gri8D3N3FX34UkkkXA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1myCgm-00AEeI-7l; Fri, 17 Dec 2021 12:50:20 +0000 Received: from michel.telenet-ops.be ([2a02:1800:110:4::f00:18]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1myCgJ-00AEFx-4K for linux-riscv@lists.infradead.org; Fri, 17 Dec 2021 12:49:54 +0000 Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed20:d13f:527c:5504:a743]) by michel.telenet-ops.be with bizsmtp id XQpl2600n250X3006QpmH9; Fri, 17 Dec 2021 13:49:49 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1myCgD-005YxO-CA; Fri, 17 Dec 2021 13:49:45 +0100 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1myCgC-00ASr4-Hs; Fri, 17 Dec 2021 13:49:44 +0100 From: Geert Uytterhoeven To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Rob Herring , Damien Le Moal , Lewis Hanly , Krzysztof Kozlowski , Conor Dooley , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v3 04/11] riscv: dts: microchip: mpfs: Fix PLIC node Date: Fri, 17 Dec 2021 13:49:25 +0100 Message-Id: <8b3221b08be13af537aafc3a7f6aac9211991724.1639744905.git.geert@linux-m68k.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211217_044951_349356_0F83D371 X-CRM114-Status: UNSURE ( 9.19 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Fix the device node for the Platform-Level Interrupt Controller (PLIC): - Add missing "#address-cells" property, - Sort properties according to DT bindings. Signed-off-by: Geert Uytterhoeven Reviewed-by: Krzysztof Kozlowski Reviewed-by: Conor Dooley Tested-by: Conor Dooley --- v3: - Add Tested-by, v2: - Add Reviewed-by. --- arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi index 794da883acb19256..ee59751544a0d3bc 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi @@ -168,16 +168,17 @@ &cpu3_intc 3 &cpu3_intc 7 }; plic: interrupt-controller@c000000 { - #interrupt-cells = <1>; compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; reg = <0x0 0xc000000 0x0 0x4000000>; - riscv,ndev = <186>; + #address-cells = <0>; + #interrupt-cells = <1>; interrupt-controller; interrupts-extended = <&cpu0_intc 11 &cpu1_intc 11 &cpu1_intc 9 &cpu2_intc 11 &cpu2_intc 9 &cpu3_intc 11 &cpu3_intc 9 &cpu4_intc 11 &cpu4_intc 9>; + riscv,ndev = <186>; }; dma@3000000 { From patchwork Fri Dec 17 12:49:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 12684555 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5B2C5C433FE for ; Fri, 17 Dec 2021 12:50:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Iub0oBbYG8SaB6i9HwOhSdCEk65w7BY387VNnZaYOn0=; b=T9cwS78200udM6 /HD1CnbY85SuJQn6Hl3aThzJLYie9Wb/0QSF3bUtR5nFAdsE40TZYtgjC/OLFtpOqL5SIWgnWVo2o wm0ZOI9b3vfLiRwPgx1BLMqbE/jolSw4Kp10OKh4MmxX+HMnuPvUDLRcKjecJcxv2Y1IVFULrja0j l88Bx8X41jOwwmso3uclYoD0yv/cDtGCmcuNoVxrnSp/Etrx9bmnYQIPOB8a2gTnuSfMPFRj3MzeT SU5/SqkSEVz2f8IcIhRFc58BGQj6bZUl2GFgA1jeFfa7UK8mYrE7Ref9z5UcWdqF89yc2DktIZtkA rK+9CE03vLU+mmAapnAA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1myCgY-00AES6-Qz; Fri, 17 Dec 2021 12:50:06 +0000 Received: from laurent.telenet-ops.be ([2a02:1800:110:4::f00:19]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1myCgI-00AEEr-Aa for linux-riscv@lists.infradead.org; Fri, 17 Dec 2021 12:49:52 +0000 Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed20:d13f:527c:5504:a743]) by laurent.telenet-ops.be with bizsmtp id XQpm2600E250X3001QpmGP; Fri, 17 Dec 2021 13:49:47 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1myCgD-005YxP-Jz; Fri, 17 Dec 2021 13:49:45 +0100 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1myCgC-00ASrB-IX; Fri, 17 Dec 2021 13:49:44 +0100 From: Geert Uytterhoeven To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Rob Herring , Damien Le Moal , Lewis Hanly , Krzysztof Kozlowski , Conor Dooley , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v3 05/11] riscv: dts: microchip: mpfs: Fix reference clock node Date: Fri, 17 Dec 2021 13:49:26 +0100 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211217_044950_638386_FE086726 X-CRM114-Status: GOOD ( 10.07 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org "make dtbs_check" reports: arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dt.yaml: soc: refclk: {'compatible': ['fixed-clock'], '#clock-cells': [[0]], 'clock-frequency': [[600000000]], 'clock-output-names': ['msspllclk'], 'phandle': [[7]]} should not be valid under {'type': 'object'} From schema: dtschema/schemas/simple-bus.yaml Fix this by moving the node out of the "soc" subnode. While at it, rename it to "msspllclk", and drop the now superfluous "clock-output-names" property. Move the actual clock-frequency value to the board DTS, since it is not set until bitstream programming time. Signed-off-by: Geert Uytterhoeven Acked-by: Krzysztof Kozlowski Reviewed-by: Conor Dooley Tested-by: Conor Dooley --- v3: - Add Reviewed-by, Tested-by, v2: - Add Acked-by, - Move clock-frequency to board DTS. --- .../boot/dts/microchip/microchip-mpfs-icicle-kit.dts | 4 ++++ arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 12 +++++------- 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts index fc1e5869df1b9fc5..0c748ae1b0068df7 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts @@ -35,6 +35,10 @@ memory@80000000 { }; }; +&refclk { + clock-frequency = <600000000>; +}; + &serial0 { status = "okay"; }; diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi index ee59751544a0d3bc..b372bc6459bf163a 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi @@ -139,6 +139,11 @@ cpu4_intc: interrupt-controller { }; }; + refclk: msspllclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + soc { #address-cells = <2>; #size-cells = <2>; @@ -189,13 +194,6 @@ dma@3000000 { #dma-cells = <1>; }; - refclk: refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <600000000>; - clock-output-names = "msspllclk"; - }; - clkcfg: clkcfg@20002000 { compatible = "microchip,mpfs-clkcfg"; reg = <0x0 0x20002000 0x0 0x1000>; From patchwork Fri Dec 17 12:49:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 12684561 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1CB8EC433F5 for ; Fri, 17 Dec 2021 12:50:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=3udlL9Kd6MRV6IgCguNWkO77LG1ZC4M0zjUWa77Qo7c=; b=V4/kl25d93TEoR Ht7iDpSqnd9aC7nSfosihdX9izwD4wqsyb6DbxO9p7WLer94gh9FoXzDEW7ChywKvE3wGwEA8UvrG RSeTv1K7aoCMYlqDA/yEVwRiKDYcPmvFw624pGK8Cl9xZffSFED9kkeG7ZW2pmFEzIDf+tAJB8U2t cXdz70bi7EnVajzagTiEwQQPSMsv6P9rPaA0BPwtXIkIU522tsSaTnRxrH7NmBEIWEyq9JP/uj9AM YYk2OMWUqwUR/lj3NclyTuw+acyvPOV++RLlPDwxUidj5MbUOOipm/y0au4p1fQ2o/VvT6f3jYDeV iOxbrw88Ff+79pY1/mYQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1myCgj-00AEb6-2t; Fri, 17 Dec 2021 12:50:17 +0000 Received: from laurent.telenet-ops.be ([2a02:1800:110:4::f00:19]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1myCgI-00AEEt-BF for linux-riscv@lists.infradead.org; Fri, 17 Dec 2021 12:49:54 +0000 Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed20:d13f:527c:5504:a743]) by laurent.telenet-ops.be with bizsmtp id XQpm2600K250X3001QpmGQ; Fri, 17 Dec 2021 13:49:47 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1myCgD-005YxQ-Kj; Fri, 17 Dec 2021 13:49:45 +0100 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1myCgC-00ASrI-JL; Fri, 17 Dec 2021 13:49:44 +0100 From: Geert Uytterhoeven To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Rob Herring , Damien Le Moal , Lewis Hanly , Krzysztof Kozlowski , Conor Dooley , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v3 06/11] riscv: dts: microchip: mpfs: Fix clock controller node Date: Fri, 17 Dec 2021 13:49:27 +0100 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211217_044950_725269_4885CCCB X-CRM114-Status: UNSURE ( 7.36 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Fix the device node for the clock controller: - Remove bogus "reg-names" property, - Remove unneeded "clock-output-names" property. Signed-off-by: Geert Uytterhoeven Reviewed-by: Conor Dooley Tested-by: Conor Dooley --- v3: - Add Reviewed-by, Tested-by, v2: - New. --- arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 9 --------- 1 file changed, 9 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi index b372bc6459bf163a..d9c1dee3fb25beb8 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi @@ -197,17 +197,8 @@ dma@3000000 { clkcfg: clkcfg@20002000 { compatible = "microchip,mpfs-clkcfg"; reg = <0x0 0x20002000 0x0 0x1000>; - reg-names = "mss_sysreg"; clocks = <&refclk>; #clock-cells = <1>; - clock-output-names = "cpu", "axi", "ahb", "envm", /* 0-3 */ - "mac0", "mac1", "mmc", "timer", /* 4-7 */ - "mmuart0", "mmuart1", "mmuart2", "mmuart3", /* 8-11 */ - "mmuart4", "spi0", "spi1", "i2c0", /* 12-15 */ - "i2c1", "can0", "can1", "usb", /* 16-19 */ - "rsvd", "rtc", "qspi", "gpio0", /* 20-23 */ - "gpio1", "gpio2", "ddrc", "fic0", /* 24-27 */ - "fic1", "fic2", "fic3", "athena", "cfm"; /* 28-32 */ }; serial0: serial@20000000 { From patchwork Fri Dec 17 12:49:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 12684547 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BCF64C433F5 for ; Fri, 17 Dec 2021 12:50:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=aGL1tMAOQOnuUtgWXbmmy7dgMebntfTwzbkUCY5lM+0=; b=rk0DoMwzqhGGwx VgVJq2sng0X+JI0zAGpsoLc+Pzkpp5rZ0br4BeMJA605Bjx/mn/1K+P5Gu2WZTilZyRcS8rOZHvRt sDEWQxcNDvWpGQvoZHkxf+4SFeljI15Jner7aE241+7YPpAOjLuQK9QbFyfHs1Jg+727mqIh8BFVR zE7O7USaUqdp9xVoQe29J6yQSbukqpvFQNpsgwiTB65PlEEP4lM/Wt/+/sW2jAyuMOhg/wZvMvY7l 3LnJv6IkqZypcnKmH5AKtt/j5nk7fSPkjGWMF0pUA/R4NL19TizrWkqkzY7vf/2jER8tnJSROBIee 9pYwC0xa/Vd+E8ySeh6g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1myCgO-00AEL0-4b; Fri, 17 Dec 2021 12:49:56 +0000 Received: from albert.telenet-ops.be ([2a02:1800:110:4::f00:1a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1myCgG-00AEEe-TI for linux-riscv@lists.infradead.org; Fri, 17 Dec 2021 12:49:50 +0000 Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed20:d13f:527c:5504:a743]) by albert.telenet-ops.be with bizsmtp id XQpm2600F250X3006QpmK3; Fri, 17 Dec 2021 13:49:47 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1myCgD-005YxR-J9; Fri, 17 Dec 2021 13:49:45 +0100 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1myCgC-00ASrP-KC; Fri, 17 Dec 2021 13:49:44 +0100 From: Geert Uytterhoeven To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Rob Herring , Damien Le Moal , Lewis Hanly , Krzysztof Kozlowski , Conor Dooley , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v3 07/11] riscv: dts: microchip: mpfs: Group tuples in interrupt properties Date: Fri, 17 Dec 2021 13:49:28 +0100 Message-Id: <7e4bffff6d6d6f76e5ac6c0d649b9ca0140f4dc8.1639744905.git.geert@linux-m68k.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211217_044949_111786_0A363B5D X-CRM114-Status: UNSURE ( 7.76 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org To improve human readability and enable automatic validation, the tuples in the various properties containing interrupt specifiers should be grouped. Fix this by grouping the tuples of "interrupts" and "interrupts-extended" properties using angle brackets. Signed-off-by: Geert Uytterhoeven Reviewed-by: Krzysztof Kozlowski Reviewed-by: Conor Dooley Tested-by: Conor Dooley --- v3: - Add Tested-by, v2: - Add Reviewed-by. --- .../boot/dts/microchip/microchip-mpfs.dtsi | 31 ++++++++++--------- 1 file changed, 16 insertions(+), 15 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi index d9c1dee3fb25beb8..869aaf0d5c066c9d 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi @@ -158,18 +158,18 @@ cache-controller@2010000 { cache-size = <2097152>; cache-unified; interrupt-parent = <&plic>; - interrupts = <1 2 3>; + interrupts = <1>, <2>, <3>; reg = <0x0 0x2010000 0x0 0x1000>; }; clint@2000000 { compatible = "sifive,fu540-c000-clint", "sifive,clint0"; reg = <0x0 0x2000000 0x0 0xC000>; - interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 - &cpu1_intc 3 &cpu1_intc 7 - &cpu2_intc 3 &cpu2_intc 7 - &cpu3_intc 3 &cpu3_intc 7 - &cpu4_intc 3 &cpu4_intc 7>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>, + <&cpu2_intc 3>, <&cpu2_intc 7>, + <&cpu3_intc 3>, <&cpu3_intc 7>, + <&cpu4_intc 3>, <&cpu4_intc 7>; }; plic: interrupt-controller@c000000 { @@ -178,11 +178,11 @@ plic: interrupt-controller@c000000 { #address-cells = <0>; #interrupt-cells = <1>; interrupt-controller; - interrupts-extended = <&cpu0_intc 11 - &cpu1_intc 11 &cpu1_intc 9 - &cpu2_intc 11 &cpu2_intc 9 - &cpu3_intc 11 &cpu3_intc 9 - &cpu4_intc 11 &cpu4_intc 9>; + interrupts-extended = <&cpu0_intc 11>, + <&cpu1_intc 11>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu2_intc 9>, + <&cpu3_intc 11>, <&cpu3_intc 9>, + <&cpu4_intc 11>, <&cpu4_intc 9>; riscv,ndev = <186>; }; @@ -190,7 +190,8 @@ dma@3000000 { compatible = "sifive,fu540-c000-pdma"; reg = <0x0 0x3000000 0x0 0x8000>; interrupt-parent = <&plic>; - interrupts = <23 24 25 26 27 28 29 30>; + interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>, + <30>; #dma-cells = <1>; }; @@ -254,7 +255,7 @@ mmc: mmc@20008000 { compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc"; reg = <0x0 0x20008000 0x0 0x1000>; interrupt-parent = <&plic>; - interrupts = <88 89>; + interrupts = <88>, <89>; clocks = <&clkcfg 6>; max-frequency = <200000000>; status = "disabled"; @@ -264,7 +265,7 @@ emac0: ethernet@20110000 { compatible = "cdns,macb"; reg = <0x0 0x20110000 0x0 0x2000>; interrupt-parent = <&plic>; - interrupts = <64 65 66 67>; + interrupts = <64>, <65>, <66>, <67>; local-mac-address = [00 00 00 00 00 00]; clocks = <&clkcfg 4>, <&clkcfg 2>; clock-names = "pclk", "hclk"; @@ -277,7 +278,7 @@ emac1: ethernet@20112000 { compatible = "cdns,macb"; reg = <0x0 0x20112000 0x0 0x2000>; interrupt-parent = <&plic>; - interrupts = <70 71 72 73>; + interrupts = <70>, <71>, <72>, <73>; local-mac-address = [00 00 00 00 00 00]; clocks = <&clkcfg 5>, <&clkcfg 2>; status = "disabled"; From patchwork Fri Dec 17 12:49:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 12684545 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 66061C433F5 for ; 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Fri, 17 Dec 2021 12:49:53 +0000 Received: from albert.telenet-ops.be ([2a02:1800:110:4::f00:1a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1myCgG-00AEEd-Ng for linux-riscv@lists.infradead.org; Fri, 17 Dec 2021 12:49:50 +0000 Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed20:d13f:527c:5504:a743]) by albert.telenet-ops.be with bizsmtp id XQpm26003250X3006QpmK2; Fri, 17 Dec 2021 13:49:47 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1myCgD-005YxS-Ev; Fri, 17 Dec 2021 13:49:45 +0100 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1myCgC-00ASrW-LG; Fri, 17 Dec 2021 13:49:44 +0100 From: Geert Uytterhoeven To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Rob Herring , Damien Le Moal , Lewis Hanly , Krzysztof Kozlowski , Conor Dooley , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v3 08/11] riscv: dts: sifive: Group tuples in interrupt properties Date: Fri, 17 Dec 2021 13:49:29 +0100 Message-Id: <2cb6205b2d6de2a35323f86e8fbc0922ba32fb08.1639744905.git.geert@linux-m68k.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211217_044948_935620_3B9A3F23 X-CRM114-Status: UNSURE ( 7.58 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org To improve human readability and enable automatic validation, the tuples in the various properties containing interrupt specifiers should be grouped. Fix this by grouping the tuples of "interrupts" and "interrupts-extended" properties using angle brackets. Signed-off-by: Geert Uytterhoeven Reviewed-by: Krzysztof Kozlowski --- v3: - No changes, v2: - Add Reviewed-by. --- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 21 +++++++++++---------- arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 14 +++++++------- 2 files changed, 18 insertions(+), 17 deletions(-) diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi index 0655b5c4201d9f71..0caca0ccf6711ded 100644 --- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi @@ -145,12 +145,12 @@ plic0: interrupt-controller@c000000 { reg = <0x0 0xc000000 0x0 0x4000000>; riscv,ndev = <53>; interrupt-controller; - interrupts-extended = < - &cpu0_intc 0xffffffff - &cpu1_intc 0xffffffff &cpu1_intc 9 - &cpu2_intc 0xffffffff &cpu2_intc 9 - &cpu3_intc 0xffffffff &cpu3_intc 9 - &cpu4_intc 0xffffffff &cpu4_intc 9>; + interrupts-extended = + <&cpu0_intc 0xffffffff>, + <&cpu1_intc 0xffffffff>, <&cpu1_intc 9>, + <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>, + <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>, + <&cpu4_intc 0xffffffff>, <&cpu4_intc 9>; }; prci: clock-controller@10000000 { compatible = "sifive,fu540-c000-prci"; @@ -170,7 +170,8 @@ dma: dma@3000000 { compatible = "sifive,fu540-c000-pdma"; reg = <0x0 0x3000000 0x0 0x8000>; interrupt-parent = <&plic0>; - interrupts = <23 24 25 26 27 28 29 30>; + interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>, + <30>; #dma-cells = <1>; }; uart1: serial@10011000 { @@ -243,7 +244,7 @@ pwm0: pwm@10020000 { compatible = "sifive,fu540-c000-pwm", "sifive,pwm0"; reg = <0x0 0x10020000 0x0 0x1000>; interrupt-parent = <&plic0>; - interrupts = <42 43 44 45>; + interrupts = <42>, <43>, <44>, <45>; clocks = <&prci PRCI_CLK_TLCLK>; #pwm-cells = <3>; status = "disabled"; @@ -252,7 +253,7 @@ pwm1: pwm@10021000 { compatible = "sifive,fu540-c000-pwm", "sifive,pwm0"; reg = <0x0 0x10021000 0x0 0x1000>; interrupt-parent = <&plic0>; - interrupts = <46 47 48 49>; + interrupts = <46>, <47>, <48>, <49>; clocks = <&prci PRCI_CLK_TLCLK>; #pwm-cells = <3>; status = "disabled"; @@ -265,7 +266,7 @@ l2cache: cache-controller@2010000 { cache-size = <2097152>; cache-unified; interrupt-parent = <&plic0>; - interrupts = <1 2 3>; + interrupts = <1>, <2>, <3>; reg = <0x0 0x2010000 0x0 0x1000>; }; gpio: gpio@10060000 { diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi index abbb960f90a00ac2..8464b0e3c88791e1 100644 --- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi @@ -147,12 +147,12 @@ plic0: interrupt-controller@c000000 { reg = <0x0 0xc000000 0x0 0x4000000>; riscv,ndev = <69>; interrupt-controller; - interrupts-extended = < - &cpu0_intc 0xffffffff - &cpu1_intc 0xffffffff &cpu1_intc 9 - &cpu2_intc 0xffffffff &cpu2_intc 9 - &cpu3_intc 0xffffffff &cpu3_intc 9 - &cpu4_intc 0xffffffff &cpu4_intc 9>; + interrupts-extended = + <&cpu0_intc 0xffffffff>, + <&cpu1_intc 0xffffffff>, <&cpu1_intc 9>, + <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>, + <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>, + <&cpu4_intc 0xffffffff>, <&cpu4_intc 9>; }; prci: clock-controller@10000000 { compatible = "sifive,fu740-c000-prci"; @@ -273,7 +273,7 @@ ccache: cache-controller@2010000 { cache-size = <2097152>; cache-unified; interrupt-parent = <&plic0>; - interrupts = <19 21 22 20>; + interrupts = <19>, <21>, <22>, <20>; reg = <0x0 0x2010000 0x0 0x1000>; }; gpio: gpio@10060000 { From patchwork Fri Dec 17 12:49:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 12684543 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C6443C433F5 for ; Fri, 17 Dec 2021 12:49:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Fri, 17 Dec 2021 13:49:45 +0100 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1myCgC-00ASrd-MH; Fri, 17 Dec 2021 13:49:44 +0100 From: Geert Uytterhoeven To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Rob Herring , Damien Le Moal , Lewis Hanly , Krzysztof Kozlowski , Conor Dooley , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v3 09/11] riscv: dts: sifive: Group tuples in register properties Date: Fri, 17 Dec 2021 13:49:30 +0100 Message-Id: <333f37a8c2a6181d66172a06b3705a0551143c9c.1639744905.git.geert@linux-m68k.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211217_044947_770940_B626C97B X-CRM114-Status: UNSURE ( 8.09 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org To improve human readability and enable automatic validation, the tuples in "reg" properties containing register blocks should be grouped using angle brackets. Signed-off-by: Geert Uytterhoeven Reviewed-by: Krzysztof Kozlowski --- v3: - No changes, v2: - Add Reviewed-by. --- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi index 0caca0ccf6711ded..e2efcf08210926f8 100644 --- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi @@ -196,8 +196,8 @@ i2c0: i2c@10030000 { }; qspi0: spi@10040000 { compatible = "sifive,fu540-c000-spi", "sifive,spi0"; - reg = <0x0 0x10040000 0x0 0x1000 - 0x0 0x20000000 0x0 0x10000000>; + reg = <0x0 0x10040000 0x0 0x1000>, + <0x0 0x20000000 0x0 0x10000000>; interrupt-parent = <&plic0>; interrupts = <51>; clocks = <&prci PRCI_CLK_TLCLK>; @@ -207,8 +207,8 @@ qspi0: spi@10040000 { }; qspi1: spi@10041000 { compatible = "sifive,fu540-c000-spi", "sifive,spi0"; - reg = <0x0 0x10041000 0x0 0x1000 - 0x0 0x30000000 0x0 0x10000000>; + reg = <0x0 0x10041000 0x0 0x1000>, + <0x0 0x30000000 0x0 0x10000000>; interrupt-parent = <&plic0>; interrupts = <52>; clocks = <&prci PRCI_CLK_TLCLK>; @@ -230,8 +230,8 @@ eth0: ethernet@10090000 { compatible = "sifive,fu540-c000-gem"; interrupt-parent = <&plic0>; interrupts = <53>; - reg = <0x0 0x10090000 0x0 0x2000 - 0x0 0x100a0000 0x0 0x1000>; + reg = <0x0 0x10090000 0x0 0x2000>, + <0x0 0x100a0000 0x0 0x1000>; local-mac-address = [00 00 00 00 00 00]; clock-names = "pclk", "hclk"; clocks = <&prci PRCI_CLK_GEMGXLPLL>, From patchwork Fri Dec 17 12:49:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 12684557 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ADD89C433F5 for ; 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Fri, 17 Dec 2021 12:50:09 +0000 Received: from michel.telenet-ops.be ([2a02:1800:110:4::f00:18]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1myCgI-00AEEx-8B for linux-riscv@lists.infradead.org; Fri, 17 Dec 2021 12:49:52 +0000 Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed20:d13f:527c:5504:a743]) by michel.telenet-ops.be with bizsmtp id XQpm2600X250X3006QpmHJ; Fri, 17 Dec 2021 13:49:47 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1myCgD-005YxU-RC; Fri, 17 Dec 2021 13:49:45 +0100 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1myCgC-00ASrk-NB; Fri, 17 Dec 2021 13:49:44 +0100 From: Geert Uytterhoeven To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Rob Herring , Damien Le Moal , Lewis Hanly , Krzysztof Kozlowski , Conor Dooley , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v3 10/11] riscv: dts: sifive: fu540-c000: Drop bogus soc node compatible values Date: Fri, 17 Dec 2021 13:49:31 +0100 Message-Id: <473e1aadb0c4ef35efe0e93e590fea3f559b067c.1639744905.git.geert@linux-m68k.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211217_044950_532967_249D3F8B X-CRM114-Status: GOOD ( 10.58 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org "make dtbs_check": arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dt.yaml: soc: $nodename:0: '/' was expected From schema: Documentation/devicetree/bindings/riscv/sifive.yaml arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dt.yaml: soc: compatible: 'oneOf' conditional failed, one must be fixed: 'sifive,fu540-c000' is not one of ['sifive,hifive-unleashed-a00'] 'sifive,fu540-c000' is not one of ['sifive,hifive-unmatched-a00'] 'sifive,fu540-c000' was expected 'sifive,fu740-c000' was expected 'sifive,fu540' was expected 'sifive,fu740' was expected From schema: Documentation/devicetree/bindings/riscv/sifive.yaml This happens because the "soc" subnode declares compatibility with "sifive,fu540-c000" and "sifive,fu540", while these are only intended for the root node. Fix this by removing the bogus compatible values from the "soc" node. Signed-off-by: Geert Uytterhoeven Reviewed-by: Krzysztof Kozlowski --- v3: - No changes, v2: - Add Reviewed-by. --- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi index e2efcf08210926f8..b1250c16816f5c9d 100644 --- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi @@ -137,7 +137,7 @@ cpu4_intc: interrupt-controller { soc { #address-cells = <2>; #size-cells = <2>; - compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus"; + compatible = "simple-bus"; ranges; plic0: interrupt-controller@c000000 { #interrupt-cells = <1>; From patchwork Fri Dec 17 12:49:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 12684559 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4B983C433FE for ; Fri, 17 Dec 2021 12:50:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Yb/mJvyLPyumP40r4F/0bVAxvAPCPnHjIgesnogv/SQ=; b=kUmPab33EWh3yj vehFiOWzoUxyH9pROjnm4SqwerrMQFxxP95pW++WEOIdvgp47HSzwuz9phjOBgIjq/DlFIF8tl8NB odbKOhqdnrne3jopIhi5xjLCiXbD8EC6CVd87GqNccgtzXukJzGPa/m+Qhp89yj/YkQDCvjr6P5ha 2Jm6BanI4Nj+5b29QVwFmyeQyIVkEPDqMC3XcbX5sGM3Ye8k/9+ALDUU2sTkNQ/ttHKeUs6s56byv jLV2Vpf944zKOZ+LVbQq/y1bI0oi3xlRFpxxQvZ1+OYal11IZ6Y69eyoTIAA6EkBvSIiOLiBfCn45 UmbgeqQ6k6aL1BuceelQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1myCge-00AEXT-PQ; Fri, 17 Dec 2021 12:50:12 +0000 Received: from laurent.telenet-ops.be ([2a02:1800:110:4::f00:19]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1myCgI-00AEEs-Aa for linux-riscv@lists.infradead.org; Fri, 17 Dec 2021 12:49:53 +0000 Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed20:d13f:527c:5504:a743]) by laurent.telenet-ops.be with bizsmtp id XQpm2600B250X3001QpmGJ; Fri, 17 Dec 2021 13:49:47 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1myCgD-005YxV-Hl; Fri, 17 Dec 2021 13:49:45 +0100 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1myCgC-00ASrr-P1; Fri, 17 Dec 2021 13:49:44 +0100 From: Geert Uytterhoeven To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Rob Herring , Damien Le Moal , Lewis Hanly , Krzysztof Kozlowski , Conor Dooley , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v3 11/11] riscv: dts: sifive: fu540-c000: Fix PLIC node Date: Fri, 17 Dec 2021 13:49:32 +0100 Message-Id: <41497b8f509254e9ad21f5f7a34b7159ece5ba82.1639744905.git.geert@linux-m68k.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211217_044950_682133_F28DA29C X-CRM114-Status: UNSURE ( 9.55 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Fix the device node for the Platform-Level Interrupt Controller (PLIC): - Add missing "#address-cells" property, - Sort properties according to DT bindings. Signed-off-by: Geert Uytterhoeven --- v3: - No changes, v2: - New. --- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi index b1250c16816f5c9d..3eef52b1a59b5cb4 100644 --- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi @@ -140,10 +140,10 @@ soc { compatible = "simple-bus"; ranges; plic0: interrupt-controller@c000000 { - #interrupt-cells = <1>; compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; reg = <0x0 0xc000000 0x0 0x4000000>; - riscv,ndev = <53>; + #address-cells = <0>; + #interrupt-cells = <1>; interrupt-controller; interrupts-extended = <&cpu0_intc 0xffffffff>, @@ -151,6 +151,7 @@ plic0: interrupt-controller@c000000 { <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>, <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>, <&cpu4_intc 0xffffffff>, <&cpu4_intc 9>; + riscv,ndev = <53>; }; prci: clock-controller@10000000 { compatible = "sifive,fu540-c000-prci";