From patchwork Fri Dec 17 16:22:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 12685259 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7498BC433FE for ; Fri, 17 Dec 2021 16:22:58 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id 48DE1C36AEA; Fri, 17 Dec 2021 16:22:58 +0000 (UTC) Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.kernel.org (Postfix) with ESMTPS id B8FC9C36AE8; Fri, 17 Dec 2021 16:22:57 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.kernel.org B8FC9C36AE8 Authentication-Results: smtp.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.kernel.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-wr1-f49.google.com with SMTP id a9so5042178wrr.8; Fri, 17 Dec 2021 08:22:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=G8pUod1rJ8BKM00tNDrqEm69jNJuPPsCXj/GPzLhEkg=; b=qgcswfc2FeMKuVZJt9dTF9WELwWEHfzvuj3QJVngxi6Ew8rwMCnolub9lMsTh+nqXt wdvmaPa1FmR+TuHHR5pKtlEnqY1c3R48UK9EyAW7Y8syaRNvQygo7W8ppSA4hh2fZO4R VHBJX0X+TKIgFYicVLHZyVcp2Q/6f5PzmwuEZ7J4S2EsajM/DA5cTvIoQaX4Qpuazigl 6EUqCOscXP7fvjE8HtH49au1neBtnYH3FuYvqS3gNtHwDtauUGC4iE3KxlDD9mQXDVjW gxWe7JIuizEGnBi5BBi0ZY9EJmiXkJpRvf3Npvzi4Jyt+OS9btFrv/bAC24g7wKaZyBv OawQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=G8pUod1rJ8BKM00tNDrqEm69jNJuPPsCXj/GPzLhEkg=; b=gIMWRg/2STjeSQPd8+ujNedDzilGp0ecOItUw6mDra2Y0drhecqfd9Pfet0hgDBS1U 9zgDHeJkHpKUWaGkjI6G8gwjth8A+dAxhxIkP7oVS2cHcVcgZ1P+5K+wMIOjEcmGVu9M to38WBALSpWRKLUCKsmjV0pJ1R+GxGpmiWSkLMWKnozsa9WXzGtCWcFJuvn3VpWNlpEg mYh0Cndeoi99c0vUInnchDQm/sPmSnQb1IPwo0LtieZIoS65EeVya4SbVuhr+9TRLcr5 g4EvU+1v+OYPbqRvXAQL2LYOtG9lTCx7Y2gGP02jwPPCgY7u0Mi3uOXBgE07BcP/r06v Plng== X-Gm-Message-State: AOAM533gGD0YKaTpSZAGvq7wXyc0IkJsveQjB60A/wrdDDXyqmWHD4Yb QLuJICtiSPxIqRCaRM88rX+wPBtynv+FwQ== X-Google-Smtp-Source: ABdhPJz/bOkEs4384vt3/kweTJfOmZ0H7sRcry48HWvxwFLtpAuSa+XR8tfOaFtLOPySt0urpAtWqg== X-Received: by 2002:a05:6000:1449:: with SMTP id v9mr1396032wrx.280.1639758175667; Fri, 17 Dec 2021 08:22:55 -0800 (PST) Received: from localhost ([193.209.96.43]) by smtp.gmail.com with ESMTPSA id d1sm7536400wrz.92.2021.12.17.08.22.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Dec 2021 08:22:55 -0800 (PST) From: Thierry Reding List-Id: To: arm@kernel.org, soc@kernel.org Cc: Thierry Reding , Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [GIT PULL 1/6] soc/tegra: Changes for v5.17-rc1 Date: Fri, 17 Dec 2021 17:22:48 +0100 Message-Id: <20211217162253.1801077-1-thierry.reding@gmail.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Hi ARM SoC maintainers, The following changes since commit fa55b7dcdc43c1aa1ba12bca9d2dd4318c2a0dbf: Linux 5.16-rc1 (2021-11-14 13:56:52 -0800) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-5.17-soc for you to fetch changes up to 81c4c86c66650f61c6d7a712737d43a3e4d072bf: soc/tegra: pmc: Rename core power domain (2021-12-16 14:03:38 +0100) Thanks, Thierry ---------------------------------------------------------------- soc/tegra: Changes for v5.17-rc1 This set of changes contains some preparatory work that is shared by several branches and trees to support DVFS via power domains. There's also a bit of cleanup and improvements to reboot on chips that use PSCI. ---------------------------------------------------------------- Dmitry Osipenko (8): soc/tegra: Enable runtime PM during OPP state-syncing soc/tegra: Add devm_tegra_core_dev_init_opp_table_common() soc/tegra: Don't print error message when OPPs not available soc/tegra: fuse: Reset hardware soc/tegra: fuse: Use resource-managed helpers soc/tegra: regulators: Prepare for suspend soc/tegra: pmc: Rename 3d power domains soc/tegra: pmc: Rename core power domain Jon Hunter (1): soc/tegra: pmc: Add reboot notifier drivers/soc/tegra/common.c | 29 +++++++- drivers/soc/tegra/fuse/fuse-tegra.c | 51 +++++++++++--- drivers/soc/tegra/fuse/fuse-tegra20.c | 33 ++++++++- drivers/soc/tegra/fuse/fuse.h | 1 + drivers/soc/tegra/pmc.c | 41 ++++++++--- drivers/soc/tegra/regulators-tegra20.c | 99 ++++++++++++++++++++++++++ drivers/soc/tegra/regulators-tegra30.c | 122 +++++++++++++++++++++++++++++++++ include/soc/tegra/common.h | 15 ++++ 8 files changed, 366 insertions(+), 25 deletions(-) From patchwork Fri Dec 17 16:22:49 2021 Content-Type: text/plain; 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These have all been acked by the respective maintainers and go through the Tegra tree to more easily handle the build dependency. ---------------------------------------------------------------- Dmitry Osipenko (9): soc/tegra: Enable runtime PM during OPP state-syncing soc/tegra: Add devm_tegra_core_dev_init_opp_table_common() usb: chipidea: tegra: Add runtime PM and OPP support bus: tegra-gmi: Add runtime PM and OPP support pwm: tegra: Add runtime PM and OPP support mmc: sdhci-tegra: Add runtime PM and OPP support mtd: rawnand: tegra: Add runtime PM and OPP support spi: tegra20-slink: Add OPP support media: staging: tegra-vde: Support generic power domain Thierry Reding (1): Merge branch 'tegra-for-5.17-soc-opp' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into for-5.17/drivers drivers/bus/tegra-gmi.c | 50 ++++++++++++++++++--- drivers/mmc/host/sdhci-tegra.c | 81 +++++++++++++++++++++++++++------- drivers/mtd/nand/raw/tegra_nand.c | 58 +++++++++++++++++++++---- drivers/pwm/pwm-tegra.c | 82 +++++++++++++++++++++++++++-------- drivers/soc/tegra/common.c | 25 +++++++++++ drivers/spi/spi-tegra20-slink.c | 9 +++- drivers/staging/media/tegra-vde/vde.c | 63 ++++++++++++++++++++++----- drivers/usb/chipidea/ci_hdrc_tegra.c | 53 +++++++++++++++++++--- include/soc/tegra/common.h | 15 +++++++ 9 files changed, 369 insertions(+), 67 deletions(-) From patchwork Fri Dec 17 16:22:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 12685263 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B46D0C43219 for ; Fri, 17 Dec 2021 16:23:03 +0000 (UTC) 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AOAM530R58HlkGDR58t6rUu0Ho6rc3KkVXFf8LDZVUvl6zfymMYUZgh9 heFXOLm5lO2Y3e2cbLVclaVOcuqSyCThEA== X-Google-Smtp-Source: ABdhPJxardNs1rsi+MQgGCUSM23XRQ9cYjZtSqMQYgYVueaW1DH/eRxQeDG/rC6XCH8Bfa+3z8EkXg== X-Received: by 2002:adf:d1e2:: with SMTP id g2mr3141701wrd.346.1639758180469; Fri, 17 Dec 2021 08:23:00 -0800 (PST) Received: from localhost ([193.209.96.43]) by smtp.gmail.com with ESMTPSA id d2sm11199026wmb.24.2021.12.17.08.22.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Dec 2021 08:22:59 -0800 (PST) From: Thierry Reding List-Id: To: arm@kernel.org, soc@kernel.org Cc: Thierry Reding , Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [GIT PULL 3/6] dt-bindings: Changes for v5.17-rc1 Date: Fri, 17 Dec 2021 17:22:50 +0100 Message-Id: <20211217162253.1801077-3-thierry.reding@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211217162253.1801077-1-thierry.reding@gmail.com> References: <20211217162253.1801077-1-thierry.reding@gmail.com> MIME-Version: 1.0 Hi ARM SoC maintainers, The following changes since commit fa55b7dcdc43c1aa1ba12bca9d2dd4318c2a0dbf: Linux 5.16-rc1 (2021-11-14 13:56:52 -0800) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-5.17-dt-bindings for you to fetch changes up to c9059a6bb993db31cd85f3a4081766af9e61be40: media: dt: bindings: tegra-vde: Document OPP and power domain (2021-12-17 14:58:06 +0100) Thanks, Thierry ---------------------------------------------------------------- dt-bindings: Changes for v5.17-rc1 This contains a bunch of json-schema conversions for various Tegra- related DT bindings and additions for new SoC and board support. ---------------------------------------------------------------- David Heidelberg (1): dt-bindings: ARM: tegra: Document Pegatron Chagall Dmitry Osipenko (5): dt-bindings: clock: tegra-car: Document new clock sub-nodes dt-bindings: host1x: Document OPP and power domain properties dt-bindings: host1x: Document Memory Client resets of Host1x, GR2D and GR3D media: dt: bindings: tegra-vde: Convert to schema media: dt: bindings: tegra-vde: Document OPP and power domain Jon Hunter (1): dt-bindings: Add YAML bindings for NVENC and NVJPG Mikko Perttunen (1): dt-bindings: Update headers for Tegra234 Svyatoslav Ryhel (1): dt-bindings: ARM: tegra: Document ASUS Transformers Thierry Reding (21): dt-bindings: memory: tegra: Update for Tegra194 dt-bindings: memory: tegra: Add Tegra234 support dt-bindings: tegra: Describe recent developer kits consistently dt-bindings: tegra: Document Jetson AGX Orin (and devkit) dt-bindings: sram: Document NVIDIA Tegra SYSRAM dt-bindings: misc: Convert Tegra MISC to json-schema dt-bindings: mmc: tegra: Convert to json-schema dt-bindings: mailbox: tegra: Convert to json-schema dt-bindings: mailbox: tegra: Document Tegra234 HSP dt-bindings: rtc: tegra: Convert to json-schema dt-bindings: rtc: tegra: Document Tegra234 RTC dt-bindings: fuse: tegra: Convert to json-schema dt-bindings: fuse: tegra: Document Tegra234 FUSE dt-bindings: mmc: tegra: Document Tegra234 SDHCI dt-bindings: serial: 8250: Document Tegra234 UART dt-bindings: tegra: pmc: Convert to json-schema dt-bindings: firmware: tegra: Convert to json-schema dt-bindings: thermal: tegra186-bpmp: Convert to json-schema dt-bindings: serial: tegra-tcu: Convert to json-schema dt-bindings: serial: Document Tegra234 TCU dt-bindings: usb: tegra-xudc: Document interconnects and iommus properties Documentation/devicetree/bindings/arm/tegra.yaml | 48 +++- .../bindings/arm/tegra/nvidia,tegra186-pmc.txt | 133 --------- .../bindings/arm/tegra/nvidia,tegra186-pmc.yaml | 198 +++++++++++++ .../bindings/clock/nvidia,tegra20-car.yaml | 37 +++ .../display/tegra/nvidia,tegra20-host1x.txt | 53 ++++ .../bindings/firmware/nvidia,tegra186-bpmp.txt | 107 ------- .../bindings/firmware/nvidia,tegra186-bpmp.yaml | 186 ++++++++++++ .../bindings/fuse/nvidia,tegra20-fuse.txt | 42 --- .../bindings/fuse/nvidia,tegra20-fuse.yaml | 89 ++++++ .../bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml | 135 +++++++++ .../bindings/gpu/host1x/nvidia,tegra210-nvjpg.yaml | 94 ++++++ .../bindings/mailbox/nvidia,tegra186-hsp.txt | 72 ----- .../bindings/mailbox/nvidia,tegra186-hsp.yaml | 114 ++++++++ .../devicetree/bindings/media/nvidia,tegra-vde.txt | 64 ----- .../bindings/media/nvidia,tegra-vde.yaml | 119 ++++++++ .../memory-controllers/nvidia,tegra186-mc.yaml | 98 ++++++- .../bindings/misc/nvidia,tegra186-misc.txt | 14 - .../bindings/misc/nvidia,tegra186-misc.yaml | 43 +++ .../bindings/misc/nvidia,tegra20-apbmisc.txt | 17 -- .../bindings/misc/nvidia,tegra20-apbmisc.yaml | 51 ++++ .../bindings/mmc/nvidia,tegra20-sdhci.txt | 143 ---------- .../bindings/mmc/nvidia,tegra20-sdhci.yaml | 317 +++++++++++++++++++++ .../devicetree/bindings/rtc/nvidia,tegra20-rtc.txt | 24 -- .../bindings/rtc/nvidia,tegra20-rtc.yaml | 61 ++++ Documentation/devicetree/bindings/serial/8250.yaml | 3 +- .../bindings/serial/nvidia,tegra194-tcu.txt | 35 --- .../bindings/serial/nvidia,tegra194-tcu.yaml | 61 ++++ Documentation/devicetree/bindings/sram/sram.yaml | 3 + .../thermal/nvidia,tegra186-bpmp-thermal.txt | 33 --- .../thermal/nvidia,tegra186-bpmp-thermal.yaml | 42 +++ .../devicetree/bindings/usb/nvidia,tegra-xudc.yaml | 13 + include/dt-bindings/clock/tegra234-clock.h | 26 +- include/dt-bindings/memory/tegra234-mc.h | 32 +++ include/dt-bindings/reset/tegra234-reset.h | 12 +- 34 files changed, 1809 insertions(+), 710 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml delete mode 100644 Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt create mode 100644 Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml delete mode 100644 Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt create mode 100644 Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml create mode 100644 Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml create mode 100644 Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvjpg.yaml delete mode 100644 Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt create mode 100644 Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml delete mode 100644 Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt create mode 100644 Documentation/devicetree/bindings/media/nvidia,tegra-vde.yaml delete mode 100644 Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt create mode 100644 Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.yaml delete mode 100644 Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt create mode 100644 Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.yaml delete mode 100644 Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt create mode 100644 Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml delete mode 100644 Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt create mode 100644 Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml delete mode 100644 Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.txt create mode 100644 Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml delete mode 100644 Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt create mode 100644 Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.yaml create mode 100644 include/dt-bindings/memory/tegra234-mc.h From patchwork Fri Dec 17 16:22:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 12685265 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 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linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [GIT PULL 4/6] arm64: tegra: Device tree changes for v5.17-rc1 Date: Fri, 17 Dec 2021 17:22:51 +0100 Message-Id: <20211217162253.1801077-4-thierry.reding@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211217162253.1801077-1-thierry.reding@gmail.com> References: <20211217162253.1801077-1-thierry.reding@gmail.com> MIME-Version: 1.0 Hi ARM SoC maintainers, The following changes since commit fa55b7dcdc43c1aa1ba12bca9d2dd4318c2a0dbf: Linux 5.16-rc1 (2021-11-14 13:56:52 -0800) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-5.17-arm64-dt for you to fetch changes up to 914ed1f56581f99094035f1cc989ab4498104e94: arm64: tegra: Add host1x hotflush reset on Tegra210 (2021-12-17 14:58:58 +0100) Thanks, Thierry ---------------------------------------------------------------- arm64: tegra: Device tree changes for v5.17-rc1 The vast majority of this contains various updates and cleanups to the Tegra device trees that will eventually help validate all of them using the dt-schema infrastructure. Another notable chunk of this contains additional Tegra234 support as well as support for the new Jetson AGX Orin Developer Kit. ---------------------------------------------------------------- Jon Hunter (3): arm64: tegra: Add NVENC and NVJPG nodes for Tegra186 and Tegra194 arm64: tegra: Add ISO SMMU controller for Tegra194 arm64: tegra: Add dma-coherent for Tegra194 VIC Mikko Perttunen (6): dt-bindings: Update headers for Tegra234 arm64: tegra: Add clock for Tegra234 RTC arm64: tegra: Update Tegra234 BPMP channel addresses arm64: tegra: Fill in properties for Tegra234 eMMC arm64: tegra: Add Tegra234 TCU device arm64: tegra: Add NVIDIA Jetson AGX Orin Developer Kit support Prathamesh Shete (2): arm64: tegra: Add support to enumerate SD in UHS mode arm64: tegra: Update SDMMC4 speeds for Tegra194 Thierry Reding (40): dt-bindings: memory: tegra: Update for Tegra194 dt-bindings: memory: tegra: Add Tegra234 support Merge tag 'tegra-for-5.17-dt-bindings-memory' into for-5.17/arm64/dt arm64: tegra: Fixup SYSRAM references arm64: tegra: Add main and AON GPIO controllers on Tegra234 arm64: tegra: Describe Tegra234 CPU hierarchy arm64: tegra: Rename top-level clocks arm64: tegra: Rename top-level regulators arm64: tegra: Add native timer support on Tegra186 arm64: tegra: Fix unit-addresses on Norrin arm64: tegra: Remove unsupported properties on Norrin arm64: tegra: Fix compatible string for Tegra132 timer arm64: tegra: Add OPP tables on Tegra132 arm64: tegra: Fix Tegra132 I2C compatible string list arm64: tegra: Drop unused AHCI clocks on Tegra132 arm64: tegra: Sort Tegra132 XUSB clocks correctly arm64: tegra: Rename thermal zones nodes arm64: tegra: Rename power-monitor input nodes arm64: tegra: Fix Tegra186 compatible string list arm64: tegra: Adjust length of CCPLEX cluster MMIO region arm64: tegra: Drop unit-address for audio card graph endpoints arm64: tegra: Use JEDEC vendor prefix for SPI NOR flash chips arm64: tegra: Drop unsupported nvidia,lpdr property arm64: tegra: Fix Tegra194 HSP compatible string arm64: tegra: Drop unused properties for Tegra194 PCIe arm64: tegra: Remove undocumented Tegra194 PCIe "core_m" clock arm64: tegra: Rename TCU node to "serial" arm64: tegra: Remove unsupported regulator properties arm64: tegra: Rename GPIO hog nodes to match schema arm64: tegra: jetson-tx1: Remove extra PLL power supplies for PCIe and XUSB arm64: tegra: smaug: Remove extra PLL power supplies for XUSB arm64: tegra: jetson-nano: Remove extra PLL power supplies for PCIe and XUSB arm64: tegra: Add missing TSEC properties on Tegra210 arm64: tegra: Sort Tegra210 XUSB clocks correctly arm64: tegra: Remove unused only-1-8-v properties arm64: tegra: Rename Ethernet PHY nodes arm64: tegra: Add EMC general interrupt on Tegra194 arm64: tegra: Add memory controller on Tegra234 arm64: tegra: Hook up MMC and BPMP to memory controller arm64: tegra: Add host1x hotflush reset on Tegra210 .../memory-controllers/nvidia,tegra186-mc.yaml | 98 +++- arch/arm64/boot/dts/nvidia/Makefile | 1 + arch/arm64/boot/dts/nvidia/tegra132-norrin.dts | 36 +- .../boot/dts/nvidia/tegra132-peripherals-opp.dtsi | 426 ++++++++++++++++ arch/arm64/boot/dts/nvidia/tegra132.dtsi | 48 +- arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 20 +- arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 20 +- .../dts/nvidia/tegra186-p3509-0000+p3636-0001.dts | 32 +- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 95 +++- arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 12 +- arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts | 8 +- .../arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi | 20 +- .../arm64/boot/dts/nvidia/tegra194-p3668-0000.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 231 +++++++-- arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 4 +- arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts | 3 - arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 37 +- arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi | 40 +- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 53 +- arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 22 +- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 27 +- .../arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi | 24 + .../dts/nvidia/tegra234-p3737-0000+p3701-0000.dts | 24 + .../arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi | 5 + arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dts | 1 - arch/arm64/boot/dts/nvidia/tegra234.dtsi | 541 ++++++++++++++++++++- include/dt-bindings/clock/tegra234-clock.h | 26 +- include/dt-bindings/memory/tegra234-mc.h | 32 ++ include/dt-bindings/reset/tegra234-reset.h | 12 +- 31 files changed, 1606 insertions(+), 298 deletions(-) create mode 100644 arch/arm64/boot/dts/nvidia/tegra132-peripherals-opp.dtsi create mode 100644 arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi create mode 100644 arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts create mode 100644 arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi create mode 100644 include/dt-bindings/memory/tegra234-mc.h From patchwork Fri Dec 17 16:22:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 12685267 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 894C6C433FE for ; Fri, 17 Dec 2021 16:23:08 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id 7781AC36AEB; Fri, 17 Dec 2021 16:23:08 +0000 (UTC) Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate 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08:23:05 -0800 (PST) Received: from localhost ([193.209.96.43]) by smtp.gmail.com with ESMTPSA id 10sm9746674wrb.75.2021.12.17.08.23.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Dec 2021 08:23:04 -0800 (PST) From: Thierry Reding List-Id: To: arm@kernel.org, soc@kernel.org Cc: Thierry Reding , Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [GIT PULL 5/6] ARM: tegra: Changes for v5.17-rc1 Date: Fri, 17 Dec 2021 17:22:52 +0100 Message-Id: <20211217162253.1801077-5-thierry.reding@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211217162253.1801077-1-thierry.reding@gmail.com> References: <20211217162253.1801077-1-thierry.reding@gmail.com> MIME-Version: 1.0 Hi ARM SoC maintainers, The following changes since commit fa55b7dcdc43c1aa1ba12bca9d2dd4318c2a0dbf: Linux 5.16-rc1 (2021-11-14 13:56:52 -0800) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-5.17-arm-dt for you to fetch changes up to bd048487af68a9782ebccc3af6606e9e0d7d9f8b: ARM: tegra: Add host1x hotflush reset on Tegra124 (2021-12-17 14:55:32 +0100) Thanks, Thierry ---------------------------------------------------------------- ARM: tegra: Changes for v5.17-rc1 A large part of this is cleanups to existing device trees in order to improve validation of the device trees using the dt-schema tooling. This also contains a set of new device trees for various boards that have been contributed by community members as well as fixes to existing devices. ---------------------------------------------------------------- Anton Bambura (2): ARM: tegra: Add device-tree for ASUS Transformer Pad TF701T ARM: tegra: Enable video decoder on Tegra114 David Heidelberg (2): ARM: tegra: Rename top-level clocks ARM: tegra: nexus7: Drop clock-frequency from NFC node Dmitry Osipenko (16): ARM: tegra: Rename top-level regulators ARM: tegra: Rename CPU and EMC OPP table device-tree nodes ARM: tegra: Add device-tree for 1080p version of Nyan Big ARM: tegra: Enable HDMI CEC on Nyan ARM: tegra: Enable CPU DFLL on Nyan ARM: tegra: Add CPU thermal zones to Nyan device-tree ARM: tegra: Add 500 MHz entry to Tegra30 memory OPP table ARM: tegra: Add OPP tables and power domains to Tegra20 device-trees ARM: tegra: Add OPP tables and power domains to Tegra30 device-trees ARM: tegra: Add Memory Client resets to Tegra20 GR2D, GR3D and Host1x ARM: tegra: Add Memory Client resets to Tegra30 GR2D, GR3D and Host1x ARM: tegra20/30: Disable unused host1x hardware ARM: tegra: Add S/PDIF node to Tegra20 device-tree ARM: tegra: Add HDMI audio graph to Tegra20 device-tree ARM: tegra: acer-a500: Enable S/PDIF and HDMI audio ARM: tegra: paz00: Enable S/PDIF and HDMI audio Maxim Schwalm (2): ARM: tegra: Add common device-tree for LVDS display panels of Tegra30 ASUS tablets ARM: tegra: nexus7: Use common LVDS display device-tree Michał Mirosław (1): ARM: tegra: Add device-tree for ASUS Transformer Pad TF300T Nikola Milosavljevic (1): ARM: tegra: Add device-tree for ASUS Transformer EeePad TF101 Stefan Agner (1): ARM: tegra: Add back gpio-ranges properties Stefan Eichenberger (1): ARM: tegra: Add usb-role-switch property to USB OTG ports Svyatoslav Ryhel (5): ARM: tegra: Add common device-tree base for Tegra30 ASUS Transformers ARM: tegra: Add device-tree for ASUS Transformer Prime TF201 ARM: tegra: Add device-tree for ASUS Transformer Pad TF300TG ARM: tegra: Add device-tree for ASUS Transformer Infinity TF700T ARM: tegra: Add device-tree for Pegatron Chagall Thierry Reding (24): ARM: tegra: Clean up external memory controller nodes ARM: tegra: Specify correct PMIC compatible on Tegra114 boards ARM: tegra: Rename SPI flash chip nodes ARM: tegra: Fix compatible string for Tegra114+ timer ARM: tegra: Add #reset-cells for Tegra114 MC ARM: tegra: Rename GPIO hog nodes to match schema ARM: tegra: Rename GPU node on Tegra124 ARM: tegra: Drop reg-shift for Tegra HS UART ARM: tegra: Rename thermal zone nodes ARM: tegra: Fix Tegra124 I2C compatible string list ARM: tegra: Drop unused AHCI clocks on Tegra124 ARM: tegra: Sort Tegra124 XUSB clocks correctly ARM: tegra: Avoid pwm- prefix in pinmux nodes ARM: tegra: Add compatible string for built-in ASIX on Colibri boards ARM: tegra: Remove PHY reset GPIO references from USB controller node ARM: tegra: Add dummy backlight power supplies ARM: tegra: Use correct vendor prefix for Invensense ARM: tegra: Remove unsupported properties on Apalis ARM: tegra: Remove stray #reset-cells property ARM: tegra: Fix SLINK compatible string on Tegra30 ARM: tegra: Fix I2C mux reset GPIO reference on Cardhu ARM: tegra: Avoid phandle indirection on Ouya ARM: tegra: Add memory client hotflush resets on Tegra114 ARM: tegra: Add host1x hotflush reset on Tegra124 arch/arm/boot/dts/Makefile | 10 +- arch/arm/boot/dts/tegra114-asus-tf701t.dts | 807 ++ arch/arm/boot/dts/tegra114-dalmore.dts | 21 +- arch/arm/boot/dts/tegra114-roth.dts | 16 +- arch/arm/boot/dts/tegra114-tn7.dts | 10 +- arch/arm/boot/dts/tegra114.dtsi | 58 +- arch/arm/boot/dts/tegra124-apalis-emc.dtsi | 436 +- arch/arm/boot/dts/tegra124-apalis-eval.dts | 2 +- arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts | 2 +- arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 16 +- arch/arm/boot/dts/tegra124-apalis.dtsi | 16 +- arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi | 652 +- arch/arm/boot/dts/tegra124-jetson-tk1.dts | 39 +- arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi | 1782 ++--- arch/arm/boot/dts/tegra124-nyan-big-fhd.dts | 11 + arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi | 604 +- arch/arm/boot/dts/tegra124-nyan.dtsi | 86 +- arch/arm/boot/dts/tegra124-peripherals-opp.dtsi | 140 +- arch/arm/boot/dts/tegra124-venice2.dts | 35 +- arch/arm/boot/dts/tegra124.dtsi | 45 +- arch/arm/boot/dts/tegra20-acer-a500-picasso.dts | 27 +- arch/arm/boot/dts/tegra20-asus-tf101.dts | 1280 +++ arch/arm/boot/dts/tegra20-colibri-eval-v3.dts | 4 +- arch/arm/boot/dts/tegra20-colibri-iris.dts | 4 +- arch/arm/boot/dts/tegra20-colibri.dtsi | 18 +- arch/arm/boot/dts/tegra20-cpu-opp-microvolt.dtsi | 82 +- arch/arm/boot/dts/tegra20-cpu-opp.dtsi | 82 +- arch/arm/boot/dts/tegra20-harmony.dts | 21 +- arch/arm/boot/dts/tegra20-medcom-wide.dts | 11 +- arch/arm/boot/dts/tegra20-paz00.dts | 22 +- arch/arm/boot/dts/tegra20-peripherals-opp.dtsi | 948 ++- arch/arm/boot/dts/tegra20-plutux.dts | 8 +- arch/arm/boot/dts/tegra20-seaboard.dts | 23 +- arch/arm/boot/dts/tegra20-tamonten.dtsi | 7 +- arch/arm/boot/dts/tegra20-tec.dts | 8 +- arch/arm/boot/dts/tegra20-trimslice.dts | 26 +- arch/arm/boot/dts/tegra20-ventana.dts | 15 +- arch/arm/boot/dts/tegra20.dtsi | 162 +- arch/arm/boot/dts/tegra30-apalis-eval.dts | 2 +- arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts | 2 +- arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi | 6 +- arch/arm/boot/dts/tegra30-apalis.dtsi | 6 +- arch/arm/boot/dts/tegra30-asus-lvds-display.dtsi | 61 + .../dts/tegra30-asus-nexus7-grouper-common.dtsi | 67 +- .../tegra30-asus-nexus7-grouper-maxim-pmic.dtsi | 4 +- ...tegra30-asus-nexus7-grouper-memory-timings.dtsi | 12 +- .../dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi | 2 +- arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi | 1 - arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi | 2 - arch/arm/boot/dts/tegra30-asus-tf201.dts | 627 ++ arch/arm/boot/dts/tegra30-asus-tf300t.dts | 1034 +++ arch/arm/boot/dts/tegra30-asus-tf300tg.dts | 1087 +++ arch/arm/boot/dts/tegra30-asus-tf700t.dts | 823 ++ .../boot/dts/tegra30-asus-transformer-common.dtsi | 1787 +++++ arch/arm/boot/dts/tegra30-beaver.dts | 24 +- arch/arm/boot/dts/tegra30-cardhu-a02.dts | 12 +- arch/arm/boot/dts/tegra30-cardhu-a04.dts | 14 +- arch/arm/boot/dts/tegra30-cardhu.dtsi | 35 +- arch/arm/boot/dts/tegra30-colibri.dtsi | 25 +- arch/arm/boot/dts/tegra30-cpu-opp-microvolt.dtsi | 144 +- arch/arm/boot/dts/tegra30-cpu-opp.dtsi | 144 +- arch/arm/boot/dts/tegra30-ouya.dts | 8149 ++++++++++---------- arch/arm/boot/dts/tegra30-pegatron-chagall.dts | 2859 +++++++ arch/arm/boot/dts/tegra30-peripherals-opp.dtsi | 1370 +++- arch/arm/boot/dts/tegra30.dtsi | 189 +- 65 files changed, 19640 insertions(+), 6384 deletions(-) create mode 100644 arch/arm/boot/dts/tegra114-asus-tf701t.dts create mode 100644 arch/arm/boot/dts/tegra124-nyan-big-fhd.dts create mode 100644 arch/arm/boot/dts/tegra20-asus-tf101.dts create mode 100644 arch/arm/boot/dts/tegra30-asus-lvds-display.dtsi create mode 100644 arch/arm/boot/dts/tegra30-asus-tf201.dts create mode 100644 arch/arm/boot/dts/tegra30-asus-tf300t.dts create mode 100644 arch/arm/boot/dts/tegra30-asus-tf300tg.dts create mode 100644 arch/arm/boot/dts/tegra30-asus-tf700t.dts create mode 100644 arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi create mode 100644 arch/arm/boot/dts/tegra30-pegatron-chagall.dts From patchwork Fri Dec 17 16:22:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 12685269 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 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AOAM5338BWmpgTqsIu84PSC/b96XxvFa/m0E4jfy9rihxpqKJqeLL2al 0W+Rbj5MYw5TO59WEh6JYMLaDfBm3X3gig== X-Google-Smtp-Source: ABdhPJzUKFqMKerARbdeozSVPlNcrSwBYqllzI6iiAxtsYmgl6N92DBgcw9iyU0dghLUf1JzNZZOTA== X-Received: by 2002:adf:d0c7:: with SMTP id z7mr3158709wrh.236.1639758187785; Fri, 17 Dec 2021 08:23:07 -0800 (PST) Received: from localhost ([193.209.96.43]) by smtp.gmail.com with ESMTPSA id j2sm2016322wms.3.2021.12.17.08.23.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Dec 2021 08:23:06 -0800 (PST) From: Thierry Reding List-Id: To: arm@kernel.org, soc@kernel.org Cc: Thierry Reding , Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [GIT PULL 6/6] ARM: tegra: Default configuration changes for v5.17-rc1 Date: Fri, 17 Dec 2021 17:22:53 +0100 Message-Id: <20211217162253.1801077-6-thierry.reding@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211217162253.1801077-1-thierry.reding@gmail.com> References: <20211217162253.1801077-1-thierry.reding@gmail.com> MIME-Version: 1.0 Hi ARM SoC maintainers, The following changes since commit fa55b7dcdc43c1aa1ba12bca9d2dd4318c2a0dbf: Linux 5.16-rc1 (2021-11-14 13:56:52 -0800) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-5.17-arm-defconfig for you to fetch changes up to 8ed567fbea94ad05298d060974d5fa59946cf689: ARM: config: multi v7: Enable NVIDIA Tegra20 APB DMA driver (2021-12-16 15:03:33 +0100) Thanks, Thierry ---------------------------------------------------------------- ARM: tegra: Default configuration changes for v5.17-rc1 These patches enable various drivers used by new and existing boards in both the Tegra default configuration and the multi-v7 configuration. ---------------------------------------------------------------- Dmitry Osipenko (5): ARM: tegra_defconfig: Enable drivers wanted by Acer Chromebooks and ASUS tablets ARM: config: multi v7: Enable display drivers used by Tegra devices ARM: tegra_defconfig: Enable S/PDIF driver ARM: config: multi v7: Enable NVIDIA Tegra20 S/PDIF driver ARM: config: multi v7: Enable NVIDIA Tegra20 APB DMA driver arch/arm/configs/multi_v7_defconfig | 7 +++++++ arch/arm/configs/tegra_defconfig | 13 +++++++++++++ 2 files changed, 20 insertions(+)