From patchwork Sat Dec 18 10:05:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sander Vanheule X-Patchwork-Id: 12686019 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6F043C4332F for ; Sat, 18 Dec 2021 10:05:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229632AbhLRKFZ (ORCPT ); Sat, 18 Dec 2021 05:05:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51382 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230361AbhLRKFY (ORCPT ); Sat, 18 Dec 2021 05:05:24 -0500 Received: from polaris.svanheule.net (polaris.svanheule.net [IPv6:2a00:c98:2060:a004:1::200]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 30564C06173E for ; Sat, 18 Dec 2021 02:05:24 -0800 (PST) Received: from terra.local.svanheule.net (unknown [IPv6:2a02:a03f:eafe:c901:e9c7:274f:a8f6:5f25]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sander@svanheule.net) by polaris.svanheule.net (Postfix) with ESMTPSA id 1E674282FBB; Sat, 18 Dec 2021 11:05:22 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=svanheule.net; s=mail1707; t=1639821922; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=auJPP3VEV6IR+9oakofmiczq/H4iU4bivONnXyJLUvk=; b=U8fA/8JpN4nLZGn8uXfPwAdmRJBQdg9U4YKH+N3+t8+uHvGJgftuiQfhXdOmvdSbkR4oyg 9AkcmdftGXdjJrzFYzl1EhjrkyehzE2M1UtkpOYJzlkTM3JhlUzcoCsp5vN2Kjt70Fb6r2 i3qqmSY2B4czJ/f1r42I3EPm/qFy5itmzI1s65WyAHNHzgzZ16ONL+GY/SgWBACEObSMIy Jw9nZ0KuqaQ7h4w2eWMrBWQyfmZDEVeJg6+JTUTNEoAeU2l+EPsrw+ZJF+c8SzrisDSRh5 HTh4HXHFitgBLeei5TuxThufkIdctkyU+hBV9aqAFVL9q9rzXZ3qCJy+nRT+Yw== From: Sander Vanheule To: linux-mips@vger.kernel.org Cc: INAGAKI Hiroshi , Jiaxun Yang , Paul Burton , Thomas Bogendoerfer , linux-kernel@vger.kernel.org, Sander Vanheule Subject: [PATCH v2 1/2] MIPS: only register MT SMP ops if MT is supported Date: Sat, 18 Dec 2021 11:05:10 +0100 Message-Id: <20211218100511.42508-2-sander@svanheule.net> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211218100511.42508-1-sander@svanheule.net> References: <20211218100511.42508-1-sander@svanheule.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Verify that the current CPU actually supports multi-threading before registering MT SMP ops, instead of unconditionally registering them if the kernel is compiled with CONFIG_MIPS_MT_SMP. Suggested-by: Jiaxun Yang Signed-off-by: Sander Vanheule --- arch/mips/include/asm/smp-ops.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/mips/include/asm/smp-ops.h b/arch/mips/include/asm/smp-ops.h index 65618ff1280c..864aea803984 100644 --- a/arch/mips/include/asm/smp-ops.h +++ b/arch/mips/include/asm/smp-ops.h @@ -101,6 +101,9 @@ static inline int register_vsmp_smp_ops(void) #ifdef CONFIG_MIPS_MT_SMP extern const struct plat_smp_ops vsmp_smp_ops; + if (!cpu_has_mipsmt) + return -ENODEV; + register_smp_ops(&vsmp_smp_ops); return 0; From patchwork Sat Dec 18 10:05:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sander Vanheule X-Patchwork-Id: 12686021 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A16DC433F5 for ; Sat, 18 Dec 2021 10:05:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230290AbhLRKF0 (ORCPT ); Sat, 18 Dec 2021 05:05:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51386 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231364AbhLRKF0 (ORCPT ); Sat, 18 Dec 2021 05:05:26 -0500 Received: from polaris.svanheule.net (polaris.svanheule.net [IPv6:2a00:c98:2060:a004:1::200]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C0429C061574 for ; Sat, 18 Dec 2021 02:05:25 -0800 (PST) Received: from terra.local.svanheule.net (unknown [IPv6:2a02:a03f:eafe:c901:e9c7:274f:a8f6:5f25]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sander@svanheule.net) by polaris.svanheule.net (Postfix) with ESMTPSA id C72FC282FBC; Sat, 18 Dec 2021 11:05:22 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=svanheule.net; s=mail1707; t=1639821923; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=H2SKZv6WDFCLBPFkqaOhYWcJOAHmG0CfGPXMaenmT9I=; b=t2oZ9oVSOkAO/ti0EEg6BCyib0jP8RMYivk8MpZ+RRLk1ZiL0JnewS2ND31Um/1SKooqSM ZXBE1EkHxzBwptJStCP2YjYiMX1JI1PeJi316NW9sn3hUsfwPqXExdHfFvmmW+rAS89rpe M4GDGVZnaIBqrwqCQiDV3s6G18Ria8dqFFqdBr66kziPjk5lSHtkHGuvBx/D7O3I8nKDnW z/VcQxrkSNC4mWivDxXQ7SMzLzFqit94bVSVuqm/1tJGqtJVkgAMvcz2Ca6HQ4WHJtaDjS Y6dw8S6DDlOQKO8xtulnYCtLNCKXvPTTMhKt1YjwGgvcUhGA2fwpDovylpS9sw== From: Sander Vanheule To: linux-mips@vger.kernel.org Cc: INAGAKI Hiroshi , Jiaxun Yang , Paul Burton , Thomas Bogendoerfer , linux-kernel@vger.kernel.org, Sander Vanheule Subject: [PATCH v2 2/2] MIPS: generic: enable SMP on SMVP systems Date: Sat, 18 Dec 2021 11:05:11 +0100 Message-Id: <20211218100511.42508-3-sander@svanheule.net> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211218100511.42508-1-sander@svanheule.net> References: <20211218100511.42508-1-sander@svanheule.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org In addition to CPS SMP setups, also try to initialise MT SMP setups with multiple VPEs per CPU core. CMP SMP support is not provided as it is considered deprecated. Additionally, rework the code by dropping the err variable and make it similar to how other platforms perform this initialisation. Co-developed-by: INAGAKI Hiroshi Signed-off-by: INAGAKI Hiroshi Signed-off-by: Sander Vanheule --- arch/mips/generic/init.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/mips/generic/init.c b/arch/mips/generic/init.c index 1842cddd8356..1d712eac1617 100644 --- a/arch/mips/generic/init.c +++ b/arch/mips/generic/init.c @@ -110,14 +110,15 @@ void __init plat_mem_setup(void) void __init device_tree_init(void) { - int err; - unflatten_and_copy_device_tree(); mips_cpc_probe(); - err = register_cps_smp_ops(); - if (err) - err = register_up_smp_ops(); + if (!register_cps_smp_ops()) + return; + if (!register_vsmp_smp_ops()) + return; + + register_up_smp_ops(); } int __init apply_mips_fdt_fixups(void *fdt_out, size_t fdt_out_size,