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Miller" , Florian Fainelli , Vivien Didelot , Andrew Lunn , UNGLinuxDriver@microchip.com, Alexandre Belloni , Claudiu Manoil , Vladimir Oltean , Lee Jones Subject: [RFC v5 net-next 01/13] mfd: ocelot: add support for external mfd control over SPI for the VSC7512 Date: Sat, 18 Dec 2021 13:49:42 -0800 Message-Id: <20211218214954.109755-2-colin.foster@in-advantage.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211218214954.109755-1-colin.foster@in-advantage.com> References: <20211218214954.109755-1-colin.foster@in-advantage.com> X-ClientProxiedBy: MWHPR02CA0011.namprd02.prod.outlook.com (2603:10b6:300:4b::21) To MWHPR1001MB2351.namprd10.prod.outlook.com (2603:10b6:301:35::37) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f7aa40a9-dbfa-4510-52c5-08d9c2705a8d X-MS-TrafficTypeDiagnostic: CO6PR10MB5633:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5797; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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This should allow any ocelot driver (pinctrl, miim, etc.) to be used externally, provided they utilize regmaps. Signed-off-by: Colin Foster --- drivers/mfd/Kconfig | 15 ++ drivers/mfd/Makefile | 3 + drivers/mfd/ocelot-core.c | 149 +++++++++++++++ drivers/mfd/ocelot-mfd.h | 19 ++ drivers/mfd/ocelot-spi.c | 374 ++++++++++++++++++++++++++++++++++++++ 5 files changed, 560 insertions(+) create mode 100644 drivers/mfd/ocelot-core.c create mode 100644 drivers/mfd/ocelot-mfd.h create mode 100644 drivers/mfd/ocelot-spi.c diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 3fb480818599..af76c9780a10 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -954,6 +954,21 @@ config MFD_MENF21BMC This driver can also be built as a module. If so the module will be called menf21bmc. +config MFD_OCELOT_CORE + tristate "Microsemi Ocelot External Control Support" + select MFD_CORE + help + Say yes here to add support for Ocelot chips (VSC7511, VSC7512, + VSC7513, VSC7514) controlled externally. + +config MFD_OCELOT_SPI + tristate "Microsemi Ocelot SPI interface" + depends on MFD_OCELOT_CORE + depends on SPI_MASTER + select REGMAP_SPI + help + Say yes here to add control to the MFD_OCELOT chips via SPI. + config EZX_PCAP bool "Motorola EZXPCAP Support" depends on SPI_MASTER diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 0b1b629aef3e..dff83f474fb5 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -120,6 +120,9 @@ obj-$(CONFIG_MFD_MC13XXX_I2C) += mc13xxx-i2c.o obj-$(CONFIG_MFD_CORE) += mfd-core.o +obj-$(CONFIG_MFD_OCELOT_CORE) += ocelot-core.o +obj-$(CONFIG_MFD_OCELOT_SPI) += ocelot-spi.o + obj-$(CONFIG_EZX_PCAP) += ezx-pcap.o obj-$(CONFIG_MFD_CPCAP) += motorola-cpcap.o diff --git a/drivers/mfd/ocelot-core.c b/drivers/mfd/ocelot-core.c new file mode 100644 index 000000000000..a65619a8190b --- /dev/null +++ b/drivers/mfd/ocelot-core.c @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Innovative Advantage Inc. + */ + +#include +#include +#include +#include +#include + +#include "ocelot-mfd.h" + +#define REG(reg, offset) [reg] = offset + +enum ocelot_mfd_gcb_regs { + GCB_SOFT_RST, + GCB_REG_MAX, +}; + +enum ocelot_mfd_gcb_regfields { + GCB_SOFT_RST_CHIP_RST, + GCB_REGFIELD_MAX, +}; + +static const u32 vsc7512_gcb_regmap[] = { + REG(GCB_SOFT_RST, 0x0008), +}; + +static const struct reg_field vsc7512_mfd_gcb_regfields[GCB_REGFIELD_MAX] = { + [GCB_SOFT_RST_CHIP_RST] = REG_FIELD(vsc7512_gcb_regmap[GCB_SOFT_RST], 0, 0), +}; + +struct ocelot_mfd_core { + struct ocelot_mfd_config *config; + struct regmap *gcb_regmap; + struct regmap_field *gcb_regfields[GCB_REGFIELD_MAX]; +}; + +static const struct resource vsc7512_gcb_resource = { + .start = 0x71070000, + .end = 0x7107022b, + .name = "devcpu_gcb", +}; + +static int ocelot_mfd_reset(struct ocelot_mfd_core *core) +{ + int ret; + + dev_info(core->config->dev, "resetting ocelot chip\n"); + + ret = regmap_field_write(core->gcb_regfields[GCB_SOFT_RST_CHIP_RST], 1); + if (ret) + return ret; + + /* + * Note: This is adapted from the PCIe reset strategy. The manual doesn't + * suggest how to do a reset over SPI, and the register strategy isn't + * possible. + */ + msleep(100); + + ret = core->config->init_bus(core->config); + if (ret) + return ret; + + return 0; +} + +void ocelot_mfd_get_resource_name(char *name, const struct resource *res, + int size) +{ + if (res->name) + snprintf(name, size - 1, "ocelot_mfd-%s", res->name); + else + snprintf(name, size - 1, "ocelot_mfd@0x%08x", res->start); +} +EXPORT_SYMBOL(ocelot_mfd_get_resource_name); + +static struct regmap *ocelot_mfd_regmap_init(struct ocelot_mfd_core *core, + const struct resource *res) +{ + struct device *dev = core->config->dev; + struct regmap *regmap; + char name[32]; + + ocelot_mfd_get_resource_name(name, res, sizeof(name) - 1); + + regmap = dev_get_regmap(dev, name); + + if (!regmap) + regmap = core->config->get_regmap(core->config, res, name); + + return regmap; +} + +int ocelot_mfd_init(struct ocelot_mfd_config *config) +{ + struct device *dev = config->dev; + const struct reg_field *regfield; + struct ocelot_mfd_core *core; + int i, ret; + + core = devm_kzalloc(dev, sizeof(struct ocelot_mfd_config), GFP_KERNEL); + if (!core) + return -ENOMEM; + + dev_set_drvdata(dev, core); + + core->config = config; + + /* Create regmaps and regfields here */ + core->gcb_regmap = ocelot_mfd_regmap_init(core, &vsc7512_gcb_resource); + if (!core->gcb_regmap) + return -ENOMEM; + + for (i = 0; i < GCB_REGFIELD_MAX; i++) { + regfield = &vsc7512_mfd_gcb_regfields[i]; + core->gcb_regfields[i] = + devm_regmap_field_alloc(dev, core->gcb_regmap, + *regfield); + if (!core->gcb_regfields[i]) + return -ENOMEM; + } + + /* Prepare the chip */ + ret = ocelot_mfd_reset(core); + if (ret) { + dev_err(dev, "ocelot mfd reset failed with code %d\n", ret); + return ret; + } + + /* Create and loop over all child devices here */ + + return 0; +} +EXPORT_SYMBOL(ocelot_mfd_init); + +int ocelot_mfd_remove(struct ocelot_mfd_config *config) +{ + /* Loop over all children and remove them */ + + return 0; +} +EXPORT_SYMBOL(ocelot_mfd_remove); + +MODULE_DESCRIPTION("Ocelot Chip MFD driver"); +MODULE_AUTHOR("Colin Foster "); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/mfd/ocelot-mfd.h b/drivers/mfd/ocelot-mfd.h new file mode 100644 index 000000000000..6af8b8c5a316 --- /dev/null +++ b/drivers/mfd/ocelot-mfd.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright 2021 Innovative Advantage Inc. + */ + +#include + +struct ocelot_mfd_config { + struct device *dev; + struct regmap *(*get_regmap)(struct ocelot_mfd_config *config, + const struct resource *res, + const char *name); + int (*init_bus)(struct ocelot_mfd_config *config); +}; + +void ocelot_mfd_get_resource_name(char *name, const struct resource *res, + int size); +int ocelot_mfd_init(struct ocelot_mfd_config *config); +int ocelot_mfd_remove(struct ocelot_mfd_config *config); diff --git a/drivers/mfd/ocelot-spi.c b/drivers/mfd/ocelot-spi.c new file mode 100644 index 000000000000..65ceb68f27af --- /dev/null +++ b/drivers/mfd/ocelot-spi.c @@ -0,0 +1,374 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Innovative Advantage Inc. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "ocelot-mfd.h" + +#define REG(reg, offset) [reg] = offset + +struct ocelot_spi { + int spi_padding_bytes; + struct spi_device *spi; + struct ocelot_mfd_config config; + struct regmap *cpuorg_regmap; + const u32 *map; +}; + +enum ocelot_dev_cpuorg_regs { + DEV_CPUORG_IF_CTRL, + DEV_CPUORG_IF_CFGSTAT, + DEV_CPUORG_REG_MAX, +}; + +static const u32 vsc7512_dev_cpuorg_regmap[] = { + REG(DEV_CPUORG_IF_CTRL, 0x0000), + REG(DEV_CPUORG_IF_CFGSTAT, 0x0004), +}; + +static const struct resource vsc7512_dev_cpuorg_resource = { + .start = 0x71000000, + .end = 0x710002ff, + .name = "devcpu_org", +}; + +#define VSC7512_BYTE_ORDER_LE 0x00000000 +#define VSC7512_BYTE_ORDER_BE 0x81818181 +#define VSC7512_BIT_ORDER_MSB 0x00000000 +#define VSC7512_BIT_ORDER_LSB 0x42424242 + +static struct ocelot_spi * +config_to_ocelot_spi(struct ocelot_mfd_config *config) +{ + return container_of(config, struct ocelot_spi, config); +} + +static int ocelot_spi_init_bus(struct ocelot_spi *ocelot_spi) +{ + struct spi_device *spi; + struct device *dev; + u32 val, check; + int err; + + spi = ocelot_spi->spi; + dev = &spi->dev; + + dev_info(dev, "initializing SPI interface for chip\n"); + + val = 0; + +#ifdef __LITTLE_ENDIAN + val |= VSC7512_BYTE_ORDER_LE; +#else + val |= VSC7512_BYTE_ORDER_BE; +#endif + + err = regmap_write(ocelot_spi->cpuorg_regmap, + ocelot_spi->map[DEV_CPUORG_IF_CTRL], val); + if (err) + return err; + + val = ocelot_spi->spi_padding_bytes; + err = regmap_write(ocelot_spi->cpuorg_regmap, + ocelot_spi->map[DEV_CPUORG_IF_CFGSTAT], val); + if (err) + return err; + + check = val | 0x02000000; + + err = regmap_read(ocelot_spi->cpuorg_regmap, + ocelot_spi->map[DEV_CPUORG_IF_CFGSTAT], &val); + if (err) + return err; + + if (check != val) { + dev_err(dev, "Error configuring SPI bus. V: 0x%08x != 0x%08x\n", + val, check); + return -ENODEV; + } + + return 0; +} + +static int ocelot_spi_init_bus_from_config(struct ocelot_mfd_config *config) +{ + struct ocelot_spi *ocelot_spi = config_to_ocelot_spi(config); + + return ocelot_spi_init_bus(ocelot_spi); +} + +static unsigned int ocelot_spi_translate_address(unsigned int reg) +{ + return cpu_to_be32((reg & 0xffffff) >> 2); +} + +struct ocelot_spi_regmap_context { + struct spi_device *spi; + u32 base; + int padding_bytes; +}; + +static int ocelot_spi_reg_read(void *context, unsigned int reg, + unsigned int *val) +{ + struct ocelot_spi_regmap_context *regmap_context = context; + struct spi_transfer tx, padding, rx; + struct ocelot_spi *ocelot_spi; + struct spi_message msg; + struct spi_device *spi; + unsigned int addr; + u8 *tx_buf; + + WARN_ON(!val); + + spi = regmap_context->spi; + + ocelot_spi = spi_get_drvdata(spi); + + addr = ocelot_spi_translate_address(reg + regmap_context->base); + tx_buf = (u8 *)&addr; + + spi_message_init(&msg); + + memset(&tx, 0, sizeof(struct spi_transfer)); + + /* Ignore the first byte for the 24-bit address */ + tx.tx_buf = &tx_buf[1]; + tx.len = 3; + + spi_message_add_tail(&tx, &msg); + + if (regmap_context->padding_bytes > 0) { + u8 dummy_buf[16] = {0}; + + memset(&padding, 0, sizeof(struct spi_transfer)); + + /* Just toggle the clock for padding bytes */ + padding.len = regmap_context->padding_bytes; + padding.tx_buf = dummy_buf; + padding.dummy_data = 1; + + spi_message_add_tail(&padding, &msg); + } + + memset(&rx, 0, sizeof(struct spi_transfer)); + rx.rx_buf = val; + rx.len = 4; + + spi_message_add_tail(&rx, &msg); + + return spi_sync(spi, &msg); +} + +static int ocelot_spi_reg_write(void *context, unsigned int reg, + unsigned int val) +{ + struct ocelot_spi_regmap_context *regmap_context = context; + struct spi_transfer tx[2] = {0}; + struct spi_message msg; + struct spi_device *spi; + unsigned int addr; + u8 *tx_buf; + + spi = regmap_context->spi; + + addr = ocelot_spi_translate_address(reg + regmap_context->base); + tx_buf = (u8 *)&addr; + + spi_message_init(&msg); + + /* Ignore the first byte for the 24-bit address and set the write bit */ + tx_buf[1] |= BIT(7); + tx[0].tx_buf = &tx_buf[1]; + tx[0].len = 3; + + spi_message_add_tail(&tx[0], &msg); + + memset(&tx[1], 0, sizeof(struct spi_transfer)); + tx[1].tx_buf = &val; + tx[1].len = 4; + + spi_message_add_tail(&tx[1], &msg); + + return spi_sync(spi, &msg); +} + +static const struct regmap_config ocelot_spi_regmap_config = { + .reg_bits = 24, + .reg_stride = 4, + .val_bits = 32, + + .reg_read = ocelot_spi_reg_read, + .reg_write = ocelot_spi_reg_write, + + .max_register = 0xffffffff, + .use_single_write = true, + .use_single_read = true, + .can_multi_write = false, + + .reg_format_endian = REGMAP_ENDIAN_BIG, + .val_format_endian = REGMAP_ENDIAN_NATIVE, +}; + +static struct regmap * +ocelot_spi_get_regmap(struct ocelot_mfd_config *config, + const struct resource *res, const char *name) +{ + struct ocelot_spi *ocelot_spi = config_to_ocelot_spi(config); + struct ocelot_spi_regmap_context *context; + struct regmap_config regmap_config; + struct regmap *regmap; + struct device *dev; + + + dev = &ocelot_spi->spi->dev; + + /* Don't re-allocate another regmap if we have one */ + regmap = dev_get_regmap(dev, name); + if (regmap) + return regmap; + + context = devm_kzalloc(dev, sizeof(struct ocelot_spi_regmap_context), + GFP_KERNEL); + + if (IS_ERR(context)) + return ERR_CAST(context); + + context->base = res->start; + context->spi = ocelot_spi->spi; + context->padding_bytes = ocelot_spi->spi_padding_bytes; + + memcpy(®map_config, &ocelot_spi_regmap_config, + sizeof(ocelot_spi_regmap_config)); + + regmap_config.name = name; + regmap_config.max_register = res->end - res->start; + + regmap = devm_regmap_init(dev, NULL, context, ®map_config); + if (IS_ERR(regmap)) + return ERR_CAST(regmap); + + return regmap; +} + +static int ocelot_spi_probe(struct spi_device *spi) +{ + struct ocelot_spi *ocelot_spi; + struct device *dev; + char name[32]; + int err; + + dev = &spi->dev; + + ocelot_spi = devm_kzalloc(dev, sizeof(struct ocelot_spi), + GFP_KERNEL); + + if (!ocelot_spi) + return -ENOMEM; + + if (spi->max_speed_hz <= 500000) { + ocelot_spi->spi_padding_bytes = 0; + } else { + /* + * Calculation taken from the manual for IF_CFGSTAT:IF_CFG. Err + * on the side of more padding bytes, as having too few can be + * difficult to detect at runtime. + */ + ocelot_spi->spi_padding_bytes = 1 + + (spi->max_speed_hz / 1000000 + 2) / 8; + } + + ocelot_spi->spi = spi; + ocelot_spi->map = vsc7512_dev_cpuorg_regmap; + + spi->bits_per_word = 8; + + err = spi_setup(spi); + if (err < 0) { + dev_err(&spi->dev, "Error %d initializing SPI\n", err); + return err; + } + + dev_info(dev, "configured SPI bus for speed %d, rx padding bytes %d\n", + spi->max_speed_hz, ocelot_spi->spi_padding_bytes); + + /* Ensure we have devcpu_org regmap before we call ocelot_mfd_init */ + ocelot_mfd_get_resource_name(name, &vsc7512_dev_cpuorg_resource, + sizeof(name) - 1); + + /* + * Since we created dev, we know there isn't a regmap, so create one + * here directly. + */ + ocelot_spi->cpuorg_regmap = + ocelot_spi_get_regmap(&ocelot_spi->config, + &vsc7512_dev_cpuorg_resource, name); + if (!ocelot_spi->cpuorg_regmap) + return -ENOMEM; + + ocelot_spi->config.init_bus = ocelot_spi_init_bus_from_config; + ocelot_spi->config.get_regmap = ocelot_spi_get_regmap; + ocelot_spi->config.dev = dev; + + spi_set_drvdata(spi, ocelot_spi); + + /* + * The chip must be set up for SPI before it gets initialized and reset. + * Do this once here before calling mfd_init + */ + err = ocelot_spi_init_bus(ocelot_spi); + if (err) { + dev_err(dev, "Error %d initializing Ocelot SPI bus\n", err); + return err; + } + + err = ocelot_mfd_init(&ocelot_spi->config); + if (err < 0) { + dev_err(dev, "Error %d initializing Ocelot MFD\n", err); + return err; + } + + dev_info(&spi->dev, "ocelot spi mfd probed\n"); + + return 0; +} + +static int ocelot_spi_remove(struct spi_device *spi) +{ + struct ocelot_spi *ocelot_spi; + + ocelot_spi = spi_get_drvdata(spi); + devm_kfree(&spi->dev, ocelot_spi); + return 0; +} + +const struct of_device_id ocelot_mfd_of_match[] = { + { .compatible = "mscc,vsc7514_mfd_spi" }, + { .compatible = "mscc,vsc7513_mfd_spi" }, + { .compatible = "mscc,vsc7512_mfd_spi" }, + { .compatible = "mscc,vsc7511_mfd_spi" }, + { }, +}; +MODULE_DEVICE_TABLE(of, ocelot_mfd_of_match); + +static struct spi_driver ocelot_mfd_spi_driver = { + .driver = { + .name = "ocelot_mfd_spi", + .of_match_table = of_match_ptr(ocelot_mfd_of_match), + }, + .probe = ocelot_spi_probe, + .remove = ocelot_spi_remove, +}; +module_spi_driver(ocelot_mfd_spi_driver); + +MODULE_DESCRIPTION("Ocelot Chip MFD SPI driver"); +MODULE_AUTHOR("Colin Foster "); +MODULE_LICENSE("Dual MIT/GPL"); From patchwork Sat Dec 18 21:49:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Colin Foster X-Patchwork-Id: 12686435 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D03F4C433F5 for ; Sat, 18 Dec 2021 21:50:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232653AbhLRVuJ (ORCPT ); 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Miller" , Florian Fainelli , Vivien Didelot , Andrew Lunn , UNGLinuxDriver@microchip.com, Alexandre Belloni , Claudiu Manoil , Vladimir Oltean , Lee Jones Subject: [RFC v5 net-next 02/13] mfd: ocelot: offer an interface for MFD children to get regmaps Date: Sat, 18 Dec 2021 13:49:43 -0800 Message-Id: <20211218214954.109755-3-colin.foster@in-advantage.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211218214954.109755-1-colin.foster@in-advantage.com> References: <20211218214954.109755-1-colin.foster@in-advantage.com> X-ClientProxiedBy: MWHPR02CA0011.namprd02.prod.outlook.com (2603:10b6:300:4b::21) To MWHPR1001MB2351.namprd10.prod.outlook.com (2603:10b6:301:35::37) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 772ee936-3acf-487c-3865-08d9c2705af6 X-MS-TrafficTypeDiagnostic: CO6PR10MB5633:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7219; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: +yLKPA4maNdFxCQFWXcO0eWWuz4ueriambPuFrr6RMFz2o9bFJP77HQ4HvbHV2fW9PI8TSXWpRWVvVVnbw0so1Xm49cZWojq5lHE9yP0zzBtBuSlUH5XYBjEmXjqGZLkLVJoOb/CyxvSZK6370BFhnIlMRSqz2XPXBKdyhjgaRSDdzSy0C0q/TrsRDQhVk4H4620E0kwrVcWy8hAMgvPF+u1UseB4J5e1WXjVWfEr5VSNRgSjJgqxbw8j7CtLmG8V7etGVbrIuyuxPJYMQwdp9Id7Q6i6Ha5vZGJx+fy/2q/fbGzPxIRco+RmQYiG9oe4o+44WdAg2eVoJqMbEIDdM6mYXr730I+zNgtwdA3wmunDFUWOSBIxoPi2Ig+YttmmhaN0bEC7cdzT77fJY667yQTXndedyyPyf7Y8EnOyuA4YuUfNEwNCqsslBqpEjHJR2e1RN9X2cSEeJW/sOwj/NEdLYZuaC35IP6xXBMBqQ19qdRrqB2HzvJCkZ1AI3ppm6BD+GrA35jrCrWEcBfEwrkEXmKnnUOx6ViXBFuwsucr6LAssEONpeJ/+gPaedH1GJq2eW7zEWaBWp+DRW6W17OeX5MC0eDgFD6VOrtW+ObA9G6C9D4/HOCCXqWZknk/bKJQaZNlKVeOBnrOSJKv8jI2tML22A/o12etTyskXIW/0rPk95KTMJ7jIwTKyYS4AqwO7qJ1ge69E/Vc1jIFjQ== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MWHPR1001MB2351.namprd10.prod.outlook.com;PTR:;CAT:NONE;SFS:(39830400003)(396003)(366004)(346002)(376002)(136003)(6486002)(6506007)(7416002)(2906002)(36756003)(6512007)(26005)(86362001)(66556008)(66476007)(186003)(1076003)(6666004)(4326008)(66946007)(2616005)(44832011)(8936002)(8676002)(316002)(54906003)(38100700002)(5660300002)(508600001)(52116002)(38350700002);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 52kJGgRmiFBqxxPtct9OzlUAtMtU/w98dVLsO8JYZ62vGpgWv4tFxpkPlYcBh8bCnv2bpyDo8Xwz32M3/nub1LhCEjnTcguoefGaOk6mXe2NDxN3ijFD2UrCg1x9/i9JeyjlzYk4NxuZYU7dUJGaetsjf9Kl4ANpQwAnomciWtW0x0mR44v+E35rbkm9mFOjQXmfKykw7Rtp9I3349xsE+FldUKOmX2eYOXlS6howwlN8G1DTyk5aJei+0xjtqKSZcnYiXYcgpZieqYnYroNS91IZVfMq3xc7oLMbj1L1frTt00nVssija0B6RXyIrJK2NQbcJPIW53pC9ZH9FC1ZA7ox+xAfi1p+yJcHzYPb7ASW7RA9b9tyxf3hAjdJSuML/YvfmE6+0ttfd/wf/DoWXokExGK1MegFb8sJV2BGc/QjelyBkWu5MjTbqqfgT43Ra4q2cfjrhlrZyB0bFUCKqBvmQnyAE8IXHXrd+3395PtRd6dtaAm42rZgMoJKsU7Z24cFmZW0iUZ/jFqyLz78Z20GQQMV2pF3dqfLePXw9KH1QH3YzLHfIpH/vYgnRyz/Eh50Xpj2uGakfERIf7mcGEufPLeo38yll5nOBo3BuCshWv6K3pruNSHHHcyAR0NShhMUNuDx35Qs5Egs3JCzVu31erLgQ8KiKfY7OiTQ4JCv8Uit4c2K5POvUfQ7EQv90UozGnDOGLvtaDZdDpPDvFO/79qRT4hflBuiN8RnZUPEAmg7TIXkzo6cqjy3bvZfg09QTHXzY2/9sZK6EUM6vnGPZJdQ63NO2fDDEBXRPaj00wSv8x7FE5rmH1IFrNoAlgQ6aLoGarAR0GgHFtJBq2BDtzfieNnD+irwDIm+3Lo3Tr1pSXxDb9Y8M4canxas/KrUBttuBVCy7PNGy1VRxKwC4FE+eNgmkvBiSHlNzcxMQV7bAbbCY7BNj8XRlsq86d3lAHG6riKBsqEDE+5kGzfRJauhc/Gb9dx7LZIQtCuyXpEGFHSBPcqwCE/MFn7Q6rCFNQdiLaROlHZ8Wftv8pn1sbP495rwyx3RTScRE1N5ayJeJzOonJ4vxCNlgj2R3oJoHJUrMsOdlZ/O1sErW08aw8foZshF30kZO6Th7gn3UTGOfB8VcCS5G+Y1iLCcD+jqVtbZ0KoUWhusEYXrFvhFxUrond6hhAlvB2nOS4mVun8lsCBHpL8rzm28BVZyaWn/lkLoZ/cXYDa/Bphb6R8dp+r3HBxgujcOh3e9naJRrD0oAoll1PhpoGk6yOolfPBqBy6N2FP4Lb97CG9LPKHqC3rFU0NgKcvxOaUadt8CDoBnXfmLUf28n3oWu2P9cIOe2WwNNe5esdVWpV986NQmizfH2cWEOxqRoAqNW3ap96Bmo3SnxW7rtlsarMFkyBYO4PKdHk9MQT1RPNLquSI3bNFP69fXN1yVYUK/9XRzS3j5g22FBnwy/82m91CqCeD0tO9fy+yHJRpJmkIdfcZuxf756jUgpXi/Ye67Rp6cyQx10fcsk8gvjpWJA8fXY9zCSOu8WSBVFUBM/gMmCizKGaKX7NrzMYz6FVaxmKCiT+8rOVqbGmRNAz9AR63Hu5cvWydBgF9N+kvuREsk1E4TNsZEOUuN0RKqFEadnsLehY8vuK82kmIe+YjVC1uAoznXfRIjMiR83t9b3FX3w== X-OriginatorOrg: in-advantage.com X-MS-Exchange-CrossTenant-Network-Message-Id: 772ee936-3acf-487c-3865-08d9c2705af6 X-MS-Exchange-CrossTenant-AuthSource: MWHPR1001MB2351.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Dec 2021 21:50:06.9722 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 48e842ca-fbd8-4633-a79d-0c955a7d3aae X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: BG6jh2hUQq6un17S0uaJCCputh9awEm/lGvaGYsYonNh2AYXqDCqKUswJj+I/tue3FBNLnnNHQDdpH9A0p9OzqmURVW17LLizrVCuZ8kyZU= X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR10MB5633 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC Child devices need to get a regmap from a resource struct, specifically from the MFD parent. The MFD parent has the interface to the hardware layer, which could be I2C, SPI, PCIe, etc. This is somewhat a hack... ideally child devices would interface with the struct device* directly, by way of a function like devm_get_regmap_from_resource which would be akin to devm_get_and_ioremap_resource. A less ideal option would be to interface directly with MFD to get a regmap from the parent. This solution is even less ideal than both of the two suggestions, so is intentionally left in a separate commit after the initial MFD addition. Signed-off-by: Colin Foster --- drivers/mfd/ocelot-core.c | 9 +++++++++ include/soc/mscc/ocelot.h | 12 ++++++++++++ 2 files changed, 21 insertions(+) diff --git a/drivers/mfd/ocelot-core.c b/drivers/mfd/ocelot-core.c index a65619a8190b..09132ea52760 100644 --- a/drivers/mfd/ocelot-core.c +++ b/drivers/mfd/ocelot-core.c @@ -94,6 +94,15 @@ static struct regmap *ocelot_mfd_regmap_init(struct ocelot_mfd_core *core, return regmap; } +struct regmap *ocelot_mfd_get_regmap_from_resource(struct device *dev, + const struct resource *res) +{ + struct ocelot_mfd_core *core = dev_get_drvdata(dev); + + return ocelot_mfd_regmap_init(core, res); +} +EXPORT_SYMBOL(ocelot_mfd_get_regmap_from_resource); + int ocelot_mfd_init(struct ocelot_mfd_config *config) { struct device *dev = config->dev; diff --git a/include/soc/mscc/ocelot.h b/include/soc/mscc/ocelot.h index 3e9454b00562..a641c9cc6f3f 100644 --- a/include/soc/mscc/ocelot.h +++ b/include/soc/mscc/ocelot.h @@ -968,4 +968,16 @@ ocelot_mrp_del_ring_role(struct ocelot *ocelot, int port, } #endif +#if IS_ENABLED(CONFIG_MFD_OCELOT_CORE) +struct regmap *ocelot_mfd_get_regmap_from_resource(struct device *dev, + const struct resource *res); +#else +static inline regmap * +ocelot_mfd_get_regmap_from_resource(struct device *dev, + const struct resource *res) +{ + return NULL; +} +#endif + #endif From patchwork Sat Dec 18 21:49:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Colin Foster X-Patchwork-Id: 12686441 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 04BAAC4332F for ; Sat, 18 Dec 2021 21:50:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234620AbhLRVuQ (ORCPT ); Sat, 18 Dec 2021 16:50:16 -0500 Received: from mail-mw2nam10on2096.outbound.protection.outlook.com ([40.107.94.96]:43520 "EHLO NAM10-MW2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S234479AbhLRVuK (ORCPT ); Sat, 18 Dec 2021 16:50:10 -0500 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=jW2U9RYaK324VctffosFqWhu64K4ApKPz2wSJx8ELGgrwrgE+ss6BFZCvOqC3hp5g7rfTzXcrnOyK2Gr1Cn+gSXWZRN7iME+N/Xd6MU+XC/Zh3ULuq3AMOVO+gE010D3F9LorbCW+uuTZXTgaDw9XkQOr03YUciFn2ZA+7XVcIWyLHnKHuDBRidxj2gpnPtYx1FCaisbkIBg6h3K9PRAnzUCfalyu1rcgkG2r/A1b8b1JhbbnMF3gf7kQeEqmSWTzEtlWaDd9Y5JXsLkrZpfYDZBxr2zvR4j3AQORXRnO3EgyTig0l0jHCeDmCm/nT2kpubnnQv5TQCZvViB8arJnA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=gMKqmCj/Dixm2MwPAU5k40NXtdtFq9m8iCvAqRZtU4U=; b=H7pUESj1I+6fO68mnVLp1F3HBJ2Pgd36vvKMczBfQeoauJnexvQoaLd919MvhYm06szANHI26Ot5WuaO3PiVnyjEt0gfyE8+at3+Bo1WtuCwQfWPCVhW+AU1x1lkpF/BeX8IqZ5uQFFv9cRIh2uZM7aOtijK50AO+a4fZ+FTy803y7l5w3ywbWWS4DGaPRRiHgzpEBpCKBJ9FpRddWm8P/S8Cr8Lmh/iXwsqzz21/EJoLda9bkDNHaSd/+oYOreNSkX1Oaf38OQWOCJDfmvuAzkTKsIpq+FP7cswero8eQNepEe45sbQ77zsGw4TIbsV8sKhjcaWKQq0o/igYU3jzw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=in-advantage.com; dmarc=pass action=none header.from=in-advantage.com; dkim=pass header.d=in-advantage.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=inadvantage.onmicrosoft.com; s=selector2-inadvantage-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=gMKqmCj/Dixm2MwPAU5k40NXtdtFq9m8iCvAqRZtU4U=; b=fhjOOX5Gj77HrQU/6BamxX7bMByYz9WcFcXy5r7Q2mPsr1gIz1wqbQgQH61qifyT3f3vvnLfYUK3vZ1++vVnGmbLb14zd6NeN6h92NJIKbIf48EvjtaTcvmX4CIxNP5lLpP/x9MSZjHKINvKw7QJgt55qEkE7K6IGwDcbESLMyI= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=in-advantage.com; Received: from MWHPR1001MB2351.namprd10.prod.outlook.com (2603:10b6:301:35::37) by CO6PR10MB5633.namprd10.prod.outlook.com (2603:10b6:303:148::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4801.17; Sat, 18 Dec 2021 21:50:08 +0000 Received: from MWHPR1001MB2351.namprd10.prod.outlook.com ([fe80::2d52:2a96:7e6c:460f]) by MWHPR1001MB2351.namprd10.prod.outlook.com ([fe80::2d52:2a96:7e6c:460f%4]) with mapi id 15.20.4801.017; Sat, 18 Dec 2021 21:50:07 +0000 From: Colin Foster To: linux-gpio@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Linus Walleij , Russell King , Heiner Kallweit , Jakub Kicinski , "David S. Miller" , Florian Fainelli , Vivien Didelot , Andrew Lunn , UNGLinuxDriver@microchip.com, Alexandre Belloni , Claudiu Manoil , Vladimir Oltean , Lee Jones Subject: [RFC v5 net-next 03/13] net: mscc: ocelot: expose ocelot wm functions Date: Sat, 18 Dec 2021 13:49:44 -0800 Message-Id: <20211218214954.109755-4-colin.foster@in-advantage.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211218214954.109755-1-colin.foster@in-advantage.com> References: <20211218214954.109755-1-colin.foster@in-advantage.com> X-ClientProxiedBy: MWHPR02CA0011.namprd02.prod.outlook.com (2603:10b6:300:4b::21) To MWHPR1001MB2351.namprd10.prod.outlook.com (2603:10b6:301:35::37) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 87fe480e-3039-4d0f-e28b-08d9c2705b63 X-MS-TrafficTypeDiagnostic: CO6PR10MB5633:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6108; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 4T5HjLC9ZTes8pxQQI52OeRSxYAjauutj1joaUO5O9KKmzO0ESu/0ClfjOvVxqxbN/rgd8IXnvFsOUoXGIjPbmRxF4z4y2ua74AIzQRINtHDAHRbEoDzz9A+4krGenXZmcGZnIfDZxZAjs7ia/+GfSZz9aTgiaIUHZ3SofqkgUIXI1NhsqG08YBeW4FyPjiJKfK0OOiStg3cC40NyhtmV3Sak+r+YTW8v9IJPQW1hoNjJhP8Mbo8Y3noJ1wAmgiva1I7QvKTvMvA8t1a9YEp++y/TGJbHcw9ep2fB3dQi68tK5XjrlNl7YlPOepmLsYhT/D4IUMWp/697KyyeKk7jVohCZ+tl6x8Ha+pzCJTkIbPIUuYqFFbaUDrOKPJgS2OQtfUc3XTBb3qy7chsFuYRx0VY5ifdOaIuQg/qq+1Qpx74zDQijFWOAc2cFFztqjdvr4L2KA2wpF3KoJQ4+rBUT2bwYfshcsc8IXi8OH0GLroj5CS75D0S0JbytRwlds9BnQ9cjXpJrMZfYSICvNtDkPuwlYXhzUVDUrTI2OeXAAnES7zDyXN9htXx4iy4BiJd9p6pBwwieobvqMZGJZBHKzp9y3nplqLd/aEtrDSNuMQs/ipsyABiMAF6mQy/7g0Fk428Nae1knuUCx6tYw+kgxHgcUV1pxwG9hIz8yw3QgiE7LwqFt+eIXVJwa/2b+2JD5FLOFlic3b5Ud9UklQkQ== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MWHPR1001MB2351.namprd10.prod.outlook.com;PTR:;CAT:NONE;SFS:(39830400003)(396003)(366004)(346002)(376002)(136003)(6486002)(6506007)(7416002)(2906002)(36756003)(6512007)(26005)(86362001)(66556008)(66476007)(186003)(1076003)(6666004)(4326008)(83380400001)(66946007)(2616005)(44832011)(8936002)(8676002)(316002)(54906003)(38100700002)(5660300002)(508600001)(52116002)(38350700002);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: ff9IuBx0xjSi2U5kmCUlA0+57HgecFLJ0jPthUdWgZdwQXYVoWL7l0SI1ComcTVDyE39cu68FvC2NF75zHbu7sH+LLhexh+5OjBYj8MNFkC4BXF81QDSdUAwBh9qYeaEy1KFmnu9KmAaVIXfVXCY1uI3I3YP4OR0+whUtC6HD6RfwiGzPLQoD16X/TKFI/Dlp2oyVBc953k8OMFQEj+CRFRoBlfYh73YE70g+7peeGxCzj7NWFpzjFGUitsa4eDibaU6PNn8uBMSKwfsnKLc1b3W/BTLnHb5uRN/uCHKlh/NyKP4HBAd28jKEqoODCsq4AlLVYTSwSNHX/CL7hdRkNM+naJ8Z6NXkxzNzi/yWgxKTSyT2zdoJqVo6/6L3JfgUxqCs6VVs/1B9KtV3F14mdHbgnSSBB0zhEm7Ve+JlCx2rLVmKzOrX4VvVx6u4jjTp3vsLPC2lik8dZ9xYmXV5BoTkRzZoN3qazATyQzQDNDaD5pGlAW8A7VXFeuT1zZ3fDg+nsW14DlAfEqb3MEpKDaOtOYF/bZ5I4Po1rjjM9Ee/vfo54zUqYm7F+679fV7l9TdXFnDGzXL32Pv4EQsiPnFNosLMQvYM1QlxktCfFjzkXME2RnrxoCXDOuyhkynvMkamd9b99FNm+1wf426SEUGZjzqz+Qd3mtp1l5yWB4OrGsZhFIU/YP3cLZkMuUM2pzjbEeAFGevF8Acxzp5iBe2utFkjlWx7g67qSe4vWk09Z+Aw3FLg5jETzzep8q6fzRn8SJodOin7OXjk/wG4uWBseUY8VSgZ7cFl8manHOZV+Plj6wPb2yy2p50VhpywzikC7chvJE6ZckhIPvQ+M64Ao2n11NT+OE8yUhIxCVAi8vBH+knAtT6FQLizN9jsrwxQtb5md4K4htTWesQNxX6lyIK9Zn1fUb5M2aOFk9wKPixOLs4m0ng+Z12XWakL8mXD+BtN5OhPcXMRl8zMZGBt8MWAoyHKO0HgEzyoH6Pv1RtJYPLBLq2nsmUisAzT1zrjR82qIC9geXl4zxU4X7tZrw7KqTkQO7ukutAOVtTVnuHL2BXFjMvkXWPJ4nMbh2f6W/ghloo/djOPQkpfea3/xWoVFprVw9TwWiL7HBy6hSxduFEcfQ8YS1hZJjImWi7b0WIbtW/OlYOM8ZO2TjhCSvCKdZkITwA6z4ago8atc2GoPzzpX7u9Mf0PKMYLQIcwsGo1ksA2JDPTb1gBdIbodh8D5cjA2O8Kj0Epzh7a0cjfCotjermICA3qQeQddvQMfSiiljjnEhO3aDSDW6KSELw55SJv2gtJNwiQGH7K1QrvbmPBy9OOhWdPBP96FdvIFl/jI6o0pm7k4Uw2bD9f9y7ZnUsX/kSsZ/WcvvD/0cIPopsAvjZOkLHbHMySiWAFSw7Wl1mx2tL4IIGuXM94DF/IwdT+miFwTfX02IUV0xfwsGJd2f1w/3e60x9ZHWht7cQpQ5M3SQ458Y1EbRCLgWl2wFtC8kIDVKFOLF3aOadC715I7W8VGoBYfTYFYf2wA22rxvOhF4WUHzK/pduktUHLxopoJiLcH6eFr1CmLaaGIm2YZkVsj5wtq3ojtgQuMSht+7CVxkazUuiNLEO8BDUqJ4j1aeFJafYAYgKBcmcW+qZN4AxDq/G69gR7hWSNIglzQG5bXM2XuAKGg== X-OriginatorOrg: in-advantage.com X-MS-Exchange-CrossTenant-Network-Message-Id: 87fe480e-3039-4d0f-e28b-08d9c2705b63 X-MS-Exchange-CrossTenant-AuthSource: MWHPR1001MB2351.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Dec 2021 21:50:07.7690 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 48e842ca-fbd8-4633-a79d-0c955a7d3aae X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: spVaGF8tmTSzzLpxKTWumXd961pg+fzReTzo5McUBUHs0GPdhNDsvbj0YQ0erJgpyWm5eXlWt6cFQlMZ6Jt9AGlofW/m24OEZnUT0r2GJHo= X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR10MB5633 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC Expose ocelot_wm functions so they can be shared with other drivers. Signed-off-by: Colin Foster Reviewed-by: Vladimir Oltean --- drivers/net/ethernet/mscc/ocelot_devlink.c | 31 ++++++++++++++++++++++ drivers/net/ethernet/mscc/ocelot_vsc7514.c | 28 ------------------- include/soc/mscc/ocelot.h | 5 ++++ 3 files changed, 36 insertions(+), 28 deletions(-) diff --git a/drivers/net/ethernet/mscc/ocelot_devlink.c b/drivers/net/ethernet/mscc/ocelot_devlink.c index b8737efd2a85..d9ea75a14f2f 100644 --- a/drivers/net/ethernet/mscc/ocelot_devlink.c +++ b/drivers/net/ethernet/mscc/ocelot_devlink.c @@ -487,6 +487,37 @@ static void ocelot_watermark_init(struct ocelot *ocelot) ocelot_setup_sharing_watermarks(ocelot); } +/* Watermark encode + * Bit 8: Unit; 0:1, 1:16 + * Bit 7-0: Value to be multiplied with unit + */ +u16 ocelot_wm_enc(u16 value) +{ + WARN_ON(value >= 16 * BIT(8)); + + if (value >= BIT(8)) + return BIT(8) | (value / 16); + + return value; +} +EXPORT_SYMBOL(ocelot_wm_enc); + +u16 ocelot_wm_dec(u16 wm) +{ + if (wm & BIT(8)) + return (wm & GENMASK(7, 0)) * 16; + + return wm; +} +EXPORT_SYMBOL(ocelot_wm_dec); + +void ocelot_wm_stat(u32 val, u32 *inuse, u32 *maxuse) +{ + *inuse = (val & GENMASK(23, 12)) >> 12; + *maxuse = val & GENMASK(11, 0); +} +EXPORT_SYMBOL(ocelot_wm_stat); + /* Pool size and type are fixed up at runtime. Keeping this structure to * look up the cell size multipliers. */ diff --git a/drivers/net/ethernet/mscc/ocelot_vsc7514.c b/drivers/net/ethernet/mscc/ocelot_vsc7514.c index 4f4a495a60ad..5e526545ef67 100644 --- a/drivers/net/ethernet/mscc/ocelot_vsc7514.c +++ b/drivers/net/ethernet/mscc/ocelot_vsc7514.c @@ -307,34 +307,6 @@ static int ocelot_reset(struct ocelot *ocelot) return 0; } -/* Watermark encode - * Bit 8: Unit; 0:1, 1:16 - * Bit 7-0: Value to be multiplied with unit - */ -static u16 ocelot_wm_enc(u16 value) -{ - WARN_ON(value >= 16 * BIT(8)); - - if (value >= BIT(8)) - return BIT(8) | (value / 16); - - return value; -} - -static u16 ocelot_wm_dec(u16 wm) -{ - if (wm & BIT(8)) - return (wm & GENMASK(7, 0)) * 16; - - return wm; -} - -static void ocelot_wm_stat(u32 val, u32 *inuse, u32 *maxuse) -{ - *inuse = (val & GENMASK(23, 12)) >> 12; - *maxuse = val & GENMASK(11, 0); -} - static const struct ocelot_ops ocelot_ops = { .reset = ocelot_reset, .wm_enc = ocelot_wm_enc, diff --git a/include/soc/mscc/ocelot.h b/include/soc/mscc/ocelot.h index a641c9cc6f3f..37bc9d647bc2 100644 --- a/include/soc/mscc/ocelot.h +++ b/include/soc/mscc/ocelot.h @@ -812,6 +812,11 @@ void ocelot_deinit(struct ocelot *ocelot); void ocelot_init_port(struct ocelot *ocelot, int port); void ocelot_deinit_port(struct ocelot *ocelot, int port); +/* Watermark interface */ +u16 ocelot_wm_enc(u16 value); +u16 ocelot_wm_dec(u16 wm); +void ocelot_wm_stat(u32 val, u32 *inuse, u32 *maxuse); + /* DSA callbacks */ void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data); void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data); From patchwork Sat Dec 18 21:49:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Colin Foster X-Patchwork-Id: 12686443 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0BF4BC433F5 for ; Sat, 18 Dec 2021 21:50:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234636AbhLRVuR (ORCPT ); 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Miller" , Florian Fainelli , Vivien Didelot , Andrew Lunn , UNGLinuxDriver@microchip.com, Alexandre Belloni , Claudiu Manoil , Vladimir Oltean , Lee Jones Subject: [RFC v5 net-next 04/13] net: dsa: felix: add configurable device quirks Date: Sat, 18 Dec 2021 13:49:45 -0800 Message-Id: <20211218214954.109755-5-colin.foster@in-advantage.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211218214954.109755-1-colin.foster@in-advantage.com> References: <20211218214954.109755-1-colin.foster@in-advantage.com> X-ClientProxiedBy: MWHPR02CA0011.namprd02.prod.outlook.com (2603:10b6:300:4b::21) To MWHPR1001MB2351.namprd10.prod.outlook.com (2603:10b6:301:35::37) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 0c0cf8a7-4b89-4ce0-2884-08d9c2705bee X-MS-TrafficTypeDiagnostic: CO6PR10MB5633:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8273; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 20yE39jlSSbuauD7r7DFXyNY61rFPWTDgH7ji7hq/wiUg4sx+QyDtWvsGL1NlDtgmBzsa/kT+skfW1C6dzO2DsFrVw7DAOaGeRU/0Numxwu5Nhj2UYa6cKMgRrjTAMMcyJPzrFN1LZCFs9KrOoriB4ne9zTUXPGakLE7a9ZLVR3orMmK+s4OUuvuBFgiY9IjEN6pH/xJ2UdyikMAyXJg5/eQSlgdtSlYjbnhVtce9MOjKdHyzB3SGJ1m/ToVyclMaPtXi24tC6f6YrxAmilz6V0uE0Jj6yixFbqWKWnFRVj9wa8tgc7kDOJT02m6q2LPKOTbhFwqQnFqkVSMwklyTHKPS2zd4IewIDlpjI8wqkSrv8cQtWHCxfiVZhuq+X9io0Qkw5cSdmR0fijx/XbMDEgaVNlzWqff2qIP5tu9quWOAM1vi+tXCn1MxBjZK2U2VrIuN25r1nZdW3QEVvYiP8yYrj78PzfwxlU0Gmm7cr9t+kWc/csL/OFPr0dpTa3kywuZNeM3K0a2CsNjExK50iVw2Wp5K+OxemSiTVnMcMeZSK1jYP6oKNpbtxRA7gX1ylD2gbUa7LHlqtiLvgq+xj/xnhG54KMRspwoZt50DQyj3GkWwWYgCkMYT8AdiFzJG+W4ZwwtAOgoUu6B8c2dJsQmya089ALNQQ6y//l45wkjH8ZhI/9a6S/6yw0jHUfg3W0BdId0VFWhMRVb54+Jyg== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MWHPR1001MB2351.namprd10.prod.outlook.com;PTR:;CAT:NONE;SFS:(39830400003)(396003)(366004)(346002)(376002)(136003)(6486002)(6506007)(7416002)(2906002)(36756003)(6512007)(26005)(86362001)(66556008)(66476007)(186003)(1076003)(6666004)(4326008)(83380400001)(66946007)(2616005)(44832011)(8936002)(8676002)(316002)(54906003)(38100700002)(5660300002)(508600001)(52116002)(38350700002);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 1rEXSbPS8eu0Fna9gRepvjtCEeWdjdQ7tzzZe8IG5rH5SzHauLypau7RS20Ihvw/cH8Eh+CTmGRK1BRhYXw2O9vg7BmoJK1j0J7mzia8mQprNeY5ZS/J28T32q82nBPFcViW2TMr/cXsXw5rbaAHFy2rFvBodo9E59ha04SpT22mWSJlHIK/693HRihrZ7Fiq9lVBcAdGTPCOBEHMP6oSYReWMhJMkv1z+3GTKTfaUT/+8SM9z0c83IGtAxzM70YwbaIuJOEyLNxN5aI2mfo8xkOsH4dIX3QwCloAZicL6wd3vafwHoYGzXzWClL3lChmrPvJOGzbl0D2010jSK1hPVUT46X0JjMaDLrBCFIly1NCmKzFR8BbwwPr5T5+BoEYhbY5R/WL6hZHQqlqBV0L6Zq55/7l0xTIeUxJVejYx/9Y483lmXbo/robInZZqVdqppz1Joex+2pgIXBVr552kGBMGYY+AfUX7OOtJKxtoEOF8X340yIG/sc5dLUu+PfTqBNd23a7SS2Pt5DIM8vgroHaRyjCDOo/oRm9vaMGEn/BDi6zc+sZC5tWtkanLF4v0uL2GFJBedNHcetqsshsttLMeUQRH3UwEZwfguQPCSjLcb4AX2bAU4vpdzbvFbR5nkXKDiO38+QwYNhwIOfJ7jzOCASu9ShBlgQxdFWsWPIXaxHQOQNUy2istzWmCyge4iac49Bow49T9+ypsPHGATwPhyfIguT36JnNXwcd0x6lvEOTGO9FBtUAJMpIM4srI+cFGS2ZCC2uqado0kWo82PfWIFI7G9uCbWrFXrWb+DT4gSIBE0i6nuVt1sPWIzlDv3Oapyz2z1UfoV7cTatr4AM+npM9rUF9CbEJlPFRT97BRrmdW4PVOBB7hE4EaQ3i+iMtTT5R7Oxhpy1TFEN7Oi0fBNOyZpfGfvlbJ9kLH+nEV9pn+SjX31t7vB0KDpdtQgqrdsSH+NRxU5WftNvoN+2wi+geRU+URWem9xDHSezqPYFFudG0qLztfXjpwN+SgFumdXgildhP/oYdD7cdXxutMY/HZAg/5zRT/5cGrJoJUQcOgGCL6NFSeclU1xf2cp/gL9ocP2UAmRAGZmBY1lrYxBZjZl6qob1DrlJmPlhu6rRoksvyda8Kk7LcqTthsnma4ajMNyjrJ8ApkhVpSYaauwn0Hy2ocX6NPSVtJfh4kqJqhqno18I57W8+wJY5JQNUvbYddLDZEEK2t7s9sI4z26tH3UNdGwwoSK+pNqbPI//yKg4KxZOCMEV/SnpWB0JdiwZid55NtT4Vdp5QHDnIs4PNXkRhCZltyoFxzTuxLw908YZODp1DSRV0sILjbBwD1IkbhUL/n/bERhsumnay/MBYLSLZto2C2pba582a9bKXjwucFqcYI7jUywO2yHjEUFzoVvBuBen9306jWba52670HSpdqrbECzilPBxdq8igivfPCaHVn1L5dwMtXpeNIdqPDlRZbYy4XCqtdnGYhbprAe8iuY+97G7MWBidm5VCwmhBg6UPqF+AUm7nh5Uf5zAunN8ELRmjkoraFVlyTV06gszQUCUZjRs2zMeinPsez5uEzcNRprR424FvBWZ4HC7rYnklhilHj3MEe/mAbDSNTYOSnuotx8J47DPexCoB90HFOMbWefyBUsT7xcWOptrsKC+UzHV2T0uA== X-OriginatorOrg: in-advantage.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0c0cf8a7-4b89-4ce0-2884-08d9c2705bee X-MS-Exchange-CrossTenant-AuthSource: MWHPR1001MB2351.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Dec 2021 21:50:08.7377 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 48e842ca-fbd8-4633-a79d-0c955a7d3aae X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: ihxktbP1jOvvPKjvtTnhnLSe3qfMwBpQ4Aih250k9AFL2Z/y3R+P53X8IcPg4vMrJckbq6EoxwmnO672soYq3L8ReRd8mHjUuR+mTw/xAlo= X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR10MB5633 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC The define FELIX_MAC_QUIRKS was used directly in the felix.c shared driver. Other devices (VSC7512 for example) don't require the same quirks, so they need to be configured on a per-device basis. Signed-off-by: Colin Foster --- drivers/net/dsa/ocelot/felix.c | 7 +++++-- drivers/net/dsa/ocelot/felix.h | 1 + drivers/net/dsa/ocelot/felix_vsc9959.c | 1 + drivers/net/dsa/ocelot/seville_vsc9953.c | 1 + 4 files changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/net/dsa/ocelot/felix.c b/drivers/net/dsa/ocelot/felix.c index f4fc403fbc1e..757ae35f3d56 100644 --- a/drivers/net/dsa/ocelot/felix.c +++ b/drivers/net/dsa/ocelot/felix.c @@ -840,9 +840,12 @@ static void felix_phylink_mac_link_down(struct dsa_switch *ds, int port, phy_interface_t interface) { struct ocelot *ocelot = ds->priv; + struct felix *felix; + + felix = ocelot_to_felix(ocelot); ocelot_phylink_mac_link_down(ocelot, port, link_an_mode, interface, - FELIX_MAC_QUIRKS); + felix->info->quirks); } static void felix_phylink_mac_link_up(struct dsa_switch *ds, int port, @@ -857,7 +860,7 @@ static void felix_phylink_mac_link_up(struct dsa_switch *ds, int port, ocelot_phylink_mac_link_up(ocelot, port, phydev, link_an_mode, interface, speed, duplex, tx_pause, rx_pause, - FELIX_MAC_QUIRKS); + felix->info->quirks); if (felix->info->port_sched_speed_set) felix->info->port_sched_speed_set(ocelot, port, speed); diff --git a/drivers/net/dsa/ocelot/felix.h b/drivers/net/dsa/ocelot/felix.h index 515bddc012c0..69c97f35a607 100644 --- a/drivers/net/dsa/ocelot/felix.h +++ b/drivers/net/dsa/ocelot/felix.h @@ -26,6 +26,7 @@ struct felix_info { u16 vcap_pol_base2; u16 vcap_pol_max2; const struct ptp_clock_info *ptp_caps; + u32 quirks; /* Some Ocelot switches are integrated into the SoC without the * extraction IRQ line connected to the ARM GIC. By enabling this diff --git a/drivers/net/dsa/ocelot/felix_vsc9959.c b/drivers/net/dsa/ocelot/felix_vsc9959.c index 110d6c403bdd..c6ee393fd35c 100644 --- a/drivers/net/dsa/ocelot/felix_vsc9959.c +++ b/drivers/net/dsa/ocelot/felix_vsc9959.c @@ -2229,6 +2229,7 @@ static const struct felix_info felix_info_vsc9959 = { .num_mact_rows = 2048, .num_ports = 6, .num_tx_queues = OCELOT_NUM_TC, + .quirks = FELIX_MAC_QUIRKS, .quirk_no_xtr_irq = true, .ptp_caps = &vsc9959_ptp_caps, .mdio_bus_alloc = vsc9959_mdio_bus_alloc, diff --git a/drivers/net/dsa/ocelot/seville_vsc9953.c b/drivers/net/dsa/ocelot/seville_vsc9953.c index e110550e3507..a7db8781310b 100644 --- a/drivers/net/dsa/ocelot/seville_vsc9953.c +++ b/drivers/net/dsa/ocelot/seville_vsc9953.c @@ -1097,6 +1097,7 @@ static const struct felix_info seville_info_vsc9953 = { .vcap_pol_max = VSC9953_VCAP_POLICER_MAX, .vcap_pol_base2 = VSC9953_VCAP_POLICER_BASE2, .vcap_pol_max2 = VSC9953_VCAP_POLICER_MAX2, + .quirks = FELIX_MAC_QUIRKS, .num_mact_rows = 2048, .num_ports = 10, .num_tx_queues = OCELOT_NUM_TC, From patchwork Sat Dec 18 21:49:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Colin Foster X-Patchwork-Id: 12686445 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5FE4CC4167B for ; Sat, 18 Dec 2021 21:50:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234698AbhLRVuS (ORCPT ); Sat, 18 Dec 2021 16:50:18 -0500 Received: from mail-mw2nam10on2096.outbound.protection.outlook.com ([40.107.94.96]:43520 "EHLO NAM10-MW2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S234593AbhLRVuP (ORCPT ); Sat, 18 Dec 2021 16:50:15 -0500 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=N0BmOf1P3SO0BeRz3qMZRp7S9MkE86NaKg6qsFRI3eDQeHVyamIDWcvZjjm+CZSPF+e64hN5JzdSKn33tdc6+adXE24zWLHVwWoVJSGsAos0shjsr1DPBLjw7OMRsinqRpPeh/zcz+elef3GTh27NvmULCODRJuhQbhbUsOYiYPM5py+cdPUOPGrOaLWleB9c3RtrHmyu4N6P90SMNJt94LkN2pwcs5BI7QY/4D1El4RoQgzD9LEWyDmV2OqHIVBhYmWMGovUo2oWT453MwnXRasRg0qatHvrLCDomVJ+WCB4Uxbafzd7RPOCDvqLxu72OtrrXb+N3GXxtcBp1o1Lg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=orYlgVepX2TzvbBiuzCvrQ30xZBjX9RHGuownUsY77Q=; b=UgrN+6XPbEEvXSgtUYN4U9T3d7H10AogTIxyb0YlP6U2ztTcE0iZhbDJKykW7msDeHbfugBwsdEtTCWx8FznzNpZXBXv9s/lPrQkeZVXcPbTt5A6Pr26NpaMRL3soozE5h9ZXUMsi5lhCcGiQkDH0JH+wKPZ2XgM6cZUvVVsFN0KhpewEJm9xZGbRgpcYzeGQ0tgbafYWv1Oz9JnZLEdVVyzUq+viKshurEeTJlZi0w/Q4t2EaIirFa9/FrtNa9zq7skzzCiTdeSI1xcoNMwqDuvNbKSZiLYOGPvYBqPcCVACTPWTiVItUnCg+nw0mj8ymgitXvxhy84kPGql0O5vg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=in-advantage.com; dmarc=pass action=none header.from=in-advantage.com; dkim=pass header.d=in-advantage.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=inadvantage.onmicrosoft.com; s=selector2-inadvantage-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=orYlgVepX2TzvbBiuzCvrQ30xZBjX9RHGuownUsY77Q=; b=aRgOUBZcTNtMtPxhjrR/ORiMaOPxtGtDjlpOo4LmdhMNFATUTxagmcyBAnrjMkCMhmuX4+rriQEFa/QZ/hTc1apN+PGO8jUcwhU2I8p01vNiP3KLoULkN7+AEQOx0uwJSRiQXM23zstf7h0CdyKju3VwUCR/4uH3FbaV818kQnM= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=in-advantage.com; Received: from MWHPR1001MB2351.namprd10.prod.outlook.com (2603:10b6:301:35::37) by CO6PR10MB5633.namprd10.prod.outlook.com (2603:10b6:303:148::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4801.17; Sat, 18 Dec 2021 21:50:09 +0000 Received: from MWHPR1001MB2351.namprd10.prod.outlook.com ([fe80::2d52:2a96:7e6c:460f]) by MWHPR1001MB2351.namprd10.prod.outlook.com ([fe80::2d52:2a96:7e6c:460f%4]) with mapi id 15.20.4801.017; Sat, 18 Dec 2021 21:50:09 +0000 From: Colin Foster To: linux-gpio@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Linus Walleij , Russell King , Heiner Kallweit , Jakub Kicinski , "David S. Miller" , Florian Fainelli , Vivien Didelot , Andrew Lunn , UNGLinuxDriver@microchip.com, Alexandre Belloni , Claudiu Manoil , Vladimir Oltean , Lee Jones Subject: [RFC v5 net-next 05/13] net: mdio: mscc-miim: add ability to externally register phy reset control Date: Sat, 18 Dec 2021 13:49:46 -0800 Message-Id: <20211218214954.109755-6-colin.foster@in-advantage.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211218214954.109755-1-colin.foster@in-advantage.com> References: <20211218214954.109755-1-colin.foster@in-advantage.com> X-ClientProxiedBy: MWHPR02CA0011.namprd02.prod.outlook.com (2603:10b6:300:4b::21) To MWHPR1001MB2351.namprd10.prod.outlook.com (2603:10b6:301:35::37) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 0d3c8fae-3ec8-4617-0c15-08d9c2705c76 X-MS-TrafficTypeDiagnostic: CO6PR10MB5633:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:773; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: JUgJqvW41icO08e6VFz4+v6ZtiSTKUtmcWyVqesF5yjNqgaqR/BZTS24C0zA3v6uGmf5W26p3NDnWMGI82FibhCdikjER6VTNRvdTyaQWgm6aD4UHYGHrVa5BSjihWGdmUVO1ou/f7SPFo9RlWZ92NVRcB/GKX8FcsIErWS3d8FzN/UlC1jJI7+8TlDFelqc24ZdORreECN1p8JmEPAWbiRp/vHbYagYYP4ZyvufocHI+yhtsYEuoAlyg4roijZo3gBwbu44azbqQHqbg8Gh2FBl4JVeNtkiwtLQGR2nByb6867PZYdkskMbHHoKn8xg5VsGvq2oOM4g+W398ktHB7xj7vxrVpCx9ZwMgAQXBjM8jf4r0h7UZ37XB7hM55zvQlIE0iZk/q91lqPSuI0VCwH2Ka3WuUwFf/qC7/XshGsXtMT2GbMNHx/sgi7V9yOqMfIocEKPcl9J5Btvl/ZlFyZhu14gYHHqmMEX/MNBvaXOreLJbRIAY7P8F6cj29QZ3tyeNHnTo51Ny6Xy/koPScb28PErQanQZzKdtFmweMHnJk3/UnZ0rFR8gSYxRc7r+aov9kGjzwKcgoxZGr9XeZHxkCcVmwy5lhoT98zp37otKXRm93QxYiMVydqNdLVXQK9tVpHmNdCKM1X2IVC7rAFv0es360XyNRR/numNXR56iE3QOxeQWJz6rtVyq69IOYHFYt1NMRGh8nLTIBc6XQ== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MWHPR1001MB2351.namprd10.prod.outlook.com;PTR:;CAT:NONE;SFS:(39830400003)(396003)(366004)(346002)(376002)(136003)(6486002)(6506007)(7416002)(2906002)(36756003)(6512007)(26005)(86362001)(66556008)(66476007)(186003)(1076003)(6666004)(4326008)(83380400001)(66946007)(2616005)(44832011)(8936002)(8676002)(316002)(54906003)(38100700002)(5660300002)(508600001)(52116002)(38350700002);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: pFjbkToS+uWBGtkUyOUS7TgHY5RMAexs7XEmAntpnD5vmyh0QaQ4msrHdYpjx3E3fEebwRpudXNq02oifDDgj14yNf3LH6BZfaVcPAI01lSGJeMwMPCCQv8xJhFvPmHJS88NicKecJDoyMzJjGzD7T1n8Iq9y8qWoJY4fgQPc5CILrSeN3f5PJRrOnPPMzn8M1zOVCG0kPDFttEkRO81U7DyEHZUOoEixX1h9xwZfkdJW/ngPExDEkZgM2RxHV+HZYe8imFdr3i+/jhfzLn8FnAhgFOapQex9c/gzwIOgvrsd7PQAymRPy8I/m1Xb5C3J/ZIo8n5QJNqyfhqe9IJOCP/yfdMrRyvr4oHdviRLEZgk4PddSoSydSOE/tfWkFkGgr+qMoqIfIWErQPxPgsEWdiuBKChYCNzKKRFCPwoRBfoupCEuQe9NykC5lcQoCg7D8h/YCo/z7uQMW0LyGymviehNjkLCyy8OSQgtF6reVCHj9weJP9315Doh8trgFD6iJQtrUE+Qm68sTFwH6h4FelCP09+kSgZndyND540rOx6bxxZW3QT5nanVvJEz0q7Ggd0uueOGtxmY5Ot/7QXlgfh/5blvt5mQ1+cddii3Q9ZAn+O3sBlLDUEMbhQPQ6LEsqP3TLJWZRcepjeMJV62UEGL0ytKmqFhVNVhNgpY102zLd9LBBUxz30l+MJmBLF0ZT85p7Ibu8IVe1ayzbcrr04ewxXOo0YyWdZP1Hc9hKgeKxVaokaZaTZ+7leYlWNlsD/XGhtdGNBPJp3QY07fLvWD/nni1vEL/jeLzQCmAB7pYr4uf83WM4w3SC0EiuQMILyq7G4zmrmS/EueUiuF1pO5DC0BC7+zu09U0X3Dn1xcWi4+0Ny8xptOeNjWeJvBzGqn5i6GvE4zBqjw3BQvBBM/5jeuRTyxfUpldRgfSKdgwWNxJRb9VrVq0yQQg5gcNJgTLMzB+1eaGbVITm6MUe4cnuOMJ16N9J7AD2B8O7cNmpAijM+RQF8BoTJEmLqImUl7d/s7GuArEjAKyMrTtTyBWyzuHIcJcnrFkzBlsE3NasnJKPhGiliJozHAxQuDichq9D2EvWdq0LNolqcwZ/4euMiaO6oAJJ6gV8IID9Xva62KYgx1tmdx9cNA6NBSNxt8eVCaUyJ9g+Nv5raKj/Kw+gEVQ0BOFbSdvOtfo84NM1w6NyvsmioHwykafSoHh6xDcVfPPzsSvrNskZmXnyO0GaJWERlA/7rTCLIuPA9yltWwc4k+5oB/rKVuvHTTELdtElVjvzFyXl64STOH11c3PCvZogFFazmrMptE3V/J35U7VxDBYyp8gEh6B3GJkWD3dE7WbGB43Tl4ecQd6tdl2x4jimWg3qTKempXCVofTXNWjy6wD4duheFrboZy6oIg7Ite1SCz9zzx5T5D3L6VHbThQV4UGVJKifIQewfM3iFlJIqBsYenYDwVSOWons+hoVJDH/bW5XAGjTvVuHgC032Xmh4D1F0srJd5uCj1TwpWK3x7BTf1ByfdVByJsIdSB5nyUZjJGMpXjKqKioPjtmC/NnOtz8q2Pg2zjxt4tUPBfsUY7dyx5Javy/JzFiNTO33DmBFWr3tyFcfDF9xUbzglmuI+5/yDC/G5+bsLmoDkfTtToNf4dtsk6c6BlynXxu1xXU6TA6qfw+cw== X-OriginatorOrg: in-advantage.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0d3c8fae-3ec8-4617-0c15-08d9c2705c76 X-MS-Exchange-CrossTenant-AuthSource: MWHPR1001MB2351.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Dec 2021 21:50:09.5345 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 48e842ca-fbd8-4633-a79d-0c955a7d3aae X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 3Ey8rrtUci4aOxaS9AgnfmoiiiOeWh1YM+90q9iCUaVrc9nfo9zpTnZm6CsEi3nqpzdQWnY8doIERWXWF6HkV/HwGyROJvLOetz8qd4iyKo= X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR10MB5633 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC The ocelot-ext driver requires the phys to be externally controlled by an optional parameter. This commit exposes that variable so it can be utilized. Signed-off-by: Colin Foster --- drivers/net/dsa/ocelot/seville_vsc9953.c | 3 ++- drivers/net/mdio/mdio-mscc-miim.c | 10 ++++++---- include/linux/mdio/mdio-mscc-miim.h | 3 ++- 3 files changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/net/dsa/ocelot/seville_vsc9953.c b/drivers/net/dsa/ocelot/seville_vsc9953.c index a7db8781310b..95619705e486 100644 --- a/drivers/net/dsa/ocelot/seville_vsc9953.c +++ b/drivers/net/dsa/ocelot/seville_vsc9953.c @@ -1021,7 +1021,8 @@ static int vsc9953_mdio_bus_alloc(struct ocelot *ocelot) rc = mscc_miim_setup(dev, &bus, "VSC9953 internal MDIO bus", ocelot->targets[GCB], - ocelot->map[GCB][GCB_MIIM_MII_STATUS & REG_MASK]); + ocelot->map[GCB][GCB_MIIM_MII_STATUS & REG_MASK], + NULL, 0); if (rc) { dev_err(dev, "failed to setup MDIO bus\n"); diff --git a/drivers/net/mdio/mdio-mscc-miim.c b/drivers/net/mdio/mdio-mscc-miim.c index 7d2abaf2b2c9..e16ab2ffacf6 100644 --- a/drivers/net/mdio/mdio-mscc-miim.c +++ b/drivers/net/mdio/mdio-mscc-miim.c @@ -188,7 +188,8 @@ static const struct regmap_config mscc_miim_regmap_config = { }; int mscc_miim_setup(struct device *dev, struct mii_bus **pbus, const char *name, - struct regmap *mii_regmap, int status_offset) + struct regmap *mii_regmap, int status_offset, + struct regmap *phy_regmap, int phy_offset) { struct mscc_miim_dev *miim; struct mii_bus *bus; @@ -210,6 +211,8 @@ int mscc_miim_setup(struct device *dev, struct mii_bus **pbus, const char *name, miim->regs = mii_regmap; miim->mii_status_offset = status_offset; + miim->phy_regs = phy_regmap; + miim->phy_reset_offset = phy_offset; *pbus = bus; @@ -257,15 +260,14 @@ static int mscc_miim_probe(struct platform_device *pdev) } } - ret = mscc_miim_setup(&pdev->dev, &bus, "mscc_miim", mii_regmap, 0); + ret = mscc_miim_setup(&pdev->dev, &bus, "mscc_miim", mii_regmap, 0, + phy_regmap, 0); if (ret < 0) { dev_err(&pdev->dev, "Unable to setup the MDIO bus\n"); return ret; } miim = bus->priv; - miim->phy_regs = phy_regmap; - miim->phy_reset_offset = 0; ret = of_mdiobus_register(bus, pdev->dev.of_node); if (ret < 0) { diff --git a/include/linux/mdio/mdio-mscc-miim.h b/include/linux/mdio/mdio-mscc-miim.h index 5b4ed2c3cbb9..5a95e43f73f9 100644 --- a/include/linux/mdio/mdio-mscc-miim.h +++ b/include/linux/mdio/mdio-mscc-miim.h @@ -14,6 +14,7 @@ int mscc_miim_setup(struct device *device, struct mii_bus **bus, const char *name, struct regmap *mii_regmap, - int status_offset); + int status_offset, struct regmap *phy_regmap, + int phy_offset); #endif From patchwork Sat Dec 18 21:49:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Colin Foster X-Patchwork-Id: 12686447 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A14FC4332F for ; Sat, 18 Dec 2021 21:50:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234717AbhLRVuU (ORCPT ); Sat, 18 Dec 2021 16:50:20 -0500 Received: from mail-mw2nam10on2118.outbound.protection.outlook.com ([40.107.94.118]:19424 "EHLO NAM10-MW2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S234623AbhLRVuQ (ORCPT ); Sat, 18 Dec 2021 16:50:16 -0500 ARC-Seal: i=1; a=rsa-sha256; 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Sat, 18 Dec 2021 21:50:10 +0000 From: Colin Foster To: linux-gpio@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Linus Walleij , Russell King , Heiner Kallweit , Jakub Kicinski , "David S. Miller" , Florian Fainelli , Vivien Didelot , Andrew Lunn , UNGLinuxDriver@microchip.com, Alexandre Belloni , Claudiu Manoil , Vladimir Oltean , Lee Jones Subject: [RFC v5 net-next 06/13] net: dsa: ocelot: add external ocelot switch control Date: Sat, 18 Dec 2021 13:49:47 -0800 Message-Id: <20211218214954.109755-7-colin.foster@in-advantage.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211218214954.109755-1-colin.foster@in-advantage.com> References: <20211218214954.109755-1-colin.foster@in-advantage.com> X-ClientProxiedBy: MWHPR02CA0011.namprd02.prod.outlook.com (2603:10b6:300:4b::21) To MWHPR1001MB2351.namprd10.prod.outlook.com (2603:10b6:301:35::37) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: fbec9c59-db4f-4a27-a1d1-08d9c2705cef X-MS-TrafficTypeDiagnostic: CO6PR10MB5633:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4941; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: uHNW8I77dB/WTh7Wc1T5Rj2wIoYCXUXIZE/+DCqPnFQtCyLzWGPeHIHfEaMCw5Ut0PXkKzWfNFa3oIXLQn8RVXA1o1uQgLcjVnZd4Fbr30FwIN3/MbrQMPJ5qvSHV867fos7wSos2M+fulwU/TBk3Xwlv2oDMKNOQkHsZ7pYB9XTKQEBqjKh03/S8nyQOXyssa9VHRkAMwF8rMfco/V+kC31xQIc7yubfJHK8j7FJ+tlzTRHN9SigoZ8GpKmrtOWfGqQ3wMYCLAY5YeVC0vj6GW40VRncgmxudxwt5aTfU1K6Y6AdQJYQzan4V37bPjHTijk7BJoqKrT+ijSinio7aqUDGy1MWWcy0m/ZvRmaii8AtatJMgPbuSqSsav4bFF2daEXOfNKTdw+jM+NpSLz7JF9t2mgtR3AYLjQrV1coWXT2gKcE/K930YLBAXWB/BCGjkFi/khImtKdR8Kg4MRhOBVlHwRv2YEPo4VcyVyYjyC7AtXMN0gf1ckG7+Tz6HttimgRFn3lkpIZS62VAC6fdlg6TxW/w9p8pOjJurrYk1F3Jh2+Zo5ETt5ABpEK1wBryVCtnJj53xpE1va8btD6aypyNSm31SJY/tDYdGiI+gn0RLclfccuGkihLojpxonomimCc6UnPCNxEnlWwNw8mHkt1pVX14TOcgWY5pJJIYM19Dy07hZK3SZfrBPIQjUpXnTD40eVUHsvwYzypj4w== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MWHPR1001MB2351.namprd10.prod.outlook.com;PTR:;CAT:NONE;SFS:(39830400003)(396003)(366004)(346002)(376002)(136003)(6486002)(6506007)(7416002)(2906002)(36756003)(6512007)(26005)(86362001)(66556008)(66476007)(186003)(1076003)(6666004)(4326008)(83380400001)(30864003)(66946007)(2616005)(44832011)(8936002)(8676002)(316002)(54906003)(38100700002)(5660300002)(508600001)(52116002)(38350700002);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: tBQ2/a78qhngMF0Q6pxlXB0QvlAVa0QQIvudKJzGaSy2I1Cww8+VujzNgI9UAR+HB0b8niZXeCwivWUSzO6RVNbm6Sh1U5UPHGapOVkn+q/mIpPEWnWyv0l5sTF4j7AHgoLLQzAZQoyxQI49Kz/pbn9gooMwOGfQafM/6b+of0P2k6vXmyEBqRmdpZBEOswwR+WgZF9r98rDu3cxF8e2ktYJ7ZOY5cEGzRV18TG5Lst7s9iLTnoX53SLYILd9iz5cJNrmb46E5OVmB+gi6e1P1s9OZ/S3JWWMWFaXyPoJY4kgolMRrdmqsiqsu+CUU6p/8BonzbjmyiFa5TYaEffKrGaYV9S2xvN99ZiH2Fwk5UXC/9vzulpSX3RL/IJvXtWzFEsWMOIj3maVZyhg4AQIvquSsj+HIfK3GyTUNgK/EYL4+1EZi+1Xt5HVtSS6R+t3JvOAhMpjHNIJGkLmvo6MkIjvyNb/gYB5dXpc3i+4eTEz2lgvaakXaEYkfUs7XPTuyqsFZBbBvZ1GqO8y930LKNPp4aaTX2jON9d6uwBrYRUQjUL+ZrwM1x8llDoRm56nwGgzw5pL1JtOyqRtEVCKyCLlTCBtTh/aXF8bS19+NDRD++nA9NMlaQDCWKArdFQsr9yYwjRaKDytIoCIrDaKOZmfvvfFlUEXiS46VnlIIwJTtBl9VkKiTBTonM7GEbXSxZ3fExJksRbypfqH0USMuJVOpFcxawAZemVwAfc17g4eg85NhjMEUk6H4DT2zZqb+HZnu+F1i29jgbj0zB8mPIO4rZ9difJtdpOn+iluOX71orBeJ+9CQGRyQgwm1dtYU6UBzhZy7RzRsku39JLnBkpOFY5+2t4d35r556mvvqbDR1gytOa5QOR/pUa9QzxJbcT00WyJrdjj6JnMQdEllDtVvsQk2swNld8oqPDhMJ9ounk2+24YA7rdfrBcXUZQDbThdlo7vxX9WcQsYcrzRD7FgtsSBvvF+Cn6OC68n/r6HykJOpeXKdptqKB5EFRqr9lJPBXmbABfqhrlwFuFDDWEXymUpH+H3JZvUOM7OTajNpclqvRDRLDxfGb6KxaERNoM0nk23lo5zh035i7BZTNlHr4+U37B70VzXNxzzi7GE01imYiFF01/7VZdXsPGLPowE5zWF9nCPCnk+Q5FeT9dwHlxPoWUbbvHhQnWE0M4veEP/LYUuLmJ5KfX+MaHT5dtfAYE0h8Z5Q2RP5ELX06toWlHm6virZVYuybzA39t78VB//xeHBiPguPezQqV82JWo/cHKBpZxDCi+JcD90fa3rV0VVJuAEkkNTLUNmV1oYlHBSk2FTfBAGcGwWFGtYYXty7Ic/cf/hLNmf9NTcx9MDXW0Bkj9za27Q0mqMKXHmLxphr7GMffyLTKfUo/6NcragZnbKSXd8/85fcXHyGYc4/cXz8j07Xh8kJEFrh4IHRWHL6Otry1vdkfhQtIv8ln/Dnkml4De1zaqPD8nLcdnaaaPItGMhFu/U3Ju3EjoGQD26jnoD2fkgg90NttSfNH3ZyLJ5vDNmUh770Tw9s+hIrqdY6H8B+D1dqfD2rVc/C9CNIuFju90v9aISx8mJgZVhIiZNXfVtggTdpSTEqtfNjlB8r8RAo21jQucA9PXyau0U7WHeewJ0SOXA9gdARsdqF7dr6C99rBZIf5g== X-OriginatorOrg: in-advantage.com X-MS-Exchange-CrossTenant-Network-Message-Id: fbec9c59-db4f-4a27-a1d1-08d9c2705cef X-MS-Exchange-CrossTenant-AuthSource: MWHPR1001MB2351.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Dec 2021 21:50:10.4407 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 48e842ca-fbd8-4633-a79d-0c955a7d3aae X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 5s6G7n+j19VtHvM8+YuOt7B0TVliSHE2Z5N1mHQshVFDNk2AmhOnTlskOJoXu4gWdPCf317u6Ay4amYdqDD8G611olEFaaZBoKCiPxiKCLk= X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR10MB5633 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC Add control of an external VSC7512 chip by way of the ocelot-mfd interface. Signed-off-by: Colin Foster --- drivers/net/dsa/ocelot/Kconfig | 15 + drivers/net/dsa/ocelot/Makefile | 5 + drivers/net/dsa/ocelot/ocelot_ext.c | 644 ++++++++++++++++++++++++++++ include/soc/mscc/ocelot.h | 2 + 4 files changed, 666 insertions(+) create mode 100644 drivers/net/dsa/ocelot/ocelot_ext.c diff --git a/drivers/net/dsa/ocelot/Kconfig b/drivers/net/dsa/ocelot/Kconfig index 220b0b027b55..60a930f48014 100644 --- a/drivers/net/dsa/ocelot/Kconfig +++ b/drivers/net/dsa/ocelot/Kconfig @@ -1,4 +1,19 @@ # SPDX-License-Identifier: GPL-2.0-only +config NET_DSA_MSCC_OCELOT_EXT + tristate "Ocelot External Ethernet switch support" + depends on NET_DSA && SPI + depends on NET_VENDOR_MICROSEMI + select MDIO_MSCC_MIIM + select MFD_OCELOT_CORE + select MFD_OCELOT_SPI + select MSCC_OCELOT_SWITCH_LIB + select NET_DSA_TAG_OCELOT_8021Q + select NET_DSA_TAG_OCELOT + help + This driver supports the VSC7511, VSC7512, VSC7513 and VSC7514 chips + when controlled through SPI. It can be used with the Microsemi dev + boards and an external CPU or custom hardware. + config NET_DSA_MSCC_FELIX tristate "Ocelot / Felix Ethernet switch support" depends on NET_DSA && PCI diff --git a/drivers/net/dsa/ocelot/Makefile b/drivers/net/dsa/ocelot/Makefile index f6dd131e7491..d7f3f5a4461c 100644 --- a/drivers/net/dsa/ocelot/Makefile +++ b/drivers/net/dsa/ocelot/Makefile @@ -1,11 +1,16 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_NET_DSA_MSCC_FELIX) += mscc_felix.o +obj-$(CONFIG_NET_DSA_MSCC_OCELOT_EXT) += mscc_ocelot_ext.o obj-$(CONFIG_NET_DSA_MSCC_SEVILLE) += mscc_seville.o mscc_felix-objs := \ felix.o \ felix_vsc9959.o +mscc_ocelot_ext-objs := \ + felix.o \ + ocelot_ext.o + mscc_seville-objs := \ felix.o \ seville_vsc9953.o diff --git a/drivers/net/dsa/ocelot/ocelot_ext.c b/drivers/net/dsa/ocelot/ocelot_ext.c new file mode 100644 index 000000000000..e35f21ba5dc3 --- /dev/null +++ b/drivers/net/dsa/ocelot/ocelot_ext.c @@ -0,0 +1,644 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Innovative Advantage Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "felix.h" + +struct ocelot_ext_data { + struct felix felix; +}; + +static const u32 vsc7512_gcb_regmap[] = { + REG(GCB_SOFT_RST, 0x0008), + REG(GCB_MIIM_MII_STATUS, 0x009c), + REG(GCB_PHY_PHY_CFG, 0x00f0), + REG(GCB_PHY_PHY_STAT, 0x00f4), +}; + +static const u32 *vsc7512_regmap[TARGET_MAX] = { + [ANA] = vsc7514_ana_regmap, + [QS] = vsc7514_qs_regmap, + [QSYS] = vsc7514_qsys_regmap, + [REW] = vsc7514_rew_regmap, + [SYS] = vsc7514_sys_regmap, + [S0] = vsc7514_vcap_regmap, + [S1] = vsc7514_vcap_regmap, + [S2] = vsc7514_vcap_regmap, + [PTP] = vsc7514_ptp_regmap, + [GCB] = vsc7512_gcb_regmap, + [DEV_GMII] = vsc7514_dev_gmii_regmap, +}; + +#define VSC7512_BYTE_ORDER_LE 0x00000000 +#define VSC7512_BYTE_ORDER_BE 0x81818181 +#define VSC7512_BIT_ORDER_MSB 0x00000000 +#define VSC7512_BIT_ORDER_LSB 0x42424242 + +static void ocelot_ext_reset_phys(struct ocelot *ocelot) +{ + ocelot_write(ocelot, 0, GCB_PHY_PHY_CFG); + ocelot_write(ocelot, 0x1ff, GCB_PHY_PHY_CFG); + mdelay(500); +} + +static int ocelot_ext_reset(struct ocelot *ocelot) +{ + struct felix *felix = ocelot_to_felix(ocelot); + struct device *dev = ocelot->dev; + struct device_node *mdio_node; + int retries = 100; + int err, val; + + ocelot_ext_reset_phys(ocelot); + + mdio_node = of_get_child_by_name(dev->of_node, "mdio"); + if (!mdio_node) + dev_info(ocelot->dev, + "mdio children not found in device tree\n"); + + err = of_mdiobus_register(felix->imdio, mdio_node); + if (err) { + dev_err(ocelot->dev, "error registering MDIO bus\n"); + return err; + } + + felix->ds->slave_mii_bus = felix->imdio; + + /* We might need to reset the switch core here, if that is possible */ + err = regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_INIT], 1); + if (err) + return err; + + err = regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1); + if (err) + return err; + + do { + msleep(1); + regmap_field_read(ocelot->regfields[SYS_RESET_CFG_MEM_INIT], + &val); + } while (val && --retries); + + if (!retries) + return -ETIMEDOUT; + + err = regmap_field_write(ocelot->regfields[SYS_RESET_CFG_CORE_ENA], 1); + + return err; +} + +static u32 ocelot_offset_from_reg_base(struct ocelot *ocelot, u32 target, + u32 reg) +{ + return ocelot->map[target][reg & REG_MASK]; +} + +static const struct ocelot_ops vsc7512_ops = { + .reset = ocelot_ext_reset, + .wm_enc = ocelot_wm_enc, + .wm_dec = ocelot_wm_dec, + .wm_stat = ocelot_wm_stat, + .port_to_netdev = felix_port_to_netdev, + .netdev_to_port = felix_netdev_to_port, +}; + +static const struct resource vsc7512_target_io_res[TARGET_MAX] = { + [ANA] = { + .start = 0x71880000, + .end = 0x7188ffff, + .name = "ana", + }, + [QS] = { + .start = 0x71080000, + .end = 0x710800ff, + .name = "qs", + }, + [QSYS] = { + .start = 0x71800000, + .end = 0x719fffff, + .name = "qsys", + }, + [REW] = { + .start = 0x71030000, + .end = 0x7103ffff, + .name = "rew", + }, + [SYS] = { + .start = 0x71010000, + .end = 0x7101ffff, + .name = "sys", + }, + [S0] = { + .start = 0x71040000, + .end = 0x710403ff, + .name = "s0", + }, + [S1] = { + .start = 0x71050000, + .end = 0x710503ff, + .name = "s1", + }, + [S2] = { + .start = 0x71060000, + .end = 0x710603ff, + .name = "s2", + }, + [GCB] = { + .start = 0x71070000, + .end = 0x7107022b, + .name = "devcpu_gcb", + }, +}; + +static const struct resource vsc7512_port_io_res[] = { + { + .start = 0x711e0000, + .end = 0x711effff, + .name = "port0", + }, + { + .start = 0x711f0000, + .end = 0x711fffff, + .name = "port1", + }, + { + .start = 0x71200000, + .end = 0x7120ffff, + .name = "port2", + }, + { + .start = 0x71210000, + .end = 0x7121ffff, + .name = "port3", + }, + { + .start = 0x71220000, + .end = 0x7122ffff, + .name = "port4", + }, + { + .start = 0x71230000, + .end = 0x7123ffff, + .name = "port5", + }, + { + .start = 0x71240000, + .end = 0x7124ffff, + .name = "port6", + }, + { + .start = 0x71250000, + .end = 0x7125ffff, + .name = "port7", + }, + { + .start = 0x71260000, + .end = 0x7126ffff, + .name = "port8", + }, + { + .start = 0x71270000, + .end = 0x7127ffff, + .name = "port9", + }, + { + .start = 0x71280000, + .end = 0x7128ffff, + .name = "port10", + }, +}; + +static const struct reg_field vsc7512_regfields[REGFIELD_MAX] = { + [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 11, 11), + [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 10), + [ANA_ANEVENTS_MSTI_DROP] = REG_FIELD(ANA_ANEVENTS, 27, 27), + [ANA_ANEVENTS_ACLKILL] = REG_FIELD(ANA_ANEVENTS, 26, 26), + [ANA_ANEVENTS_ACLUSED] = REG_FIELD(ANA_ANEVENTS, 25, 25), + [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 24, 24), + [ANA_ANEVENTS_VS2TTL1] = REG_FIELD(ANA_ANEVENTS, 23, 23), + [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 22, 22), + [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 21, 21), + [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 20, 20), + [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 19, 19), + [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 18, 18), + [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 17, 17), + [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 16, 16), + [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 15, 15), + [ANA_ANEVENTS_DROPPED] = REG_FIELD(ANA_ANEVENTS, 14, 14), + [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 13, 13), + [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 12, 12), + [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 11, 11), + [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 10, 10), + [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 9, 9), + [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 8, 8), + [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 7, 7), + [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6), + [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5), + [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 4, 4), + [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 3, 3), + [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 2, 2), + [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 1, 1), + [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 0, 0), + [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 18, 18), + [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 10, 11), + [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 9), + [GCB_SOFT_RST_SWC_RST] = REG_FIELD(GCB_SOFT_RST, 1, 1), + [QSYS_TIMED_FRAME_ENTRY_TFRM_VLD] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 20, 20), + [QSYS_TIMED_FRAME_ENTRY_TFRM_FP] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 8, 19), + [QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 4, 7), + [QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 1, 3), + [QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 0, 0), + [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 2, 2), + [SYS_RESET_CFG_MEM_ENA] = REG_FIELD(SYS_RESET_CFG, 1, 1), + [SYS_RESET_CFG_MEM_INIT] = REG_FIELD(SYS_RESET_CFG, 0, 0), + /* Replicated per number of ports (12), register size 4 per port */ + [QSYS_SWITCH_PORT_MODE_PORT_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 14, 14, 12, 4), + [QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 11, 13, 12, 4), + [QSYS_SWITCH_PORT_MODE_YEL_RSRVD] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 10, 10, 12, 4), + [QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 9, 9, 12, 4), + [QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 12, 4), + [QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 12, 4), + [SYS_PORT_MODE_DATA_WO_TS] = REG_FIELD_ID(SYS_PORT_MODE, 5, 6, 12, 4), + [SYS_PORT_MODE_INCL_INJ_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 3, 4, 12, 4), + [SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 1, 2, 12, 4), + [SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 12, 4), + [SYS_PAUSE_CFG_PAUSE_START] = REG_FIELD_ID(SYS_PAUSE_CFG, 10, 18, 12, 4), + [SYS_PAUSE_CFG_PAUSE_STOP] = REG_FIELD_ID(SYS_PAUSE_CFG, 1, 9, 12, 4), + [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 12, 4), +}; + +static const struct ocelot_stat_layout vsc7512_stats_layout[] = { + { .offset = 0x00, .name = "rx_octets", }, + { .offset = 0x01, .name = "rx_unicast", }, + { .offset = 0x02, .name = "rx_multicast", }, + { .offset = 0x03, .name = "rx_broadcast", }, + { .offset = 0x04, .name = "rx_shorts", }, + { .offset = 0x05, .name = "rx_fragments", }, + { .offset = 0x06, .name = "rx_jabbers", }, + { .offset = 0x07, .name = "rx_crc_align_errs", }, + { .offset = 0x08, .name = "rx_sym_errs", }, + { .offset = 0x09, .name = "rx_frames_below_65_octets", }, + { .offset = 0x0A, .name = "rx_frames_65_to_127_octets", }, + { .offset = 0x0B, .name = "rx_frames_128_to_255_octets", }, + { .offset = 0x0C, .name = "rx_frames_256_to_511_octets", }, + { .offset = 0x0D, .name = "rx_frames_512_to_1023_octets", }, + { .offset = 0x0E, .name = "rx_frames_1024_to_1526_octets", }, + { .offset = 0x0F, .name = "rx_frames_over_1526_octets", }, + { .offset = 0x10, .name = "rx_pause", }, + { .offset = 0x11, .name = "rx_control", }, + { .offset = 0x12, .name = "rx_longs", }, + { .offset = 0x13, .name = "rx_classified_drops", }, + { .offset = 0x14, .name = "rx_red_prio_0", }, + { .offset = 0x15, .name = "rx_red_prio_1", }, + { .offset = 0x16, .name = "rx_red_prio_2", }, + { .offset = 0x17, .name = "rx_red_prio_3", }, + { .offset = 0x18, .name = "rx_red_prio_4", }, + { .offset = 0x19, .name = "rx_red_prio_5", }, + { .offset = 0x1A, .name = "rx_red_prio_6", }, + { .offset = 0x1B, .name = "rx_red_prio_7", }, + { .offset = 0x1C, .name = "rx_yellow_prio_0", }, + { .offset = 0x1D, .name = "rx_yellow_prio_1", }, + { .offset = 0x1E, .name = "rx_yellow_prio_2", }, + { .offset = 0x1F, .name = "rx_yellow_prio_3", }, + { .offset = 0x20, .name = "rx_yellow_prio_4", }, + { .offset = 0x21, .name = "rx_yellow_prio_5", }, + { .offset = 0x22, .name = "rx_yellow_prio_6", }, + { .offset = 0x23, .name = "rx_yellow_prio_7", }, + { .offset = 0x24, .name = "rx_green_prio_0", }, + { .offset = 0x25, .name = "rx_green_prio_1", }, + { .offset = 0x26, .name = "rx_green_prio_2", }, + { .offset = 0x27, .name = "rx_green_prio_3", }, + { .offset = 0x28, .name = "rx_green_prio_4", }, + { .offset = 0x29, .name = "rx_green_prio_5", }, + { .offset = 0x2A, .name = "rx_green_prio_6", }, + { .offset = 0x2B, .name = "rx_green_prio_7", }, + { .offset = 0x40, .name = "tx_octets", }, + { .offset = 0x41, .name = "tx_unicast", }, + { .offset = 0x42, .name = "tx_multicast", }, + { .offset = 0x43, .name = "tx_broadcast", }, + { .offset = 0x44, .name = "tx_collision", }, + { .offset = 0x45, .name = "tx_drops", }, + { .offset = 0x46, .name = "tx_pause", }, + { .offset = 0x47, .name = "tx_frames_below_65_octets", }, + { .offset = 0x48, .name = "tx_frames_65_to_127_octets", }, + { .offset = 0x49, .name = "tx_frames_128_255_octets", }, + { .offset = 0x4A, .name = "tx_frames_256_511_octets", }, + { .offset = 0x4B, .name = "tx_frames_512_1023_octets", }, + { .offset = 0x4C, .name = "tx_frames_1024_1526_octets", }, + { .offset = 0x4D, .name = "tx_frames_over_1526_octets", }, + { .offset = 0x4E, .name = "tx_yellow_prio_0", }, + { .offset = 0x4F, .name = "tx_yellow_prio_1", }, + { .offset = 0x50, .name = "tx_yellow_prio_2", }, + { .offset = 0x51, .name = "tx_yellow_prio_3", }, + { .offset = 0x52, .name = "tx_yellow_prio_4", }, + { .offset = 0x53, .name = "tx_yellow_prio_5", }, + { .offset = 0x54, .name = "tx_yellow_prio_6", }, + { .offset = 0x55, .name = "tx_yellow_prio_7", }, + { .offset = 0x56, .name = "tx_green_prio_0", }, + { .offset = 0x57, .name = "tx_green_prio_1", }, + { .offset = 0x58, .name = "tx_green_prio_2", }, + { .offset = 0x59, .name = "tx_green_prio_3", }, + { .offset = 0x5A, .name = "tx_green_prio_4", }, + { .offset = 0x5B, .name = "tx_green_prio_5", }, + { .offset = 0x5C, .name = "tx_green_prio_6", }, + { .offset = 0x5D, .name = "tx_green_prio_7", }, + { .offset = 0x5E, .name = "tx_aged", }, + { .offset = 0x80, .name = "drop_local", }, + { .offset = 0x81, .name = "drop_tail", }, + { .offset = 0x82, .name = "drop_yellow_prio_0", }, + { .offset = 0x83, .name = "drop_yellow_prio_1", }, + { .offset = 0x84, .name = "drop_yellow_prio_2", }, + { .offset = 0x85, .name = "drop_yellow_prio_3", }, + { .offset = 0x86, .name = "drop_yellow_prio_4", }, + { .offset = 0x87, .name = "drop_yellow_prio_5", }, + { .offset = 0x88, .name = "drop_yellow_prio_6", }, + { .offset = 0x89, .name = "drop_yellow_prio_7", }, + { .offset = 0x8A, .name = "drop_green_prio_0", }, + { .offset = 0x8B, .name = "drop_green_prio_1", }, + { .offset = 0x8C, .name = "drop_green_prio_2", }, + { .offset = 0x8D, .name = "drop_green_prio_3", }, + { .offset = 0x8E, .name = "drop_green_prio_4", }, + { .offset = 0x8F, .name = "drop_green_prio_5", }, + { .offset = 0x90, .name = "drop_green_prio_6", }, + { .offset = 0x91, .name = "drop_green_prio_7", }, +}; + +static void vsc7512_phylink_validate(struct ocelot *ocelot, int port, + unsigned long *supported, + struct phylink_link_state *state) +{ + struct ocelot_port *ocelot_port = ocelot->ports[port]; + + __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; + + if (state->interface != PHY_INTERFACE_MODE_NA && + state->interface != ocelot_port->phy_mode) { + bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); + return; + } + + phylink_set_port_modes(mask); + + phylink_set(mask, Pause); + phylink_set(mask, Autoneg); + phylink_set(mask, Asym_Pause); + phylink_set(mask, 10baseT_Half); + phylink_set(mask, 10baseT_Full); + phylink_set(mask, 100baseT_Half); + phylink_set(mask, 100baseT_Full); + phylink_set(mask, 1000baseT_Half); + phylink_set(mask, 1000baseT_Full); + + bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); + bitmap_and(state->advertising, state->advertising, mask, + __ETHTOOL_LINK_MODE_MASK_NBITS); +} + +static int vsc7512_prevalidate_phy_mode(struct ocelot *ocelot, int port, + phy_interface_t phy_mode) +{ + switch (phy_mode) { + case PHY_INTERFACE_MODE_INTERNAL: + if (port < 4) + return 0; + return -EOPNOTSUPP; + case PHY_INTERFACE_MODE_SGMII: + if (port < 8) + return 0; + return -EOPNOTSUPP; + case PHY_INTERFACE_MODE_QSGMII: + if (port == 7 || port == 8 || port == 10) + return 0; + return -EOPNOTSUPP; + default: + return -EOPNOTSUPP; + } +} + +static int vsc7512_port_setup_tc(struct dsa_switch *ds, int port, + enum tc_setup_type type, void *type_data) +{ + return -EOPNOTSUPP; +} + +static struct vcap_props vsc7512_vcap_props[] = { + [VCAP_ES0] = { + .action_type_width = 0, + .action_table = { + [ES0_ACTION_TYPE_NORMAL] = { + .width = 73, + .count = 1, + }, + }, + .target = S0, + .keys = vsc7514_vcap_es0_keys, + .actions = vsc7514_vcap_es0_actions, + }, + [VCAP_IS1] = { + .action_type_width = 0, + .action_table = { + [IS1_ACTION_TYPE_NORMAL] = { + .width = 78, + .count = 4, + }, + }, + .target = S1, + .keys = vsc7514_vcap_is1_keys, + .actions = vsc7514_vcap_is1_actions, + }, + [VCAP_IS2] = { + .action_type_width = 1, + .action_table = { + [IS2_ACTION_TYPE_NORMAL] = { + .width = 49, + .count = 2, + }, + [IS2_ACTION_TYPE_SMAC_SIP] = { + .width = 6, + .count = 4, + }, + }, + .target = S2, + .keys = vsc7514_vcap_is2_keys, + .actions = vsc7514_vcap_is2_actions, + }, +}; + +static struct regmap *vsc7512_regmap_init(struct ocelot *ocelot, + struct resource *res) +{ + struct device *dev = ocelot->dev; + struct regmap *regmap; + + regmap = ocelot_mfd_get_regmap_from_resource(dev->parent, res); + if (IS_ERR(regmap)) + return ERR_CAST(regmap); + + return regmap; +} + +static int vsc7512_mdio_bus_alloc(struct ocelot *ocelot) +{ + struct felix *felix = ocelot_to_felix(ocelot); + struct device *dev = ocelot->dev; + u32 mii_offset, phy_offset; + struct mii_bus *bus; + int err; + + mii_offset = ocelot_offset_from_reg_base(ocelot, GCB, + GCB_MIIM_MII_STATUS); + + phy_offset = ocelot_offset_from_reg_base(ocelot, GCB, GCB_PHY_PHY_CFG); + + err = mscc_miim_setup(dev, &bus, "ocelot_ext MDIO bus", + ocelot->targets[GCB], mii_offset, + ocelot->targets[GCB], phy_offset); + if (err) { + dev_err(dev, "failed to setup MDIO bus\n"); + return err; + } + + felix->imdio = bus; + + return err; +} + + +static void vsc7512_mdio_bus_free(struct ocelot *ocelot) +{ + struct felix *felix = ocelot_to_felix(ocelot); + + if (felix->imdio) + mdiobus_unregister(felix->imdio); +} + +static const struct felix_info ocelot_ext_info = { + .target_io_res = vsc7512_target_io_res, + .port_io_res = vsc7512_port_io_res, + .regfields = vsc7512_regfields, + .map = vsc7512_regmap, + .ops = &vsc7512_ops, + .stats_layout = vsc7512_stats_layout, + .num_stats = ARRAY_SIZE(vsc7512_stats_layout), + .vcap = vsc7512_vcap_props, + .num_mact_rows = 1024, + .num_ports = 11, + .num_tx_queues = OCELOT_NUM_TC, + .mdio_bus_alloc = vsc7512_mdio_bus_alloc, + .mdio_bus_free = vsc7512_mdio_bus_free, + .phylink_validate = vsc7512_phylink_validate, + .prevalidate_phy_mode = vsc7512_prevalidate_phy_mode, + .port_setup_tc = vsc7512_port_setup_tc, + .init_regmap = vsc7512_regmap_init, +}; + +static int ocelot_ext_probe(struct platform_device *pdev) +{ + struct ocelot_ext_data *ocelot_ext; + struct dsa_switch *ds; + struct ocelot *ocelot; + struct felix *felix; + struct device *dev; + int err; + + dev = &pdev->dev; + + ocelot_ext = devm_kzalloc(dev, sizeof(struct ocelot_ext_data), + GFP_KERNEL); + + if (!ocelot_ext) + return -ENOMEM; + + dev_set_drvdata(dev, ocelot_ext); + + felix = &ocelot_ext->felix; + + ocelot = &felix->ocelot; + ocelot->dev = dev; + + ocelot->num_flooding_pgids = 1; + + felix->info = &ocelot_ext_info; + + ds = kzalloc(sizeof(*ds), GFP_KERNEL); + if (!ds) { + err = -ENOMEM; + dev_err(dev, "Failed to allocate DSA switch\n"); + return err; + } + + ds->dev = dev; + ds->num_ports = felix->info->num_ports; + ds->num_tx_queues = felix->info->num_tx_queues; + + ds->ops = &felix_switch_ops; + ds->priv = ocelot; + felix->ds = ds; + felix->tag_proto = DSA_TAG_PROTO_OCELOT; + + err = dsa_register_switch(ds); + + if (err) { + dev_err(dev, "Failed to register DSA switch: %d\n", err); + goto err_register_ds; + } + + return 0; + +err_register_ds: + kfree(ds); + return err; +} + +static int ocelot_ext_remove(struct platform_device *pdev) +{ + struct ocelot_ext_data *ocelot_ext; + struct felix *felix; + + ocelot_ext = dev_get_drvdata(&pdev->dev); + felix = &ocelot_ext->felix; + + dsa_unregister_switch(felix->ds); + + kfree(felix->ds); + + devm_kfree(&pdev->dev, ocelot_ext); + + return 0; +} + +const struct of_device_id ocelot_ext_switch_of_match[] = { + { .compatible = "mscc,vsc7512-ext-switch" }, + { }, +}; +MODULE_DEVICE_TABLE(of, ocelot_ext_switch_of_match); + +static struct platform_driver ocelot_ext_switch_driver = { + .driver = { + .name = "ocelot-ext-switch", + .of_match_table = of_match_ptr(ocelot_ext_switch_of_match), + }, + .probe = ocelot_ext_probe, + .remove = ocelot_ext_remove, +}; +module_platform_driver(ocelot_ext_switch_driver); + +MODULE_DESCRIPTION("External Ocelot Switch driver"); +MODULE_LICENSE("GPL v2"); diff --git a/include/soc/mscc/ocelot.h b/include/soc/mscc/ocelot.h index 37bc9d647bc2..c56eaedc5e58 100644 --- a/include/soc/mscc/ocelot.h +++ b/include/soc/mscc/ocelot.h @@ -399,6 +399,8 @@ enum ocelot_reg { GCB_MIIM_MII_STATUS, GCB_MIIM_MII_CMD, GCB_MIIM_MII_DATA, + GCB_PHY_PHY_CFG, + GCB_PHY_PHY_STAT, DEV_CLOCK_CFG = DEV_GMII << TARGET_OFFSET, DEV_PORT_MISC, DEV_EVENTS, From patchwork Sat Dec 18 21:49:48 2021 Content-Type: text/plain; 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Miller" , Florian Fainelli , Vivien Didelot , Andrew Lunn , UNGLinuxDriver@microchip.com, Alexandre Belloni , Claudiu Manoil , Vladimir Oltean , Lee Jones Subject: [RFC v5 net-next 07/13] mfd: ocelot: enable the external switch interface Date: Sat, 18 Dec 2021 13:49:48 -0800 Message-Id: <20211218214954.109755-8-colin.foster@in-advantage.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211218214954.109755-1-colin.foster@in-advantage.com> References: <20211218214954.109755-1-colin.foster@in-advantage.com> X-ClientProxiedBy: MWHPR02CA0011.namprd02.prod.outlook.com (2603:10b6:300:4b::21) To MWHPR1001MB2351.namprd10.prod.outlook.com (2603:10b6:301:35::37) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 78339a6f-dd24-4e86-2129-08d9c2705d94 X-MS-TrafficTypeDiagnostic: CO6PR10MB5633:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2733; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: DnuvAWolywkJ9ogY6r/fH+HwhU1aKFemMXNE9kv5eulceM2NidtrHko0awaNzPqEPEC6RYjNB/6QJ6ppbXGLZjgZsUPzaixH9bm442L2K0hI7ESQUvTeoT6w5xJVuHDZyaphQ8YiMxeKlINlYLraj9gWAytD6CjfANbKLgf8r8epwVE6yaZI5aOYYp0lT3hJHxAf7s+nDK2XcTT2xx6ZcG3tmyyqySx8abkGy9p4HvDALCx5rLcRglphPqxJvxkrERhlZ1P/cWog25pxOpojL6/4hYHECHxQNabmLPtKBp0qxVhLdsLlPCGOE3xtfljcHWRbAmWQPW9jKzrC23yE3p0nN3XKLhEyPMBWrr4fd8L1TamAvKvSeK1Sov5xNC9686oJh8n63jkRwAxiGF/kmvR9lWv8oIYPBW8RqT13E4uYVQRjOPxZRBjOmYmX7t5AE/n3V2e00SfD5L3WN5QvKeW861gyd2xz0YPvVjBZt7+NaVvY+IFmCxvNyMVvi8k7S4q3DRwqlQD6MNwVSVdLBUXc2t5kt8bzLQNeDd155scEN8ibS4A/lT7jGXKHOYVWFxlz1UPF5qWzytITRGRSm81SbexL1PeLhWXSgw55UcYKyO3ke9BLX+3vJZtVziAEkpofHMOf95imhv8fvf0izWQr385duotjTMMBcinzW1ZxE/OUhjzg6n3WYdUvXLhOMkwqBU6RMaWiZzbha1tHPA== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MWHPR1001MB2351.namprd10.prod.outlook.com;PTR:;CAT:NONE;SFS:(39830400003)(396003)(366004)(346002)(376002)(136003)(6486002)(6506007)(7416002)(2906002)(36756003)(6512007)(26005)(86362001)(66556008)(66476007)(186003)(1076003)(6666004)(4326008)(83380400001)(66946007)(2616005)(44832011)(8936002)(8676002)(316002)(54906003)(38100700002)(5660300002)(508600001)(52116002)(38350700002);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 60rFgRtq4frtd5CCAfuFt2NGu8aaPDdrNLkeDYxSWSaHorqYcKJxvREKH7s5zNahb+aWx2mtU/IRu4yKWtQgJrxf5L9GuqBI3dcdSLJqWj3it3vL7XgZ9vSavJTwBKHh1a4pP2+vKxkflnF80URrh5ShLhGe0twe3JOuT61gFrrSHZHenJXlb7tnueFuHGWeyWF3byNjdbiNrtd50i77oocldGQYBtKu2K8PTGHNAhKmmOJl+5v8K7NgO8iRXHm8qfw+nUyEGukXAbA+0wwhQcg0l9JDInlprLI3HkXs4btv8jhiXuHv33x2STObdhilPvwai0tPNYXwoHgbUSMCP0C/kkJx8Q/fQsmX77+oY/5SLr4y8mO1WO+E+O7OoQ2i8EFHfjtFWrGwzivsAw1CmBwR7Vr7MsJ+Ujgj/YSABa861BYMonLwHZwR2+X3zir0TiPl7FxnRh3lnFpbAF6s1iABdyhHNJOd7a1SMASy6yF/4bJrB+yuZ+TQNWH7fS+qRArSNjcOArmvA69IM8uTUwgDhuO6VTFi8vL0EFS3quv5Kb57+dIa0ioVBEIuFyAWg1rMqI/U7mmFNw2yGmD56OZIv92IkSKPTt6OgS5ZYKTAkjmC33Sbpj7P3hde3HVVCziKdBzl7Iv08JRTttMcD5fIeuMPWDLLyuq2CQuaBk2IBmUTnJ4wwtEWQWOrPLvvVCAI8+URMUrcaqu39Xwb7rdiolaRXdrRPyQyk+5PYRcRvkIcDlKv85DT3L3sVNcuG4LC2r+t8GBJ64QXptFelvrQRLXjhppAZ4qfWoqy27cr2wfcpHct5+YuulNd2SkfLSU2Hm9bA8tS2rCEfC+/XREMeLJhAm8R2j6XvqSUmVq3a5SAP0qf5rK2xDRAX9ZtXbxUfomvf4a4NaD7VwzjlaWuf3ztdKFYQYRhPfRitkgBAiZeHIockmDKu/KbQmExZ9YtiLdu/JxgtCh6odq7nZwB/CPmIO6A2nq7Zpyjxm/Wjf1yaomfoYEZpSGxdq17fDJBhUt1MayT2Qt+0Lw3FfSXnGY7/RhU1Fe97VXWwF4fzLlN3ecB0n2wsHp0jVlI7ubPvuS1azqA1s8jQZBZsUBvTAopPIgCw+9fz+gjeCXa2T61uU/hrKBy0i0z7f+83UQb0h10dQOaSMxlOJkXqSMYFq//x3mPHGa8hTXRM66dtqFI35sg/weonzG3INOO+TW9wpI/Im8rea9cIidAonEANDr4yiq1HS1KwMY7hrMMI0SH0KPVbBi3hi0TQtW+Mo9lgGe1V/R3VbD6a5IP4h1iZhyHuhU6KlYTKbU8GHLCT81C11difTRb7c9UOVSTsDbKGWSkO2ZIwglvZf4eG4KkL4e/3TI6Fxej/62VTQmPQ824N9t7fHrSYTOXVNu0NREL2Va8HdCs2wVr+RJTSLWo00I1SWOvausw6a5ngkZCHA9hGmAnIBxkWwcYMRXz6k5lEYPDIuolFCgapAEMGWZ1fmzm8t6NYNvbENP53bSxW1U8k9RiwNARW2gOrUKQNwsAFixzAHXztVSoaFhLKM104a7MN397p/xndUXMiq+k/BerNUPz8kHAqA90XyJBQyRdmimT2/l6FxPnn5oCgHStHlNWyblyKLBHaHNFvxgCil0Ss4JnCRoojPC2imGKLe34GKByNsc21sSogCOpKQ== X-OriginatorOrg: in-advantage.com X-MS-Exchange-CrossTenant-Network-Message-Id: 78339a6f-dd24-4e86-2129-08d9c2705d94 X-MS-Exchange-CrossTenant-AuthSource: MWHPR1001MB2351.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Dec 2021 21:50:11.3781 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 48e842ca-fbd8-4633-a79d-0c955a7d3aae X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: KVHT5w6OAClSFN1lq6FWwbpKjMNMi99FAXUjzqI3iKmcoB/nJfjex5E9IMXxdBrM2jgk+yXVtNjRKJmUlg2IEslQWdMdBcafZLHQkPZCpXo= X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR10MB5633 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC Add the ocelot-ext child device to the MFD. This will enable device-tree configuration of the MFD to include the external switch, if desired. Signed-off-by: Colin Foster --- drivers/mfd/ocelot-core.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/mfd/ocelot-core.c b/drivers/mfd/ocelot-core.c index 09132ea52760..52aa7b824d02 100644 --- a/drivers/mfd/ocelot-core.c +++ b/drivers/mfd/ocelot-core.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include @@ -103,6 +104,13 @@ struct regmap *ocelot_mfd_get_regmap_from_resource(struct device *dev, } EXPORT_SYMBOL(ocelot_mfd_get_regmap_from_resource); +static const struct mfd_cell vsc7512_devs[] = { + { + .name = "ocelot-ext-switch", + .of_compatible = "mscc,vsc7512-ext-switch", + }, +}; + int ocelot_mfd_init(struct ocelot_mfd_config *config) { struct device *dev = config->dev; @@ -139,7 +147,10 @@ int ocelot_mfd_init(struct ocelot_mfd_config *config) return ret; } - /* Create and loop over all child devices here */ + ret = mfd_add_devices(dev, PLATFORM_DEVID_NONE, vsc7512_devs, + ARRAY_SIZE(vsc7512_devs), NULL, 0, NULL); + + dev_info(dev, "ocelot mfd core setup complete\n"); return 0; } @@ -147,7 +158,7 @@ EXPORT_SYMBOL(ocelot_mfd_init); int ocelot_mfd_remove(struct ocelot_mfd_config *config) { - /* Loop over all children and remove them */ + mfd_remove_devices(config->dev); return 0; } From patchwork Sat Dec 18 21:49:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Colin Foster X-Patchwork-Id: 12686453 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DBDF7C433F5 for ; Sat, 18 Dec 2021 21:50:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234784AbhLRVuZ (ORCPT ); Sat, 18 Dec 2021 16:50:25 -0500 Received: from mail-mw2nam10on2118.outbound.protection.outlook.com ([40.107.94.118]:19424 "EHLO NAM10-MW2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S234587AbhLRVuR (ORCPT ); Sat, 18 Dec 2021 16:50:17 -0500 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Ztey6i6A+sGBCT1rUM5FCYjdX1XYWavKmUNBpruoa3soCEoz+ptzgdlWb+QgsB+m6Se+ohYdEDkfMdOVKtKDz4zb7TxuJ+kg5IMbG1x0T5390uFCstUgEITezefAr1EN73UiNADN4gus2D6JZgBjeauOb1jd0rxAaTw8imA6Zdwb48gly06JTaVxFlqpmA8L+ULEe4iKpVckRG0AkW8J/zysvOJzt3IcVlbYPgrVy4FuHJNtxEsxhcpfMFFnQ0DpqK+uNp0K/fy7hUd4LPlovOEgJkSFFVU+LtBR0QKbBQifm8E9JZWZ6qqQeW2uLIoIbzzFWTcIxJQCdIWNpFemEg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=g+rLDXGxLvtuOdamBqUJt6dGCQ4/RX/3E87jruiMwKU=; b=WlxGdEfHNA3/G/IidEw2gcr/jZu9dk9TKjinhEOd5OfWEFmS0kF3xkjBmDJ5l8TslRk1q2BLcFhHZsE1G6iajfjEdZKtCFm6pbbxzfj8ItiKnrY4GJcuG3YVPdBAw2AvaJK/VjUwWKf1/MtKk0wFMifLiegvr/Brlpy260NwxM+AuIuZ9a0cJBHKgqOydCfo/q8uUOuteRw7x/13gJoHLCHqz4fygFcHV059GQNyL2P9i2yP0eYzhYZn4+W6P0AMsjk2puHPVvZQG0XN+PfEvoWQVyPWZtwmD3hsOFQWUSfH9MGzFUIUUyB8Y1n/yt2zcUWbgDzKtpyzuHD0fpTUdQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=in-advantage.com; dmarc=pass action=none header.from=in-advantage.com; dkim=pass header.d=in-advantage.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=inadvantage.onmicrosoft.com; s=selector2-inadvantage-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=g+rLDXGxLvtuOdamBqUJt6dGCQ4/RX/3E87jruiMwKU=; b=BnUeA+GL6EVIg1TAJghEyheC9h7oWlv4pzN+BDjfyGu21tGJa4H0Kaq73uK5tZq0e9aGHuZBn7gG99nk6V1Xyz+yRvBC4wwv6LrpTpqtRGVbQgphELUIw+03kQ8yR32goLibth7W4slsMeJIIxJ8GN1d/2o8yxY2RWyWOwZHYAQ= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=in-advantage.com; Received: from MWHPR1001MB2351.namprd10.prod.outlook.com (2603:10b6:301:35::37) by CO6PR10MB5633.namprd10.prod.outlook.com (2603:10b6:303:148::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4801.17; Sat, 18 Dec 2021 21:50:12 +0000 Received: from MWHPR1001MB2351.namprd10.prod.outlook.com ([fe80::2d52:2a96:7e6c:460f]) by MWHPR1001MB2351.namprd10.prod.outlook.com ([fe80::2d52:2a96:7e6c:460f%4]) with mapi id 15.20.4801.017; Sat, 18 Dec 2021 21:50:12 +0000 From: Colin Foster To: linux-gpio@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Linus Walleij , Russell King , Heiner Kallweit , Jakub Kicinski , "David S. Miller" , Florian Fainelli , Vivien Didelot , Andrew Lunn , UNGLinuxDriver@microchip.com, Alexandre Belloni , Claudiu Manoil , Vladimir Oltean , Lee Jones Subject: [RFC v5 net-next 08/13] mfd: add interface to check whether a device is mfd Date: Sat, 18 Dec 2021 13:49:49 -0800 Message-Id: <20211218214954.109755-9-colin.foster@in-advantage.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211218214954.109755-1-colin.foster@in-advantage.com> References: <20211218214954.109755-1-colin.foster@in-advantage.com> X-ClientProxiedBy: MWHPR02CA0011.namprd02.prod.outlook.com (2603:10b6:300:4b::21) To MWHPR1001MB2351.namprd10.prod.outlook.com (2603:10b6:301:35::37) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 3e9a4c9f-e7c9-49e8-6904-08d9c2705dff X-MS-TrafficTypeDiagnostic: CO6PR10MB5633:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4303; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: wI7owGYTJqa64Kaeb5GCxh/VWRdXQWGnvOABRfhX6WEhwVDOQiBU/zYtX8cl3R+AvCoNyeHLhMfIYYSR2iuhbtV+SU3nxA7S2t/axqDWw6rV2EnxZ1JajwZjpi9+6wryvP+dpOMe6lvgbH8MrVX1rC+SxpOPhIdL1OM8Ogzj/NiN78oA3er/Z1yKkOw3BhaTWAhO4LdrNc77Qu1nTKLARKZC8tcvp+6+IuLljIx6Xz3o6qtdS0SPvk8Em+JTOEoNPw45rnlyerKZrns0pdd6md2AVa1SwMguRY4l3cHOPCZmNxRHkiNey10I11REoRaHCk4MgLDCKxvJ1L4zVU55T3IQr6BWWjfzzKM3MPQuqPLS75ubBECmfQJkLwpNjkrbVUqi4a22virhd28bKjhomlSV0W2yoXXPO5rIHcmUs7GgkqFqGpfrmqPiOMwT213ToXD84C58F+fi44Di3tIQeLw6PcThM6JREnFSNGEZYKFkedc2tzgH1z5nszHvg8cC0jhV/14mxCmsnulJB0mXkkavVLotLabzUM8Y3b/G9WNO27DKRQ1IvopJ/QwXW04LIGZrwMHajbQop8+2IrWtoGwVgcsHDwUVxvPNoOXiTHFabSv9Fh3kQgtZoHtcoHiskL00F9HPboiPBj7evYCUsX6nX8saNpnDPHG0TolDOWKYC1Bai7a2sH5rdN2om+oTLxjFMG+SMlZnCI9vNdjllw== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MWHPR1001MB2351.namprd10.prod.outlook.com;PTR:;CAT:NONE;SFS:(39830400003)(396003)(366004)(346002)(376002)(136003)(6486002)(6506007)(7416002)(2906002)(36756003)(6512007)(26005)(86362001)(66556008)(66476007)(186003)(1076003)(6666004)(4326008)(83380400001)(66946007)(2616005)(44832011)(8936002)(8676002)(316002)(54906003)(38100700002)(5660300002)(508600001)(52116002)(38350700002);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: ATJvwAhJxN//bWL3FjnolGwvgbyzp+b6MDC/gcLWu4VvKB76DX5SJ9k/q318gqjurlVpq6HSV+Yzo8pZuVbMj2xd3kWygdzAUqcuBRxP3/rYHXc4eiQ3L9flalKEAnDqsFFMCUh40HLMv9zJhyKzCwLvLcq3vExhsva7waUNq7TjIzKb8b14ygZiwLw7T/Vk95LidaX+mN03rFssirtFyH/FwpfYcYnpY4+3EpQ7MEhxB98lHwqHIkPrM1AFWBT25eXc4owwzry4Ou0M8nW0C7nxRD9c3oDeAu/U0o2O9WSlRlleVfnBkzUW/hJJbNEEBFXqcHZxdYacRZ3HXDB0mB2XFlW7UcatojCiacG1I48uBP5RMAmt5vtqNApmq+Cs7JAoPWKjgHIYprpxZQ19dBPyNNC+7xSR1f53+U7mWoqJ2rswkBy6Ssr91J+vTBxTEtEXuUoZ7Th7FXY882+oowva1XP7xuLnOpspfYNlN4OLGKDflMJXObwgbbmjk5WdKcbLj3YP7xztvXJiOe9YYf+C4aSbBP3Qvr2WvvUEzh3eQs3DVqS7vULsi+FbbDQ3AmwX2Ua2Qc3ZNQ4fBAdMcqz195S2JhZiqmhKPQS5AlZpxBbUGz97RLamY6UmT5qW52ywR6hBPsK/1weQaTqiC5BKP07SptylJJEn+W1Rv9KVEfzu3MuZSr1X6K6f5rMh0l/PaLohjDM3Kc+abG36SyRsM5nrmci6FKRkKGKxHh2TROQAiQ8gr6kxUKKBqbV72ASaSTYtwaKLUUomu9Nj4kLx6gHv/gmEWGuIhndKHogpTNMLXThrzrIfcefP0OVGikACcHsJGdl3UxE5i8/arwVc0O6Jw4WOJXIPy3attFc03NsN7dBhfE7s2rCf5SQ8hZ5l+Wsdw07z7uk6ZfJysvtShalEgUrBI73Qbop4fam/QHOLPSSZ5yJ1MDk113/qqh9oDPg64ymHf4vZAMxxcItmsJK0dm6x716ZL8NAJ/0M3b+CyCSsTLhqw/ZkovN9WXGRIUoJVNBF7zSsFSOjNx+cHYhgS+hDmWJjQRecIV34FBeGKiIT1F92DuN1xKWf0g2wKqxFerR924M0anaV8rO6JCje/QC4hDONzBa7mEIm4TOfkgRO4eO085r5OWAJY3UNvu05m2yCb+hEDEQnVzUdPi9H3CM4MgU/L8yUwa/vQ1diUw83hhYrlwbs2mR6/coszVk3UPqVoNWrtQRrq372shYtj+fwdCV1iukGtHubI/3xpipHdVSLVEvqU5PHoRYDRkmxSONZCPPOmkBWv2FRI1yX9MWucNmT6ldfRr7HvHUNkUO2fzhiia4rCs/mMKi8XJywKnuLa46J7G9nSj73nm+wExiMwyCzyZ8cPMfFAs8jIWfnAMAye6hpRb/a44nKFbbnIVkch51VIQQVWeb3DRlMocQxPqA0erX1mwnksXEyOYG0EoujVIjhkE1JrzG4j1jlTGCaXuIQWl0o5tHfLql5lcC9n8XZWC6wd9IGRAE1E82YywNhv2CiebOxr8wp9HUDKYc0TthSFlZuSysOV9K9K05t7M1xoyHrr+jIlQ6xpsrb5pIhNLvOL7Uwu6k/kk6kO5a2zJyXzwjY9rE20wP++CysgQbfg1sqUm82sj2cPrES+4EtTxReHDTHZPs4GJ23eISgIe/1F+H4seAxEXW8+0sz91Da20Lj+Mg= X-OriginatorOrg: in-advantage.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3e9a4c9f-e7c9-49e8-6904-08d9c2705dff X-MS-Exchange-CrossTenant-AuthSource: MWHPR1001MB2351.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Dec 2021 21:50:12.1437 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 48e842ca-fbd8-4633-a79d-0c955a7d3aae X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: WWHdCZONncExQVMCp1PDpVu0Lxao1QgRO23LNuUBSv+FM1wYuNDqgWIBfDbKGtmwA/IhgVCRjdcWhSAGY+Sh8Nuh7LEXL/TcbG7/kXXP/pM= X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR10MB5633 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC Some drivers will need to create regmaps differently based on whether they are a child of an MFD or a standalone device. An example of this would be if a regmap were directly memory-mapped or an external bus. In the memory-mapped case a call to devm_regmap_init_mmio would return the correct regmap. In the case of an MFD, the regmap would need to be requested from the parent device. This addition allows the driver to correctly reason about these scenarios. Signed-off-by: Colin Foster --- drivers/mfd/mfd-core.c | 5 +++++ include/linux/mfd/core.h | 10 ++++++++++ 2 files changed, 15 insertions(+) diff --git a/drivers/mfd/mfd-core.c b/drivers/mfd/mfd-core.c index 684a011a6396..905f508a31b4 100644 --- a/drivers/mfd/mfd-core.c +++ b/drivers/mfd/mfd-core.c @@ -33,6 +33,11 @@ static struct device_type mfd_dev_type = { .name = "mfd_device", }; +int device_is_mfd(struct platform_device *pdev) +{ + return (!strcmp(pdev->dev.type->name, mfd_dev_type.name)); +} + int mfd_cell_enable(struct platform_device *pdev) { const struct mfd_cell *cell = mfd_get_cell(pdev); diff --git a/include/linux/mfd/core.h b/include/linux/mfd/core.h index 0bc7cba798a3..c0719436b652 100644 --- a/include/linux/mfd/core.h +++ b/include/linux/mfd/core.h @@ -10,6 +10,7 @@ #ifndef MFD_CORE_H #define MFD_CORE_H +#include #include #define MFD_RES_SIZE(arr) (sizeof(arr) / sizeof(struct resource)) @@ -123,6 +124,15 @@ struct mfd_cell { int num_parent_supplies; }; +#ifdef CONFIG_MFD_CORE +int device_is_mfd(struct platform_device *pdev); +#else +static inline int device_is_mfd(struct platform_device *pdev) +{ + return 0; +} +#endif + /* * Convenience functions for clients using shared cells. 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Signed-off-by: Colin Foster --- drivers/net/mdio/mdio-mscc-miim.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/net/mdio/mdio-mscc-miim.c b/drivers/net/mdio/mdio-mscc-miim.c index e16ab2ffacf6..00757e77fab0 100644 --- a/drivers/net/mdio/mdio-mscc-miim.c +++ b/drivers/net/mdio/mdio-mscc-miim.c @@ -223,6 +223,7 @@ EXPORT_SYMBOL(mscc_miim_setup); static int mscc_miim_probe(struct platform_device *pdev) { struct regmap *mii_regmap, *phy_regmap = NULL; + struct device *dev = &pdev->dev; void __iomem *regs, *phy_regs; struct mscc_miim_dev *miim; struct resource *res; @@ -231,47 +232,46 @@ static int mscc_miim_probe(struct platform_device *pdev) regs = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); if (IS_ERR(regs)) { - dev_err(&pdev->dev, "Unable to map MIIM registers\n"); + dev_err(dev, "Unable to map MIIM registers\n"); return PTR_ERR(regs); } - mii_regmap = devm_regmap_init_mmio(&pdev->dev, regs, - &mscc_miim_regmap_config); + mii_regmap = devm_regmap_init_mmio(dev, regs, &mscc_miim_regmap_config); if (IS_ERR(mii_regmap)) { - dev_err(&pdev->dev, "Unable to create MIIM regmap\n"); + dev_err(dev, "Unable to create MIIM regmap\n"); return PTR_ERR(mii_regmap); } /* This resource is optional */ res = platform_get_resource(pdev, IORESOURCE_MEM, 1); if (res) { - phy_regs = devm_ioremap_resource(&pdev->dev, res); + phy_regs = devm_ioremap_resource(dev, res); if (IS_ERR(phy_regs)) { - dev_err(&pdev->dev, "Unable to map internal phy registers\n"); + dev_err(dev, "Unable to map internal phy registers\n"); return PTR_ERR(phy_regs); } - phy_regmap = devm_regmap_init_mmio(&pdev->dev, phy_regs, + phy_regmap = devm_regmap_init_mmio(dev, phy_regs, &mscc_miim_regmap_config); if (IS_ERR(phy_regmap)) { - dev_err(&pdev->dev, "Unable to create phy register regmap\n"); + dev_err(dev, "Unable to create phy register regmap\n"); return PTR_ERR(phy_regmap); } } - ret = mscc_miim_setup(&pdev->dev, &bus, "mscc_miim", mii_regmap, 0, - phy_regmap, 0); + ret = mscc_miim_setup(dev, &bus, "mscc_miim", mii_regmap, 0, phy_regmap, + 0); if (ret < 0) { - dev_err(&pdev->dev, "Unable to setup the MDIO bus\n"); + dev_err(dev, "Unable to setup the MDIO bus\n"); return ret; } miim = bus->priv; - ret = of_mdiobus_register(bus, pdev->dev.of_node); + ret = of_mdiobus_register(bus, dev->of_node); if (ret < 0) { - dev_err(&pdev->dev, "Cannot register MDIO bus (%d)\n", ret); + dev_err(dev, "Cannot register MDIO bus (%d)\n", ret); return ret; } From patchwork Sat Dec 18 21:49:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Colin Foster X-Patchwork-Id: 12686455 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7EA2C433F5 for ; Sat, 18 Dec 2021 21:50:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234807AbhLRVu1 (ORCPT ); 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Miller" , Florian Fainelli , Vivien Didelot , Andrew Lunn , UNGLinuxDriver@microchip.com, Alexandre Belloni , Claudiu Manoil , Vladimir Oltean , Lee Jones Subject: [RFC v5 net-next 10/13] net: mdio: mscc-miim: add MFD functionality through ocelot-core Date: Sat, 18 Dec 2021 13:49:51 -0800 Message-Id: <20211218214954.109755-11-colin.foster@in-advantage.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211218214954.109755-1-colin.foster@in-advantage.com> References: <20211218214954.109755-1-colin.foster@in-advantage.com> X-ClientProxiedBy: MWHPR02CA0011.namprd02.prod.outlook.com (2603:10b6:300:4b::21) To MWHPR1001MB2351.namprd10.prod.outlook.com (2603:10b6:301:35::37) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e555cd5c-f406-45fc-bd84-08d9c2705eda X-MS-TrafficTypeDiagnostic: CO6PR10MB5633:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6108; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: oNAHMqlU/NnoGp1bVthV6JxclUVjWr7DM5BiLyjLjJWNm8CxUBFMZeSQThLBF8g9WvxqA3yhUqyvBhzK2PFoV9AyjTy6sMYmvPPuYE0FL+him1ooMHjZTxB34N10bwVXLf/rvmwkq8ha2QNB7q9oIkafA6f41eO6Cit3xUIplt5MQ6joDv3GiImiNyMNyTCrd1++peKXE37O11YzPfjnWyp73zzgaAbyM8KC3nAuUT9S1G3cemHxuPAz8BeKu8i3537hcU62iEUpBkDggUI5ZEp+Zz8Hs+LSEHIG8/6aKMC9hv87VuMDDTMWnX4yEGmTN5JcAb+UD9qfVzsdM1pmCtAuZI9NjjC0TRh/YJLJETaLR3mOe3pmELf+enMZcFFK/PFu9/q0xWBaLHt9MFafsKXd07hEn1mpioObykmG++bW9IMaOhxT52akzynGUAnApUWonKrgEBpN69TMwtmLdyG8hTqM8f9KQ1g4npl7fNanQ/6oqBh+7yexKUcpwUPncv1i6+lbQV1YTbQ3KFiNs+tuwpI9RbWMxMrTTx9DsIhGvwgqX4Zbi84XWgggrtkO55Y1k53J9r/1jCJeB1n1PaALQk+DUTho1Cx1mYMqBOH/JyOlAm99p/RK+avIFe/9LO7WC1y1trSHmX1Dreo3k5I1YeCCl53xV4aYBjnPOICFCBXUesbJSu20XnGQHOaP X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MWHPR1001MB2351.namprd10.prod.outlook.com;PTR:;CAT:NONE;SFS:(39830400003)(396003)(366004)(346002)(376002)(136003)(6486002)(6506007)(7416002)(2906002)(36756003)(6512007)(26005)(86362001)(66556008)(66476007)(186003)(1076003)(6666004)(4326008)(83380400001)(66946007)(2616005)(44832011)(8936002)(8676002)(316002)(54906003)(38100700002)(5660300002)(508600001)(52116002)(38350700002);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: eNjJ6GO5V1gsxOBb3qWGOHMy8i+BtUJie07ib13udkwI2Dy5wGBKCu7IsxpYlxpAz1CMTSnmo9NzZGhG2di+3/BATA8g23ZyXVwd4qx8JqePOGDCBL9sRMXTuocAcIGKf4irEv9//eTpCPsgAVJKFMRvgwA1WkVTv5mR2a+LwX9kMEsUViKMf5Rq2VCLLkYPOQ/qB4NPTa2psP0RWGWTyT5SXYhtuKJfKMeHeA4FmXEY3ibI8Wpay83Ku9Ch1HlxekctJn0j5PNcCpnw86bbC6i2DMKB5EQajgAz0kcywZXXKP7mNX9+O+55HxN8oTlpxqHLAEegpPXuA2JQ6Bt0hFwz63uPbDacZd1LkNaWxyo2VKn8RjD/DXhY2UjzF2Mz3Fs2clFCWd0jVslVQ82rXAedF5Yp2NnpISX3I9fHqmctH+o5gFl+mldv8v6JVQxxMpzSVHeu33s2fyxod00VUsjgBWO4U6Fij0lcMMfNJkkeiNpcxJOdGXyOQCAA64ePVLEQ2iYP0I69O2L+tWaOCP8Bb3VqU+F6+B50ccQKl/B4jOaDGfhdboE9IYjFKSABPKUQkk//dFhehCMweed5G24oPgksZuq/ofkrTnZrTHTW4zrMcuBCMd5gAjlp+kHulDRFCLMlLXcASKC4HbypCEFez4btbnsdbIoZLVb2tiiTP/on1fbzXL0mi6hHquE+YByqBgIgH2IZDY1oeK1umUIehoVOR927/E6DYmjvhWX7PIfhdX1cR2oOhKFGzupX93udlGSP+ih799/mJdy2qKyXvyd46m7SgJwRkWmt92IR4Lsn8Jzl4OkmCav73npWHiw+9mdIOwqiOPzVTUkVGmOLRcztX/oXYvd02fP7vBWetXaDTjMX4LPvLuOMBynHtNtygEvi9N1d9Ewtos9m/500z7xEh5fwkGoWzzG6symNssLuGk+NIJxp/RJ3PMzFOdfjPe18xVfIgET+hBYME1sLcsWfpS7qYppCRTS2nNOkuEveS+G/DJzMZuf0Kd2Llgu275vOsVqLm6wlDdpQUnVeE/uEpDipFBvv/ZBQax1nRQfAw0a/CqI+vzN1AzvtB/c4YjbKDrNMCwcb93xtpRFAwC0Ejw2XzEuxr3RwOgwDDnWjQgOuY+2PBy/DwS73nbC5xK+zgHyyz/B0tF6kQdxEXBOoJFpg0zM1OYrqaw4Fk7/+gnX/sUKdcpEFRDtnIYCJAI818DVDzFjq8qp72Vyc2rZL4QbZBMw6o0QjcQaLW9N5NhC24ZtlHOplosCytHEP4gH59b+JXrnEnXgv+KI2EYpAiWC2Wx9bTFSJxzbfBTVifwrrNKjmf1Kxma4ccQoNotE0e5+GW3uLtzMKnapcqvrHHOahRyIefQl54dM606ritI8iRW+ye1mBvrOfLf2SgH6AxSMBN1yD6BvIhc2mbGZvkQa5xhbeX+JXTUHC6pnu98bi6uT63lLoYOIFlRhYmz1IYXm9e9SxEWBVTN7xvuZx1GthKFMAvfXS5gaRHxws5LjVLPDMLDfIC3V30C4izhmDn8R775Sn4F9SsskCl60Chc41Fh/1zUYN74dajDBSKELh7Cajjo6zhCFDvFrJdmt4R7ksFsXndE6Tg3MuIaIX0FPy6VMc54cCrLTSANVp7p5We3ni6DmpFVq+nrt/tX7MEFhJE0cD2iGtsSFseAq2wlbNFbetlvEFcBU= X-OriginatorOrg: in-advantage.com X-MS-Exchange-CrossTenant-Network-Message-Id: e555cd5c-f406-45fc-bd84-08d9c2705eda X-MS-Exchange-CrossTenant-AuthSource: MWHPR1001MB2351.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Dec 2021 21:50:13.5030 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 48e842ca-fbd8-4633-a79d-0c955a7d3aae X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: THaj54JbtwCmbTLR81kqpBzPeo6K8MeeoqOEPn23HZP6pIAdmK7z1p7ZpP8wRGoN1h06wU3BYvr2wb358ktuh6DxTW1A/q4nvGusTe90330= X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR10MB5633 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC In the MFD case we need to request a regmap from the parent device instead of using mmio. This allows for the driver to be used in either case. Signed-off-by: Colin Foster --- drivers/net/mdio/mdio-mscc-miim.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/drivers/net/mdio/mdio-mscc-miim.c b/drivers/net/mdio/mdio-mscc-miim.c index 00757e77fab0..d35cca4672b4 100644 --- a/drivers/net/mdio/mdio-mscc-miim.c +++ b/drivers/net/mdio/mdio-mscc-miim.c @@ -11,11 +11,13 @@ #include #include #include +#include #include #include #include #include #include +#include #define MSCC_MIIM_REG_STATUS 0x0 #define MSCC_MIIM_STATUS_STAT_PENDING BIT(2) @@ -230,13 +232,21 @@ static int mscc_miim_probe(struct platform_device *pdev) struct mii_bus *bus; int ret; - regs = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); - if (IS_ERR(regs)) { - dev_err(dev, "Unable to map MIIM registers\n"); - return PTR_ERR(regs); - } + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + if (!device_is_mfd(pdev)) { + regs = devm_ioremap_resource(dev, res); + if (IS_ERR(regs)) { + dev_err(dev, "Unable to map MIIM registers\n"); + return PTR_ERR(regs); + } - mii_regmap = devm_regmap_init_mmio(dev, regs, &mscc_miim_regmap_config); + mii_regmap = devm_regmap_init_mmio(dev, regs, + &mscc_miim_regmap_config); + } else { + mii_regmap = ocelot_mfd_get_regmap_from_resource(dev->parent, + res); + } if (IS_ERR(mii_regmap)) { dev_err(dev, "Unable to create MIIM regmap\n"); From patchwork Sat Dec 18 21:49:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Colin Foster X-Patchwork-Id: 12686457 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 15927C43219 for ; Sat, 18 Dec 2021 21:50:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234815AbhLRVu3 (ORCPT ); Sat, 18 Dec 2021 16:50:29 -0500 Received: from mail-mw2nam10on2096.outbound.protection.outlook.com ([40.107.94.96]:43520 "EHLO NAM10-MW2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S234654AbhLRVuS (ORCPT ); Sat, 18 Dec 2021 16:50:18 -0500 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=W71ZG+iohx2qg0GCshLURugF+q2HQas2fEVRmg/GEjBc2TbktfAIXh00pZDv2IeUjEA2Xm6z+V2ziaK1AnNNOy3YPU5i4+bvikJEk6tPh6gkJLkxqsCK3aa3IktBCoaG5MQEu7ytfD9AxOzO+YukyoSlrPJe7e1wd6+sZbcrO8y2aq84c6ntge0w1/erDj4jFZGh4fhDrMUQBi8ikg6SRuFl4MSLVral8ySeNRf+XOpYAqgORkpCHVXpcf/uDeDAgxwRLeLVqtCKWFXv9RvrQoddym8iacSmdQ49A0Zvomet/kRDCqRItno2Yg/zADCi1q5nU/Xwmy957BH2L985Vg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=pAAoDYcWfXLcdu37KHRVrKKICtYnve9pE/vZnt5JYug=; b=WWXQs9etMqVbMjCgv+Vqmgu4CBIbHAl6ynhyCuVwUlO50UR/B4y3I9j2uphP50sOwzG3hpGgwQAEr+747WxhoPvUCbyUzAbdoYXlPBaEZv/uI3AnYPb55OuSL1MW0VuOUhpCRWC2sWJ+/H+BZsq2eQciWTW8ymhzuPo/Jk7GUYPqcEqC1TEQXt3+qMrp9Li6XwHP+Pv1ZeORVvzkAMppJJ9QVnyavdjrYzKDOGE3MP5Da9y4u99BGU53V89DA6rFrphjyIdrbKDOg4Q+s0iXxSuXDOP1QN7u3v5IEg6LsJQzMFMiZnUMvuWR4RKLLWTKUj8dYvOVoOznRFZdEj5ojw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=in-advantage.com; dmarc=pass action=none header.from=in-advantage.com; dkim=pass header.d=in-advantage.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=inadvantage.onmicrosoft.com; s=selector2-inadvantage-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=pAAoDYcWfXLcdu37KHRVrKKICtYnve9pE/vZnt5JYug=; b=hLAjVcaL+s7o33fLcw27SsrbNBZl+nu0x4pa7uLECDd3xMfv98EsBXQbrUl11h2qxXzSPkJ4vyn2XkRVPToUo7Br1M4XiljzunC97HyWGWP2BZmmTrT/WcCha8mZhTajXH6D3fstKg1AXs5OHvAHQRpJhNL4x6mZwcF4cEQlue4= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=in-advantage.com; Received: from MWHPR1001MB2351.namprd10.prod.outlook.com (2603:10b6:301:35::37) by CO6PR10MB5633.namprd10.prod.outlook.com (2603:10b6:303:148::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4801.17; Sat, 18 Dec 2021 21:50:14 +0000 Received: from MWHPR1001MB2351.namprd10.prod.outlook.com ([fe80::2d52:2a96:7e6c:460f]) by MWHPR1001MB2351.namprd10.prod.outlook.com ([fe80::2d52:2a96:7e6c:460f%4]) with mapi id 15.20.4801.017; Sat, 18 Dec 2021 21:50:14 +0000 From: Colin Foster To: linux-gpio@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Linus Walleij , Russell King , Heiner Kallweit , Jakub Kicinski , "David S. Miller" , Florian Fainelli , Vivien Didelot , Andrew Lunn , UNGLinuxDriver@microchip.com, Alexandre Belloni , Claudiu Manoil , Vladimir Oltean , Lee Jones Subject: [RFC v5 net-next 11/13] mfd: ocelot-core: add control for the external mdio interface Date: Sat, 18 Dec 2021 13:49:52 -0800 Message-Id: <20211218214954.109755-12-colin.foster@in-advantage.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211218214954.109755-1-colin.foster@in-advantage.com> References: <20211218214954.109755-1-colin.foster@in-advantage.com> X-ClientProxiedBy: MWHPR02CA0011.namprd02.prod.outlook.com (2603:10b6:300:4b::21) To MWHPR1001MB2351.namprd10.prod.outlook.com (2603:10b6:301:35::37) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 3cf24ac2-9b20-4edc-40bb-08d9c2705f41 X-MS-TrafficTypeDiagnostic: CO6PR10MB5633:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1751; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Yfb7QW+X4cCrgJ5qdfNpb+bG1fm2R8YiIjxrnaskb2Gcy2A7pj/uEt/vzFbt9HZtOF84bLnJmeqm8IugVUNX53f8nMZC2cX+aY5WiYU8qvowazEY/SKtBh5JFtlTfwX9qQgad2ocnNyWgdmOTrA4fJRhhRqhtiqWFl1srrV4w9krdY3sXd9Xhew8IGahx3I7UbkeM01dNBivihWMrbrbDzZ4zBaqRKy4EXAThVU+0yNLnY/D3itcMZa8PzGFpTa3nHPDRnBMDNtUdB/X8dwZy0VRuxSM3NBfZkBD0J7OZG3MZ3GQYeeMEP3i8wNUWZySY1GE0O5USGLyEeu9G+KdX1Q7DYO+uqZMSl8QaBQe+5mYvuW3EAuYfuQ9nCyCMMS4PGP/T1oxvuVTWxtpxd/ErxpDv8o0yqt12bYbF0HSwx+bBEqxAews0EgG/Mx5aent4LLCQMRmehqs/9UuaL1NXU0o5vMpccdiIWPggHbA9FMOmt0aX2bbaWBMt0kNB3hkHbHSKeSudawgIQ+Xl1yq3OiT7R1mliuGHCukNMUNf06p24vpGY54onVGdUzxO63+aEHRaI56jbEs53i0qzw59yMD3wb98+NBEDJZSL06N8wytsFFtH+dkNisWzfC8YlN+amJBI4RUnJU942l2+lj1cfEPNwCSzWVJRcjcTa1keQpGWgWgwaM3IF5wETqCF9eykPPaBKbufJbfDOeVhpxTQ== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MWHPR1001MB2351.namprd10.prod.outlook.com;PTR:;CAT:NONE;SFS:(39830400003)(396003)(366004)(346002)(376002)(136003)(6486002)(6506007)(7416002)(2906002)(36756003)(6512007)(26005)(86362001)(66556008)(66476007)(186003)(1076003)(6666004)(4326008)(4744005)(66946007)(2616005)(44832011)(8936002)(8676002)(316002)(54906003)(38100700002)(5660300002)(508600001)(52116002)(38350700002);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 4OXC8EQjtLcMv6MAfWbF3HtU7RPdDNuxCa9vGdUmQAee3JGUKBPaz4SR/3D2/s8krr7H1nCjv1sk2x3+stwRvHNjPxT9pg7SLsEDN+je1EPuUlO+bIOtwDoZM3m2i1MmpKl6rhXDvYx2Lc4TSSBizF03LdsuLwJ6Ye7BdjIAlGyAXnEBdgwuRSboqk0hPat7Nw1Mrki5/bXJp2e06ep6jLXbLTs4wktclcNEhBfwcis/pgbKL399NyJucwgAAgKaJRVs2VUNix/C17Q3ldDOdNm4mr2dVc9AOuldIRGCeU2j9v2fmkDSomQQ56FxyAOeaYBS1eYAFbsYG/HyyKmEXE+uLyZfGK28cruS2fBP0lXXWCb97rbEyexatPWrMXfVovCttn8G2/SjTC7ONS28yumxNxQfXqkLzTT0NrGfDZ03nlZMXN7PAIH/wCC1XfT6vIPAMhW77xolsTpWDT31AuUU46tZWD46XGGuo1mEg7/d80UKuhXTgnn097PINMR2OOvQoiV6uZ5ekw1/VjSHtv4E/JhSgafKqZnruQdY5CGgVymC+869qOULbZ8vvjsg0H/Gw9E8JzaTNqNIwXP5nfC2WQxxU4GoI3QzVChQSwbHmV6tYWcjSQ3fdnoiBoRcMv75LixVDH/ncM1VxEuJnr8r0SB25ISOPiC0zx1nUjSvoUgb8O5WgyRZOh0kCDn2hCA2hjoQ0fSVsmgVBsvfsMoIICdW+bLjmFlpZUsY5IngHOExuZw3SZYZ1RNPbgA/y/FHQwCuUarIVlamRccNvpyXwt4D9xU8cVWMFZEzlkBm1wNSmohCumSeaO+EX5eLbSutwDtdvbzd61a3rbzMXz/HkgZ2se9nzaRTXPXH0+bz1iCf9ufdi0X9Xqtd7T1EYoFl4O75uLeLCdivhDOrCXbknoysoLze1Wzwu+BQMSKErpjo4vKxlxM7FDUiQyOeae91N53r2dpUFV+mLTzALM/YPnlCiyvteXf6RoVEhHGOHpv5E2XQLZN2F37JR0jq7sXrwATPyahMGMPOujwXF9grR+yAVFWaiBvtn5G5s682u9WUkETYYRdAfDoqWggjRAYO6NngECnero7pQyxiZAcX3zXfDdbX4N1apn1HMmyvXn1I+YuBOaPhmLOLR9zAgJghnYJEY6H6Fld/YVLnkGdmjLXiUd+acN3tABa05sZ6J+kzPNgDQmHsPO/qGWYKPh7a2wRHf2BV+MmdFky1AfBzVtWpVoaAlQXNuXufL/NusD2SZ4613nc+XU/b7d21+GQ2OMRHrZdRhypAsioc+yYE0hJgPqnpb/i1cR9FJvJ08/AYX1Tb10TQ1zLligUgaTxQb1tUxc/0L4qNxXIYk5O8oRPg+P5/f34h0kpYPzYkjlkZSNx5n+AKxoKLUfflq7qM70oeVWt0IIYQ1IJN0YzLMTVBkrlY731diXGydrwy78A+k4r6mPbygbePB7plNBu0Uu8FuvtNGkH6ypQiRn59Hdrz97TkU6amoctYJcWrf4yByBsQtsCHeGHkDJLKDI4k0pihTS1rTYvD3/sz55Q8DD1RjC8RB0C12PllHVxhWT9d+PuUK7t4oosRIvRx73+SOoByOfzAN+b+ppUok7MG49MQh+V5DUohn/0FrGtK6ug5v3lWk/cJpbJYk80pMzEiqdwHmKQoRG7AeIeJWEzymLHP3zdSbOK7jhsGyP8= X-OriginatorOrg: in-advantage.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3cf24ac2-9b20-4edc-40bb-08d9c2705f41 X-MS-Exchange-CrossTenant-AuthSource: MWHPR1001MB2351.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Dec 2021 21:50:14.1748 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 48e842ca-fbd8-4633-a79d-0c955a7d3aae X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: JYJb51E4ighQkRH8mfMPOJEtgc03xOPGesoypuZNeiEImUSprS0R5oDdCJOmz2YAaW8XNvz1dNV4kdggnlm3I0SFKGvEFe+5tphxCHV0ZW0= X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR10MB5633 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC Utilize the mscc-miim-mdio driver as a child of the ocelot MFD. Signed-off-by: Colin Foster --- drivers/mfd/ocelot-core.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/mfd/ocelot-core.c b/drivers/mfd/ocelot-core.c index 52aa7b824d02..c67e433f467c 100644 --- a/drivers/mfd/ocelot-core.c +++ b/drivers/mfd/ocelot-core.c @@ -104,7 +104,22 @@ struct regmap *ocelot_mfd_get_regmap_from_resource(struct device *dev, } EXPORT_SYMBOL(ocelot_mfd_get_regmap_from_resource); +static const struct resource vsc7512_miim1_resources[] = { + { + .start = 0x710700c0, + .end = 0x710700e3, + .name = "gcb_miim1", + .flags = IORESOURCE_MEM, + }, +}; + static const struct mfd_cell vsc7512_devs[] = { + { + .name = "ocelot-miim1", + .of_compatible = "mscc,ocelot-miim", + .num_resources = ARRAY_SIZE(vsc7512_miim1_resources), + .resources = vsc7512_miim1_resources, + }, { .name = "ocelot-ext-switch", .of_compatible = "mscc,vsc7512-ext-switch", From patchwork Sat Dec 18 21:49:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Colin Foster X-Patchwork-Id: 12686459 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 46C3DC43217 for ; Sat, 18 Dec 2021 21:50:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234864AbhLRVuc (ORCPT ); Sat, 18 Dec 2021 16:50:32 -0500 Received: from mail-mw2nam10on2118.outbound.protection.outlook.com ([40.107.94.118]:19424 "EHLO NAM10-MW2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S234657AbhLRVuS (ORCPT ); Sat, 18 Dec 2021 16:50:18 -0500 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=ZIAwaJAu2C4oEQPjAMsuNDj+st2L+uT591wIXZ1fccNqmXYBFwurfE6c45Pbpk51lH9K0AD4zNOsHJCvwdwlys5OY88UCh4dfhuEOgu9F6ZU3okV/UdRAfdSpET4NHYaWgnwZKgZQob6YrqB9LeNHONt1Uup4cjy2iQtm/XoBjrQzb7tR+DnmKP2UYdL3iaNFIu7qeGEoOkoE/+C434+ctBCUyFORtR5g4x8gsUu/u+wRN7LdPK7eEycK1dckjPpKe49R7d43oSqQ9qFPfXSIgsuhFUkyMDuCKxihmLqtVyZ29rh45AaOkFlSuyx4IbZpC1zkOhO2kPWXg9VaLjxdA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=/MDQpmpKE+PnRLCj55SwiesyejzuT/VnP0S6WITX204=; b=jHnv6336JcGMqPnMfz9ZdDzf1klhmq3LZGqR8yXZPdziJF2TX0k0/ButxlZFnKUlqWXtovCymVwkDamxQD4fKZPGkeMa1wyG1Zrn1cYfDJZ7/VENne0GfDVfqeNFr2mGTYoe0apHxvxaJiyGtCpYI0EMzUr9CkC6HjrlEgymsgIyUm22hNQwkOKTS3WFs6eyGJhsU1SzZc9HO2M/3f4sX8QQJTMWnUXdMJEB3QnLsair0gmoBTfe2xtjMSGyxylLqyrpvyQpdv0lYLtQ+aw1zw19+ynjRf3ooLzAYufn5zu8XflZSvq7qU3ghMB9gCJ4QJ5hrEDEtSUvJPX1k4Ddig== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=in-advantage.com; dmarc=pass action=none header.from=in-advantage.com; dkim=pass header.d=in-advantage.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=inadvantage.onmicrosoft.com; s=selector2-inadvantage-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=/MDQpmpKE+PnRLCj55SwiesyejzuT/VnP0S6WITX204=; b=N7+qRAI1vczepwu4QUXRPHSCWZL2f2RNgydu2ozZDYL2WehlcFi51/hD8o8BmVjtXRdga53A6H/DEMdImZOUm5u0rPiqYn68cZeGFtDwp9rzSUrWB7wayvgzygEdDq4c8E1tKvJ4UZUEH6HejJCPjtwVDL5YkQAbyQzO2xHGyA4= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=in-advantage.com; Received: from MWHPR1001MB2351.namprd10.prod.outlook.com (2603:10b6:301:35::37) by CO6PR10MB5633.namprd10.prod.outlook.com (2603:10b6:303:148::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4801.17; Sat, 18 Dec 2021 21:50:15 +0000 Received: from MWHPR1001MB2351.namprd10.prod.outlook.com ([fe80::2d52:2a96:7e6c:460f]) by MWHPR1001MB2351.namprd10.prod.outlook.com ([fe80::2d52:2a96:7e6c:460f%4]) with mapi id 15.20.4801.017; Sat, 18 Dec 2021 21:50:15 +0000 From: Colin Foster To: linux-gpio@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Linus Walleij , Russell King , Heiner Kallweit , Jakub Kicinski , "David S. Miller" , Florian Fainelli , Vivien Didelot , Andrew Lunn , UNGLinuxDriver@microchip.com, Alexandre Belloni , Claudiu Manoil , Vladimir Oltean , Lee Jones Subject: [RFC v5 net-next 12/13] pinctrl: ocelot: add MFD functionality through ocelot-core Date: Sat, 18 Dec 2021 13:49:53 -0800 Message-Id: <20211218214954.109755-13-colin.foster@in-advantage.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211218214954.109755-1-colin.foster@in-advantage.com> References: <20211218214954.109755-1-colin.foster@in-advantage.com> X-ClientProxiedBy: MWHPR02CA0011.namprd02.prod.outlook.com (2603:10b6:300:4b::21) To MWHPR1001MB2351.namprd10.prod.outlook.com (2603:10b6:301:35::37) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ee9a673e-7770-4807-88aa-08d9c2705fac X-MS-TrafficTypeDiagnostic: CO6PR10MB5633:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6108; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: PexieaIh+t8htf+72eN5pr46eMC/GTffh/RnVRzfLZVN8U1ayebdgvc7Y8npbmJVCnTSiJtBhLlnXhUw2lgboWjwuckmSXU1JfJ6NabUzkNI45Qd2PTOvWGe/mWvzaMLTEboo1EeDHtq3btFG8WPxnJAdiD5kzJEkcEG0OI92HXo4/WsbCLpQ3xJiQFnNQ3744yEf2d4CUz+opMPOqk6fHM+tPhoSm2eBhY4NRDylTVFkxX7vaoL0LHDpLaa5mW//tS/7/OLvCGvfkPDJ1XDbQl7fNNORnjSqtJ8SrPLy6BHxeK3OqfKDSgvZnTZIVaf/ywHhU3rdCcR8uk+PDTTjnGSQxS45LDofxl/yDCodXPtN86bb3ohzA6wxslnGwwz3fZM2amW/NnszM11g/JjOZ7ywuDtv++EbFFq9+IAnnnorrOXsybw/a35vJlv/kNW3KTPDZzKsEEAkvF/SGHvRIkmuA43nUau6uJArS8knNI9yYwC5SRz9kW3Yfih//0dtdc8jGL5WeeNfoZNJyRoC2DU1CGdXOAGJBA/U7EK4u/aWBT0/ROq0Y925xCpKBa9GuCFkEaBkUds+m3goXy8wBAokhFwVtt2k3vnztegQmbZrWCN7mMtrKrueQK3YVCi06fgVEW6RIBZkgmQGQr284hEOcZRAHh2Tb+jQPann6BlX5LD43v3eaAY5K5XRt89m1Tv6vEfdqV+YYxBFoe9Zw== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MWHPR1001MB2351.namprd10.prod.outlook.com;PTR:;CAT:NONE;SFS:(39830400003)(396003)(366004)(346002)(376002)(136003)(6486002)(6506007)(7416002)(2906002)(36756003)(6512007)(26005)(86362001)(66556008)(66476007)(186003)(1076003)(6666004)(4326008)(83380400001)(66946007)(2616005)(44832011)(8936002)(8676002)(316002)(54906003)(38100700002)(5660300002)(508600001)(52116002)(38350700002);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: ScATJNDFSwBsomcbiVNyjrnnOGkBbt9qKrww19zvM1ztn75wlpHIp9yLek2WIiZ+t1v54w6nJFToPzykPzihAw2Y6WB9srfxpSq5YQcKX1/CRmFtrXhLPxS+QKkCIxlYNUmkjN9RHG2Ym54TX0lKie244sFZukroUMm7fRldpTB/+D79s9IqPJkOGjW4DccZrsCoFFSEZSvaKDg1DFy+sRMBDGvFGUVMIZuc/mXqqkgLh84RpxjXK0H75lBb4brV0Ka/fypP8qEwo9HafFjsysCXPBZpPYWEjxnmMIKL6xqp9tSB3DmbCxXb1odcvgHGIGfll76lupCj2ZZXhXqqoL63Yv6F/RQgp0kpWVRsTTKqqOck5psxqxK9SmbTNqUHN7B4pLV0m5KnPa2oukyFQAz1WnmXQkRSkhZ1yGybxwu2sgBcu9XYn/a1xYBdBHlDngTSB+TPVt3Mm3Ee6aGLwYFqSlPrxwDBDWVQpKMXwRBzzx1D0ashdpg/0g50hc+z6ZVvDIeMMnaK99Rq5wPhysFhSS10UOZ8MskJ6Zu/jgUF3cih8BI6f1gWydLGRO/efzth5Gu8h0D25lP+p4isJncjxXqQLK5z3GxA8zUaxcCQgxMLgriXQ3FcOEqU4qAjdzHLGbiq7mPcJgZufg6VxdugxQpOLkDbAkf6F6x/w/YZHeXA8/iKsq0zpn7b6bXbIqCwoH0bbOv0vpZVtCZDw7AIpm3SIDHW1MfskQvEGUfYo/kdqO9XaVJQd+szeTTjBe6P9sC9l0sciiZTs54V6zJz7UNlIkoC35vqtj2oi1FQ5WgybjuKYyUaq2x5rpA+HxhnZClNLNweLEpMeDOiUtAiYMmi190c6okl4JCFyj+q/U8A1yt+yovDLzrNkqj6nCLtCxd1zTAHeE+cOhxhPK+cnoVES/61FCI6LNx8OoVz5GY1afcgPQ3fezVG+ssNwDWZvGuoTCndh6p8tnjA8j0JNhua7G7X84EljkFK3Y1C/A6GZ0QIYA4Y1bHPlpy5GX8cngYO6z+OCl4uqx6XmNWXaoFe8ZGTH1HPfah0FvqYS6HR7H8Fl5khArSrHA0gBcXEapdsXqMSFhihx0WKhlHzxKGnBFLuXtHU6T2/uS/VML8++FMvQnUByzc5chP780PMCl2JX8hOzB4oJgmCXWb0KGve9cH+qL6Kkwvco0NBtPGwWMhI79ema23XAIxrNpxhZJc0Lz0BW+q7CWQHFVdJuah68jrjUNyjuRvYKbirKHeOVppj2fbpg+8HfvxDYd6T/JRmo/GmB2Peqaz3niaVpcy1U3LyghlCCngEK7nzd74VKwC5uAnl275GUDMflkMUqgzttMO2pBtZdP36B88nBDt4E/nadP3sVQ8PGPRxA7TvRKDwN/cgJCUgJOOYb2bntNvp/y4bwEt5q8vbGYbABaWpnSlWCpBvyinl/OMvRH4mwAV8z896xpXxDmakgiUSFx4TstWiiWRsZrJJotH+Ay4LSHh60U4oIQg3HMpNSfikhbpH+OZ9kZnzWhU9UPRnvjx8x2RBUGlOV5PlVF9NVS0csHVt7BwB9g2naMCKbKHti6B0AxDTAi3h857mrStSjvLwOOaYwjrOIlnGaucrFErgwjlGIJ5wcbCn3ejR6mWjZScDr2NIYPNpy1GL9qWimk0b1JOWUvvwOcy6hC+kI2nkLiN3E/2GD9UZscQ= X-OriginatorOrg: in-advantage.com X-MS-Exchange-CrossTenant-Network-Message-Id: ee9a673e-7770-4807-88aa-08d9c2705fac X-MS-Exchange-CrossTenant-AuthSource: MWHPR1001MB2351.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Dec 2021 21:50:14.8935 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 48e842ca-fbd8-4633-a79d-0c955a7d3aae X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: fbUrqt0xZ2cmT6tfWjb6snba2tFnUbmqFK+s/MKE7GAMMEHmfQrm0Sk33wQRSMxgN+G0JKnB0AfrOhd99VTy41GXgkkfWly7KxnKeWZKJ8Q= X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR10MB5633 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC In the MFD case we need to requrest a regmap from the patern device instead of using mmio. This allows for the driver to be used in either case. Signed-off-by: Colin Foster --- drivers/pinctrl/pinctrl-ocelot.c | 30 ++++++++++++++++++++++++------ 1 file changed, 24 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c index 42aab9ba049a..d07ac7a0b487 100644 --- a/drivers/pinctrl/pinctrl-ocelot.c +++ b/drivers/pinctrl/pinctrl-ocelot.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -20,6 +21,7 @@ #include #include #include +#include #include "core.h" #include "pinconf.h" @@ -1123,6 +1125,9 @@ static int lan966x_pinmux_set_mux(struct pinctrl_dev *pctldev, return 0; } +#if defined(REG) +#undef REG +#endif #define REG(r, info, p) ((r) * (info)->stride + (4 * ((p) / 32))) static int ocelot_gpio_set_direction(struct pinctrl_dev *pctldev, @@ -1805,6 +1810,7 @@ static int ocelot_pinctrl_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct ocelot_pinctrl *info; struct regmap *pincfg; + struct resource *res; void __iomem *base; int ret; struct regmap_config regmap_config = { @@ -1819,16 +1825,28 @@ static int ocelot_pinctrl_probe(struct platform_device *pdev) info->desc = (struct pinctrl_desc *)device_get_match_data(dev); - base = devm_ioremap_resource(dev, - platform_get_resource(pdev, IORESOURCE_MEM, 0)); - if (IS_ERR(base)) - return PTR_ERR(base); + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (IS_ERR(res)) { + dev_err(dev, "Failed to get resource\n"); + return PTR_ERR(res); + } info->stride = 1 + (info->desc->npins - 1) / 32; - regmap_config.max_register = OCELOT_GPIO_SD_MAP * info->stride + 15 * 4; + if (!device_is_mfd(pdev)) { + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + regmap_config.max_register = + OCELOT_GPIO_SD_MAP * info->stride + 15 * 4; + + info->map = devm_regmap_init_mmio(dev, base, ®map_config); + } else { + info->map = ocelot_mfd_get_regmap_from_resource(dev->parent, + res); + } - info->map = devm_regmap_init_mmio(dev, base, ®map_config); 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Sat, 18 Dec 2021 21:50:15 +0000 From: Colin Foster To: linux-gpio@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Linus Walleij , Russell King , Heiner Kallweit , Jakub Kicinski , "David S. Miller" , Florian Fainelli , Vivien Didelot , Andrew Lunn , UNGLinuxDriver@microchip.com, Alexandre Belloni , Claudiu Manoil , Vladimir Oltean , Lee Jones Subject: [RFC v5 net-next 13/13] mfd: ocelot: add ocelot-pinctrl as a supported child interface Date: Sat, 18 Dec 2021 13:49:54 -0800 Message-Id: <20211218214954.109755-14-colin.foster@in-advantage.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211218214954.109755-1-colin.foster@in-advantage.com> References: <20211218214954.109755-1-colin.foster@in-advantage.com> X-ClientProxiedBy: MWHPR02CA0011.namprd02.prod.outlook.com (2603:10b6:300:4b::21) To MWHPR1001MB2351.namprd10.prod.outlook.com (2603:10b6:301:35::37) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: fc6294ba-e5bc-4d8a-32d6-08d9c270601a X-MS-TrafficTypeDiagnostic: CO6PR10MB5633:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:663; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: mTynI8wa6R+WG4cUimEBDf3iBoPw2bk4NzzZObBXk349u4eDQtIt8xavVIEne4DomotfNUK1hCLVDtYE5poLWYszrobo5hpto91Mx8S4Yr/7gb94MHdj/M/pVqwfenwCAKqDD8SKyBiPJbIym8xyju72sE/dyACBMn5biVbnDKTlu2gfFueFRXoXEHSYSrfUQVWymTLu69DJ7iEMnLT2/MASIPsVrgFBiB/y9+y6pSran6ls15wB3lr25nGf82hihq/tuuwkGjkjkTHceqlLXyJB6tiNc9sRdxRosuY8x5HbmXXlbsXXj/NkuHC8H0gWl157j2TUPXuMqKKCPtmpj4qZ8UuWEeJPqNWBbwyF6Txb78pamONKOy3hPkkD/TPcGYYSceLyNiwrQ55qFqpntgu9p0Ufvx2t/2srw5tAE+E0HaQ9fcCBUwdsjBSU/KYAtq5JNHska9qriOMmCGKOYOpXi9zU6x+PFqRKBk3CrEhpEdR7mE95D8f7rPbNEDPwz9v1EEzGYVaCCqt5phRgTpBYvKI7Vg6gSYeTyWM6f1iQ47pVIKc4HD5BqQij81oWrg+ogHWewUNUAH2hiCOlxcctxeG3mUWmjfCBYVcXMGSWfPzZXgxusHz35tKIygVddNmdpBvBh2DItCbpvqtHPZtr4p0yagNkScQWwY3SU11l9SZz6uy/48q37RYJvfhHxvtL+ZyBM+s/LEUF4cTO/A== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MWHPR1001MB2351.namprd10.prod.outlook.com;PTR:;CAT:NONE;SFS:(39830400003)(396003)(366004)(346002)(376002)(136003)(6486002)(6506007)(7416002)(2906002)(36756003)(6512007)(26005)(86362001)(66556008)(66476007)(186003)(1076003)(6666004)(4326008)(66946007)(2616005)(44832011)(8936002)(8676002)(316002)(54906003)(38100700002)(5660300002)(508600001)(52116002)(38350700002);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: vxbVbJ2cDePuS7+ML4qL6JlmteSU/+yVKVLnnIdezk9050tOfRi78E8gOLCepcMwIg55+NCnAM02lU0jVFwDQthxB0AZ3tiUZjc+omh2Bgvu61D8dgA4HUH1wWBrwC69dft2NrbG9/P8vrhIFJIPOflD2bkkkM4GSnoAFXRZn4w/JBxOBu2FZiP6FzUGsedera2QvLoACSHE2yS94qa/VcchZrIuEDCyIcs4c56ayptjm0MG5felnf0dtXEQAD8HRfk8ypcs9jj83cMWxtjMRV0YtoFYbtHEj4NPHhTDWsqlb0k7uKPF2y8mkKoZUVJU1hxUKVFI59L1NDErnoY4IiBm/LzaJ1gUlasLquTAgfYTXmztjndM9MLrdVpWMcN4+AiZylINQwV8liiGn39v8UB4cgwsyosLiPROAQg8dYCm1S/6WlE2O20kGSKTy6dPqJKr6mDpSwose+73eZrUB/Xs5RfLaL1zVJKd8rv6WwV0DEoDpk72LlbRBaG2shiuVtq2vP7qqE4+wDCntKSeWBrHf/i2tcpnE/YpBnzHiZ/+iLfN3UW7qgYAV7d9C0gn+g+BsQhuOPCKYcaUKZRLOzdVrrFcfrjQtlPgZRwz95ccEgkS8s0pbVdHjQNLzqcbtdd5/DzNmg+V27v/1dazrsOUlmb4k2tfdDR806jf4rGSfX2K+HnMsivp+lagMdK3efyjmuJMpHatYJpEvE78gvrR2M/UuHTPuEKaa8q/3Hdb6J+a7O/p1pWdJdl8oirGITHZ+Z+S2ABJHVmIK5u56dOeps0qK99S2ga1bMmwHkphTzMGcCDyT3mfUIcsaIPe09Ip9LLL3qJhHrg/cLS9To/WQMybzFfJmcHoGdfpnQJSENMxyOtcQHx2VWMLeAOETScXMCFsMvqHA2Fq2o0DghWYOp2pLr+pHx4G46yXBvxiEQqezjec94+wJZBrkXooBzk5nEr42I8yKfIVEHqzrU24buQl33laRIBd1EY68F9bF24UacopJ66mh7eBPr5p//X4EGDs8AIhWj9xwYLs9zQnHSvUE4R1LwFkyIR89c+HwRS4DX0TV/CPX+amEd5DSw3/Ftt2yrLj0sMaQ3HlAh8Q5Mqa90hjA8n70Gkx8kXqX3ks6J23aU9ymGGq2RzQxXUqwOoWiO/u7Iy30eaOZR7Ox0+cPDQo5kpnyRINcyeQxfIzgjMf89IFZtupsx2LT7JrjIbQ5lfKQm+h+3lfRGejJgW3LWg8pi/Mt5HsWLrjXpKL/OZ10rsUIPi5/zcdn6U/YleITZgUzpEzYNuVFCZsK9bh8ehZfLHFC8cg659W3VjUZ1qXCg/9GkJZVJWmqYpwUj9xSGBEnQfUqEKY/O989Wo6OEDspm6d3I4eW5idk0bE6S0IH0GbiUbKn+ZR72CSA/UWS+a4CMZprDjAUrfGhDiTI5NUS8EYGUD7ZxRMrnl6kybM6bf+Y+IGOMwEjfgLW8j/KGTyLFx0rlQ2FpS+GlIyqBctESVxEPeN7iCtSMnalIOM10b0je+5Wbp30NzLLSdYZHKr4M7GFuD1pW+WLamqPAK4sVnDgv8M/BW0w0x6swdeylVqaa30pfr6m3gEkiAaCSF/7CMNYa5OODsbgOllNeFLXEWrM7AudhSP1S8yUo4JKUV3uLZS+tzFJFddp2QpudbumaxuPXcfnOOp7lBTJFtEPFEyLvcAEJI= X-OriginatorOrg: in-advantage.com X-MS-Exchange-CrossTenant-Network-Message-Id: fc6294ba-e5bc-4d8a-32d6-08d9c270601a X-MS-Exchange-CrossTenant-AuthSource: MWHPR1001MB2351.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Dec 2021 21:50:15.5809 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 48e842ca-fbd8-4633-a79d-0c955a7d3aae X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: MxJ9YxZfSRcz2TkpUp+A7edsWuMvOnIoDYClRA13JiPkC9lRRxX7rw4ZQ1xB3Hf8TiJ9W/87KefJc6pFnn16VN1qlvQ29mjo1C+cdh/9Q6Q= X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR10MB5633 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC The ocelot-pinctrl device is able to be utilized by ocelot_mfd. This simply enables that child driver. Signed-off-by: Colin Foster --- drivers/mfd/ocelot-core.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/mfd/ocelot-core.c b/drivers/mfd/ocelot-core.c index c67e433f467c..71e062934812 100644 --- a/drivers/mfd/ocelot-core.c +++ b/drivers/mfd/ocelot-core.c @@ -113,7 +113,22 @@ static const struct resource vsc7512_miim1_resources[] = { }, }; +static const struct resource vsc7512_pinctrl_resources[] = { + { + .start = 0x71070034, + .end = 0x7107009f, + .name = "gcb_gpio", + .flags = IORESOURCE_MEM, + }, +}; + static const struct mfd_cell vsc7512_devs[] = { + { + .name = "pinctrl-ocelot", + .of_compatible = "mscc,ocelot-pinctrl", + .num_resources = ARRAY_SIZE(vsc7512_pinctrl_resources), + .resources = vsc7512_pinctrl_resources, + }, { .name = "ocelot-miim1", .of_compatible = "mscc,ocelot-miim", @@ -164,6 +179,10 @@ int ocelot_mfd_init(struct ocelot_mfd_config *config) ret = mfd_add_devices(dev, PLATFORM_DEVID_NONE, vsc7512_devs, ARRAY_SIZE(vsc7512_devs), NULL, 0, NULL); + if (ret) { + dev_err(dev, "error adding mfd devices\n"); + return ret; + } dev_info(dev, "ocelot mfd core setup complete\n");