From patchwork Mon Dec 20 19:33:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Cercueil X-Patchwork-Id: 12688445 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 855CFC433FE for ; Mon, 20 Dec 2021 19:33:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240824AbhLTTdi (ORCPT ); Mon, 20 Dec 2021 14:33:38 -0500 Received: from aposti.net ([89.234.176.197]:38760 "EHLO aposti.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237942AbhLTTde (ORCPT ); Mon, 20 Dec 2021 14:33:34 -0500 From: Paul Cercueil To: Michael Turquette , Stephen Boyd , Rob Herring Cc: list@opendingux.net, linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Paul Cercueil Subject: [PATCH v3 1/2] dt-bindings: clk/ingenic: Add MDMA and BDMA clocks Date: Mon, 20 Dec 2021 19:33:18 +0000 Message-Id: <20211220193319.114974-2-paul@crapouillou.net> In-Reply-To: <20211220193319.114974-1-paul@crapouillou.net> References: <20211220193319.114974-1-paul@crapouillou.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The Ingenic JZ4760 and JZ4770 both have an extra DMA core named BDMA dedicated to the NAND and BCH controller, but which can also do memory-to-memory transfers. The JZ4760 additionally has a DMA core named MDMA dedicated to memory-to-memory transfers. The programming manual for the JZ4770 does have a bit for a MDMA clock, but does not seem to have the hardware wired in. Add macros for the MDMA and BDMA clocks to the dt-bindings include files, so that they can be used within Device Tree files. Signed-off-by: Paul Cercueil Acked-by: Rob Herring --- Notes: v3: New patch include/dt-bindings/clock/ingenic,jz4760-cgu.h | 2 ++ include/dt-bindings/clock/ingenic,jz4770-cgu.h | 1 + 2 files changed, 3 insertions(+) diff --git a/include/dt-bindings/clock/ingenic,jz4760-cgu.h b/include/dt-bindings/clock/ingenic,jz4760-cgu.h index 4bb2e19c4743..9fb04ebac6de 100644 --- a/include/dt-bindings/clock/ingenic,jz4760-cgu.h +++ b/include/dt-bindings/clock/ingenic,jz4760-cgu.h @@ -50,5 +50,7 @@ #define JZ4760_CLK_LPCLK_DIV 41 #define JZ4760_CLK_TVE 42 #define JZ4760_CLK_LPCLK 43 +#define JZ4760_CLK_MDMA 44 +#define JZ4760_CLK_BDMA 45 #endif /* __DT_BINDINGS_CLOCK_JZ4760_CGU_H__ */ diff --git a/include/dt-bindings/clock/ingenic,jz4770-cgu.h b/include/dt-bindings/clock/ingenic,jz4770-cgu.h index d68a7695a1f8..0b475e8ae321 100644 --- a/include/dt-bindings/clock/ingenic,jz4770-cgu.h +++ b/include/dt-bindings/clock/ingenic,jz4770-cgu.h @@ -54,5 +54,6 @@ #define JZ4770_CLK_OTG_PHY 45 #define JZ4770_CLK_EXT512 46 #define JZ4770_CLK_RTC 47 +#define JZ4770_CLK_BDMA 48 #endif /* __DT_BINDINGS_CLOCK_JZ4770_CGU_H__ */ From patchwork Mon Dec 20 19:33:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Cercueil X-Patchwork-Id: 12688447 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A711DC433F5 for ; Mon, 20 Dec 2021 19:33:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240850AbhLTTdp (ORCPT ); Mon, 20 Dec 2021 14:33:45 -0500 Received: from aposti.net ([89.234.176.197]:38784 "EHLO aposti.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240847AbhLTTdo (ORCPT ); Mon, 20 Dec 2021 14:33:44 -0500 From: Paul Cercueil To: Michael Turquette , Stephen Boyd , Rob Herring Cc: list@opendingux.net, linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Paul Cercueil Subject: [PATCH v3 2/2] clk: ingenic: Add MDMA and BDMA clocks Date: Mon, 20 Dec 2021 19:33:19 +0000 Message-Id: <20211220193319.114974-3-paul@crapouillou.net> In-Reply-To: <20211220193319.114974-1-paul@crapouillou.net> References: <20211220193319.114974-1-paul@crapouillou.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The Ingenic JZ4760 and JZ4770 both have an extra DMA core named BDMA dedicated to the NAND and BCH controller, but which can also do memory-to-memory transfers. The JZ4760 additionally has a DMA core named MDMA dedicated to memory-to-memory transfers. The programming manual for the JZ4770 does have a bit for a MDMA clock, but does not seem to have the hardware wired in. Add the BDMA and MDMA clocks to the JZ4760 CGU code, and the BDMA clock to the JZ4770 code, so that the BDMA and MDMA controllers can be used. Signed-off-by: Paul Cercueil --- Notes: v2: No change v3: Split off dt-bindings include changes to its own patch drivers/clk/ingenic/jz4760-cgu.c | 10 ++++++++++ drivers/clk/ingenic/jz4770-cgu.c | 5 +++++ 2 files changed, 15 insertions(+) diff --git a/drivers/clk/ingenic/jz4760-cgu.c b/drivers/clk/ingenic/jz4760-cgu.c index 080d492ac95c..8fdd383560fb 100644 --- a/drivers/clk/ingenic/jz4760-cgu.c +++ b/drivers/clk/ingenic/jz4760-cgu.c @@ -313,6 +313,16 @@ static const struct ingenic_cgu_clk_info jz4760_cgu_clocks[] = { .parents = { JZ4760_CLK_H2CLK, }, .gate = { CGU_REG_CLKGR0, 21 }, }, + [JZ4760_CLK_MDMA] = { + "mdma", CGU_CLK_GATE, + .parents = { JZ4760_CLK_HCLK, }, + .gate = { CGU_REG_CLKGR0, 25 }, + }, + [JZ4760_CLK_BDMA] = { + "bdma", CGU_CLK_GATE, + .parents = { JZ4760_CLK_HCLK, }, + .gate = { CGU_REG_CLKGR1, 0 }, + }, [JZ4760_CLK_I2C0] = { "i2c0", CGU_CLK_GATE, .parents = { JZ4760_CLK_EXT, }, diff --git a/drivers/clk/ingenic/jz4770-cgu.c b/drivers/clk/ingenic/jz4770-cgu.c index 8c6c1208f462..7ef91257630e 100644 --- a/drivers/clk/ingenic/jz4770-cgu.c +++ b/drivers/clk/ingenic/jz4770-cgu.c @@ -329,6 +329,11 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = { .parents = { JZ4770_CLK_H2CLK, }, .gate = { CGU_REG_CLKGR0, 21 }, }, + [JZ4770_CLK_BDMA] = { + "bdma", CGU_CLK_GATE, + .parents = { JZ4770_CLK_H2CLK, }, + .gate = { CGU_REG_CLKGR1, 0 }, + }, [JZ4770_CLK_I2C0] = { "i2c0", CGU_CLK_GATE, .parents = { JZ4770_CLK_EXT, },