From patchwork Tue Dec 21 14:14:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 12689797 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A702DC433F5 for ; Tue, 21 Dec 2021 14:56:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238731AbhLUO4z (ORCPT ); Tue, 21 Dec 2021 09:56:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52106 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238704AbhLUO4v (ORCPT ); Tue, 21 Dec 2021 09:56:51 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EAD14C06173F; Tue, 21 Dec 2021 06:56:50 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 842A861659; Tue, 21 Dec 2021 14:56:50 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 32573C36AF1; Tue, 21 Dec 2021 14:56:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1640098610; bh=iOm7uhs+2+Y00wU5942hoH5Ypg2VEv9NlwRanu6QquM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Y8JGCyWQiEo0FeYt4MhAer93WIjm9rkmEHCBYUc8ETBTMpv/I4bjQYagB28X+ul+I M1PIAjpdaHrzVIwIQo1DqMgkaZ9x+QYGvAD81STAzNYi0CJ0otvX4ibGz2rtuFTR4K q+eKkEwbS8Z5yCrxNZFnaETERxtPGjmSfyXiJVklLiwerDdl4CA6GevhgLdXNu7ujo xRacVza+ntAs+QBFDve3C0lNiA0jydBC+3gPKWa6O8kzgYH9k4RoAxjOgKpuqar53Q sb2iO1vF83AD3ZCExX709WzVHaxAE8tvDI5Go6+vGhmvLolr+0umW301WJmS330AbU TPe+OyEra98iQ== Received: by pali.im (Postfix) id 24FCE284D; Tue, 21 Dec 2021 15:18:12 +0100 (CET) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: "Thomas Petazzoni" , "Lorenzo Pieralisi" , "Rob Herring" , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , "Bjorn Helgaas" , =?utf-8?q?Marek_Beh=C3=BAn?= Cc: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 01/11] =?utf-8?q?MAINTAINERS=3A_Add_Pali_Roh=C3=A1r_as_pci-m?= =?utf-8?q?vebu=2Ec_maintainer?= Date: Tue, 21 Dec 2021 15:14:45 +0100 Message-Id: <20211221141455.30011-2-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20211221141455.30011-1-pali@kernel.org> References: <20211221141455.30011-1-pali@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Signed-off-by: Pali Rohár Acked-by: Thomas Petazzoni --- I discussed with Thomas and he ask me for taking maintenance of pci-mvebu.c driver. --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 7a2345ce8521..24527789d933 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14617,6 +14617,7 @@ F: drivers/pci/controller/mobiveil/pcie-mobiveil* PCI DRIVER FOR MVEBU (Marvell Armada 370 and Armada XP SOC support) M: Thomas Petazzoni +M: Pali Rohár L: linux-pci@vger.kernel.org L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained From patchwork Tue Dec 21 14:14:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 12689791 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 15A70C433F5 for ; Tue, 21 Dec 2021 14:56:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238712AbhLUO4w (ORCPT ); Tue, 21 Dec 2021 09:56:52 -0500 Received: from ams.source.kernel.org ([145.40.68.75]:38056 "EHLO ams.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238697AbhLUO4u (ORCPT ); Tue, 21 Dec 2021 09:56:50 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 30FBAB8172E; Tue, 21 Dec 2021 14:56:49 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C3909C36AEB; Tue, 21 Dec 2021 14:56:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1640098607; bh=QKua9WgN49q+Sz5vAXpEygIK8zQDaGYklGosEd8el0I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=j5qIL7hJn3PnjTem3tU/WrYcC63sG+E+IRLEbKfcTjR6eWwyPt5HjKX2wVlSd7bef uS848wT/gLFOaD+gKrT8xgw0odIKfoRfbMF8N6tSPqA7yHG/U9GyByATnwNYGYqe1m XA/IVlAYvQIo40XfBAbTsABWtNFSvbyfOdiAnnG55CSQOiFtCx8N7noa/xEJ5T4cNp 37sJnygGc6btafthtB4APDxgYXgUHbwmNIg6agxxu89rXHKIIc6raP/fhaXQkGJdBI BdLXjf506rc0cJZWkVFN6/4zOx9nREEmueILrigu2sYkF+g3CAEzqhK8R8dXZF1JFt oa6FaoRoHKg6Q== Received: by pali.im (Postfix) id A428F284E; Tue, 21 Dec 2021 15:18:12 +0100 (CET) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: "Thomas Petazzoni" , "Lorenzo Pieralisi" , "Rob Herring" , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , "Bjorn Helgaas" , =?utf-8?q?Marek_Beh=C3=BAn?= Cc: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 02/11] PCI: pci-bridge-emul: Make struct pci_bridge_emul_ops as const Date: Tue, 21 Dec 2021 15:14:46 +0100 Message-Id: <20211221141455.30011-3-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20211221141455.30011-1-pali@kernel.org> References: <20211221141455.30011-1-pali@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org It is read-only constant structure, so properly mark it with const keyword. Signed-off-by: Pali Rohár Acked-by: Thomas Petazzoni --- drivers/pci/controller/pci-aardvark.c | 2 +- drivers/pci/controller/pci-mvebu.c | 2 +- drivers/pci/pci-bridge-emul.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 62fc55f2ed40..1fa6fe1e022a 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -928,7 +928,7 @@ advk_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge, } } -static struct pci_bridge_emul_ops advk_pci_bridge_emul_ops = { +static const struct pci_bridge_emul_ops advk_pci_bridge_emul_ops = { .read_base = advk_pci_bridge_emul_base_conf_read, .write_base = advk_pci_bridge_emul_base_conf_write, .read_pcie = advk_pci_bridge_emul_pcie_conf_read, diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c index 68aa94a258ff..2ecc1ab12249 100644 --- a/drivers/pci/controller/pci-mvebu.c +++ b/drivers/pci/controller/pci-mvebu.c @@ -709,7 +709,7 @@ mvebu_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge, } } -static struct pci_bridge_emul_ops mvebu_pci_bridge_emul_ops = { +static const struct pci_bridge_emul_ops mvebu_pci_bridge_emul_ops = { .read_base = mvebu_pci_bridge_emul_base_conf_read, .write_base = mvebu_pci_bridge_emul_base_conf_write, .read_pcie = mvebu_pci_bridge_emul_pcie_conf_read, diff --git a/drivers/pci/pci-bridge-emul.h b/drivers/pci/pci-bridge-emul.h index 49bbd37ee318..0690b6369755 100644 --- a/drivers/pci/pci-bridge-emul.h +++ b/drivers/pci/pci-bridge-emul.h @@ -112,7 +112,7 @@ struct pci_bridge_reg_behavior; struct pci_bridge_emul { struct pci_bridge_emul_conf conf; struct pci_bridge_emul_pcie_conf pcie_conf; - struct pci_bridge_emul_ops *ops; + const struct pci_bridge_emul_ops *ops; struct pci_bridge_reg_behavior *pci_regs_behavior; struct pci_bridge_reg_behavior *pcie_cap_regs_behavior; void *data; From patchwork Tue Dec 21 14:14:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 12689801 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F96CC433EF for ; Tue, 21 Dec 2021 14:56:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238744AbhLUO44 (ORCPT ); Tue, 21 Dec 2021 09:56:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52112 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238707AbhLUO4w (ORCPT ); Tue, 21 Dec 2021 09:56:52 -0500 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CAD9AC061574; Tue, 21 Dec 2021 06:56:51 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id DC886B8171C; Tue, 21 Dec 2021 14:56:49 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5C20AC36AF8; Tue, 21 Dec 2021 14:56:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1640098608; bh=JtEZRkg2SAAc4D3UAOmtCOS7Vb63QZjN6gULYttb+eQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=k4GjjhHppEj0/3o4n9w43Kb+FxOrJnc96/qoZoZrd0Sy+P9/K+w8rx2216ax6WUeB Ef7gu+sI00xV00V9wMjCAepI1BTloSMxfLRzSIcw4Nud/B0aMjLATIpJCOlPTj2bB1 4oQKnJSUrlDmkI8nTnYPg1gh0SnJGIHDu9jDwdd8zfaLE6ihLQiDU7UYkTONMsI5ro 56JQw55A6z6wpkZ8o1IRyi5nP9fRn0kWnsczsP6NT/R1y0GNnQLFjENX1LjyIVAyVH wRlXxCoXXHId8fILqFrtapXu+apIrJTXY663toSB8ODBKRn4FMH9jpR5gKmHlhyF4I 3fiN951ufB9Gg== Received: by pali.im (Postfix) id 330152857; Tue, 21 Dec 2021 15:18:13 +0100 (CET) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: "Thomas Petazzoni" , "Lorenzo Pieralisi" , "Rob Herring" , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , "Bjorn Helgaas" , =?utf-8?q?Marek_Beh=C3=BAn?= Cc: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 03/11] PCI: pci-bridge-emul: Rename PCI_BRIDGE_EMUL_NO_PREFETCHABLE_BAR to PCI_BRIDGE_EMUL_NO_PREFMEM_FORWARD Date: Tue, 21 Dec 2021 15:14:47 +0100 Message-Id: <20211221141455.30011-4-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20211221141455.30011-1-pali@kernel.org> References: <20211221141455.30011-1-pali@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org This flag describe whether PCI bridge supports forwarding of prefetchable memory requests in given range between primary and secondary buses. It does not specify if bridge has support for prefetchable memory BAR (moreover this pci-bridge-emul.c driver does not provide support for BARs). So change name of this flag to be less misleading. Signed-off-by: Pali Rohár --- drivers/pci/controller/pci-mvebu.c | 2 +- drivers/pci/pci-bridge-emul.c | 2 +- drivers/pci/pci-bridge-emul.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c index 2ecc1ab12249..2e10ade660a1 100644 --- a/drivers/pci/controller/pci-mvebu.c +++ b/drivers/pci/controller/pci-mvebu.c @@ -747,7 +747,7 @@ static int mvebu_pci_bridge_emul_init(struct mvebu_pcie_port *port) bridge->data = port; bridge->ops = &mvebu_pci_bridge_emul_ops; - return pci_bridge_emul_init(bridge, PCI_BRIDGE_EMUL_NO_PREFETCHABLE_BAR); + return pci_bridge_emul_init(bridge, PCI_BRIDGE_EMUL_NO_PREFMEM_FORWARD); } static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys) diff --git a/drivers/pci/pci-bridge-emul.c b/drivers/pci/pci-bridge-emul.c index 79b947528455..432b1bec2e22 100644 --- a/drivers/pci/pci-bridge-emul.c +++ b/drivers/pci/pci-bridge-emul.c @@ -373,7 +373,7 @@ int pci_bridge_emul_init(struct pci_bridge_emul *bridge, ~(BIT(10) << 16); } - if (flags & PCI_BRIDGE_EMUL_NO_PREFETCHABLE_BAR) { + if (flags & PCI_BRIDGE_EMUL_NO_PREFMEM_FORWARD) { bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].ro = ~0; bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].rw = 0; } diff --git a/drivers/pci/pci-bridge-emul.h b/drivers/pci/pci-bridge-emul.h index 0690b6369755..88877ebefbac 100644 --- a/drivers/pci/pci-bridge-emul.h +++ b/drivers/pci/pci-bridge-emul.h @@ -120,7 +120,7 @@ struct pci_bridge_emul { }; enum { - PCI_BRIDGE_EMUL_NO_PREFETCHABLE_BAR = BIT(0), + PCI_BRIDGE_EMUL_NO_PREFMEM_FORWARD = BIT(0), }; int pci_bridge_emul_init(struct pci_bridge_emul *bridge, From patchwork Tue Dec 21 14:14:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 12689783 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1365C433EF for ; Tue, 21 Dec 2021 14:56:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238692AbhLUO4t (ORCPT ); Tue, 21 Dec 2021 09:56:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52092 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238683AbhLUO4t (ORCPT ); Tue, 21 Dec 2021 09:56:49 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 147CCC061574; Tue, 21 Dec 2021 06:56:49 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id A50D46163B; Tue, 21 Dec 2021 14:56:48 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id DCBD8C36AEC; Tue, 21 Dec 2021 14:56:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1640098608; bh=zB+LhZA/mMW0h3avW6Wp5dGr4zLsowcd1TtLd2uAcf4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qe+GY47Bi2ExCyR8FnxN8h/z5Qne05/DB2EqjLqhav+pZYXofgYtxbVawiyZVBkUJ XLtkour7BtiJCZn8yRjgJhKwIT7t1XBUtb+JZuLmGqq0l1R43+zE46RpLtrpFgPQ+9 N4FmYDfTJG7hBHEfYEmQGTFMJyQ67U3SvcJKU9cV4mFat6ZH9XixU8HB2e7G97i99L N84P2NufEzDV8cRoeb3xYwat6oRypLmBADusIENzwIFlPiaLSk4SzJwudmWPQPfhAI sOI2/NOE9Wt+uzX/WgWjarVYN5+CQpiH3gFyksd18Y+o9DVTOPwzW9qbDt9QazkmcV zDSjdorzUBZnA== Received: by pali.im (Postfix) id AA7A62862; Tue, 21 Dec 2021 15:18:13 +0100 (CET) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: "Thomas Petazzoni" , "Lorenzo Pieralisi" , "Rob Herring" , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , "Bjorn Helgaas" , =?utf-8?q?Marek_Beh=C3=BAn?= Cc: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 04/11] PCI: pci-bridge-emul: Add support for new flag PCI_BRIDGE_EMUL_NO_IO_FORWARD Date: Tue, 21 Dec 2021 15:14:48 +0100 Message-Id: <20211221141455.30011-5-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20211221141455.30011-1-pali@kernel.org> References: <20211221141455.30011-1-pali@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Like PCI_BRIDGE_EMUL_NO_PREFMEM_FORWARD, this new flag specifies that emulated PCI bridge does not support forwarding of IO requests in given range between primary and secondary buses. This flag should be used as argument for pci_bridge_emul_init() for hardware setup without IO support. Setting this flag cause that IO base and limit registers are read-only. Signed-off-by: Pali Rohár --- drivers/pci/pci-bridge-emul.c | 9 +++++++++ drivers/pci/pci-bridge-emul.h | 1 + 2 files changed, 10 insertions(+) diff --git a/drivers/pci/pci-bridge-emul.c b/drivers/pci/pci-bridge-emul.c index 432b1bec2e22..033bbeb99176 100644 --- a/drivers/pci/pci-bridge-emul.c +++ b/drivers/pci/pci-bridge-emul.c @@ -378,6 +378,15 @@ int pci_bridge_emul_init(struct pci_bridge_emul *bridge, bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].rw = 0; } + if (flags & PCI_BRIDGE_EMUL_NO_IO_FORWARD) { + bridge->pci_regs_behavior[PCI_COMMAND / 4].ro |= PCI_COMMAND_IO; + bridge->pci_regs_behavior[PCI_COMMAND / 4].rw &= ~PCI_COMMAND_IO; + bridge->pci_regs_behavior[PCI_IO_BASE / 4].ro |= GENMASK(15, 0); + bridge->pci_regs_behavior[PCI_IO_BASE / 4].rw &= ~GENMASK(15, 0); + bridge->pci_regs_behavior[PCI_IO_BASE_UPPER16 / 4].ro = ~0; + bridge->pci_regs_behavior[PCI_IO_BASE_UPPER16 / 4].rw = 0; + } + return 0; } EXPORT_SYMBOL_GPL(pci_bridge_emul_init); diff --git a/drivers/pci/pci-bridge-emul.h b/drivers/pci/pci-bridge-emul.h index 88877ebefbac..ab33609c598b 100644 --- a/drivers/pci/pci-bridge-emul.h +++ b/drivers/pci/pci-bridge-emul.h @@ -121,6 +121,7 @@ struct pci_bridge_emul { enum { PCI_BRIDGE_EMUL_NO_PREFMEM_FORWARD = BIT(0), + PCI_BRIDGE_EMUL_NO_IO_FORWARD = BIT(1), }; int pci_bridge_emul_init(struct pci_bridge_emul *bridge, From patchwork Tue Dec 21 14:14:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 12689795 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9EB3C433EF for ; Tue, 21 Dec 2021 14:56:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238726AbhLUO4y (ORCPT ); Tue, 21 Dec 2021 09:56:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52104 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238702AbhLUO4v (ORCPT ); Tue, 21 Dec 2021 09:56:51 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D534EC061574; Tue, 21 Dec 2021 06:56:50 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 6BF9C61655; Tue, 21 Dec 2021 14:56:50 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 19D1EC36AEF; Tue, 21 Dec 2021 14:56:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1640098610; bh=XitsvLC/8XJT/51VWhTuEEqkPH1X2y3/JU2pM5KluWc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KBE0gq6r3q7Oi/WAoEZr4Exsun8OSvQOwhBAN857k6nbdRJtP4xpJ66+RDIy2R7F9 xeYCVrhtcgPSe1QcW8zGPr3ew48V+hV16V4vVs6LBhXItDTxWMpdRkMqq0To44uIxU a0+CuifReh9juMvMcqlpsP1JwDkeo2kQA/ee0n/u2v0ylAxpwq2TjjHQXA9ke6aphy 8NBXa59vFBJ0gF1gHqHla/mSV15m71yUVbOHemj7mCMnaTPOso70bLUmG7yhaj0j6x vtjzmbE2sAgzPDi29Idaxdn7zl9Kf3sWayzlqxWVBjHKVwliiYCl6oNKQ1VQkSSPhC YAN9yru8u4OQw== Received: by pali.im (Postfix) id 4574228D5; Tue, 21 Dec 2021 15:18:14 +0100 (CET) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: "Thomas Petazzoni" , "Lorenzo Pieralisi" , "Rob Herring" , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , "Bjorn Helgaas" , =?utf-8?q?Marek_Beh=C3=BAn?= Cc: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 05/11] PCI: mvebu: Add help string for CONFIG_PCI_MVEBU option Date: Tue, 21 Dec 2021 15:14:49 +0100 Message-Id: <20211221141455.30011-6-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20211221141455.30011-1-pali@kernel.org> References: <20211221141455.30011-1-pali@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org There is no description for CONFIG_PCI_MVEBU option. Add it. Signed-off-by: Pali Rohár Acked-by: Thomas Petazzoni --- drivers/pci/controller/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig index 67189bcd5d89..534b446f2cf0 100644 --- a/drivers/pci/controller/Kconfig +++ b/drivers/pci/controller/Kconfig @@ -10,6 +10,10 @@ config PCI_MVEBU depends on ARM depends on OF select PCI_BRIDGE_EMUL + help + Add support for Marvell EBU PCIe controller. This PCIe controller + is used on 32-bit Marvell ARM SoCs: Dove, Kirkwood, Armada 370, + Armada XP, Armada 375, Armada 38x and Armada 39x. config PCI_AARDVARK tristate "Aardvark PCIe controller" From patchwork Tue Dec 21 14:14:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 12689803 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 80A10C433F5 for ; Tue, 21 Dec 2021 14:57:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238719AbhLUO4x (ORCPT ); Tue, 21 Dec 2021 09:56:53 -0500 Received: from dfw.source.kernel.org ([139.178.84.217]:43892 "EHLO dfw.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238687AbhLUO4t (ORCPT ); Tue, 21 Dec 2021 09:56:49 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 4BCC66163F; Tue, 21 Dec 2021 14:56:49 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5FE3BC36AFA; Tue, 21 Dec 2021 14:56:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1640098608; bh=JIc9DZvQtZV6dPDjTKJepvnaF8txTQekZ8XLf4Z30Bo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WAJWQLvJT5LTxmJCJ6lxdGPpgtcSiq13Vvn+OQ5USyhM8xP1qSBZp4Pz4A8K4FCJE X8odFUY10I0i/nP+UWT+BUeM33aeiDlqdPUHDqsFZr8ywu9ZxgWdfe68wmO7obOWQu RB84ejBxaZdmkhjMSlcUsJVoAmWExRewDLY+oiUsV7y4ujH7JHvl3xZ9B0lcSq1OMP 6VfOq5B8X1iwdJjd4IWvaBJMZM1Ol0w6FJ9J0tHnyoi7aETmZnndm8lN70MxpRtoQ6 WeJcsiDQ2I+szF4iHrsDWi+N69W18F9joP3aylG7iHWLLOlGt2feGPN9TzsEiQYILZ A7V6Luv50I41w== Received: by pali.im (Postfix) id B0C792A85; Tue, 21 Dec 2021 15:18:14 +0100 (CET) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: "Thomas Petazzoni" , "Lorenzo Pieralisi" , "Rob Herring" , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , "Bjorn Helgaas" , =?utf-8?q?Marek_Beh=C3=BAn?= Cc: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 06/11] PCI: mvebu: Remove duplicate nports assignment Date: Tue, 21 Dec 2021 15:14:50 +0100 Message-Id: <20211221141455.30011-7-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20211221141455.30011-1-pali@kernel.org> References: <20211221141455.30011-1-pali@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Member pcie->nports is initialized to correct value before the previous for-loop. There is not need to initialize it more times. Signed-off-by: Pali Rohár Acked-by: Thomas Petazzoni --- drivers/pci/controller/pci-mvebu.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c index 2e10ade660a1..016f709b3067 100644 --- a/drivers/pci/controller/pci-mvebu.c +++ b/drivers/pci/controller/pci-mvebu.c @@ -1337,8 +1337,6 @@ static int mvebu_pcie_probe(struct platform_device *pdev) mvebu_pcie_set_local_bus_nr(port, 0); } - pcie->nports = i; - bridge->sysdata = pcie; bridge->ops = &mvebu_pcie_ops; bridge->align_resource = mvebu_pcie_align_resource; From patchwork Tue Dec 21 14:14:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 12689799 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9229DC4332F for ; Tue, 21 Dec 2021 14:56:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238740AbhLUO4z (ORCPT ); Tue, 21 Dec 2021 09:56:55 -0500 Received: from ams.source.kernel.org ([145.40.68.75]:38112 "EHLO ams.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238705AbhLUO4v (ORCPT ); Tue, 21 Dec 2021 09:56:51 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 79036B81734; Tue, 21 Dec 2021 14:56:50 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8733CC36AFC; Tue, 21 Dec 2021 14:56:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1640098608; bh=rDql2jTgdjUK7vxWWT90TbqSpfdmGCwQYg2uMRYgxk4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JL5FYR4sMP/bh/ow18GHbvdUQXmwddzhZGO+eaP89DdwPZQO+RwnxLN6PmUJv0CJp 6KDDeldkyYxYqoDNFpDsota9248R5dciFsBMs1TFCWgbPoHcfyVtzLgLhEtIyadFnb qTHm+RE9yA2KqecqmeOp7y5Aha2hwpkcba0uEh4SVUFT9PjC6emw+1rMlxfn70sk7F uY2hPVdQCoF+wHK2FVJyj/IDqKlsQwmLPX4QAWQzVy5XAovXHeVf2jlbF4zdIaMn3z 3aHUsyE7BwnBfpGCNPLBITWf7gy3bnj/LpwQj0p2fL+D4OGpna3hIdQTymT/erMRMO uXBPp/V7z7UFw== Received: by pali.im (Postfix) id 28DF92A9D; Tue, 21 Dec 2021 15:18:15 +0100 (CET) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: "Thomas Petazzoni" , "Lorenzo Pieralisi" , "Rob Herring" , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , "Bjorn Helgaas" , =?utf-8?q?Marek_Beh=C3=BAn?= Cc: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 07/11] PCI: mvebu: Set PCI_BRIDGE_EMUL_NO_IO_FORWARD when IO is unsupported Date: Tue, 21 Dec 2021 15:14:51 +0100 Message-Id: <20211221141455.30011-8-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20211221141455.30011-1-pali@kernel.org> References: <20211221141455.30011-1-pali@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org This will make PCI bridge to return zeros when accessing IO base and limit registers, as required by PCIe base specification. This allows to remove adhoc checks around mvebu_pcie_handle_iobase_change() function for unsupported IO ranges. PCI_BRIDGE_EMUL_NO_IO_FORWARD ensures that there will be no non-zeros write to IO registers when IO is not supported. Signed-off-by: Pali Rohár --- drivers/pci/controller/pci-mvebu.c | 29 ++++++++++------------------- 1 file changed, 10 insertions(+), 19 deletions(-) diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c index 016f709b3067..551f55af5226 100644 --- a/drivers/pci/controller/pci-mvebu.c +++ b/drivers/pci/controller/pci-mvebu.c @@ -438,12 +438,6 @@ static int mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port) return mvebu_pcie_set_window(port, port->io_target, port->io_attr, &desired, &port->iowin); - if (!mvebu_has_ioport(port)) { - dev_WARN(&port->pcie->pdev->dev, - "Attempt to set IO when IO is disabled\n"); - return -EOPNOTSUPP; - } - /* * We read the PCI-to-PCI bridge emulated registers, and * calculate the base address and size of the address decoding @@ -599,24 +593,18 @@ mvebu_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge, switch (reg) { case PCI_COMMAND: - if (!mvebu_has_ioport(port)) { - conf->command = cpu_to_le16( - le16_to_cpu(conf->command) & ~PCI_COMMAND_IO); - new &= ~PCI_COMMAND_IO; - } - mvebu_writel(port, new, PCIE_CMD_OFF); break; case PCI_IO_BASE: - if ((mask & 0xffff) && mvebu_pcie_handle_iobase_change(port)) { + if ((mask & 0xffff) && mvebu_has_ioport(port) && + mvebu_pcie_handle_iobase_change(port)) { /* On error disable IO range */ conf->iobase &= ~0xf0; conf->iolimit &= ~0xf0; + conf->iobase |= 0xf0; conf->iobaseupper = cpu_to_le16(0x0000); conf->iolimitupper = cpu_to_le16(0x0000); - if (mvebu_has_ioport(port)) - conf->iobase |= 0xf0; } break; @@ -630,14 +618,14 @@ mvebu_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge, break; case PCI_IO_BASE_UPPER16: - if (mvebu_pcie_handle_iobase_change(port)) { + if (mvebu_has_ioport(port) && + mvebu_pcie_handle_iobase_change(port)) { /* On error disable IO range */ conf->iobase &= ~0xf0; conf->iolimit &= ~0xf0; + conf->iobase |= 0xf0; conf->iobaseupper = cpu_to_le16(0x0000); conf->iolimitupper = cpu_to_le16(0x0000); - if (mvebu_has_ioport(port)) - conf->iobase |= 0xf0; } break; @@ -722,6 +710,7 @@ static const struct pci_bridge_emul_ops mvebu_pci_bridge_emul_ops = { */ static int mvebu_pci_bridge_emul_init(struct mvebu_pcie_port *port) { + unsigned int bridge_flags = PCI_BRIDGE_EMUL_NO_PREFMEM_FORWARD; struct pci_bridge_emul *bridge = &port->bridge; u32 pcie_cap = mvebu_readl(port, PCIE_CAP_PCIEXP); u8 pcie_cap_ver = ((pcie_cap >> 16) & PCI_EXP_FLAGS_VERS); @@ -735,6 +724,8 @@ static int mvebu_pci_bridge_emul_init(struct mvebu_pcie_port *port) /* We support 32 bits I/O addressing */ bridge->conf.iobase = PCI_IO_RANGE_TYPE_32; bridge->conf.iolimit = PCI_IO_RANGE_TYPE_32; + } else { + bridge_flags |= PCI_BRIDGE_EMUL_NO_IO_FORWARD; } /* @@ -747,7 +738,7 @@ static int mvebu_pci_bridge_emul_init(struct mvebu_pcie_port *port) bridge->data = port; bridge->ops = &mvebu_pci_bridge_emul_ops; - return pci_bridge_emul_init(bridge, PCI_BRIDGE_EMUL_NO_PREFMEM_FORWARD); + return pci_bridge_emul_init(bridge, bridge_flags); } static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys) From patchwork Tue Dec 21 14:14:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 12689793 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EE91AC43219 for ; Tue, 21 Dec 2021 14:56:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238711AbhLUO4x (ORCPT ); Tue, 21 Dec 2021 09:56:53 -0500 Received: from ams.source.kernel.org ([145.40.68.75]:38048 "EHLO ams.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238695AbhLUO4u (ORCPT ); Tue, 21 Dec 2021 09:56:50 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 2623BB81729; Tue, 21 Dec 2021 14:56:49 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C184FC36AEA; Tue, 21 Dec 2021 14:56:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1640098607; bh=5rM1AcOc3PS1pgnZALHKjdSUqdfRbqAmu6E9C1EEBE4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OhzGxqWh6aWOldNXcCKillJ/acf4fW+XGebyC4jeQS6NYKAZAYbvjP1OiT2tTDABb m8gMySo1+HQa65b+yZZXGCT5ygv05Fkba1DtmWwpTC3awDhsm6jmPc1zw5KtrTddbx 8EkeJZoPS0em1h8D8jdRJveJVZPZgQ9LtA1Tfg7A4Mc0FAZ2XrfepLfWFtkVTfE54p +KMF6hZUmu6JxgAljueKO3HSD9J+2WdrY4DUYq3SgKpwXql1LVgziTgdZyYh0kZZlj k0zh0hVKG9JSTJ3b3aGOHAH7RvKZiULo7pp5Lcu3jHr02cODSfO3J47cXJ0vIy8Otb L7l/UqCwMOfGA== Received: by pali.im (Postfix) id AB41A2AAD; Tue, 21 Dec 2021 15:18:15 +0100 (CET) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: "Thomas Petazzoni" , "Lorenzo Pieralisi" , "Rob Herring" , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , "Bjorn Helgaas" , =?utf-8?q?Marek_Beh=C3=BAn?= Cc: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 08/11] PCI: mvebu: Properly initialize vendor, device and revision of emulated bridge Date: Tue, 21 Dec 2021 15:14:52 +0100 Message-Id: <20211221141455.30011-9-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20211221141455.30011-1-pali@kernel.org> References: <20211221141455.30011-1-pali@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org With this change also PCI vendor id is read from mvebu registers. Signed-off-by: Pali Rohár --- drivers/pci/controller/pci-mvebu.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c index 551f55af5226..94ef00b6d697 100644 --- a/drivers/pci/controller/pci-mvebu.c +++ b/drivers/pci/controller/pci-mvebu.c @@ -712,13 +712,14 @@ static int mvebu_pci_bridge_emul_init(struct mvebu_pcie_port *port) { unsigned int bridge_flags = PCI_BRIDGE_EMUL_NO_PREFMEM_FORWARD; struct pci_bridge_emul *bridge = &port->bridge; + u32 dev_id = mvebu_readl(port, PCIE_DEV_ID_OFF); + u32 dev_rev = mvebu_readl(port, PCIE_DEV_REV_OFF); u32 pcie_cap = mvebu_readl(port, PCIE_CAP_PCIEXP); u8 pcie_cap_ver = ((pcie_cap >> 16) & PCI_EXP_FLAGS_VERS); - bridge->conf.vendor = PCI_VENDOR_ID_MARVELL; - bridge->conf.device = mvebu_readl(port, PCIE_DEV_ID_OFF) >> 16; - bridge->conf.class_revision = - mvebu_readl(port, PCIE_DEV_REV_OFF) & 0xff; + bridge->conf.vendor = cpu_to_le16(dev_id & 0xffff); + bridge->conf.device = cpu_to_le16(dev_id >> 16); + bridge->conf.class_revision = cpu_to_le32(dev_rev & 0xff); if (mvebu_has_ioport(port)) { /* We support 32 bits I/O addressing */ From patchwork Tue Dec 21 14:14:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 12689787 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3A90FC4332F for ; Tue, 21 Dec 2021 14:56:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238680AbhLUO4v (ORCPT ); Tue, 21 Dec 2021 09:56:51 -0500 Received: from dfw.source.kernel.org ([139.178.84.217]:43888 "EHLO dfw.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238685AbhLUO4t (ORCPT ); Tue, 21 Dec 2021 09:56:49 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 469F46163B; Tue, 21 Dec 2021 14:56:49 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5E567C36AF9; Tue, 21 Dec 2021 14:56:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1640098608; bh=uG8b6cgDUIxA5J6r1/yrflQam4I3mKXv7eeo14u0x7E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XGuXWjzNpMsCbwhwKBwyE485895PsET52JbD9yqC3D5PnhIJSk/dFZ+OT8FNR9/+k 9vDIAHnIn8dMOucAw+JyLKvVis6LmmZEASLg9lf0gJdgAb1DMZ3dekkeDwnxGDzs0V NjsJenxBxiY7fns0WUATrQs5UO8RVEcKTNBt/659LsIZjEv+J8OEs8xs9icKXZ6Ojh w9DEE6SpE1MOHdSHBx3BZo4JOJ7NhxTgK/zULyUxYFppmWXZtWWcMXgQo84FT+nZUv lM5WtdmBCtc5EiDRSEFJrqgh8jSdiyVFoQEGqleDy8iliixQH9UyhoVxoHoP7O3gJy b8i41UhlatYWQ== Received: by pali.im (Postfix) id 381AF2AB3; Tue, 21 Dec 2021 15:18:16 +0100 (CET) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: "Thomas Petazzoni" , "Lorenzo Pieralisi" , "Rob Herring" , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , "Bjorn Helgaas" , =?utf-8?q?Marek_Beh=C3=BAn?= Cc: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 09/11] PCI: mvebu: Update comment for PCI_EXP_LNKCAP register on emulated bridge Date: Tue, 21 Dec 2021 15:14:53 +0100 Message-Id: <20211221141455.30011-10-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20211221141455.30011-1-pali@kernel.org> References: <20211221141455.30011-1-pali@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Reason for clearing this bit is because mvebu hw returns incorrectly this bit set to 1. Signed-off-by: Pali Rohár --- drivers/pci/controller/pci-mvebu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c index 94ef00b6d697..1aac65977b97 100644 --- a/drivers/pci/controller/pci-mvebu.c +++ b/drivers/pci/controller/pci-mvebu.c @@ -546,8 +546,8 @@ mvebu_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge, case PCI_EXP_LNKCAP: /* - * PCIe requires the clock power management capability to be - * hard-wired to zero for downstream ports + * PCIe requires that the Clock Power Management capability bit + * is hard-wired to zero for downstream ports but HW returns 1. */ *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP) & ~PCI_EXP_LNKCAP_CLKPM; From patchwork Tue Dec 21 14:14:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 12689789 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4FE0EC433EF for ; Tue, 21 Dec 2021 14:56:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238709AbhLUO4w (ORCPT ); Tue, 21 Dec 2021 09:56:52 -0500 Received: from ams.source.kernel.org ([145.40.68.75]:38040 "EHLO ams.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238696AbhLUO4u (ORCPT ); Tue, 21 Dec 2021 09:56:50 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 1C523B8171F; Tue, 21 Dec 2021 14:56:49 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id BEDB9C36AE9; Tue, 21 Dec 2021 14:56:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1640098607; bh=xxyZnGOuH63mToYeFJtMrqvVZxip4BN1x7ap3lhZeHA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=idtSM6rMG+OrXmXorvmrw2fZYYLnc+eEStSm/wS7s1kslRoLHbzSL6Sty8lOYWrnq L6ET6iT/H+SBW6t2KdOrIqQI2Ne6+WU4s5sKaZF03lRZD3BfxbacrSlD2vLtd0/SR6 YdB5MWPvwMBivOufHymMy83vf27qs9XjPseSXHzaB7T/wGzBq8+ndkeJPoQk8qZpzB fqNdiCauJAN3khpLKyNQAq0vmA6G/N13omI+xyLEGV7Uk3J3S5CkW+FVscRVcQ4BHx 0GVWk2kO30/4Zk8SFBLQB7+KOSPx63p4TlkwGzQTosuG5SxLqPVKbaukSpjhQ9Aon4 l0uPHjpF1C3Ag== Received: by pali.im (Postfix) id AAFD62ABF; Tue, 21 Dec 2021 15:18:16 +0100 (CET) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: "Thomas Petazzoni" , "Lorenzo Pieralisi" , "Rob Herring" , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , "Bjorn Helgaas" , =?utf-8?q?Marek_Beh=C3=BAn?= Cc: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 10/11] PCI: mvebu: Update comment for PCI_EXP_LNKCTL register on emulated bridge Date: Tue, 21 Dec 2021 15:14:54 +0100 Message-Id: <20211221141455.30011-11-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20211221141455.30011-1-pali@kernel.org> References: <20211221141455.30011-1-pali@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Logic and code for clearing PCI_EXP_LNKCTL_CLKREQ_EN bit is correct, but comment describing it is misleading. PCI_EXP_LNKCTL_CLKREQ_EN bit should be hardwired to zero but mvebu hw allows to change it. Signed-off-by: Pali Rohár --- drivers/pci/controller/pci-mvebu.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c index 1aac65977b97..dffa330de174 100644 --- a/drivers/pci/controller/pci-mvebu.c +++ b/drivers/pci/controller/pci-mvebu.c @@ -663,10 +663,9 @@ mvebu_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge, case PCI_EXP_LNKCTL: /* - * If we don't support CLKREQ, we must ensure that the - * CLKREQ enable bit always reads zero. Since we haven't - * had this capability, and it's dependent on board wiring, - * disable it for the time being. + * PCIe requires that the Enable Clock Power Management bit + * is hard-wired to zero for downstream ports but HW allows + * to change it. */ new &= ~PCI_EXP_LNKCTL_CLKREQ_EN; From patchwork Tue Dec 21 14:14:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 12689785 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42BADC433F5 for ; Tue, 21 Dec 2021 14:56:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238701AbhLUO4u (ORCPT ); Tue, 21 Dec 2021 09:56:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52098 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238698AbhLUO4t (ORCPT ); Tue, 21 Dec 2021 09:56:49 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B4A61C061574; Tue, 21 Dec 2021 06:56:49 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 4DBB761642; Tue, 21 Dec 2021 14:56:49 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 86465C36AFB; Tue, 21 Dec 2021 14:56:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1640098608; bh=GN5jKZEodCfeZz6pv/k5h1jk1jhWdZrxDcJsdMUC48E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AzSpo5/3vAT9c3YzIf6tWgRlrYUm0hDpposd0f4C7oA+n5ZQWEyMwdgt+aFKQb1ii f2mzl8K0g4yEZ+IAd2BxAdR69TT2a2xA/fRULXXaG+P2oyy7mGSt5l9wW43yWa9/l4 LjvyAWHeDW7uKM8diu851K6taRP3OcMYugnnPzeZGElH61nY6N+FsuRNY9eKTA+CO9 5efYElAR1xwawFQJjpMPytbw4mHAu+walgbPqQ2m0N0Y2WOCWsNrvxXobH3MBSHGg2 fiMppdAiyeBg1GY4Wtn5BMfqmVXyutId4PtxlhJmJWd+aVBEwBlRHA03vP9Bm5dgMM GrdQ6r1U4fo/w== Received: by pali.im (Postfix) id 222672AC1; Tue, 21 Dec 2021 15:18:17 +0100 (CET) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: "Thomas Petazzoni" , "Lorenzo Pieralisi" , "Rob Herring" , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , "Bjorn Helgaas" , =?utf-8?q?Marek_Beh=C3=BAn?= Cc: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 11/11] PCI: mvebu: Fix reporting Data Link Layer Link Active on emulated bridge Date: Tue, 21 Dec 2021 15:14:55 +0100 Message-Id: <20211221141455.30011-12-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20211221141455.30011-1-pali@kernel.org> References: <20211221141455.30011-1-pali@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add support for reporting PCI_EXP_LNKSTA_DLLLA bit in Link Control register on emulated bridge via PCIE_STAT_OFF reg. Function mvebu_pcie_link_up() already parses this register and returns if Data Link is Active or not. Also correctly indicate DLLLA capability via PCI_EXP_LNKCAP_DLLLARC bit in Link Control Capability register which is required for reporting DLLLA bit. Signed-off-by: Pali Rohár --- drivers/pci/controller/pci-mvebu.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c index dffa330de174..a075ba26cff1 100644 --- a/drivers/pci/controller/pci-mvebu.c +++ b/drivers/pci/controller/pci-mvebu.c @@ -548,13 +548,18 @@ mvebu_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge, /* * PCIe requires that the Clock Power Management capability bit * is hard-wired to zero for downstream ports but HW returns 1. + * Additionally enable Data Link Layer Link Active Reporting + * Capable bit as DL_Active indication is provided too. */ - *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP) & - ~PCI_EXP_LNKCAP_CLKPM; + *value = (mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP) & + ~PCI_EXP_LNKCAP_CLKPM) | PCI_EXP_LNKCAP_DLLLARC; break; case PCI_EXP_LNKCTL: - *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL); + /* DL_Active indication is provided via PCIE_STAT_OFF */ + *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL) | + (mvebu_pcie_link_up(port) ? + (PCI_EXP_LNKSTA_DLLLA << 16) : 0); break; case PCI_EXP_SLTCTL: