From patchwork Wed Dec 22 13:45:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 12691663 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C17FEC433FE for ; Wed, 22 Dec 2021 13:53:46 +0000 (UTC) Received: from localhost ([::1]:49680 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n023t-0000Z3-RM for qemu-devel@archiver.kernel.org; Wed, 22 Dec 2021 08:53:45 -0500 Received: from eggs.gnu.org ([209.51.188.92]:39710) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n01wB-0008Jw-RK; Wed, 22 Dec 2021 08:45:47 -0500 Received: from [2607:f8b0:4864:20::733] (port=45916 helo=mail-qk1-x733.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n01w9-0004Zz-8T; Wed, 22 Dec 2021 08:45:47 -0500 Received: by mail-qk1-x733.google.com with SMTP id e16so2270176qkl.12; Wed, 22 Dec 2021 05:45:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0tPWroKf8+zwMZ81fuDdcOR55HvCkDzSknyMhykBjvk=; b=XS2uP2iBEdBvT64xBshNOvgwVVkmzSMw5IC+XAvWwALvALbOzpFPyEogIG67u/EfnG Sh8ATA3dXS2x8EjurYsbXXyJi3oFydeZzhs9M8iljBmrKPw5b8LOERsOXKkIU86dpHZb hNdxV84Zp2GEx67qrfnwEKsO/UfLYqE4na7SHU6/AaCAFHTiUHiBj4aNIx2FkCq96xJ1 6TS4GLPEfz6nPyiujAZYgvTN2/+fgyEZgzkF+sRFcHBRji2HQfIlon9BJN5GGs2HE7eY ww9/k+b7aNPpQV13dVq+iKl4pkuBn2Knplv3Pf5bFrDY3U0X0lxYWJBgwHqvjgZqGpQL Di8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0tPWroKf8+zwMZ81fuDdcOR55HvCkDzSknyMhykBjvk=; b=14jinDBWozVojtFM9HnqImbmPfg8853PbZRO4/t6HyhWnlICZygVJe5iLSe+T/pfvf VfrfuEIZBHVYEUUyoNXJ4jsRlXVArdHsKrL3ZPXSvEutCbtSuJCnFJMagDt4LCAG4qn3 Lu9uyHrABggMHTQKmF0auAbmHUeSVvzGZxRjpVA7k1loOKFYIXA++E8ni+37yeeMOXGQ NZ0xRS/8gdmvTwljOFCUlVNDaGdem29wbaSrUVsnkPPc5dfIV+IcPDJmIJHvW/Psigrv McA/KaGrlVkiD3tECbWmPbCHtZ+eYQJjXHZ7PBiFb1KLupgRgvSiBR+FMYS8uBLWJEm7 AFPg== X-Gm-Message-State: AOAM532zn28NYGAHm5/TdIL7uFYtMB/9mjjiE9KgPq4lSOZ44cxtNPO6 SDNS7kE1d5Ml0nyUVubqRnSLfnTt6hg= X-Google-Smtp-Source: ABdhPJzN0G/LM5/TfAlzFWwWTcbfExMZxBT7k8ESARyyAeKe668hVWWpNDRO6re2gt2Zb+HgWFBTuQ== X-Received: by 2002:a05:620a:e13:: with SMTP id y19mr1924102qkm.112.1640180743782; Wed, 22 Dec 2021 05:45:43 -0800 (PST) Received: from rekt.ibmuc.com ([170.239.133.233]) by smtp.gmail.com with ESMTPSA id j16sm1757054qtx.92.2021.12.22.05.45.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Dec 2021 05:45:43 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH 1/8] target/ppc: introduce power8-pmu-insn-cnt.c.inc Date: Wed, 22 Dec 2021 10:45:13 -0300 Message-Id: <20211222134520.587877-2-danielhb413@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211222134520.587877-1-danielhb413@gmail.com> References: <20211222134520.587877-1-danielhb413@gmail.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::733 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::733; envelope-from=danielhb413@gmail.com; helo=mail-qk1-x733.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, Daniel Henrique Barboza , qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" We're going to add a significant amount of TCG ops code for instruction counting, eventually getting rid of the 'helper_insn_inc' helper entirely. Create a new file to avoid putting even more stuff on the already crowded target/ppc/translate.c. Signed-off-by: Daniel Henrique Barboza --- target/ppc/power8-pmu-insn-cnt.c.inc | 54 ++++++++++++++++++++++++++++ target/ppc/translate.c | 44 ++--------------------- 2 files changed, 56 insertions(+), 42 deletions(-) create mode 100644 target/ppc/power8-pmu-insn-cnt.c.inc diff --git a/target/ppc/power8-pmu-insn-cnt.c.inc b/target/ppc/power8-pmu-insn-cnt.c.inc new file mode 100644 index 0000000000..2febbcc27e --- /dev/null +++ b/target/ppc/power8-pmu-insn-cnt.c.inc @@ -0,0 +1,54 @@ +/* + * PMU instruction counting for TCG IBM POWER chips + * + * Copyright IBM Corp. 2021 + * + * Authors: + * Daniel Henrique Barboza + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#if defined(TARGET_PPC64) +static void pmu_count_insns(DisasContext *ctx) +{ + /* + * Do not bother calling the helper if the PMU isn't counting + * instructions. + */ + if (!ctx->pmu_insn_cnt) { + return; + } + + #if !defined(CONFIG_USER_ONLY) + /* + * The PMU insns_inc() helper stops the internal PMU timer if a + * counter overflows happens. In that case, if the guest is + * running with icount and we do not handle it beforehand, + * the helper can trigger a 'bad icount read'. + */ + gen_icount_io_start(ctx); + + gen_helper_insns_inc(cpu_env, tcg_constant_i32(ctx->base.num_insns)); +#else + /* + * User mode can read (but not write) PMC5 and start/stop + * the PMU via MMCR0_FC. In this case just increment + * PMC5 with base.num_insns. + */ + TCGv t0 = tcg_temp_new(); + + gen_load_spr(t0, SPR_POWER_PMC5); + tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); + gen_store_spr(SPR_POWER_PMC5, t0); + + tcg_temp_free(t0); +#endif /* #if !defined(CONFIG_USER_ONLY) */ +} +#else +static void pmu_count_insns(DisasContext *ctx) +{ + return; +} +#endif /* #if defined(TARGET_PPC64) */ diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 114456148c..44773bc6cd 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -4183,48 +4183,8 @@ static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) #endif } -#if defined(TARGET_PPC64) -static void pmu_count_insns(DisasContext *ctx) -{ - /* - * Do not bother calling the helper if the PMU isn't counting - * instructions. - */ - if (!ctx->pmu_insn_cnt) { - return; - } - - #if !defined(CONFIG_USER_ONLY) - /* - * The PMU insns_inc() helper stops the internal PMU timer if a - * counter overflows happens. In that case, if the guest is - * running with icount and we do not handle it beforehand, - * the helper can trigger a 'bad icount read'. - */ - gen_icount_io_start(ctx); - - gen_helper_insns_inc(cpu_env, tcg_constant_i32(ctx->base.num_insns)); -#else - /* - * User mode can read (but not write) PMC5 and start/stop - * the PMU via MMCR0_FC. In this case just increment - * PMC5 with base.num_insns. - */ - TCGv t0 = tcg_temp_new(); - - gen_load_spr(t0, SPR_POWER_PMC5); - tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); - gen_store_spr(SPR_POWER_PMC5, t0); - - tcg_temp_free(t0); -#endif /* #if !defined(CONFIG_USER_ONLY) */ -} -#else -static void pmu_count_insns(DisasContext *ctx) -{ - return; -} -#endif /* #if defined(TARGET_PPC64) */ +/* For pmu_count_insns */ +#include "target/ppc/power8-pmu-insn-cnt.c.inc" static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) { From patchwork Wed Dec 22 13:45:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 12691661 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B0F9DC433EF for ; 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Wed, 22 Dec 2021 05:45:45 -0800 (PST) Received: from rekt.ibmuc.com ([170.239.133.233]) by smtp.gmail.com with ESMTPSA id j16sm1757054qtx.92.2021.12.22.05.45.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Dec 2021 05:45:45 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH 2/8] target/ppc/power8-pmu-insn-cnt: add pmu_inc_pmc5() Date: Wed, 22 Dec 2021 10:45:14 -0300 Message-Id: <20211222134520.587877-3-danielhb413@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211222134520.587877-1-danielhb413@gmail.com> References: <20211222134520.587877-1-danielhb413@gmail.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::735 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::735; envelope-from=danielhb413@gmail.com; helo=mail-qk1-x735.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, Daniel Henrique Barboza , qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The first PMC to be counted using exclusively TCG ops will be PMC5. pmu_inc_pmc5() will always be called inside pmu_count_insns() since it's able to avoid incrementing PMC5 by checking for MMCR0_FC56 beforehand. Note that we've already checked that MMCR0_FC is cleared at this point via ctx->pmu_insn_cnt being set. Signed-off-by: Daniel Henrique Barboza --- target/ppc/power8-pmu-insn-cnt.c.inc | 42 ++++++++++++++++++++++------ 1 file changed, 34 insertions(+), 8 deletions(-) diff --git a/target/ppc/power8-pmu-insn-cnt.c.inc b/target/ppc/power8-pmu-insn-cnt.c.inc index 2febbcc27e..c683573104 100644 --- a/target/ppc/power8-pmu-insn-cnt.c.inc +++ b/target/ppc/power8-pmu-insn-cnt.c.inc @@ -10,6 +10,38 @@ * See the COPYING file in the top-level directory. */ +#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) +/* + * Increments PMC5 if MMCR0_FC is cleared. + */ +static void pmu_inc_pmc5(DisasContext *ctx) +{ + TCGv t0, t1; + TCGLabel *l_skip_pmc; + + /* + * If MMCR0_FC56 is set skip PMC5 increment. + */ + l_skip_pmc = gen_new_label(); + + t0 = tcg_temp_new(); + gen_load_spr(t0, SPR_POWER_MMCR0); + + tcg_gen_andi_tl(t0, t0, MMCR0_FC56); + tcg_gen_brcondi_tl(TCG_COND_EQ, t0, MMCR0_FC56, l_skip_pmc); + + t1 = tcg_temp_new(); + gen_load_spr(t1, SPR_POWER_PMC5); + tcg_gen_addi_tl(t1, t1, ctx->base.num_insns); + gen_store_spr(SPR_POWER_PMC5, t1); + + gen_set_label(l_skip_pmc); + + tcg_temp_free(t0); + tcg_temp_free(t1); +} +#endif /* #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ + #if defined(TARGET_PPC64) static void pmu_count_insns(DisasContext *ctx) { @@ -22,15 +54,9 @@ static void pmu_count_insns(DisasContext *ctx) } #if !defined(CONFIG_USER_ONLY) - /* - * The PMU insns_inc() helper stops the internal PMU timer if a - * counter overflows happens. In that case, if the guest is - * running with icount and we do not handle it beforehand, - * the helper can trigger a 'bad icount read'. - */ - gen_icount_io_start(ctx); - gen_helper_insns_inc(cpu_env, tcg_constant_i32(ctx->base.num_insns)); + pmu_inc_pmc5(ctx); + #else /* * User mode can read (but not write) PMC5 and start/stop From patchwork Wed Dec 22 13:45:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 12691659 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9E481C433EF for ; Wed, 22 Dec 2021 13:49:20 +0000 (UTC) Received: from localhost ([::1]:41874 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n01zb-0003XG-ML for qemu-devel@archiver.kernel.org; Wed, 22 Dec 2021 08:49:19 -0500 Received: from eggs.gnu.org ([209.51.188.92]:39754) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n01wF-0008U1-4C; Wed, 22 Dec 2021 08:45:51 -0500 Received: from [2607:f8b0:4864:20::830] (port=44584 helo=mail-qt1-x830.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n01wD-0004bn-Bz; Wed, 22 Dec 2021 08:45:50 -0500 Received: by mail-qt1-x830.google.com with SMTP id a1so1896799qtx.11; Wed, 22 Dec 2021 05:45:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/4vnV+34LS00hqGjUJM9oubs2x+ordorJ8i9lKjwwzU=; b=CqnA/epjN4IinCH2DtwfrsqXIhpNsqSj0jsWIYP+YrdusVJ/ihf7RhJWWtsuhI0vkw zzXnb276g4vo+HAp+s4Z1orq/GJMM5E7eKMmllLuLFBrkAeVLJo2zXiJU7+lbp799khA HGV9Xo70lY1DxXA7vl4095X8HnufYhbsNOHiFHF7x0TD3MIQjqAqc19QYASDCPTPZ5EM lU8/hCVpcjwTTn/PY+Atvo97nsfLYTUSEuKfXy+uF9bTUMDGrS9o+4UaCBcJok0nCJt4 EuEvDISO7j1ljlp6hD/tVUrhVHsGusUHR5q/n/8Jh8T4iUvtWH9pzwWqQfhXEt/RkU86 TuFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/4vnV+34LS00hqGjUJM9oubs2x+ordorJ8i9lKjwwzU=; b=2hOaOTiB6D8Mz6pNvmQg5Z5QmmafGYrZeHGzGWagYNHhUQs/O99Ia7Eu5bLW/uYSSP LMouQ1YkVLoOmZIIpWA6UoPkEWxyUEmQHoHBgcn5IQnO37F1YC4+goBQiSG8c7Hqc3nX kdDTqZDA3o7UOKnNGT/SrnEUT++0wWLKmA22v+WyHQZ5hIz5HVNCzycWHTWfZAvDJ6zW zkQP6EKGsjBbtqsx0ubzIUs7G6n5iEKGlErWXf0jEC6fdq5oEhOF4KD5M9zKZzR86q2q eLBoUdX6woudAxzgaqc2ps0XH63f76oh60BNFd4xfzKXrsVKp52tDZsgBdemPQ/LXhBZ owWw== X-Gm-Message-State: AOAM533dD2dd8dXEqNvyBawOoMQzTuXBhCBM90Q09c4lHv7PHSkIWz+Y eVJQiI53/xKJbOQg6YxC1C0Qk4Npn+A= X-Google-Smtp-Source: ABdhPJyyt1zS8H0jo3kNmYJAqKMgU26NTG1nX52xmQVdpXa9hBf4CsHU69u9g2BxPWsUnwLQneghgg== X-Received: by 2002:ac8:5a0d:: with SMTP id n13mr2065776qta.555.1640180748074; Wed, 22 Dec 2021 05:45:48 -0800 (PST) Received: from rekt.ibmuc.com ([170.239.133.233]) by smtp.gmail.com with ESMTPSA id j16sm1757054qtx.92.2021.12.22.05.45.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Dec 2021 05:45:47 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH 3/8] target/ppc/power8-pmu-insn-cnt: add pmu_inc_pmc1() Date: Wed, 22 Dec 2021 10:45:15 -0300 Message-Id: <20211222134520.587877-4-danielhb413@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211222134520.587877-1-danielhb413@gmail.com> References: <20211222134520.587877-1-danielhb413@gmail.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::830 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::830; envelope-from=danielhb413@gmail.com; helo=mail-qt1-x830.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, Daniel Henrique Barboza , qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" pmu_inc_pmc1() will use TCG Ops to increment the PMC1 counter when it's counting PM_INST_CMPL events. At this moment we're supporting two values of MMCR1_PMC1SEL for this event: 0x02 and 0xFE. This function, and all the soon to be added PMC2-4 insn count functions, does not check if MMCR0_FC14 is set. This check is done inside pmu_count_insns, which will allow us to skip all PMC1-4 instruction count functions at once if the proper conditions aren't met. Signed-off-by: Daniel Henrique Barboza --- target/ppc/power8-pmu-insn-cnt.c.inc | 76 ++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/target/ppc/power8-pmu-insn-cnt.c.inc b/target/ppc/power8-pmu-insn-cnt.c.inc index c683573104..3661fb0022 100644 --- a/target/ppc/power8-pmu-insn-cnt.c.inc +++ b/target/ppc/power8-pmu-insn-cnt.c.inc @@ -11,6 +11,56 @@ */ #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) + +#define MMCR1_PMC1_INS_CNT 0x02000000 +#define MMCR1_PMC1_INS_CNT2 0xFE000000 + +/* + * Increments PMC1 checking if MMCR1_PMC1SEL has one of the following + * events: + * + * - 0x02: implementation dependent PM_INSN_CMPL + * - 0xFE: ISA architected PM_INSN_CMPL + * + * This function assumes that MMCR0_FC14 is cleared. + */ +static void pmu_inc_pmc1(DisasContext *ctx) +{ + TCGv t0, t1, t2; + TCGLabel *l_inc_pmc; + TCGLabel *l_skip_pmc; + + /* + * PMC1 will be incremented if MMCR1_PMC1SEL = 0x2 + * or 0xFE. + */ + l_inc_pmc = gen_new_label(); + l_skip_pmc = gen_new_label(); + + t0 = tcg_temp_new(); + gen_load_spr(t0, SPR_POWER_MMCR1); + tcg_gen_andi_tl(t0, t0, MMCR1_PMC1_INS_CNT); + tcg_gen_brcondi_tl(TCG_COND_EQ, t0, MMCR1_PMC1_INS_CNT, l_inc_pmc); + + t1 = tcg_temp_new(); + gen_load_spr(t1, SPR_POWER_MMCR1); + tcg_gen_andi_tl(t1, t1, MMCR1_PMC1_INS_CNT2); + tcg_gen_brcondi_tl(TCG_COND_NE, t1, MMCR1_PMC1_INS_CNT2, l_skip_pmc); + + gen_set_label(l_inc_pmc); + + t2 = tcg_temp_new(); + gen_load_spr(t2, SPR_POWER_PMC1); + tcg_gen_addi_tl(t2, t2, ctx->base.num_insns); + gen_store_spr(SPR_POWER_PMC1, t2); + + gen_set_label(l_skip_pmc); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(t2); +} + /* * Increments PMC5 if MMCR0_FC is cleared. */ @@ -55,8 +105,34 @@ static void pmu_count_insns(DisasContext *ctx) #if !defined(CONFIG_USER_ONLY) + TCGv t_mmcr0, t_mmcr1; + TCGLabel *l_skip_pmc14; + pmu_inc_pmc5(ctx); + /* + * Skip PMC1-4 increment if: + * - MMCR0_FC14 is set OR + * - MMCR1 is cleared + */ + l_skip_pmc14 = gen_new_label(); + + t_mmcr0 = tcg_temp_new(); + gen_load_spr(t_mmcr0, SPR_POWER_MMCR0); + tcg_gen_andi_tl(t_mmcr0, t_mmcr0, MMCR0_FC14); + tcg_gen_brcondi_tl(TCG_COND_EQ, t_mmcr0, MMCR0_FC14, l_skip_pmc14); + + t_mmcr1 = tcg_temp_new(); + gen_load_spr(t_mmcr1, SPR_POWER_MMCR1); + tcg_gen_brcondi_tl(TCG_COND_EQ, t_mmcr1, 0x0, l_skip_pmc14); + + pmu_inc_pmc1(ctx); + + gen_set_label(l_skip_pmc14); + + tcg_temp_free(t_mmcr0); + tcg_temp_free(t_mmcr1); + #else /* * User mode can read (but not write) PMC5 and start/stop From patchwork Wed Dec 22 13:45:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 12691665 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BAC9DC433EF for ; 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Wed, 22 Dec 2021 05:45:50 -0800 (PST) Received: from rekt.ibmuc.com ([170.239.133.233]) by smtp.gmail.com with ESMTPSA id j16sm1757054qtx.92.2021.12.22.05.45.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Dec 2021 05:45:49 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH 4/8] target/ppc/power8-pmu-insn-cnt: add pmu_inc_pmc2() Date: Wed, 22 Dec 2021 10:45:16 -0300 Message-Id: <20211222134520.587877-5-danielhb413@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211222134520.587877-1-danielhb413@gmail.com> References: <20211222134520.587877-1-danielhb413@gmail.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::736 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::736; envelope-from=danielhb413@gmail.com; helo=mail-qk1-x736.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, Daniel Henrique Barboza , qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Add PMC2 PM_INST_CMPL count with TCG Ops. Signed-off-by: Daniel Henrique Barboza --- target/ppc/power8-pmu-insn-cnt.c.inc | 32 ++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/target/ppc/power8-pmu-insn-cnt.c.inc b/target/ppc/power8-pmu-insn-cnt.c.inc index 3661fb0022..be0e2dc3b5 100644 --- a/target/ppc/power8-pmu-insn-cnt.c.inc +++ b/target/ppc/power8-pmu-insn-cnt.c.inc @@ -14,6 +14,7 @@ #define MMCR1_PMC1_INS_CNT 0x02000000 #define MMCR1_PMC1_INS_CNT2 0xFE000000 +#define MMCR1_PMC2_INS_CNT 0x00020000 /* * Increments PMC1 checking if MMCR1_PMC1SEL has one of the following @@ -61,6 +62,36 @@ static void pmu_inc_pmc1(DisasContext *ctx) tcg_temp_free(t2); } +/* + * Increments PMC2 checking if MMCR1_PMC2SEL = 0x02 + * (PM_INST_CMPL event). + * + * This function assumes that MMCR0_FC14 is cleared. + */ +static void pmu_inc_pmc2(DisasContext *ctx) +{ + TCGv t0, t1; + TCGLabel *l_skip_pmc; + + /* PMC2 will be incremented if MMCR1_PMC2SEL is 0x2 */ + l_skip_pmc = gen_new_label(); + + t0 = tcg_temp_new(); + gen_load_spr(t0, SPR_POWER_MMCR1); + tcg_gen_andi_tl(t0, t0, MMCR1_PMC2_INS_CNT); + tcg_gen_brcondi_tl(TCG_COND_NE, t0, MMCR1_PMC2_INS_CNT, l_skip_pmc); + + t1 = tcg_temp_new(); + gen_load_spr(t1, SPR_POWER_PMC2); + tcg_gen_addi_tl(t1, t1, ctx->base.num_insns); + gen_store_spr(SPR_POWER_PMC2, t1); + + gen_set_label(l_skip_pmc); + + tcg_temp_free(t0); + tcg_temp_free(t1); +} + /* * Increments PMC5 if MMCR0_FC is cleared. */ @@ -127,6 +158,7 @@ static void pmu_count_insns(DisasContext *ctx) tcg_gen_brcondi_tl(TCG_COND_EQ, t_mmcr1, 0x0, l_skip_pmc14); pmu_inc_pmc1(ctx); + pmu_inc_pmc2(ctx); gen_set_label(l_skip_pmc14); From patchwork Wed Dec 22 13:45:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 12691673 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C596AC433F5 for ; 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Wed, 22 Dec 2021 05:45:52 -0800 (PST) Received: from rekt.ibmuc.com ([170.239.133.233]) by smtp.gmail.com with ESMTPSA id j16sm1757054qtx.92.2021.12.22.05.45.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Dec 2021 05:45:51 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH 5/8] target/ppc/power8-pmu-insn-cnt: add pmu_inc_pmc3() Date: Wed, 22 Dec 2021 10:45:17 -0300 Message-Id: <20211222134520.587877-6-danielhb413@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211222134520.587877-1-danielhb413@gmail.com> References: <20211222134520.587877-1-danielhb413@gmail.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::731 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::731; envelope-from=danielhb413@gmail.com; helo=mail-qk1-x731.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, Daniel Henrique Barboza , qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Add PMC3 PM_INST_CMPL count with TCG Ops. Signed-off-by: Daniel Henrique Barboza --- target/ppc/power8-pmu-insn-cnt.c.inc | 32 ++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/target/ppc/power8-pmu-insn-cnt.c.inc b/target/ppc/power8-pmu-insn-cnt.c.inc index be0e2dc3b5..a84d688503 100644 --- a/target/ppc/power8-pmu-insn-cnt.c.inc +++ b/target/ppc/power8-pmu-insn-cnt.c.inc @@ -15,6 +15,7 @@ #define MMCR1_PMC1_INS_CNT 0x02000000 #define MMCR1_PMC1_INS_CNT2 0xFE000000 #define MMCR1_PMC2_INS_CNT 0x00020000 +#define MMCR1_PMC3_INS_CNT 0x00000200 /* * Increments PMC1 checking if MMCR1_PMC1SEL has one of the following @@ -92,6 +93,36 @@ static void pmu_inc_pmc2(DisasContext *ctx) tcg_temp_free(t1); } +/* + * Increments PMC3 checking if MMCR1_PMC3SEL = 0x02 + * (PM_INST_CMPL event). + * + * This function assumes that MMCR0_FC14 is cleared. + */ +static void pmu_inc_pmc3(DisasContext *ctx) +{ + TCGv t0, t1; + TCGLabel *l_skip_pmc; + + /* PMC3 will be incremented if MMCR1_PMC3SEL is 0x2 */ + l_skip_pmc = gen_new_label(); + + t0 = tcg_temp_new(); + gen_load_spr(t0, SPR_POWER_MMCR1); + tcg_gen_andi_tl(t0, t0, MMCR1_PMC3_INS_CNT); + tcg_gen_brcondi_tl(TCG_COND_NE, t0, MMCR1_PMC3_INS_CNT, l_skip_pmc); + + t1 = tcg_temp_new(); + gen_load_spr(t1, SPR_POWER_PMC3); + tcg_gen_addi_tl(t1, t1, ctx->base.num_insns); + gen_store_spr(SPR_POWER_PMC3, t1); + + gen_set_label(l_skip_pmc); + + tcg_temp_free(t0); + tcg_temp_free(t1); +} + /* * Increments PMC5 if MMCR0_FC is cleared. */ @@ -159,6 +190,7 @@ static void pmu_count_insns(DisasContext *ctx) pmu_inc_pmc1(ctx); pmu_inc_pmc2(ctx); + pmu_inc_pmc3(ctx); gen_set_label(l_skip_pmc14); From patchwork Wed Dec 22 13:45:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 12691671 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E1B5DC433EF for ; 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Wed, 22 Dec 2021 05:45:54 -0800 (PST) Received: from rekt.ibmuc.com ([170.239.133.233]) by smtp.gmail.com with ESMTPSA id j16sm1757054qtx.92.2021.12.22.05.45.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Dec 2021 05:45:54 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH 6/8] target/ppc/power8-pmu-insn-cnt.c: add pmu_inc_pmc4() Date: Wed, 22 Dec 2021 10:45:18 -0300 Message-Id: <20211222134520.587877-7-danielhb413@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211222134520.587877-1-danielhb413@gmail.com> References: <20211222134520.587877-1-danielhb413@gmail.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::f2d (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::f2d; envelope-from=danielhb413@gmail.com; helo=mail-qv1-xf2d.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, Daniel Henrique Barboza , qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" pmu_inc_pmc4() will count both PM_INST_CMPL and PM_RUN_INST_CMPL. Signed-off-by: Daniel Henrique Barboza --- target/ppc/power8-pmu-insn-cnt.c.inc | 60 ++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/target/ppc/power8-pmu-insn-cnt.c.inc b/target/ppc/power8-pmu-insn-cnt.c.inc index a84d688503..d3dd6d4685 100644 --- a/target/ppc/power8-pmu-insn-cnt.c.inc +++ b/target/ppc/power8-pmu-insn-cnt.c.inc @@ -16,6 +16,8 @@ #define MMCR1_PMC1_INS_CNT2 0xFE000000 #define MMCR1_PMC2_INS_CNT 0x00020000 #define MMCR1_PMC3_INS_CNT 0x00000200 +#define MMCR1_PMC4_INS_CNT 0x00000002 +#define MMCR1_PMC4_INS_LATCH_CNT 0x000000FA /* * Increments PMC1 checking if MMCR1_PMC1SEL has one of the following @@ -123,6 +125,63 @@ static void pmu_inc_pmc3(DisasContext *ctx) tcg_temp_free(t1); } +/* + * Increments PMC4 checking if MMCR1_PMC4SEL has one of the following + * events: + * + * - 0x02: implementation dependent PM_INST_CMPL + * - 0xFE: ISA architected PM_RUN_INST_CMPL (run latch) + * + * This function assumes that MMCR0_FC14 is cleared. + */ +static void pmu_inc_pmc4(DisasContext *ctx) +{ + TCGv t0, t1, t2, t3; + TCGLabel *l_inc_pmc; + TCGLabel *l_skip_pmc; + + /* + * PMC4 will be incremented if MMCR1_PMC4SEL = 0x2 + * or 0xFA. For 0xFA (INSN_RUN_LATCH) we need to do an + * extra check with SPR_CTRL & CTRL_RUN. + */ + l_inc_pmc = gen_new_label(); + l_skip_pmc = gen_new_label(); + + t0 = tcg_temp_new(); + gen_load_spr(t0, SPR_POWER_MMCR1); + tcg_gen_andi_tl(t0, t0, MMCR1_PMC4_INS_CNT); + tcg_gen_brcondi_tl(TCG_COND_EQ, t0, MMCR1_PMC4_INS_CNT, l_inc_pmc); + + t1 = tcg_temp_new(); + gen_load_spr(t1, SPR_POWER_MMCR1); + tcg_gen_andi_tl(t1, t1, MMCR1_PMC4_INS_LATCH_CNT); + tcg_gen_brcondi_tl(TCG_COND_NE, t1, MMCR1_PMC4_INS_LATCH_CNT, l_skip_pmc); + + /* + * MMCR1_PMC4SEL is 0xFA at this point. Check if we have + * the run latch, skip if we don't. + */ + t2 = tcg_temp_new(); + gen_load_spr(t2, SPR_CTRL); + tcg_gen_andi_tl(t2, t2, CTRL_RUN); + tcg_gen_brcondi_tl(TCG_COND_NE, t2, CTRL_RUN, l_skip_pmc); + + gen_set_label(l_inc_pmc); + + t3 = tcg_temp_new(); + gen_load_spr(t3, SPR_POWER_PMC4); + tcg_gen_addi_tl(t3, t3, ctx->base.num_insns); + gen_store_spr(SPR_POWER_PMC4, t3); + + gen_set_label(l_skip_pmc); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(t2); + tcg_temp_free(t3); +} + /* * Increments PMC5 if MMCR0_FC is cleared. */ @@ -191,6 +250,7 @@ static void pmu_count_insns(DisasContext *ctx) pmu_inc_pmc1(ctx); pmu_inc_pmc2(ctx); pmu_inc_pmc3(ctx); + pmu_inc_pmc4(ctx); gen_set_label(l_skip_pmc14); From patchwork Wed Dec 22 13:45:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 12691669 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DB112C433EF for ; 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Wed, 22 Dec 2021 05:45:56 -0800 (PST) Received: from rekt.ibmuc.com ([170.239.133.233]) by smtp.gmail.com with ESMTPSA id j16sm1757054qtx.92.2021.12.22.05.45.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Dec 2021 05:45:56 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH 7/8] target/ppc/power8-pmu-insn-cnt: add pmu_check_overflow() Date: Wed, 22 Dec 2021 10:45:19 -0300 Message-Id: <20211222134520.587877-8-danielhb413@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211222134520.587877-1-danielhb413@gmail.com> References: <20211222134520.587877-1-danielhb413@gmail.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::829 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::829; envelope-from=danielhb413@gmail.com; helo=mail-qt1-x829.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, Daniel Henrique Barboza , qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" pmu_check_overflow() will verify for overflow in the PMC1-5 counters, firing a performance monitor alert if an overflow happened with the proper MMCR0 bits set. The alert is fired by using helper_pmu_overflow(). Signed-off-by: Daniel Henrique Barboza --- target/ppc/helper.h | 1 + target/ppc/power8-pmu-insn-cnt.c.inc | 89 ++++++++++++++++++++++++++++ target/ppc/power8-pmu.c | 8 +++ 3 files changed, 98 insertions(+) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index fb6cac38b4..4d8193caab 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -26,6 +26,7 @@ DEF_HELPER_2(store_mmcr1, void, env, tl) DEF_HELPER_3(store_pmc, void, env, i32, i64) DEF_HELPER_2(read_pmc, tl, env, i32) DEF_HELPER_2(insns_inc, void, env, i32) +DEF_HELPER_1(pmu_overflow, void, env) #endif DEF_HELPER_1(check_tlb_flush_local, void, env) DEF_HELPER_1(check_tlb_flush_global, void, env) diff --git a/target/ppc/power8-pmu-insn-cnt.c.inc b/target/ppc/power8-pmu-insn-cnt.c.inc index d3dd6d4685..7bd07d8105 100644 --- a/target/ppc/power8-pmu-insn-cnt.c.inc +++ b/target/ppc/power8-pmu-insn-cnt.c.inc @@ -19,6 +19,7 @@ #define MMCR1_PMC4_INS_CNT 0x00000002 #define MMCR1_PMC4_INS_LATCH_CNT 0x000000FA +#define PMC_COUNTER_NEGATIVE_VAL 0x80000000UL /* * Increments PMC1 checking if MMCR1_PMC1SEL has one of the following * events: @@ -211,6 +212,92 @@ static void pmu_inc_pmc5(DisasContext *ctx) tcg_temp_free(t0); tcg_temp_free(t1); } + +/* + * Check for overflow of PMC1-PMC5 counters and call the overflow + * helper in case any counter has overflown. + */ +static void pmu_check_overflow(DisasContext *ctx) +{ + TCGv t_pmc1, t_pmc2, t_pmc3, t_pmc4, t_pmc5; + TCGv t0, t1; + TCGLabel *l_pmc_overflow; + TCGLabel *l_skip_pmc1_overflow; + TCGLabel *l_skip_overflow; + + /* + * Check if we have overflow bits set and fire an overflow + * event if necessary. Skip directly to 'l_pmc_overflow' + * right after finding the first overflow. + */ + l_pmc_overflow = gen_new_label(); + l_skip_pmc1_overflow = gen_new_label(); + + t0 = tcg_temp_new(); + gen_load_spr(t0, SPR_POWER_MMCR0); + tcg_gen_andi_tl(t0, t0, MMCR0_PMC1CE); + tcg_gen_brcondi_tl(TCG_COND_NE, t0, MMCR0_PMC1CE, l_skip_pmc1_overflow); + + t_pmc1 = tcg_temp_new(); + gen_load_spr(t_pmc1, SPR_POWER_PMC1); + tcg_gen_brcondi_tl(TCG_COND_GE, t_pmc1, PMC_COUNTER_NEGATIVE_VAL, + l_pmc_overflow); + + gen_set_label(l_skip_pmc1_overflow); + + l_skip_overflow = gen_new_label(); + + /* + * At this point we're sure PMC1 didn't overflow. If MMCR0_PMCjCE + * isn't set we can skip everything since PMC2-5 overflow is + * disabled. + */ + t1 = tcg_temp_new(); + gen_load_spr(t1, SPR_POWER_MMCR0); + tcg_gen_andi_tl(t1, t1, MMCR0_PMCjCE); + tcg_gen_brcondi_tl(TCG_COND_NE, t1, MMCR0_PMCjCE, l_skip_overflow); + + t_pmc2 = tcg_temp_new(); + gen_load_spr(t_pmc2, SPR_POWER_PMC2); + tcg_gen_brcondi_tl(TCG_COND_GE, t_pmc2, PMC_COUNTER_NEGATIVE_VAL, + l_pmc_overflow); + + t_pmc3 = tcg_temp_new(); + gen_load_spr(t_pmc3, SPR_POWER_PMC3); + tcg_gen_brcondi_tl(TCG_COND_GE, t_pmc3, PMC_COUNTER_NEGATIVE_VAL, + l_pmc_overflow); + + t_pmc4 = tcg_temp_new(); + gen_load_spr(t_pmc4, SPR_POWER_PMC4); + tcg_gen_brcondi_tl(TCG_COND_GE, t_pmc4, PMC_COUNTER_NEGATIVE_VAL, + l_pmc_overflow); + + t_pmc5 = tcg_temp_new(); + gen_load_spr(t_pmc5, SPR_POWER_PMC5); + tcg_gen_brcondi_tl(TCG_COND_LE, t_pmc5, PMC_COUNTER_NEGATIVE_VAL, + l_skip_overflow); + + gen_set_label(l_pmc_overflow); + + /* + * The PMU overflow helper manipuilates the internal PMU timer. + * In that case, if the guest is running with icount and we do not + * handle it beforehand, the helper can trigger a 'bad icount + * read'. + */ + gen_icount_io_start(ctx); + gen_helper_pmu_overflow(cpu_env); + + gen_set_label(l_skip_overflow); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(t_pmc1); + tcg_temp_free(t_pmc2); + tcg_temp_free(t_pmc3); + tcg_temp_free(t_pmc4); + tcg_temp_free(t_pmc5); +} #endif /* #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ #if defined(TARGET_PPC64) @@ -254,6 +341,8 @@ static void pmu_count_insns(DisasContext *ctx) gen_set_label(l_skip_pmc14); + pmu_check_overflow(ctx); + tcg_temp_free(t_mmcr0); tcg_temp_free(t_mmcr1); diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c index 08d1902cd5..6696c9b3ae 100644 --- a/target/ppc/power8-pmu.c +++ b/target/ppc/power8-pmu.c @@ -323,6 +323,14 @@ void helper_insns_inc(CPUPPCState *env, uint32_t num_insns) } } +/* Helper to fire a PMC interrupt from TCG code */ +void helper_pmu_overflow(CPUPPCState *env) +{ + PowerPCCPU *cpu = env_archcpu(env); + + fire_PMC_interrupt(cpu); +} + static void cpu_ppc_pmu_timer_cb(void *opaque) { PowerPCCPU *cpu = opaque; From patchwork Wed Dec 22 13:45:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 12691675 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3B8A4C433F5 for ; Wed, 22 Dec 2021 13:57:47 +0000 (UTC) Received: from localhost ([::1]:59246 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n027m-00079E-49 for qemu-devel@archiver.kernel.org; Wed, 22 Dec 2021 08:57:46 -0500 Received: from eggs.gnu.org ([209.51.188.92]:39860) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n01wP-0000VA-NE; Wed, 22 Dec 2021 08:46:02 -0500 Received: from [2607:f8b0:4864:20::f33] (port=34456 helo=mail-qv1-xf33.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n01wO-0005Gl-0N; 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Wed, 22 Dec 2021 05:45:58 -0800 (PST) Received: from rekt.ibmuc.com ([170.239.133.233]) by smtp.gmail.com with ESMTPSA id j16sm1757054qtx.92.2021.12.22.05.45.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Dec 2021 05:45:58 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH 8/8] target/ppc/power8-pmu.c: remove helper_insns_inc() Date: Wed, 22 Dec 2021 10:45:20 -0300 Message-Id: <20211222134520.587877-9-danielhb413@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211222134520.587877-1-danielhb413@gmail.com> References: <20211222134520.587877-1-danielhb413@gmail.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::f33 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::f33; envelope-from=danielhb413@gmail.com; helo=mail-qv1-xf33.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, Daniel Henrique Barboza , qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" After moving all the instruction counting to TCG Ops code this helper is not needed anymore. Signed-off-by: Daniel Henrique Barboza --- target/ppc/helper.h | 1 - target/ppc/power8-pmu-insn-cnt.c.inc | 4 -- target/ppc/power8-pmu.c | 60 ---------------------------- 3 files changed, 65 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 4d8193caab..de80e82ebe 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -25,7 +25,6 @@ DEF_HELPER_2(store_mmcr0, void, env, tl) DEF_HELPER_2(store_mmcr1, void, env, tl) DEF_HELPER_3(store_pmc, void, env, i32, i64) DEF_HELPER_2(read_pmc, tl, env, i32) -DEF_HELPER_2(insns_inc, void, env, i32) DEF_HELPER_1(pmu_overflow, void, env) #endif DEF_HELPER_1(check_tlb_flush_local, void, env) diff --git a/target/ppc/power8-pmu-insn-cnt.c.inc b/target/ppc/power8-pmu-insn-cnt.c.inc index 7bd07d8105..8b1604b4c7 100644 --- a/target/ppc/power8-pmu-insn-cnt.c.inc +++ b/target/ppc/power8-pmu-insn-cnt.c.inc @@ -303,10 +303,6 @@ static void pmu_check_overflow(DisasContext *ctx) #if defined(TARGET_PPC64) static void pmu_count_insns(DisasContext *ctx) { - /* - * Do not bother calling the helper if the PMU isn't counting - * instructions. - */ if (!ctx->pmu_insn_cnt) { return; } diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c index 6696c9b3ae..bfc052b49e 100644 --- a/target/ppc/power8-pmu.c +++ b/target/ppc/power8-pmu.c @@ -135,52 +135,6 @@ bool pmu_insn_cnt_enabled(CPUPPCState *env) return false; } -static bool pmu_increment_insns(CPUPPCState *env, uint32_t num_insns) -{ - bool overflow_triggered = false; - int sprn; - - /* PMC6 never counts instructions */ - for (sprn = SPR_POWER_PMC1; sprn <= SPR_POWER_PMC5; sprn++) { - PMUEventType evt_type = pmc_get_event(env, sprn); - bool insn_event = evt_type == PMU_EVENT_INSTRUCTIONS || - evt_type == PMU_EVENT_INSN_RUN_LATCH; - - if (pmc_is_inactive(env, sprn) || !insn_event) { - continue; - } - - if (evt_type == PMU_EVENT_INSTRUCTIONS) { - env->spr[sprn] += num_insns; - } - - if (evt_type == PMU_EVENT_INSN_RUN_LATCH && - env->spr[SPR_CTRL] & CTRL_RUN) { - env->spr[sprn] += num_insns; - } - - if (env->spr[sprn] >= PMC_COUNTER_NEGATIVE_VAL && - pmc_has_overflow_enabled(env, sprn)) { - - overflow_triggered = true; - - /* - * The real PMU will always trigger a counter overflow with - * PMC_COUNTER_NEGATIVE_VAL. We don't have an easy way to - * do that since we're counting block of instructions at - * the end of each translation block, and we're probably - * passing this value at this point. - * - * Let's write PMC_COUNTER_NEGATIVE_VAL to the overflowed - * counter to simulate what the real hardware would do. - */ - env->spr[sprn] = PMC_COUNTER_NEGATIVE_VAL; - } - } - - return overflow_triggered; -} - static void pmu_update_cycles(CPUPPCState *env) { uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); @@ -309,20 +263,6 @@ static void fire_PMC_interrupt(PowerPCCPU *cpu) return; } -/* This helper assumes that the PMC is running. */ -void helper_insns_inc(CPUPPCState *env, uint32_t num_insns) -{ - bool overflow_triggered; - PowerPCCPU *cpu; - - overflow_triggered = pmu_increment_insns(env, num_insns); - - if (overflow_triggered) { - cpu = env_archcpu(env); - fire_PMC_interrupt(cpu); - } -} - /* Helper to fire a PMC interrupt from TCG code */ void helper_pmu_overflow(CPUPPCState *env) {