From patchwork Wed Dec 15 04:34:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 12691896 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EFE5BC433F5 for ; Wed, 15 Dec 2021 04:34:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239729AbhLOEe6 (ORCPT ); Tue, 14 Dec 2021 23:34:58 -0500 Received: from dfw.source.kernel.org ([139.178.84.217]:51436 "EHLO dfw.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239728AbhLOEe5 (ORCPT ); Tue, 14 Dec 2021 23:34:57 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 5A95A617D8; Wed, 15 Dec 2021 04:34:57 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6A2BBC34609; Wed, 15 Dec 2021 04:34:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1639542896; bh=iFUGNRSlbfzY5N/ic/T+O+wJG5QqysKcHSimi0HoZ8Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gsbgtqOLngnrgSt1R8lStTLqR4siXYLxzSzcW14jXvW7K1v7jPA35U6qcgENr8waq RgG6oZHdyVBC2vBkh5cEPTjmxEpAQgSdgW9ZlKbSGSY/sf3BhWZ3Uci9QAOuRjxfwj yfVss1dw0cM9090f7dvEH1yMC6Ywel3jw69q5ePVuYhDQyLQaz2T5PuRqZSLgc+fZ+ fkgbnTrqyhnOnexzm/ACW79S5J8XLK8NGkEg51tjYVorPxhwMPuop1+wnzPDstQzBK Ra5bZ7mSjN2ug0D19XdtsmurRfx0VXfRpl0geWjVtt0vP3LVdwU40L7QMB2x8HL5dp t9Gb14ofUrZCQ== From: Vinod Koul To: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, Vinod Koul , Andy Gross , Rob Herring , Konrad Dybcio , devicetree@vger.kernel.org Subject: [PATCH v3 01/11] arm64: dts: qcom: Add base SM8450 DTSI Date: Wed, 15 Dec 2021 10:04:30 +0530 Message-Id: <20211215043440.605624-2-vkoul@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211215043440.605624-1-vkoul@kernel.org> References: <20211215043440.605624-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This add based DTSI for SM8450 SoC and includes base description of CPUs, GCC, RPMHCC, UART, interuupt-controller which helps to boot to shell with console on boards with this SoC Signed-off-by: Vinod Koul Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 476 +++++++++++++++++++++++++++ 1 file changed, 476 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm8450.dtsi diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi new file mode 100644 index 000000000000..96fbf4be3f89 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -0,0 +1,476 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Linaro Limited + */ + +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <76800000>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32000>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo780"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + L2_0: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + L3_0: l3-cache { + compatible = "cache"; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo780"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&L2_100>; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; + L2_100: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo780"; + reg = <0x0 0x200>; + enable-method = "psci"; + next-level-cache = <&L2_200>; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; + L2_200: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo780"; + reg = <0x0 0x300>; + enable-method = "psci"; + next-level-cache = <&L2_300>; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; + L2_300: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo780"; + reg = <0x0 0x400>; + enable-method = "psci"; + next-level-cache = <&L2_400>; + power-domains = <&CPU_PD4>; + power-domain-names = "psci"; + L2_400: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo780"; + reg = <0x0 0x500>; + enable-method = "psci"; + next-level-cache = <&L2_500>; + power-domains = <&CPU_PD5>; + power-domain-names = "psci"; + L2_500: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "qcom,kryo780"; + reg = <0x0 0x600>; + enable-method = "psci"; + next-level-cache = <&L2_600>; + power-domains = <&CPU_PD6>; + power-domain-names = "psci"; + L2_600: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "qcom,kryo780"; + reg = <0x0 0x700>; + enable-method = "psci"; + next-level-cache = <&L2_700>; + power-domains = <&CPU_PD7>; + power-domain-names = "psci"; + L2_700: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + + core4 { + cpu = <&CPU4>; + }; + + core5 { + cpu = <&CPU5>; + }; + + core6 { + cpu = <&CPU6>; + }; + + core7 { + cpu = <&CPU7>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + idle-state-name = "silver-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <274>; + exit-latency-us = <480>; + min-residency-us = <3934>; + local-timer-stop; + }; + + BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + idle-state-name = "gold-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <327>; + exit-latency-us = <1502>; + min-residency-us = <4488>; + local-timer-stop; + }; + }; + + domain-idle-states { + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "domain-idle-state"; + idle-state-name = "cluster-l3-off"; + arm,psci-suspend-param = <0x4100c344>; + entry-latency-us = <584>; + exit-latency-us = <2332>; + min-residency-us = <6118>; + local-timer-stop; + }; + + CLUSTER_SLEEP_1: cluster-sleep-1 { + compatible = "domain-idle-state"; + idle-state-name = "cluster-power-collapse"; + arm,psci-suspend-param = <0x4100c344>; + entry-latency-us = <2893>; + exit-latency-us = <4023>; + min-residency-us = <9987>; + local-timer-stop; + }; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-sm8450", "qcom,scm"; + #reset-cells = <1>; + }; + }; + + memory@a0000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0x0 0xa0000000 0x0 0x0>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + CPU_PD0: cpu0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD1: cpu1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD2: cpu2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD3: cpu3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD4: cpu4 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD5: cpu5 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD6: cpu6 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD7: cpu7 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CLUSTER_PD: cpu-cluster0 { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_SLEEP_0>; + }; + }; + + soc: soc@0 { + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x10 0>; + compatible = "simple-bus"; + + gcc: clock-controller@100000 { + compatible = "qcom,gcc-sm8450"; + reg = <0x0 0x00100000 0x0 0x1f4200>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clock-names = "bi_tcxo", "sleep_clk"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; + }; + + qupv3_id_0: geniqup@9c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x009c0000 0x0 0x2000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + uart7: serial@99c000 { + compatible = "qcom,geni-debug-uart"; + reg = <0 0x0099c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x01f40000 0x0 0x40000>; + #hwlock-cells = <1>; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,sm8450-pdc", "qcom,pdc"; + reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; + qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>, + <94 609 31>, <125 63 1>, <126 716 12>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + intc: interrupt-controller@17100000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x40000>; + reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */ + <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */ + interrupts = ; + }; + + timer@17420000 { + compatible = "arm,armv7-timer-mem"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + reg = <0x0 0x17420000 0x0 0x1000>; + clock-frequency = <19200000>; + + frame@17421000 { + frame-number = <0>; + interrupts = , + ; + reg = <0x0 0x17421000 0x0 0x1000>, + <0x0 0x17422000 0x0 0x1000>; + }; + + frame@17423000 { + frame-number = <1>; + interrupts = ; + reg = <0x0 0x17423000 0x0 0x1000>; + status = "disabled"; + }; + + frame@17425000 { + frame-number = <2>; + interrupts = ; + reg = <0x0 0x17425000 0x0 0x1000>; + status = "disabled"; + }; + + frame@17427000 { + frame-number = <3>; + interrupts = ; + reg = <0x0 0x17427000 0x0 0x1000>; + status = "disabled"; + }; + + frame@17429000 { + frame-number = <4>; + interrupts = ; + reg = <0x0 0x17429000 0x0 0x1000>; + status = "disabled"; + }; + + frame@1742b000 { + frame-number = <5>; + interrupts = ; + reg = <0x0 0x1742b000 0x0 0x1000>; + status = "disabled"; + }; + + frame@1742d000 { + frame-number = <6>; + interrupts = ; + reg = <0x0 0x1742d000 0x0 0x1000>; + status = "disabled"; + }; + }; + + apps_rsc: rsc@17a00000 { + label = "apps_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0x0 0x17a00000 0x0 0x10000>, + <0x0 0x17a10000 0x0 0x10000>, + <0x0 0x17a20000 0x0 0x10000>, + <0x0 0x17a30000 0x0 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; + interrupts = , + , + ; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = , , + , ; + + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible = "qcom,sm8450-rpmh-clk"; + #clock-cells = <1>; + clock-names = "xo"; + clocks = <&xo_board>; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <19200000>; + }; +}; From patchwork Wed Dec 15 04:34:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 12691897 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3D405C433EF for ; Wed, 15 Dec 2021 04:35:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239734AbhLOEfF (ORCPT ); Tue, 14 Dec 2021 23:35:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56390 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239735AbhLOEfE (ORCPT ); Tue, 14 Dec 2021 23:35:04 -0500 Received: from sin.source.kernel.org (sin.source.kernel.org [IPv6:2604:1380:40e1:4800::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1051BC06173F; Tue, 14 Dec 2021 20:35:04 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id B1812CE1BFB; Wed, 15 Dec 2021 04:35:01 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 609ADC3460B; Wed, 15 Dec 2021 04:34:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1639542899; bh=ew2ogF06dXNGi9pAo0OWriibGYCVYjyM2fN8TTJwYQM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Vf6dZfgE5Ixs7NA8Eo8bjwYubQ1QD6jZIeRIlBdaap7UsZL+dos98zqCw5GAHu8ES iP9JDhcKVqllBGXQ3NhVGchxg7zk0A7G2NTcq29GY6JeZlGQax6RER+tZI/U2R73Nr NefBpADVHVTgHvM/uNmF/pkCFZ2nPUmi6VkMLkHwEAgkdMo7B4qsJR4s/y2yxI4Uwe K5xMCkHIF1iTiJbITBXSnSnlsjhoexktga3NJUph6h5XthPUaQi5fGyjM4PStW9ccQ V+BoK84GMtdTpIqQHtuErErMbZ5xm42Qkwr3Ws5jEhoY3l/k71AHyqwJypt3fcRrDz FdFdAnJqP1f2w== From: Vinod Koul To: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, Vinod Koul , Andy Gross , Rob Herring , Konrad Dybcio , devicetree@vger.kernel.org Subject: [PATCH v3 02/11] arm64: dts: qcom: sm8450: Add tlmm nodes Date: Wed, 15 Dec 2021 10:04:31 +0530 Message-Id: <20211215043440.605624-3-vkoul@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211215043440.605624-1-vkoul@kernel.org> References: <20211215043440.605624-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add tlmm node found in SM8450 SoC and uart pin configuration Signed-off-by: Vinod Koul --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 96fbf4be3f89..fb93d53d3433 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -343,6 +343,8 @@ uart7: serial@99c000 { reg = <0 0x0099c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -366,6 +368,32 @@ pdc: interrupt-controller@b220000 { interrupt-controller; }; + tlmm: pinctrl@f100000 { + compatible = "qcom,sm8450-tlmm"; + reg = <0 0x0f100000 0 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 211>; + wakeup-parent = <&pdc>; + + qup_uart7_rx: qup-uart7-rx { + pins = "gpio26"; + function = "qup7"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart7_tx: qup-uart7-tx { + pins = "gpio27"; + function = "qup7"; + drive-strength = <2>; + bias-disable; + }; + }; + intc: interrupt-controller@17100000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; From patchwork Wed Dec 15 04:34:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 12691898 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D237AC433FE for ; Wed, 15 Dec 2021 04:35:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239738AbhLOEfH (ORCPT ); Tue, 14 Dec 2021 23:35:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56408 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239732AbhLOEfG (ORCPT ); Tue, 14 Dec 2021 23:35:06 -0500 Received: from sin.source.kernel.org (sin.source.kernel.org [IPv6:2604:1380:40e1:4800::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2D247C061401; Tue, 14 Dec 2021 20:35:06 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id 78F0BCE1850; Wed, 15 Dec 2021 04:35:04 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 56F87C3460A; Wed, 15 Dec 2021 04:35:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1639542902; bh=SvMTDeyaRslD0+1QSsuP7dl4oIdZ/KKgvgWO8xpCdYA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Q/Sb0xjWSf5DpYn3LNtk1sS/pt18I5jXmpRfEU5mTekAAyNlKW4OOAw6UMqfUpUx+ QEBXeQ1zVt+8ZTgnAAJldu9TuODr+D9Ssmx4BICvmVzTwgUNcFQxBALmw+t7jyWk8H 3bvZR5FHjBk42wTBZacMCMJ0rmIU8JmVlCgL31Gp9NRXLGZvV5ZTgqLB1h1B3lp5Cs zGvkeEGPn1xEehyCi7iILbdtMsDaHqPAnAYWEjTGogyAt7wYbb8SIeVYvjTM6JhKH8 9/BYrRBXRj4j7Zk1vfA1JU1/aVrrNvxxsEV8l1rNL8jAXIJJGXOCLmNMYh/i+leRvX zp071FsT6kF6A== From: Vinod Koul To: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, Vinod Koul , Andy Gross , Rob Herring , Konrad Dybcio , devicetree@vger.kernel.org Subject: [PATCH v3 03/11] arm64: dts: qcom: sm8450: Add reserved memory nodes Date: Wed, 15 Dec 2021 10:04:32 +0530 Message-Id: <20211215043440.605624-4-vkoul@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211215043440.605624-1-vkoul@kernel.org> References: <20211215043440.605624-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the reserved memory nodes for SM8450. This is based on the downstream documentation. Signed-off-by: Vinod Koul --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 221 +++++++++++++++++++++++++++ 1 file changed, 221 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index fb93d53d3433..d9439c6ebfa2 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -310,6 +310,227 @@ CLUSTER_PD: cpu-cluster0 { }; }; + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: memory@80000000 { + reg = <0x0 0x80000000 0x0 0x600000>; + no-map; + }; + + xbl_dt_log_mem: memory@80600000 { + reg = <0x0 0x80600000 0x0 0x40000>; + no-map; + }; + + xbl_ramdump_mem: memory@80640000 { + reg = <0x0 0x80640000 0x0 0x180000>; + no-map; + }; + + xbl_sc_mem: memory@807c0000 { + reg = <0x0 0x807c0000 0x0 0x40000>; + no-map; + }; + + aop_image_mem: memory@80800000 { + reg = <0x0 0x80800000 0x0 0x60000>; + no-map; + }; + + aop_cmd_db_mem: memory@80860000 { + compatible = "qcom,cmd-db"; + reg = <0x0 0x80860000 0x0 0x20000>; + no-map; + }; + + aop_config_mem: memory@80880000 { + reg = <0x0 0x80880000 0x0 0x20000>; + no-map; + }; + + tme_crash_dump_mem: memory@808a0000 { + reg = <0x0 0x808a0000 0x0 0x40000>; + no-map; + }; + + tme_log_mem: memory@808e0000 { + reg = <0x0 0x808e0000 0x0 0x4000>; + no-map; + }; + + uefi_log_mem: memory@808e4000 { + reg = <0x0 0x808e4000 0x0 0x10000>; + no-map; + }; + + /* secdata region can be reused by apps */ + smem: memory@80900000 { + compatible = "qcom,smem"; + reg = <0x0 0x80900000 0x0 0x200000>; + hwlocks = <&tcsr_mutex 3>; + no-map; + }; + + cpucp_fw_mem: memory@80b00000 { + reg = <0x0 0x80b00000 0x0 0x100000>; + no-map; + }; + + cdsp_secure_heap: memory@80c00000 { + reg = <0x0 0x80c00000 0x0 0x4600000>; + no-map; + }; + + camera_mem: memory@85200000 { + reg = <0x0 0x85200000 0x0 0x500000>; + no-map; + }; + + video_mem: memory@85700000 { + reg = <0x0 0x85700000 0x0 0x700000>; + no-map; + }; + + adsp_mem: memory@85e00000 { + reg = <0x0 0x85e00000 0x0 0x2100000>; + no-map; + }; + + slpi_mem: memory@88000000 { + reg = <0x0 0x88000000 0x0 0x1900000>; + no-map; + }; + + cdsp_mem: memory@89900000 { + reg = <0x0 0x89900000 0x0 0x2000000>; + no-map; + }; + + ipa_fw_mem: memory@8b900000 { + reg = <0x0 0x8b900000 0x0 0x10000>; + no-map; + }; + + ipa_gsi_mem: memory@8b910000 { + reg = <0x0 0x8b910000 0x0 0xa000>; + no-map; + }; + + gpu_micro_code_mem: memory@8b91a000 { + reg = <0x0 0x8b91a000 0x0 0x2000>; + no-map; + }; + + spss_region_mem: memory@8ba00000 { + reg = <0x0 0x8ba00000 0x0 0x180000>; + no-map; + }; + + /* First part of the "SPU secure shared memory" region */ + spu_tz_shared_mem: memory@8bb80000 { + reg = <0x0 0x8bb80000 0x0 0x60000>; + no-map; + }; + + /* Second part of the "SPU secure shared memory" region */ + spu_modem_shared_mem: memory@8bbe0000 { + reg = <0x0 0x8bbe0000 0x0 0x20000>; + no-map; + }; + + mpss_mem: memory@8bc00000 { + reg = <0x0 0x8bc00000 0x0 0x13200000>; + no-map; + }; + + cvp_mem: memory@9ee00000 { + reg = <0x0 0x9ee00000 0x0 0x700000>; + no-map; + }; + + global_sync_mem: memory@a6f00000 { + reg = <0x0 0xa6f00000 0x0 0x100000>; + no-map; + }; + + /* uefi region can be reused by APPS */ + + /* Linux kernel image is loaded at 0xa0000000 */ + + oem_vm_mem: memory@bb000000 { + reg = <0x0 0xbb000000 0x0 0x5000000>; + no-map; + }; + + mte_mem: memory@c0000000 { + reg = <0x0 0xc0000000 0x0 0x20000000>; + no-map; + }; + + qheebsp_reserved_mem: memory@e0000000 { + reg = <0x0 0xe0000000 0x0 0x600000>; + no-map; + }; + + cpusys_vm_mem: memory@e0600000 { + reg = <0x0 0xe0600000 0x0 0x400000>; + no-map; + }; + + hyp_reserved_mem: memory@e0a00000 { + reg = <0x0 0xe0a00000 0x0 0x100000>; + no-map; + }; + + trust_ui_vm_mem: memory@e0b00000 { + reg = <0x0 0xe0b00000 0x0 0x4af3000>; + no-map; + }; + + trust_ui_vm_qrtr: memory@e55f3000 { + reg = <0x0 0xe55f3000 0x0 0x9000>; + no-map; + }; + + trust_ui_vm_vblk0_ring: memory@e55fc000 { + reg = <0x0 0xe55fc000 0x0 0x4000>; + no-map; + }; + + trust_ui_vm_swiotlb: memory@e5600000 { + reg = <0x0 0xe5600000 0x0 0x100000>; + no-map; + }; + + tz_stat_mem: memory@e8800000 { + reg = <0x0 0xe8800000 0x0 0x100000>; + no-map; + }; + + tags_mem: memory@e8900000 { + reg = <0x0 0xe8900000 0x0 0x1200000>; + no-map; + }; + + qtee_mem: memory@e9b00000 { + reg = <0x0 0xe9b00000 0x0 0x500000>; + no-map; + }; + + trusted_apps_mem: memory@ea000000 { + reg = <0x0 0xea000000 0x0 0x3900000>; + no-map; + }; + + trusted_apps_ext_mem: memory@ed900000 { + reg = <0x0 0xed900000 0x0 0x3b00000>; + no-map; + }; + }; + soc: soc@0 { #address-cells = <2>; #size-cells = <2>; From patchwork Wed Dec 15 04:34:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 12691899 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7CE75C433F5 for ; Wed, 15 Dec 2021 04:35:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239728AbhLOEfL (ORCPT ); Tue, 14 Dec 2021 23:35:11 -0500 Received: from sin.source.kernel.org ([145.40.73.55]:46486 "EHLO sin.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236512AbhLOEfJ (ORCPT ); Tue, 14 Dec 2021 23:35:09 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id 72793CE1C09; Wed, 15 Dec 2021 04:35:07 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4DEEFC34600; Wed, 15 Dec 2021 04:35:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1639542905; bh=o43MS1iwY7lmLuBfPF6I5dCF09PMcpDX/HWgUMI+gDY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=khoy2vXylEnhKC7Y13qdpPVvvHKci5Q91HssNRiwq3hGoHktQs/oU5V2B3Ob6ra6C qz6iIMxPIsjEnhuRz/cYD60dpgwsqJX4XtZ0W5Z2RSYEXrAFHa7MCfk2aeuFhjEmBa xM/zloqiwY/35KbstZDu2pxmPaUXnHB+dJi1dqYpP6YxSZWGrhKAMDNaK/JKxFHLs/ M+Sp8iMU6dKfZvtiMLp+Rm+sWUPOTbxy431g7FkYDpzEGBlopNV2WgD/LhrK8V8e+z BYFiAFxkJZpPzrjdE/M8v3bQMmChiewvdYcoQY6doCjPsSwyrtMjsbmEqb/Oq1K0hy pGSWL9Grbc4GA== From: Vinod Koul To: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, Vinod Koul , Andy Gross , Rob Herring , Konrad Dybcio , devicetree@vger.kernel.org Subject: [PATCH v3 04/11] arm64: dts: qcom: sm8450: add smmu nodes Date: Wed, 15 Dec 2021 10:04:33 +0530 Message-Id: <20211215043440.605624-5-vkoul@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211215043440.605624-1-vkoul@kernel.org> References: <20211215043440.605624-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the apps smmu node as found in the SM8450 SoC Signed-off-by: Vinod Koul Acked-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 103 +++++++++++++++++++++++++++ 1 file changed, 103 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index d9439c6ebfa2..d29680c405bf 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -615,6 +615,109 @@ qup_uart7_tx: qup-uart7-tx { }; }; + apps_smmu: iommu@15000000 { + compatible = "qcom,sm8450-smmu-500", "arm,mmu-500"; + reg = <0 0x15000000 0 0x100000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + intc: interrupt-controller@17100000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; From patchwork Wed Dec 15 04:34:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 12691900 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9E5CC433EF for ; Wed, 15 Dec 2021 04:35:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239737AbhLOEfM (ORCPT ); Tue, 14 Dec 2021 23:35:12 -0500 Received: from sin.source.kernel.org ([145.40.73.55]:46514 "EHLO sin.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236512AbhLOEfM (ORCPT ); Tue, 14 Dec 2021 23:35:12 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id 6A57DCE1C1D; Wed, 15 Dec 2021 04:35:10 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 45563C34605; Wed, 15 Dec 2021 04:35:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1639542908; bh=0UJXfbwZTLWPS7ofrVooBY3SOutsZgnk0uYQcrrmfPs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=U9N3y+D7UvMQ/MAtGg8IUbNHiaFe1pkhO4KHXxutc796799vEuYzwEBolSUk5n4qM Vyw+9rwtOpQrIbvegfmc3m/H6wQw9KqwsX9ghdnmwEAgZfZp0rBffbaOGkQ7q+BVcd JFcR0wHw62hlorCqu3TZ8hbccRiBfkbxh8G0zVnwvwhp1XitqYqJP+ZUPHvF+AIPyL Nm3tUn9SjJBsPApF3zIWme83PTMeZ9vKjB8OFb5/nu5GrBOE3XKM4oC58RcF/UvQac /CCEDZa4YKeuWoCDlDxE50pyBHWjXsVb/7hug9NoxN7wKHIvXUPiwEvPgYCo7/8AFy J6cfvUJ0O0hyQ== From: Vinod Koul To: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, Vinod Koul , Andy Gross , Rob Herring , Konrad Dybcio , devicetree@vger.kernel.org Subject: [PATCH v3 05/11] arm64: dts: qcom: Add base SM8450 QRD DTS Date: Wed, 15 Dec 2021 10:04:34 +0530 Message-Id: <20211215043440.605624-6-vkoul@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211215043440.605624-1-vkoul@kernel.org> References: <20211215043440.605624-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add DTS for Qualcomm QRD platform which uses SM8450 SoC and mark the reserved nodes. Signed-off-by: Vinod Koul Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 33 +++++++++++++++++++++++++ 2 files changed, 34 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm8450-qrd.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 6b816eb33309..9b37261484cf 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -107,3 +107,4 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx203.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx206.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8350-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8350-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8450-qrd.dtb diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts new file mode 100644 index 000000000000..8dcd41c4e5ab --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Linaro Limited + */ + +/dts-v1/; + +#include "sm8450.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8450 QRD"; + compatible = "qcom,sm8450-qrd", "qcom,sm8450"; + + aliases { + serial0 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <28 4>, <36 4>; +}; + +&uart7 { + status = "okay"; +}; From patchwork Wed Dec 15 04:34:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 12691902 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6314FC433FE for ; Wed, 15 Dec 2021 04:35:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239746AbhLOEfQ (ORCPT ); Tue, 14 Dec 2021 23:35:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56466 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239740AbhLOEfP (ORCPT ); Tue, 14 Dec 2021 23:35:15 -0500 Received: from sin.source.kernel.org (sin.source.kernel.org [IPv6:2604:1380:40e1:4800::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4C1A0C061401; Tue, 14 Dec 2021 20:35:15 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id 62613CE1C19; Wed, 15 Dec 2021 04:35:13 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3B03AC34600; Wed, 15 Dec 2021 04:35:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1639542911; bh=MLcth3GqvPfAn11zBAA6LYQFqDp7r0n82PmISY+SfSQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BDyC+7m5QmNTQuww4PjIAzaIxL3vQEmDB8ATzg31i+TRg3FWtHuTCzclzx8X4K+gJ 6KRczt5RYXh0oICFAOL7ZfxmhdZqh5kpizZx3H4R/i5AEnPZA9FpfIMHEHoELBhK01 4tB5mHNeuhcKdUi3GUBy8qSCI3ryFP/S2J0YiKH+aWuYjaV/FYyi1jMCDbd8nItMD8 PEBBYYbmkUtXb8Ami9s1fm6qjc2/gu08r8WO9x3OKdAePIfD5lXKUjqjt8TXut2iKm B0WByfhqPzM2U9PkBpfybpaN6HCkTn4pDFoa6b9Lz3St0wMUjvWamqMOIwCKVrhkpo Ej9KY/Eah9rbw== From: Vinod Koul To: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, Vinod Koul , Andy Gross , Rob Herring , Konrad Dybcio , devicetree@vger.kernel.org Subject: [PATCH v3 06/11] arm64: dts: qcom: sm8450-qrd: Add rpmh regulator nodes Date: Wed, 15 Dec 2021 10:04:35 +0530 Message-Id: <20211215043440.605624-7-vkoul@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211215043440.605624-1-vkoul@kernel.org> References: <20211215043440.605624-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the RPMH regulators found in QRD-SM8450 platform Signed-off-by: Vinod Koul Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 322 ++++++++++++++++++++++++ 1 file changed, 322 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index 8dcd41c4e5ab..2ab19608a455 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include #include "sm8450.dtsi" / { @@ -18,6 +19,327 @@ aliases { chosen { stdout-path = "serial0:115200n8"; }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; +}; + +&apps_rsc { + pm8350-rpmh-regulators { + compatible = "qcom,pm8350-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-s11-supply = <&vph_pwr>; + vdd-s12-supply = <&vph_pwr>; + + vdd-l1-l4-supply = <&vreg_s11b_0p95>; + vdd-l2-l7-supply = <&vreg_bob>; + vdd-l3-l5-supply = <&vreg_bob>; + vdd-l6-l9-l10-supply = <&vreg_s12b_1p25>; + vdd-l8-supply = <&vreg_s2h_0p95>; + + vreg_s10b_1p8: smps10 { + regulator-name = "vreg_s10b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_s11b_0p95: smps11 { + regulator-name = "vreg_s11b_0p95"; + regulator-min-microvolt = <848000>; + regulator-max-microvolt = <1104000>; + }; + + vreg_s12b_1p25: smps12 { + regulator-name = "vreg_s12b_1p25"; + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1400000>; + }; + + vreg_l1b_0p91: ldo1 { + regulator-name = "vreg_l1b_0p91"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p07: ldo2 { + regulator-name = "vreg_l2b_3p07"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l3b_0p9: ldo3 { + regulator-name = "vreg_l3b_0p9"; + regulator-min-microvolt = <904000>; + regulator-max-microvolt = <904000>; + regulator-initial-mode = ; + }; + + vreg_l5b_0p88: ldo5 { + regulator-name = "vreg_l5b_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <888000>; + regulator-initial-mode = ; + }; + + vreg_l6b_1p2: ldo6 { + regulator-name = "vreg_l6b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l7b_2p5: ldo7 { + regulator-name = "vreg_l7b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = ; + }; + + vreg_l9b_1p2: ldo9 { + regulator-name = "vreg_l9b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + pm8350c-rpmh-regulators { + compatible = "qcom,pm8350c-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + + vdd-l1-l12-supply = <&vreg_bob>; + vdd-l2-l8-supply = <&vreg_bob>; + vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob>; + vdd-l6-l9-l11-supply = <&vreg_bob>; + + vdd-bob-supply = <&vph_pwr>; + + vreg_s1c_1p86: smps1 { + regulator-name = "vreg_s1c_1p86"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2024000>; + }; + + vreg_s10c_1p05: smps10 { + regulator-name = "vreg_s10c_1p05"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + }; + + vreg_bob: bob { + regulator-name = "vreg_bob"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_l1c_1p8: ldo1 { + regulator-name = "vreg_l1c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l3c_3p0: ldo3 { + regulator-name = "vreg_l3c_3p0"; + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + vreg_l4c_1p8: ldo4 { + regulator-name = "vreg_l4c_1p8"; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l5c_1p8: ldo5 { + regulator-name = "vreg_l5c_1p8"; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l6c_1p8: ldo6 { + regulator-name = "vreg_l6c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l7c_3p0: ldo7 { + regulator-name = "vreg_l7c_3p0"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l8c_1p8: ldo8 { + regulator-name = "vreg_l8c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l9c_2p96: ldo9 { + regulator-name = "vreg_l9c_2p96"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l12c_1p8: ldo12 { + regulator-name = "vreg_l12c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1968000>; + regulator-initial-mode = ; + }; + + vreg_l13c_3p0: ldo13 { + regulator-name = "vreg_l13c_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + }; + + pm8450-rpmh-regulators { + compatible = "qcom,pm8450-rpmh-regulators"; + qcom,pmic-id = "h"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + + vdd-l2-supply = <&vreg_bob>; + vdd-l3-supply = <&vreg_bob>; + vdd-l4-supply = <&vreg_bob>; + + vreg_s2h_0p95: smps2 { + regulator-name = "vreg_s2h_0p95"; + regulator-min-microvolt = <848000>; + regulator-max-microvolt = <1104000>; + }; + + vreg_s3h_0p5: smps3 { + regulator-name = "vreg_s3h_0p5"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <500000>; + }; + + vreg_l2h_0p91: ldo2 { + regulator-name = "vreg_l2h_0p91"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l3h_0p91: ldo3 { + regulator-name = "vreg_l3h_0p91"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + }; + + pmr735a-rpmh-regulators { + compatible = "qcom,pmr735a-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + + vdd-l1-l2-supply = <&vreg_s2e_0p85>; + vdd-l3-supply = <&vreg_s1e_1p25>; + vdd-l4-supply = <&vreg_s1c_1p86>; + vdd-l5-l6-supply = <&vreg_s1c_1p86>; + vdd-l7-bob-supply = <&vreg_bob>; + + vreg_s1e_1p25: smps1 { + regulator-name = "vreg_s1e_1p25"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1296000>; + }; + + vreg_s2e_0p85: smps2 { + regulator-name = "vreg_s2e_0p85"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1040000>; + }; + + vreg_l1e_0p8: ldo1 { + regulator-name = "vreg_l1e_0p8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + }; + + vreg_l2e_0p8: ldo2 { + regulator-name = "vreg_l2e_0p8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vreg_l4e_1p7: ldo4 { + regulator-name = "vreg_l4e_1p7"; + regulator-min-microvolt = <1776000>; + regulator-max-microvolt = <1776000>; + }; + + vreg_l5e_0p88: ldo5 { + regulator-name = "vreg_l5e_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + }; + + vreg_l6e_1p2: ldo6 { + regulator-name = "vreg_l6e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + }; }; &qupv3_id_0 { From patchwork Wed Dec 15 04:34:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 12691901 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59A09C433F5 for ; Wed, 15 Dec 2021 04:35:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239744AbhLOEfP (ORCPT ); Tue, 14 Dec 2021 23:35:15 -0500 Received: from dfw.source.kernel.org ([139.178.84.217]:51732 "EHLO dfw.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239741AbhLOEfP (ORCPT ); Tue, 14 Dec 2021 23:35:15 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 1DA54617D7; Wed, 15 Dec 2021 04:35:15 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 311D4C34604; Wed, 15 Dec 2021 04:35:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1639542914; bh=yTb5v+MXsxOvthbocV50YF6Ma7wZxkLSZxgBWsbzZqc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qBChwHGhyoA5csTEiF9d7kkk37P9nSNTPtPDYxnz/Z08on5PHzZgUcXmnnQ5FRAw2 Mg3gmFyaEZcMc/NgfFAsnziaXhuEzdp4L3+5m4Auj42z0u55NFYJxfk3Wh/bsKXYqd ZxPjuG3YYV/Su16OOR/KYS3pmUZnz7TbzFdOi8Zg/W4C5sXTS3++1dqy+AriyYbC0n dMzVBkvpXwU2j7HaGjZXPlNSh/oq6IdPdjFy0fw1EIidpYLF9b33+DnVwD5/x5icpP 3B4yrCNcmHHujOecFe/DBFZnEvy19wUKDBytcd+5Uh7eK577gfvitVGnDDpnR7b/h2 BRGAPC9Qpzhhw== From: Vinod Koul To: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, Vinod Koul , Andy Gross , Rob Herring , Konrad Dybcio , devicetree@vger.kernel.org Subject: [PATCH v3 07/11] arm64: dts: qcom: sm8450: add ufs nodes Date: Wed, 15 Dec 2021 10:04:36 +0530 Message-Id: <20211215043440.605624-8-vkoul@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211215043440.605624-1-vkoul@kernel.org> References: <20211215043440.605624-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the UFS and QMP PHY node for SM8450 SoC Signed-off-by: Vinod Koul Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 72 ++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index d29680c405bf..9556d2fc46e0 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -815,6 +815,78 @@ rpmhcc: clock-controller { clocks = <&xo_board>; }; }; + + ufs_mem_hc: ufshc@1d84000 { + compatible = "qcom,sm8450-ufshc", "qcom,ufshc", + "jedec,ufs-2.0"; + reg = <0 0x01d84000 0 0x3000>; + interrupts = ; + phys = <&ufs_mem_phy_lanes>; + phy-names = "ufsphy"; + lanes-per-direction = <2>; + #reset-cells = <1>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + power-domains = <&gcc UFS_PHY_GDSC>; + + iommus = <&apps_smmu 0xe0 0x0>; + + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = + <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + freq-table-hz = + <75000000 300000000>, + <0 0>, + <0 0>, + <75000000 300000000>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>; + status = "disabled"; + }; + + ufs_mem_phy: phy@1d87000 { + compatible = "qcom,sm8450-qmp-ufs-phy"; + reg = <0 0x01d87000 0 0xe10>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clock-names = "ref", "ref_aux", "qref"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_UFS_0_CLKREF_EN>; + + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + status = "disabled"; + + ufs_mem_phy_lanes: lanes@1d87400 { + reg = <0 0x01d87400 0 0x108>, + <0 0x01d87600 0 0x1e0>, + <0 0x01d87c00 0 0x1dc>, + <0 0x01d87800 0 0x108>, + <0 0x01d87a00 0 0x1e0>; + #phy-cells = <0>; + #clock-cells = <0>; + }; + }; }; timer { From patchwork Wed Dec 15 04:34:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 12691903 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53BD3C43219 for ; Wed, 15 Dec 2021 04:35:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239748AbhLOEfS (ORCPT ); Tue, 14 Dec 2021 23:35:18 -0500 Received: from dfw.source.kernel.org ([139.178.84.217]:51764 "EHLO dfw.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239740AbhLOEfS (ORCPT ); Tue, 14 Dec 2021 23:35:18 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 100D2617DA; Wed, 15 Dec 2021 04:35:18 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2763AC34600; Wed, 15 Dec 2021 04:35:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1639542917; bh=DHq8x3NS0uPYWBdWXJqA4Z7Tx3toHalCV1Y52lRkrWg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Y5eiaHd9n45pJP5VFROxNP9+oZIKWUhyPgfb2hioa9FgLYMS5afYmWAnCwenwwTCU cULkRzZ4SV5y/aqnYz5jB91lhIOgrcpHLquzk6ZYZDvgA2OHHBSoSq9SHoT7P+u7cD NTp8VG3t2ZysEizKm31rx09iwoJ0wDGfrvojWlqDIfV9vcX1BEK5Y/LURWM/V6cMv/ HYwoETrPi+Jh5FLWre1VDCcLeAwt2xY3+8sDyFGcn02vR1SG4yHiAMW37vSgz/PEYZ oB3xlyFgWTvQtEjYR303+oaIuGScQnY2j3Y1JbYbHvnD2NGpLKXSBM1lfBgq1eqtRa Mj5f4x0sK+K/Q== From: Vinod Koul To: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, Vinod Koul , Andy Gross , Rob Herring , Konrad Dybcio , devicetree@vger.kernel.org Subject: [PATCH v3 08/11] arm64: dts: qcom: sm8450-qrd: enable ufs nodes Date: Wed, 15 Dec 2021 10:04:37 +0530 Message-Id: <20211215043440.605624-9-vkoul@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211215043440.605624-1-vkoul@kernel.org> References: <20211215043440.605624-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Enable the UFS and phy node and add the regulators used by them. Signed-off-by: Vinod Koul Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index 2ab19608a455..4b7ad190d538 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -353,3 +353,23 @@ &tlmm { &uart7 { status = "okay"; }; + +&ufs_mem_hc { + status = "okay"; + + reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l7b_2p5>; + vcc-max-microamp = <1100000>; + vccq-supply = <&vreg_l9b_1p2>; + vccq-max-microamp = <1200000>; +}; + +&ufs_mem_phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l5b_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + vdda-max-microamp = <173000>; + vdda-pll-max-microamp = <24900>; +}; From patchwork Wed Dec 15 04:34:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 12691904 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 45D35C433EF for ; Wed, 15 Dec 2021 04:35:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239740AbhLOEf0 (ORCPT ); Tue, 14 Dec 2021 23:35:26 -0500 Received: from sin.source.kernel.org ([145.40.73.55]:46610 "EHLO sin.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239750AbhLOEfY (ORCPT ); Tue, 14 Dec 2021 23:35:24 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id 80E56CE19FE; Wed, 15 Dec 2021 04:35:22 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1E36BC3460B; Wed, 15 Dec 2021 04:35:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1639542920; bh=3MItG0wNgCNBgLYtrgkE/oMfbnjgT58GogXqb80fJd8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LFcppvpM5ogA9CcfCiWclLb7Y/tfucbiOXfNX4VFl79+Sk4AMkEcqgFtUFZioy2jU G4Mu4RzNTsjqWHFVIG7LTleaLw9SansppC6ohs0k7yZ7iafObDw0fgSOdatoVtsqNS PuTDCnsf8Ab4wVh41bvbkB8G8b23042pWXY2hAHjS0zyhCfOCGG8xgWzdoLfakIHYw n8963zoPGD6814f0QCL9iSM8K51woGOqk8mh0p615lYomeLsII62MREy+qT/1Vm+QE tGAE6MN1nUpucxyw6sNYyYAdQ+2rSulMTw55V5gw6u06SWdkqDQJM1upbqwkceTC7S AY3+5mESOwtRw== From: Vinod Koul To: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, Dmitry Baryshkov , Andy Gross , Rob Herring , Konrad Dybcio , devicetree@vger.kernel.org, Vinod Koul Subject: [PATCH v3 09/11] arm64: dts: qcom: sm8450: Add rpmhpd node Date: Wed, 15 Dec 2021 10:04:38 +0530 Message-Id: <20211215043440.605624-10-vkoul@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211215043440.605624-1-vkoul@kernel.org> References: <20211215043440.605624-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Dmitry Baryshkov This adds RPMH power domain found in SM8450 SoC Signed-off-by: Dmitry Baryshkov Signed-off-by: Vinod Koul Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 51 ++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 9556d2fc46e0..8fff4d54933f 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include #include / { @@ -814,6 +815,56 @@ rpmhcc: clock-controller { clock-names = "xo"; clocks = <&xo_board>; }; + + rpmhpd: power-controller { + compatible = "qcom,sm8450-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp1 { + opp-level = ; + }; + + rpmhpd_opp_min_svs: opp2 { + opp-level = ; + }; + + rpmhpd_opp_low_svs: opp3 { + opp-level = ; + }; + + rpmhpd_opp_svs: opp4 { + opp-level = ; + }; + + rpmhpd_opp_svs_l1: opp5 { + opp-level = ; + }; + + rpmhpd_opp_nom: opp6 { + opp-level = ; + }; + + rpmhpd_opp_nom_l1: opp7 { + opp-level = ; + }; + + rpmhpd_opp_nom_l2: opp8 { + opp-level = ; + }; + + rpmhpd_opp_turbo: opp9 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l1: opp10 { + opp-level = ; + }; + }; + }; }; ufs_mem_hc: ufshc@1d84000 { From patchwork Wed Dec 15 04:34:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 12691905 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7DB67C433FE for ; Wed, 15 Dec 2021 04:35:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239751AbhLOEf1 (ORCPT ); Tue, 14 Dec 2021 23:35:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56518 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239726AbhLOEfZ (ORCPT ); Tue, 14 Dec 2021 23:35:25 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F07ACC06173E; Tue, 14 Dec 2021 20:35:24 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 82235617D2; Wed, 15 Dec 2021 04:35:24 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5570BC34608; Wed, 15 Dec 2021 04:35:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1639542923; bh=Vd9kxCRzDbGb5FCo+00iF4zQOsjd4QYOTa28clj2axY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=s0J9kR+TDDl4WDjiTluGePS9httKRvEU8WUe4S8ivQtOMTenl7BvH4HnP6rWqZeNR gk0j81yiXvkXvsiUOwqfZPjNcc0Qap6CS8mov5yi+HqYwpYRlFzGATPpze/YUOjJGR 8aYPUwpbFgXNff9IpQkhk7wy5IrEoEPlgFo8XJhyG6actcid2gzzSXzn4nD/GZOdfK BBiBd6LQyU3idoMvJMzJ6UWJZCnguo0uDAZ8O4muOANbgdUpHayKYr+mNmPRPfKQHZ bSsE60ReLxApoSAfXtg00YmTghq3HbNYS/is+QRrdwMlHVxHjC0DBn74+s3WbtSJih CZPPnDOYBVNlg== From: Vinod Koul To: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, Vladimir Zapolskiy , Andy Gross , Rob Herring , Konrad Dybcio , devicetree@vger.kernel.org, Vinod Koul Subject: [PATCH v3 10/11] arm64: dts: qcom: sm8450: add cpufreq support Date: Wed, 15 Dec 2021 10:04:39 +0530 Message-Id: <20211215043440.605624-11-vkoul@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211215043440.605624-1-vkoul@kernel.org> References: <20211215043440.605624-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Vladimir Zapolskiy The change adds a description of a SM8450 cpufreq-epss controller and references to it from CPU nodes. Signed-off-by: Vladimir Zapolskiy Signed-off-by: Vinod Koul --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 8fff4d54933f..56e3e8f771bd 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -44,6 +44,7 @@ CPU0: cpu@0 { next-level-cache = <&L2_0>; power-domains = <&CPU_PD0>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; L2_0: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -61,6 +62,7 @@ CPU1: cpu@100 { next-level-cache = <&L2_100>; power-domains = <&CPU_PD1>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; L2_100: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -75,6 +77,7 @@ CPU2: cpu@200 { next-level-cache = <&L2_200>; power-domains = <&CPU_PD2>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; L2_200: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -89,6 +92,7 @@ CPU3: cpu@300 { next-level-cache = <&L2_300>; power-domains = <&CPU_PD3>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; L2_300: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -103,6 +107,7 @@ CPU4: cpu@400 { next-level-cache = <&L2_400>; power-domains = <&CPU_PD4>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; L2_400: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -117,6 +122,7 @@ CPU5: cpu@500 { next-level-cache = <&L2_500>; power-domains = <&CPU_PD5>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; L2_500: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -132,6 +138,7 @@ CPU6: cpu@600 { next-level-cache = <&L2_600>; power-domains = <&CPU_PD6>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; L2_600: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -146,6 +153,7 @@ CPU7: cpu@700 { next-level-cache = <&L2_700>; power-domains = <&CPU_PD7>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 2>; L2_700: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -867,6 +875,21 @@ rpmhpd_opp_turbo_l1: opp10 { }; }; + cpufreq_hw: cpufreq@17d91000 { + compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss"; + reg = <0 0x17d91000 0 0x1000>, + <0 0x17d92000 0 0x1000>, + <0 0x17d93000 0 0x1000>; + reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + interrupts = , + , + ; + interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; + #freq-domain-cells = <1>; + }; + ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sm8450-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; From patchwork Wed Dec 15 04:34:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 12691906 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5797C433EF for ; Wed, 15 Dec 2021 04:35:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239754AbhLOEfb (ORCPT ); Tue, 14 Dec 2021 23:35:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56546 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239752AbhLOEfb (ORCPT ); Tue, 14 Dec 2021 23:35:31 -0500 Received: from sin.source.kernel.org (sin.source.kernel.org [IPv6:2604:1380:40e1:4800::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A1C90C06173F; Tue, 14 Dec 2021 20:35:30 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id ED944CE19FE; Wed, 15 Dec 2021 04:35:28 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8BEEDC34604; Wed, 15 Dec 2021 04:35:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1639542927; bh=s9qdFU5s4Bc7u1OfBiWw3v8lMOxZJV5ftKA5FqmSElo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WIcYykmRBOl2SAo8NI9b3Ya9Pv9wQBQw2O/o5/DcCY2eRRVjmOjpPxkUjRwDLQFQe Nudxhr/kcRbfwsEmhkQzsvH7i/ICyHMynL1oItXFXhxShj/v5J1pOMjvfyS8KqzEbe +tKBy5KkZHaUtHjGPhwcOQItAE9YHXeAjHPawXLalvAWqvTyW0FK27mCUEAvi8yHtw E/yX2f/tADaEER7EGuzxW2Z218GbZR+bghU/DTh+rQLQ24LMg3ywwwe5kY24Sx4nCp xIByNWQ6wgugnkML8iFXGYwdDJFgvRhvnyzeCahaA7bWhtpQtOD+OlLvTffDnh0p0A FFJ8f/177xKWg== From: Vinod Koul To: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, Dmitry Baryshkov , Andy Gross , Rob Herring , Konrad Dybcio , devicetree@vger.kernel.org, Vinod Koul Subject: [PATCH v3 11/11] arm64: dts: qcom: sm8450: add i2c13 and i2c14 device nodes Date: Wed, 15 Dec 2021 10:04:40 +0530 Message-Id: <20211215043440.605624-12-vkoul@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211215043440.605624-1-vkoul@kernel.org> References: <20211215043440.605624-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Dmitry Baryshkov Add device tree nodes for two i2c blocks: i2c13 and i2c14. Signed-off-by: Dmitry Baryshkov Signed-off-by: Vinod Koul Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 52 ++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 56e3e8f771bd..62082ed5335d 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -582,6 +582,44 @@ uart7: serial@99c000 { }; }; + qupv3_id_1: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x00ac0000 0x0 0x6000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + i2c13: i2c@a94000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a94000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c13_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c14: i2c@a98000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a98000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c14_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x40000>; @@ -609,6 +647,20 @@ tlmm: pinctrl@f100000 { gpio-ranges = <&tlmm 0 0 211>; wakeup-parent = <&pdc>; + qup_i2c13_data_clk: qup-i2c13-data-clk { + pins = "gpio48", "gpio49"; + function = "qup13"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c14_data_clk: qup-i2c14-data-clk { + pins = "gpio52", "gpio53"; + function = "qup14"; + drive-strength = <2>; + bias-pull-up; + }; + qup_uart7_rx: qup-uart7-rx { pins = "gpio26"; function = "qup7";