From patchwork Tue Dec 21 07:19:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenglin Wu X-Patchwork-Id: 12692034 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C051DC4332F for ; Tue, 21 Dec 2021 07:20:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234953AbhLUHUq (ORCPT ); Tue, 21 Dec 2021 02:20:46 -0500 Received: from alexa-out.qualcomm.com ([129.46.98.28]:44568 "EHLO alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234934AbhLUHUq (ORCPT ); Tue, 21 Dec 2021 02:20:46 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1640071246; x=1671607246; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=BT3ij+o+RNqqmo+4+LR+KXAEY8VWuAd61fJQJ8OAeq8=; b=LL5eHQt91GNX6iWSdWxVwxVi0a4tO3MDnPFiJ2axQvMf/1jubn2/uSV1 uJJSc8ZFVbDnBje21ya7Xeol0gz6+CWJL3OpiMrx0WUOGpYHWgJLnICe4 3KMpgLEpGznBl6enySXrd4/kQojfFvvdrvrFxJeZBSc4Jx3IVSHUDdCPc k=; Received: from ironmsg09-lv.qualcomm.com ([10.47.202.153]) by alexa-out.qualcomm.com with ESMTP; 20 Dec 2021 23:20:45 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg09-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Dec 2021 23:20:45 -0800 Received: from nalasex01c.na.qualcomm.com (10.47.97.35) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Mon, 20 Dec 2021 23:20:44 -0800 Received: from fenglinw-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Mon, 20 Dec 2021 23:20:42 -0800 From: Fenglin Wu To: , , CC: , , , , , Abhijeet Dharmapurikar Subject: [PATCH v4 01/11] spmi: pmic-arb: add a print in cleanup_irq Date: Tue, 21 Dec 2021 15:19:59 +0800 Message-ID: <1640071211-31462-2-git-send-email-quic_fenglinw@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1640071211-31462-1-git-send-email-quic_fenglinw@quicinc.com> References: <1640071211-31462-1-git-send-email-quic_fenglinw@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Abhijeet Dharmapurikar The cleanup_irq() was meant to clear and mask interrupts that were left enabled in the hardware but there was no interrupt handler registered for it. Add an error print when it gets invoked. Signed-off-by: Abhijeet Dharmapurikar Signed-off-by: David Collins Signed-off-by: Fenglin Wu --- drivers/spmi/spmi-pmic-arb.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c index 2113be4..5a99723 100644 --- a/drivers/spmi/spmi-pmic-arb.c +++ b/drivers/spmi/spmi-pmic-arb.c @@ -590,6 +590,8 @@ static void cleanup_irq(struct spmi_pmic_arb *pmic_arb, u16 apid, int id) u8 per = ppid & 0xFF; u8 irq_mask = BIT(id); + dev_err_ratelimited(&pmic_arb->spmic->dev, "%s apid=%d sid=0x%x per=0x%x irq=%d\n", + __func__, apid, sid, per, id); writel_relaxed(irq_mask, pmic_arb->ver_ops->irq_clear(pmic_arb, apid)); if (pmic_arb_write_cmd(pmic_arb->spmic, SPMI_CMD_EXT_WRITEL, sid, From patchwork Tue Dec 21 07:20:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenglin Wu X-Patchwork-Id: 12692035 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC9B5C433EF for ; Tue, 21 Dec 2021 07:20:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234979AbhLUHUu (ORCPT ); Tue, 21 Dec 2021 02:20:50 -0500 Received: from alexa-out-sd-02.qualcomm.com ([199.106.114.39]:41931 "EHLO alexa-out-sd-02.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229999AbhLUHUt (ORCPT ); Tue, 21 Dec 2021 02:20:49 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1640071249; x=1671607249; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=g3rY4bpEO25fMFkUyVjEe7VfSZehXBwtx/lekwobvxU=; b=ppL2sO5Cno5YcqfJO7HzgAs8BqTcBHbEm0JUXoeJycOV/66uOHlptC9n Kpmj+wtwS1SyxIyJ1Akwvdkkf1nL8hnYuo9LT8ULpqwT8vOcZFpMsy3Kx AwHRvYvmc4B3zXm4RHc3NFUPHu7IN2PRByMmATFIx1epFWQsRpSNxv17r A=; Received: from unknown (HELO ironmsg05-sd.qualcomm.com) ([10.53.140.145]) by alexa-out-sd-02.qualcomm.com with ESMTP; 20 Dec 2021 23:20:48 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg05-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Dec 2021 23:20:47 -0800 Received: from nalasex01c.na.qualcomm.com (10.47.97.35) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Mon, 20 Dec 2021 23:20:47 -0800 Received: from fenglinw-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Mon, 20 Dec 2021 23:20:45 -0800 From: Fenglin Wu To: , , CC: , , , , Subject: [PATCH v4 02/11] spmi: pmic-arb: handle spurious interrupt Date: Tue, 21 Dec 2021 15:20:00 +0800 Message-ID: <1640071211-31462-3-git-send-email-quic_fenglinw@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1640071211-31462-1-git-send-email-quic_fenglinw@quicinc.com> References: <1640071211-31462-1-git-send-email-quic_fenglinw@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Call handle_bad_irq() when the summary interrupt is fired spuriously. Signed-off-by: Fenglin Wu --- drivers/spmi/spmi-pmic-arb.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c index 5a99723..719bd73 100644 --- a/drivers/spmi/spmi-pmic-arb.c +++ b/drivers/spmi/spmi-pmic-arb.c @@ -605,10 +605,11 @@ static void cleanup_irq(struct spmi_pmic_arb *pmic_arb, u16 apid, int id) irq_mask, ppid); } -static void periph_interrupt(struct spmi_pmic_arb *pmic_arb, u16 apid) +static int periph_interrupt(struct spmi_pmic_arb *pmic_arb, u16 apid) { unsigned int irq; u32 status, id; + int handled = 0; u8 sid = (pmic_arb->apid_data[apid].ppid >> 8) & 0xF; u8 per = pmic_arb->apid_data[apid].ppid & 0xFF; @@ -623,7 +624,10 @@ static void periph_interrupt(struct spmi_pmic_arb *pmic_arb, u16 apid) continue; } generic_handle_irq(irq); + handled++; } + + return handled; } static void pmic_arb_chained_irq(struct irq_desc *desc) @@ -634,7 +638,7 @@ static void pmic_arb_chained_irq(struct irq_desc *desc) int first = pmic_arb->min_apid >> 5; int last = pmic_arb->max_apid >> 5; u8 ee = pmic_arb->ee; - u32 status, enable; + u32 status, enable, handled = 0; int i, id, apid; chained_irq_enter(chip, desc); @@ -649,10 +653,14 @@ static void pmic_arb_chained_irq(struct irq_desc *desc) enable = readl_relaxed( ver_ops->acc_enable(pmic_arb, apid)); if (enable & SPMI_PIC_ACC_ENABLE_BIT) - periph_interrupt(pmic_arb, apid); + if (periph_interrupt(pmic_arb, apid) != 0) + handled++; } } + if (handled == 0) + handle_bad_irq(desc); + chained_irq_exit(chip, desc); } From patchwork Tue Dec 21 07:20:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenglin Wu X-Patchwork-Id: 12692036 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 63595C433EF for ; Tue, 21 Dec 2021 07:21:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235035AbhLUHVC (ORCPT ); Tue, 21 Dec 2021 02:21:02 -0500 Received: from alexa-out.qualcomm.com ([129.46.98.28]:34095 "EHLO alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235039AbhLUHUy (ORCPT ); Tue, 21 Dec 2021 02:20:54 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1640071255; x=1671607255; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=OhR72xqFkzDx/cOjDRLsolT9JZibeLMb3xt2MB4DjB8=; b=tNuOi2nhRX2IFNOPg2LJtYrvUQrtmHEN844fA5c8N1NC6Z3okq438q/8 WDt3Stg7mosR2Ox/UC9wkVvfbLfWW9JoA+24hnrGSe6zbzhIHSnR5LkXU p+7ee/kUrFcb3e2l7t8FbCSSHcyDVdHxOl/nXFkItzCIg/RB3jQfxp6S7 4=; Received: from ironmsg08-lv.qualcomm.com ([10.47.202.152]) by alexa-out.qualcomm.com with ESMTP; 20 Dec 2021 23:20:54 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg08-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Dec 2021 23:20:53 -0800 Received: from nalasex01c.na.qualcomm.com (10.47.97.35) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Mon, 20 Dec 2021 23:20:53 -0800 Received: from fenglinw-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Mon, 20 Dec 2021 23:20:49 -0800 From: Fenglin Wu To: , , , Greg Kroah-Hartman , "Kiran Gunda" , Abhijeet Dharmapurikar CC: , , , , Subject: [PATCH v4 03/11] spmi: pmic-arb: do not ack and clear peripheral interrupts in cleanup_irq Date: Tue, 21 Dec 2021 15:20:01 +0800 Message-ID: <1640071211-31462-4-git-send-email-quic_fenglinw@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1640071211-31462-1-git-send-email-quic_fenglinw@quicinc.com> References: <1640071211-31462-1-git-send-email-quic_fenglinw@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Subbaraman Narayanamurthy Currently, cleanup_irq() is invoked when a peripheral's interrupt fires and there is no mapping present in the interrupt domain of spmi interrupt controller. The cleanup_irq clears the arbiter bit, clears the pmic interrupt and disables it at the pmic in that order. The last disable in cleanup_irq races with request_irq() in that it stomps over the enable issued by request_irq. Fix this by not writing to the pmic in cleanup_irq. The latched bit will be left set in the pmic, which will not send us more interrupts even if the enable bit stays enabled. When a client wants to request an interrupt, use the activate callback on the irq_domain to clear latched bit. This ensures that the latched, if set due to the above changes in cleanup_irq or when the bootloader leaves it set, gets cleaned up, paving way for upcoming interrupts to trigger. With this, there is a possibility of unwanted triggering of interrupt right after the latched bit is cleared - the interrupt may be left enabled too. To avoid that, clear the enable first followed by clearing the latched bit in the activate callback. Fixes: 6bc546e71e50 ("spmi: pmic-arb: cleanup unrequested irqs") Fixes: 02abec3616c1 ("spmi: pmic-arb: rename pa_xx to pmic_arb_xx and other cleanup") Signed-off-by: Subbaraman Narayanamurthy [collinsd@codeaurora.org: fix merge conflict] Signed-off-by: David Collins Signed-off-by: Fenglin Wu --- drivers/spmi/spmi-pmic-arb.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c index 719bd73..2bc3b88 100644 --- a/drivers/spmi/spmi-pmic-arb.c +++ b/drivers/spmi/spmi-pmic-arb.c @@ -593,16 +593,6 @@ static void cleanup_irq(struct spmi_pmic_arb *pmic_arb, u16 apid, int id) dev_err_ratelimited(&pmic_arb->spmic->dev, "%s apid=%d sid=0x%x per=0x%x irq=%d\n", __func__, apid, sid, per, id); writel_relaxed(irq_mask, pmic_arb->ver_ops->irq_clear(pmic_arb, apid)); - - if (pmic_arb_write_cmd(pmic_arb->spmic, SPMI_CMD_EXT_WRITEL, sid, - (per << 8) + QPNPINT_REG_LATCHED_CLR, &irq_mask, 1)) - dev_err_ratelimited(&pmic_arb->spmic->dev, "failed to ack irq_mask = 0x%x for ppid = %x\n", - irq_mask, ppid); - - if (pmic_arb_write_cmd(pmic_arb->spmic, SPMI_CMD_EXT_WRITEL, sid, - (per << 8) + QPNPINT_REG_EN_CLR, &irq_mask, 1)) - dev_err_ratelimited(&pmic_arb->spmic->dev, "failed to ack irq_mask = 0x%x for ppid = %x\n", - irq_mask, ppid); } static int periph_interrupt(struct spmi_pmic_arb *pmic_arb, u16 apid) @@ -780,6 +770,7 @@ static int qpnpint_irq_domain_activate(struct irq_domain *domain, u16 apid = hwirq_to_apid(d->hwirq); u16 sid = hwirq_to_sid(d->hwirq); u16 irq = hwirq_to_irq(d->hwirq); + u8 buf; if (pmic_arb->apid_data[apid].irq_ee != pmic_arb->ee) { dev_err(&pmic_arb->spmic->dev, "failed to xlate sid = %#x, periph = %#x, irq = %u: ee=%u but owner=%u\n", @@ -788,6 +779,10 @@ static int qpnpint_irq_domain_activate(struct irq_domain *domain, return -ENODEV; } + buf = BIT(irq); + qpnpint_spmi_write(d, QPNPINT_REG_EN_CLR, &buf, 1); + qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &buf, 1); + return 0; } From patchwork Tue Dec 21 07:20:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenglin Wu X-Patchwork-Id: 12692037 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0901C433FE for ; Tue, 21 Dec 2021 07:21:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235058AbhLUHVF (ORCPT ); Tue, 21 Dec 2021 02:21:05 -0500 Received: from alexa-out-sd-02.qualcomm.com ([199.106.114.39]:42877 "EHLO alexa-out-sd-02.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229999AbhLUHU5 (ORCPT ); Tue, 21 Dec 2021 02:20:57 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1640071257; x=1671607257; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=dHMURxnIsgonyHWuwt/5fkDXVTWfVe9P2gTB2bgBiiA=; b=FwWyN8mdSF1F/bxfGHj22j5KoPobxx4q+al00MJ/VwWefiQk6nXrNs6t 6l1UcHqhDxDaKMjcY/OGejiTZve6S8J5sDI648zNpilyNMrXDolNBSSI4 lHplstpAJAr9QbWwOzBMDyhhA2dJblv6kPLnpYAIVDyD8MTffCNxn03An c=; Received: from unknown (HELO ironmsg05-sd.qualcomm.com) ([10.53.140.145]) by alexa-out-sd-02.qualcomm.com with ESMTP; 20 Dec 2021 23:20:57 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg05-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Dec 2021 23:20:57 -0800 Received: from nalasex01c.na.qualcomm.com (10.47.97.35) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Mon, 20 Dec 2021 23:20:56 -0800 Received: from fenglinw-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Mon, 20 Dec 2021 23:20:54 -0800 From: Fenglin Wu To: , , CC: , , , , Subject: [PATCH v4 04/11] spmi: pmic-arb: check apid against limits before calling irq handler Date: Tue, 21 Dec 2021 15:20:02 +0800 Message-ID: <1640071211-31462-5-git-send-email-quic_fenglinw@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1640071211-31462-1-git-send-email-quic_fenglinw@quicinc.com> References: <1640071211-31462-1-git-send-email-quic_fenglinw@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: David Collins Check that the apid for an SPMI interrupt falls between the min_apid and max_apid that can be handled by the APPS processor before invoking the per-apid interrupt handler: periph_interrupt(). This avoids an access violation in rare cases where the status bit is set for an interrupt that is not owned by the APPS processor. Signed-off-by: David Collins Signed-off-by: Fenglin Wu --- drivers/spmi/spmi-pmic-arb.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c index 2bc3b88..e19eaec 100644 --- a/drivers/spmi/spmi-pmic-arb.c +++ b/drivers/spmi/spmi-pmic-arb.c @@ -625,21 +625,26 @@ static void pmic_arb_chained_irq(struct irq_desc *desc) struct spmi_pmic_arb *pmic_arb = irq_desc_get_handler_data(desc); const struct pmic_arb_ver_ops *ver_ops = pmic_arb->ver_ops; struct irq_chip *chip = irq_desc_get_chip(desc); - int first = pmic_arb->min_apid >> 5; - int last = pmic_arb->max_apid >> 5; + int first = pmic_arb->min_apid; + int last = pmic_arb->max_apid; u8 ee = pmic_arb->ee; u32 status, enable, handled = 0; int i, id, apid; chained_irq_enter(chip, desc); - for (i = first; i <= last; ++i) { + for (i = first >> 5; i <= last >> 5; ++i) { status = readl_relaxed( ver_ops->owner_acc_status(pmic_arb, ee, i)); while (status) { id = ffs(status) - 1; status &= ~BIT(id); apid = id + i * 32; + if (apid < first || apid > last) { + WARN_ONCE(true, "spurious spmi irq received for apid=%d\n", + apid); + continue; + } enable = readl_relaxed( ver_ops->acc_enable(pmic_arb, apid)); if (enable & SPMI_PIC_ACC_ENABLE_BIT) From patchwork Tue Dec 21 07:20:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenglin Wu X-Patchwork-Id: 12692038 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 308F8C433F5 for ; Tue, 21 Dec 2021 07:21:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235148AbhLUHVL (ORCPT ); Tue, 21 Dec 2021 02:21:11 -0500 Received: from alexa-out.qualcomm.com ([129.46.98.28]:9352 "EHLO alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235089AbhLUHVB (ORCPT ); Tue, 21 Dec 2021 02:21:01 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1640071262; x=1671607262; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=vFm/1iPltzV2y4DMijEhe5IyJTZ/LWY1V45aTZ9IiEs=; b=OQpwVkCW/XEoXSKlwmhvKvEMYmG58mmOvZOTpZuLypfNTdfUxIDQMgaJ GNRvdVMyvfc/eNA9RpFObvSVnRcYeSyr8B/7r7wcHwr0LkPRziNxMfKD9 sCHMF1AGhDdJGaURpnDVhZh533e1djxJwOi6FTy5QsUl5F5MChDQyTbRd 4=; Received: from ironmsg09-lv.qualcomm.com ([10.47.202.153]) by alexa-out.qualcomm.com with ESMTP; 20 Dec 2021 23:21:01 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg09-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Dec 2021 23:21:01 -0800 Received: from nalasex01c.na.qualcomm.com (10.47.97.35) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Mon, 20 Dec 2021 23:21:00 -0800 Received: from fenglinw-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Mon, 20 Dec 2021 23:20:57 -0800 From: Fenglin Wu To: , , CC: , , , , , "Ashay Jaiswal" Subject: [PATCH v4 05/11] spmi: pmic-arb: add support to dispatch interrupt based on IRQ status Date: Tue, 21 Dec 2021 15:20:03 +0800 Message-ID: <1640071211-31462-6-git-send-email-quic_fenglinw@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1640071211-31462-1-git-send-email-quic_fenglinw@quicinc.com> References: <1640071211-31462-1-git-send-email-quic_fenglinw@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Ashay Jaiswal Current implementation of SPMI arbiter dispatches interrupt based on the Arbiter's accumulator status, in some cases the accumulator status may remain zero and the interrupt remains un-handled. Add logic to dispatch interrupts based Arbiter's IRQ status if the accumulator status is zero. Signed-off-by: Ashay Jaiswal Signed-off-by: David Collins Signed-off-by: Fenglin Wu --- drivers/spmi/spmi-pmic-arb.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c index e19eaec..56f2294 100644 --- a/drivers/spmi/spmi-pmic-arb.c +++ b/drivers/spmi/spmi-pmic-arb.c @@ -630,12 +630,18 @@ static void pmic_arb_chained_irq(struct irq_desc *desc) u8 ee = pmic_arb->ee; u32 status, enable, handled = 0; int i, id, apid; + /* status based dispatch */ + bool acc_valid = false; + u32 irq_status = 0; chained_irq_enter(chip, desc); for (i = first >> 5; i <= last >> 5; ++i) { status = readl_relaxed( ver_ops->owner_acc_status(pmic_arb, ee, i)); + if (status) + acc_valid = true; + while (status) { id = ffs(status) - 1; status &= ~BIT(id); @@ -653,6 +659,29 @@ static void pmic_arb_chained_irq(struct irq_desc *desc) } } + /* ACC_STATUS is empty but IRQ fired check IRQ_STATUS */ + if (!acc_valid) { + for (i = first; i <= last; i++) { + /* skip if APPS is not irq owner */ + if (pmic_arb->apid_data[i].irq_ee != pmic_arb->ee) + continue; + + irq_status = readl_relaxed( + ver_ops->irq_status(pmic_arb, i)); + if (irq_status) { + enable = readl_relaxed( + ver_ops->acc_enable(pmic_arb, i)); + if (enable & SPMI_PIC_ACC_ENABLE_BIT) { + dev_dbg(&pmic_arb->spmic->dev, + "Dispatching IRQ for apid=%d status=%x\n", + i, irq_status); + if (periph_interrupt(pmic_arb, i) != 0) + handled++; + } + } + } + } + if (handled == 0) handle_bad_irq(desc); From patchwork Tue Dec 21 07:20:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenglin Wu X-Patchwork-Id: 12692039 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 39C38C433EF for ; Tue, 21 Dec 2021 07:21:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235128AbhLUHVP (ORCPT ); Tue, 21 Dec 2021 02:21:15 -0500 Received: from alexa-out-sd-01.qualcomm.com ([199.106.114.38]:16980 "EHLO alexa-out-sd-01.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235116AbhLUHVE (ORCPT ); Tue, 21 Dec 2021 02:21:04 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1640071264; x=1671607264; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=HlBrxxqz8GrpwuEBJfdNjgmehq5A3syFPfEQuqOMWpg=; b=ucGCgG7EPMk1bPkASIJHU9vv8Vy/EuoI348RYxPFrRZPjcr3Xl6oqxhp trTLdRGxIrwBA6iOdl9OL1cC7OiVAL/akc2C4/jbb6+2MJk61qQxKzq1w upA8WkyrN0JVVLSoo13EnyZ2cRi9wZW6N9bexWbcDC16qhFboCIAnVAHV s=; Received: from unknown (HELO ironmsg05-sd.qualcomm.com) ([10.53.140.145]) by alexa-out-sd-01.qualcomm.com with ESMTP; 20 Dec 2021 23:21:04 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg05-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Dec 2021 23:21:04 -0800 Received: from nalasex01c.na.qualcomm.com (10.47.97.35) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Mon, 20 Dec 2021 23:21:03 -0800 Received: from fenglinw-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Mon, 20 Dec 2021 23:21:01 -0800 From: Fenglin Wu To: , , , Greg Kroah-Hartman , "Kiran Gunda" , David Collins CC: , , , Subject: [PATCH v4 06/11] spmi: pmic-arb: correct duplicate APID to PPID mapping logic Date: Tue, 21 Dec 2021 15:20:04 +0800 Message-ID: <1640071211-31462-7-git-send-email-quic_fenglinw@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1640071211-31462-1-git-send-email-quic_fenglinw@quicinc.com> References: <1640071211-31462-1-git-send-email-quic_fenglinw@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: David Collins Correct the way that duplicate PPID mappings are handled for PMIC arbiter v5. The final APID mapped to a given PPID should be the one which has write owner = APPS EE, if it exists, or if not that, then the first APID mapped to the PPID, if it exists. Fixes: 40f318f0ed67 ("spmi: pmic-arb: add support for HW version 5") Signed-off-by: David Collins Signed-off-by: Fenglin Wu --- drivers/spmi/spmi-pmic-arb.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c index 56f2294..cf92abc 100644 --- a/drivers/spmi/spmi-pmic-arb.c +++ b/drivers/spmi/spmi-pmic-arb.c @@ -1031,7 +1031,8 @@ static int pmic_arb_read_apid_map_v5(struct spmi_pmic_arb *pmic_arb) * version 5, there is more than one APID mapped to each PPID. * The owner field for each of these mappings specifies the EE which is * allowed to write to the APID. The owner of the last (highest) APID - * for a given PPID will receive interrupts from the PPID. + * which has the IRQ owner bit set for a given PPID will receive + * interrupts from the PPID. */ for (i = 0; ; i++, apidd++) { offset = pmic_arb->ver_ops->apid_map_offset(i); @@ -1054,16 +1055,16 @@ static int pmic_arb_read_apid_map_v5(struct spmi_pmic_arb *pmic_arb) apid = pmic_arb->ppid_to_apid[ppid] & ~PMIC_ARB_APID_VALID; prev_apidd = &pmic_arb->apid_data[apid]; - if (valid && is_irq_ee && - prev_apidd->write_ee == pmic_arb->ee) { + if (!valid || apidd->write_ee == pmic_arb->ee) { + /* First PPID mapping or one for this EE */ + pmic_arb->ppid_to_apid[ppid] = i | PMIC_ARB_APID_VALID; + } else if (valid && is_irq_ee && + prev_apidd->write_ee == pmic_arb->ee) { /* * Duplicate PPID mapping after the one for this EE; * override the irq owner */ prev_apidd->irq_ee = apidd->irq_ee; - } else if (!valid || is_irq_ee) { - /* First PPID mapping or duplicate for another EE */ - pmic_arb->ppid_to_apid[ppid] = i | PMIC_ARB_APID_VALID; } apidd->ppid = ppid; From patchwork Tue Dec 21 07:20:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenglin Wu X-Patchwork-Id: 12692042 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6B9DC433F5 for ; Tue, 21 Dec 2021 07:21:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235019AbhLUHV2 (ORCPT ); Tue, 21 Dec 2021 02:21:28 -0500 Received: from alexa-out.qualcomm.com ([129.46.98.28]:17256 "EHLO alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235168AbhLUHVW (ORCPT ); Tue, 21 Dec 2021 02:21:22 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1640071283; x=1671607283; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=C/nKcvGohh66HEoXJpfjN/wkXoY3VldhRoiyN4/ZYtg=; b=cSfQfNwwVrrW2VTHE2NBZR8na+NmYQTsgZXTq1uHHXI1K+5fYHTP47L5 MKmYmD0GTlBVG/vzZA0cOS1i9xivmxYfntgmY4kbSlghqrXMb0+n6GgPl FW2EXdKuhPUxuRlSkKYJI8rAC40arRqh+NQIi3ZjC3lz+wkWDIBujrHOP 0=; Received: from ironmsg-lv-alpha.qualcomm.com ([10.47.202.13]) by alexa-out.qualcomm.com with ESMTP; 20 Dec 2021 23:21:22 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg-lv-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Dec 2021 23:21:07 -0800 Received: from nalasex01c.na.qualcomm.com (10.47.97.35) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Mon, 20 Dec 2021 23:21:06 -0800 Received: from fenglinw-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Mon, 20 Dec 2021 23:21:04 -0800 From: Fenglin Wu To: , , CC: , , , , Subject: [PATCH v4 07/11] spmi: pmic-arb: block access for invalid PMIC arbiter v5 SPMI writes Date: Tue, 21 Dec 2021 15:20:05 +0800 Message-ID: <1640071211-31462-8-git-send-email-quic_fenglinw@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1640071211-31462-1-git-send-email-quic_fenglinw@quicinc.com> References: <1640071211-31462-1-git-send-email-quic_fenglinw@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: David Collins The system crashes due to an access permission violation when writing to a PMIC peripheral which is not owned by the current ee. Add a check for PMIC arbiter version 5 for such invalid write requests and return an error instead of crashing the system. Signed-off-by: David Collins Signed-off-by: Fenglin Wu --- drivers/spmi/spmi-pmic-arb.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c index cf92abc..39f25bc 100644 --- a/drivers/spmi/spmi-pmic-arb.c +++ b/drivers/spmi/spmi-pmic-arb.c @@ -1133,6 +1133,11 @@ static int pmic_arb_offset_v5(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr, offset = 0x10000 * pmic_arb->ee + 0x80 * apid; break; case PMIC_ARB_CHANNEL_RW: + if (pmic_arb->apid_data[apid].write_ee != pmic_arb->ee) { + dev_err(&pmic_arb->spmic->dev, "disallowed SPMI write to sid=%u, addr=0x%04X\n", + sid, addr); + return -EPERM; + } offset = 0x10000 * apid; break; } From patchwork Tue Dec 21 07:20:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenglin Wu X-Patchwork-Id: 12692040 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D1D81C433F5 for ; Tue, 21 Dec 2021 07:21:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235085AbhLUHVR (ORCPT ); Tue, 21 Dec 2021 02:21:17 -0500 Received: from alexa-out-sd-01.qualcomm.com ([199.106.114.38]:16998 "EHLO alexa-out-sd-01.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235019AbhLUHVL (ORCPT ); Tue, 21 Dec 2021 02:21:11 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1640071271; x=1671607271; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=JGow5gSyCVGGIvARjpIWCWieeUWr8i3gh6AHITcaPMM=; b=XObdVQvIQwosaJ6zmf/U0xngpAmN0dPLMj4/WMNVa4fVT81sQoK+BmcA N7rmS7FYOXU2GyqnISyO4ymT9Cay/tqeJXDDKRCTnDyKXstGvN+oB8uFu 6lDjQ3NHXRlXV46qHVqKkQdA/J5GvNjlv3gatZFiZB+mEnWjKqGlrZqb3 Y=; Received: from unknown (HELO ironmsg05-sd.qualcomm.com) ([10.53.140.145]) by alexa-out-sd-01.qualcomm.com with ESMTP; 20 Dec 2021 23:21:10 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg05-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Dec 2021 23:21:10 -0800 Received: from nalasex01c.na.qualcomm.com (10.47.97.35) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Mon, 20 Dec 2021 23:21:10 -0800 Received: from fenglinw-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Mon, 20 Dec 2021 23:21:07 -0800 From: Fenglin Wu To: , , , Andy Gross , Bjorn Andersson , Rob Herring , CC: , , , , Subject: [PATCH v4 08/11] bindings: spmi: spmi-pmic-arb: mark interrupt properties as optional Date: Tue, 21 Dec 2021 15:20:06 +0800 Message-ID: <1640071211-31462-9-git-send-email-quic_fenglinw@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1640071211-31462-1-git-send-email-quic_fenglinw@quicinc.com> References: <1640071211-31462-1-git-send-email-quic_fenglinw@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: David Collins Mark all interrupt related properties as optional instead of required. Some boards do not required PMIC IRQ support and it isn't needed to handle SPMI bus transactions, so specify it as optional. Signed-off-by: David Collins Signed-off-by: Fenglin Wu --- Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt b/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt index ca645e2..6332507 100644 --- a/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt +++ b/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt @@ -29,6 +29,8 @@ Required properties: - #size-cells : must be set to 0 - qcom,ee : indicates the active Execution Environment identifier (0-5) - qcom,channel : which of the PMIC Arb provided channels to use for accesses (0-5) + +Optional properties: - interrupts : interrupt list for the PMIC Arb controller, must contain a single interrupt entry for the peripheral interrupt - interrupt-names : corresponding interrupt names for the interrupts From patchwork Tue Dec 21 07:20:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenglin Wu X-Patchwork-Id: 12692041 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58A81C433F5 for ; Tue, 21 Dec 2021 07:21:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235146AbhLUHVW (ORCPT ); Tue, 21 Dec 2021 02:21:22 -0500 Received: from alexa-out-sd-01.qualcomm.com ([199.106.114.38]:16980 "EHLO alexa-out-sd-01.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235089AbhLUHVO (ORCPT ); Tue, 21 Dec 2021 02:21:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1640071274; x=1671607274; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=9W8MONWCB3nHa5cG39eCdoNQ68ZRf4zFDKZRUOobOfU=; b=Zp4t+dFdlGGdAEOlw4i05OtVJBPnuCXXieBYY7x/I22Kdk/nwR1Z4pKV CEKLTF3EduApfiKXIpYsuN5cU5CGQhPh0QY90iFC3INJX1UcFzprhSKHv ipkKzIajMmxnT6WclDj7uePWPTvaB1dVzhDvtCp+krUxEYG0utq7C6Kfg Y=; Received: from unknown (HELO ironmsg05-sd.qualcomm.com) ([10.53.140.145]) by alexa-out-sd-01.qualcomm.com with ESMTP; 20 Dec 2021 23:21:13 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg05-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Dec 2021 23:21:13 -0800 Received: from nalasex01c.na.qualcomm.com (10.47.97.35) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Mon, 20 Dec 2021 23:21:13 -0800 Received: from fenglinw-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Mon, 20 Dec 2021 23:21:10 -0800 From: Fenglin Wu To: , , CC: , , , , Subject: [PATCH v4 09/11] spmi: pmic-arb: make interrupt support optional Date: Tue, 21 Dec 2021 15:20:07 +0800 Message-ID: <1640071211-31462-10-git-send-email-quic_fenglinw@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1640071211-31462-1-git-send-email-quic_fenglinw@quicinc.com> References: <1640071211-31462-1-git-send-email-quic_fenglinw@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: David Collins Make the support of PMIC peripheral interrupts optional for spmi-pmic-arb devices. This is useful in situations where SPMI address mapping is required without the need for IRQ support. Signed-off-by: David Collins Signed-off-by: Fenglin Wu --- drivers/spmi/spmi-pmic-arb.c | 45 +++++++++++++++++++++++++++----------------- 1 file changed, 28 insertions(+), 17 deletions(-) diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c index 39f25bc..0496e5d 100644 --- a/drivers/spmi/spmi-pmic-arb.c +++ b/drivers/spmi/spmi-pmic-arb.c @@ -1386,10 +1386,12 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev) goto err_put_ctrl; } - pmic_arb->irq = platform_get_irq_byname(pdev, "periph_irq"); - if (pmic_arb->irq < 0) { - err = pmic_arb->irq; - goto err_put_ctrl; + if (of_find_property(pdev->dev.of_node, "interrupt-controller", NULL)) { + pmic_arb->irq = platform_get_irq_byname(pdev, "periph_irq"); + if (pmic_arb->irq < 0) { + err = pmic_arb->irq; + goto err_put_ctrl; + } } err = of_property_read_u32(pdev->dev.of_node, "qcom,channel", &channel); @@ -1449,17 +1451,22 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev) } } - dev_dbg(&pdev->dev, "adding irq domain\n"); - pmic_arb->domain = irq_domain_add_tree(pdev->dev.of_node, - &pmic_arb_irq_domain_ops, pmic_arb); - if (!pmic_arb->domain) { - dev_err(&pdev->dev, "unable to create irq_domain\n"); - err = -ENOMEM; - goto err_put_ctrl; + if (pmic_arb->irq > 0) { + dev_dbg(&pdev->dev, "adding irq domain\n"); + pmic_arb->domain = irq_domain_add_tree(pdev->dev.of_node, + &pmic_arb_irq_domain_ops, pmic_arb); + if (!pmic_arb->domain) { + dev_err(&pdev->dev, "unable to create irq_domain\n"); + err = -ENOMEM; + goto err_put_ctrl; + } + + irq_set_chained_handler_and_data(pmic_arb->irq, + pmic_arb_chained_irq, pmic_arb); + } else { + dev_dbg(&pdev->dev, "not supporting PMIC interrupts\n"); } - irq_set_chained_handler_and_data(pmic_arb->irq, pmic_arb_chained_irq, - pmic_arb); err = spmi_controller_add(ctrl); if (err) goto err_domain_remove; @@ -1467,8 +1474,10 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev) return 0; err_domain_remove: - irq_set_chained_handler_and_data(pmic_arb->irq, NULL, NULL); - irq_domain_remove(pmic_arb->domain); + if (pmic_arb->irq > 0) { + irq_set_chained_handler_and_data(pmic_arb->irq, NULL, NULL); + irq_domain_remove(pmic_arb->domain); + } err_put_ctrl: spmi_controller_put(ctrl); return err; @@ -1479,8 +1488,10 @@ static int spmi_pmic_arb_remove(struct platform_device *pdev) struct spmi_controller *ctrl = platform_get_drvdata(pdev); struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl); spmi_controller_remove(ctrl); - irq_set_chained_handler_and_data(pmic_arb->irq, NULL, NULL); - irq_domain_remove(pmic_arb->domain); + if (pmic_arb->irq > 0) { + irq_set_chained_handler_and_data(pmic_arb->irq, NULL, NULL); + irq_domain_remove(pmic_arb->domain); + } spmi_controller_put(ctrl); return 0; } From patchwork Tue Dec 21 07:20:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenglin Wu X-Patchwork-Id: 12692043 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C1D54C433F5 for ; Tue, 21 Dec 2021 07:21:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235089AbhLUHVc (ORCPT ); Tue, 21 Dec 2021 02:21:32 -0500 Received: from alexa-out.qualcomm.com ([129.46.98.28]:17256 "EHLO alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232712AbhLUHV2 (ORCPT ); Tue, 21 Dec 2021 02:21:28 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1640071288; x=1671607288; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=Ht5tFAx/b0oY9oX+FB+kzZOocBM2sta/Sgzs8nZLw/o=; b=tdhuhzpjcFvRw3m+Zr/T3b5yu4Qfnl80CkuK/NPoq0P3mzUqyFgSO70j t1tv3+axezVYjvYKHFafirbPhwsTA2TBid0xCCDicItJ1ADj48qh7fRtF 4UvmY+t4Yf4qE8JwzzjNziSrxnHWEiM6/8Q65DaevtHl3m40zqr1DRAKJ 4=; Received: from ironmsg-lv-alpha.qualcomm.com ([10.47.202.13]) by alexa-out.qualcomm.com with ESMTP; 20 Dec 2021 23:21:22 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg-lv-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Dec 2021 23:21:16 -0800 Received: from nalasex01c.na.qualcomm.com (10.47.97.35) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Mon, 20 Dec 2021 23:21:16 -0800 Received: from fenglinw-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Mon, 20 Dec 2021 23:21:13 -0800 From: Fenglin Wu To: , , CC: , , , , Subject: [PATCH v4 10/11] spmi: pmic-arb: increase SPMI transaction timeout delay Date: Tue, 21 Dec 2021 15:20:08 +0800 Message-ID: <1640071211-31462-11-git-send-email-quic_fenglinw@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1640071211-31462-1-git-send-email-quic_fenglinw@quicinc.com> References: <1640071211-31462-1-git-send-email-quic_fenglinw@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: David Collins Increase the SPMI transaction timeout delay from 100 us to 1000 us in order to account for the slower execution time found on some simulator targets. Signed-off-by: David Collins Signed-off-by: Fenglin Wu --- drivers/spmi/spmi-pmic-arb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c index 0496e5d..45f9344 100644 --- a/drivers/spmi/spmi-pmic-arb.c +++ b/drivers/spmi/spmi-pmic-arb.c @@ -91,7 +91,7 @@ enum pmic_arb_channel { /* Maximum number of support PMIC peripherals */ #define PMIC_ARB_MAX_PERIPHS 512 -#define PMIC_ARB_TIMEOUT_US 100 +#define PMIC_ARB_TIMEOUT_US 1000 #define PMIC_ARB_MAX_TRANS_BYTES (8) #define PMIC_ARB_APID_MASK 0xFF From patchwork Tue Dec 21 07:20:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenglin Wu X-Patchwork-Id: 12692044 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97188C433FE for ; Tue, 21 Dec 2021 07:21:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235026AbhLUHVi (ORCPT ); Tue, 21 Dec 2021 02:21:38 -0500 Received: from alexa-out.qualcomm.com ([129.46.98.28]:17256 "EHLO alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232272AbhLUHVh (ORCPT ); Tue, 21 Dec 2021 02:21:37 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1640071297; x=1671607297; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=BXUd5mLERRNpJA7Tv/2hWsmJChcJtiZEKnhjjQqT8yM=; b=jlPQHx+MVwfQ8hYDZZqeegcw5G/Zzbk9+MbJQRfX/c6imv32L2ImVR3k wzN2wh4S1jZ7wBPGRS369mR6gTW4Mas3yBtgrGoMlLqXPpTPiJkY5ppvA z4ATySzD371p3A61RXHZlnd4eY3eAFw+7Pk3XrVmv+V75xIZAkktLT+9H M=; Received: from ironmsg08-lv.qualcomm.com ([10.47.202.152]) by alexa-out.qualcomm.com with ESMTP; 20 Dec 2021 23:21:37 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg08-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Dec 2021 23:21:36 -0800 Received: from nalasex01c.na.qualcomm.com (10.47.97.35) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Mon, 20 Dec 2021 23:21:36 -0800 Received: from fenglinw-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Mon, 20 Dec 2021 23:21:32 -0800 From: Fenglin Wu To: , , , Andy Gross , Bjorn Andersson , Rob Herring , Fenglin Wu , Subbaraman Narayanamurthy , CC: , , , Subject: [PATCH v4 11/11] dt-bindings: convert qcom,spmi-pmic-arb binding to YAML format Date: Tue, 21 Dec 2021 15:20:09 +0800 Message-ID: <1640071211-31462-12-git-send-email-quic_fenglinw@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1640071211-31462-1-git-send-email-quic_fenglinw@quicinc.com> References: <1640071211-31462-1-git-send-email-quic_fenglinw@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Convert the SPMI PMIC arbiter documentation to JSON/yaml. Signed-off-by: Fenglin Wu --- .../bindings/spmi/qcom,spmi-pmic-arb.txt | 67 ---------- .../bindings/spmi/qcom,spmi-pmic-arb.yaml | 146 +++++++++++++++++++++ 2 files changed, 146 insertions(+), 67 deletions(-) delete mode 100644 Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt create mode 100644 Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.yaml diff --git a/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt b/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt deleted file mode 100644 index 6332507..0000000 --- a/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt +++ /dev/null @@ -1,67 +0,0 @@ -Qualcomm SPMI Controller (PMIC Arbiter) - -The SPMI PMIC Arbiter is found on Snapdragon chipsets. It is an SPMI -controller with wrapping arbitration logic to allow for multiple on-chip -devices to control a single SPMI master. - -The PMIC Arbiter can also act as an interrupt controller, providing interrupts -to slave devices. - -See Documentation/devicetree/bindings/spmi/spmi.yaml for the generic SPMI -controller binding requirements for child nodes. - -See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt for -generic interrupt controller binding documentation. - -Required properties: -- compatible : should be "qcom,spmi-pmic-arb". -- reg-names : must contain: - "core" - core registers - "intr" - interrupt controller registers - "cnfg" - configuration registers - Registers used only for V2 PMIC Arbiter: - "chnls" - tx-channel per virtual slave registers. - "obsrvr" - rx-channel (called observer) per virtual slave registers. - -- reg : address + size pairs describing the PMIC arb register sets; order must - correspond with the order of entries in reg-names -- #address-cells : must be set to 2 -- #size-cells : must be set to 0 -- qcom,ee : indicates the active Execution Environment identifier (0-5) -- qcom,channel : which of the PMIC Arb provided channels to use for accesses (0-5) - -Optional properties: -- interrupts : interrupt list for the PMIC Arb controller, must contain a - single interrupt entry for the peripheral interrupt -- interrupt-names : corresponding interrupt names for the interrupts - listed in the 'interrupts' property, must contain: - "periph_irq" - summary interrupt for PMIC peripherals -- interrupt-controller : boolean indicator that the PMIC arbiter is an interrupt controller -- #interrupt-cells : must be set to 4. Interrupts are specified as a 4-tuple: - cell 1: slave ID for the requested interrupt (0-15) - cell 2: peripheral ID for requested interrupt (0-255) - cell 3: the requested peripheral interrupt (0-7) - cell 4: interrupt flags indicating level-sense information, as defined in - dt-bindings/interrupt-controller/irq.h - -Example: - - spmi { - compatible = "qcom,spmi-pmic-arb"; - reg-names = "core", "intr", "cnfg"; - reg = <0xfc4cf000 0x1000>, - <0xfc4cb000 0x1000>, - <0xfc4ca000 0x1000>; - - interrupt-names = "periph_irq"; - interrupts = <0 190 0>; - - qcom,ee = <0>; - qcom,channel = <0>; - - #address-cells = <2>; - #size-cells = <0>; - - interrupt-controller; - #interrupt-cells = <4>; - }; diff --git a/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.yaml b/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.yaml new file mode 100644 index 0000000..df8cfb7 --- /dev/null +++ b/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.yaml @@ -0,0 +1,146 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spmi/qcom,spmi-pmic-arb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SPMI PMIC Arbiter + +maintainers: + - Fenglin Wu + - Subbaraman Narayanamurthy + +description: | + The SPMI PMIC Arbiter is found on Snapdragon chipsets. It is an SPMI + controller with wrapping arbitration logic to allow for multiple + on-chip devices to control a single SPMI master. + + The PMIC Arbiter can also act as an interrupt controller, providing + interrupts to slave devices. + + See Documentation/devicetree/bindings/spmi/spmi.yaml for the generic + SPMI controller binding requirements for child nodes. + +allOf: + - $ref: spmi.yaml# + +properties: + $nodename: + pattern: "^spmi@.*" + + compatible: + const: qcom,spmi-pmic-arb + + reg-names: + $ref: /schemas/types.yaml#/definitions/string-array + anyOf: + - minItems: 3 + - maxItems: 3 + - enum: ["core", "intr", "cnfg"] + + - minItems: 5 + - maxItems: 5 + - enum: ["core", "intr", "cnfg", "chnls", "obsrvr"] + + reg: + minItems: 3 + maxItems: 5 + description: | + Specifies base physical address and size of the registers in SPMI PMIC + Arbiter HW module, with the following order. + - SPMI PMIC arbiter core registers (core) + - SPMI PMIC arbiter interrupt controller registers (intr) + - SPMI PMIC arbiter configuration registers (cnfg) + - SPMI PMIC arbiter tx-channel per virtual slave registers (chnls) + - SPMI PMIC arbiter rx-channel per virtual slave registers (obsrvr). + Register for "chnls" and "obsrvr" are only applicable for PMIC arbiter + with HW version greater than V2. + + "#address-cells": + const: 2 + + "#size-cells": + const: 0 + + interrupts: + description: The summary interrupt for the PMIC Arb controller. + maxItems: 1 + + interrupt-names: + const: periph_irq + + interrupt-controller: true + + "#interrupt-cells": + const: 4 + description: | + Specifies the number of cells needed to encode any interrupt source. + The 1st cell is the slave ID for the requested interrupt, its valid + range is [0-15]. + The 2nd cell is the peripheral ID for requested interrupt, its valid + range is [0-255]. + The 3rd cell is the requested peripheral interrupt, its valid range + is [0-7]. + The 4th cell is interrupt flags indicating level-sense information, + as defined in dt-bindings/interrupt-controller/irq.h + + qcom,ee: + description: the active Execution Environment identifier + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3, 4, 5] + + qcom,channel: + description: which of the PMIC Arbiter provided channels to use for accesses + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3, 4, 5] + +patternProperties: + "@[0-9a-f]$": + description: up to 16 child PMIC nodes + type: object + + properties: + reg: + items: + - minItems: 1 + items: + - minimum: 0 + maximum: 0xf + - enum: [ 0 ] + description: + 0 means user ID address. 1 is reserved for group ID + address. + + required: + - reg + +required: + - compatible + - reg-names + - reg + - "#address-cells" + - "#size-cells" + - qcom,ee + - qcom,channel + +additionalProperties: false + +examples: + - | + spmi@fc4cf000 { + compatible = "qcom,spmi-pmic-arb"; + reg-names = "core", "intr", "cnfg"; + reg = <0xfc4cf000 0x1000>, + <0xfc4cb000 0x1000>, + <0xfc4ca000 0x1000>; + interrupt-names = "periph_irq"; + interrupts = <0 190 0>; + interrupt-controller; + #interrupt-cells = <4>; + + qcom,ee = <0>; + qcom,channel = <0>; + + #address-cells = <2>; + #size-cells = <0>; + };