From patchwork Sat Nov 13 02:43:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 12692477 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 339C1C433EF for ; Sat, 13 Nov 2021 02:47:39 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0285260FBF for ; Sat, 13 Nov 2021 02:47:38 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 0285260FBF Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=rhA7pY3t9Oqdy0hZZ1fpAUH7bJeBuEA8eyfsXxvbCCA=; b=yOhzD4AgQngIS5 8DQeMQajh0slOXhv6+GxKIsq4r3A1t8mIjMO+AaJwtyVR0xQ8JV5/EuJwGqU8sdJgXv8rpbQb+q6O C+yN33Xeiju7ICiO47/WxFqNOxky6PS+aWF6Q1tpQNBr9m703CkF66sm8kGTyzz/hmpHJ8gvtRY2i TXOgYXkLVWUjcHTRgfg++Ws4L6Pk4H1uaI6x+V1eVr9PopCXSbeYVcI8zHmh4liOrIEfJQnF680yk 4atIjzgLVBiwOw0KjkmA3mwaGuYQgcdEtpxgkrVKNSTffRa3Xklp3i91Sz6RB5q3B9q5W/iq1oLbd XsGlY7W0UsuEuef/i+Ow==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mlj2w-00C4JZ-2A; Sat, 13 Nov 2021 02:45:38 +0000 Received: from fllv0016.ext.ti.com ([198.47.19.142]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mlj2r-00C4Iv-09 for linux-arm-kernel@lists.infradead.org; Sat, 13 Nov 2021 02:45:36 +0000 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 1AD2hn8W013163; Fri, 12 Nov 2021 20:43:49 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1636771429; bh=mhr8E9T4/nfsYQVYgx7OTXivgSgiT+8i+vo9IYLf+YY=; h=From:To:CC:Subject:Date; b=uaDWQc/kDocfHQnEV95+Choi3i8YXEXg88nOzLxrqyLZ4VU2JHUIeR0M41c+BMc0y 1zEDU2c4+Zu0l+RzR/giE9YiRKbyFzBxut2W+m8EsVOWpu7xCkGfXcPXzFnfg+oDAf 92U7+Mr016wctSzSZl3V0zljX65FxR98h+tsvFUk= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 1AD2hn79109998 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 12 Nov 2021 20:43:49 -0600 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Fri, 12 Nov 2021 20:43:49 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Fri, 12 Nov 2021 20:43:49 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 1AD2hnY0110243; Fri, 12 Nov 2021 20:43:49 -0600 From: Nishanth Menon To: Rob Herring , Tero Kristo , Vignesh Raghavendra CC: , , , Nishanth Menon , , Peng Fan Subject: [PATCH] arm64: dts: k3-j7200: Correct the d-cache-sets info Date: Fri, 12 Nov 2021 20:43:48 -0600 Message-ID: <20211113024348.29257-1-nm@ti.com> X-Mailer: git-send-email 2.32.0 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211112_184533_110903_53A22EBC X-CRM114-Status: GOOD ( 10.56 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org A72 Cluster (chapter 1.3,1 [1]) has 48KB Icache, 32KB Dcache and 1MB L2 Cache - ICache is 3-way set-associative - Dcache is 2-way set-associative - Line size are 64bytes 32KB (Dcache)/64 (fixed line length of 64 bytes) = 512 ways 512 ways / 2 (Dcache is 2-way per set) = 256 sets. So, correct the d-cache-sets info. [1] https://www.ti.com/lit/pdf/spruiu1 Fixes: d361ed88455f ("arm64: dts: ti: Add support for J7200 SoC") Reported-by: Peng Fan Signed-off-by: Nishanth Menon Reviewed-by: Kishon Vijay Abraham I --- arch/arm64/boot/dts/ti/k3-j7200.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi index 47567cb260c2..958587d3a33d 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi @@ -62,7 +62,7 @@ cpu0: cpu@0 { i-cache-sets = <256>; d-cache-size = <0x8000>; d-cache-line-size = <64>; - d-cache-sets = <128>; + d-cache-sets = <256>; next-level-cache = <&L2_0>; }; @@ -76,7 +76,7 @@ cpu1: cpu@1 { i-cache-sets = <256>; d-cache-size = <0x8000>; d-cache-line-size = <64>; - d-cache-sets = <128>; + d-cache-sets = <256>; next-level-cache = <&L2_0>; }; };