From patchwork Thu Nov 18 18:46:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 12693070 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05775C433F5 for ; Thu, 18 Nov 2021 18:48:59 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B3AF561101 for ; Thu, 18 Nov 2021 18:48:58 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org B3AF561101 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=gIEXrj1QBmF7l4pH14hA5wITllemvK3IoUeXuIJgo04=; b=GY6RfKENl0nAJF nJ0QMk6wq6HMsGG+jDx0QiOxMG9EO+gBnLK/XHEn/9kdeLqpY3G0DrHTIMVaa7LkiDPHBIKwdMzD4 zxps60kiWzkh3dP00Ntk8h98q9zughOPdOCVKbXDqS2Iw7B5z71S0XE5H5ngJ9Ng+wziGiqnV3gRL FceNfjM9YoQ95yHdjTbgwnmXgejea0jtj1SZCJ8Hp8FcAwMvf35it0D11NNCTur8vTWFKnN/PI1SQ NF67e3ySBilpTKYoWUPkNrRKMHn2drcfnQJNHH2+m1unRgpgJwesf/LWaOb5ztOpMFH7lXFjuTeIq EBP5x5xMJ8CnM2+8uAGA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mnmRb-008d4k-Mi; Thu, 18 Nov 2021 18:47:35 +0000 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mnmR1-008cuG-6Z for linux-arm-kernel@lists.infradead.org; Thu, 18 Nov 2021 18:47:00 +0000 Received: by mail-wr1-x429.google.com with SMTP id d24so13498959wra.0 for ; Thu, 18 Nov 2021 10:46:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FbAh+aztF0zh2yPX+S7IKVelQO7NqMfexMVIl0szM/Q=; b=dKTCZqGr5BEyXulWz04B3VqIQibV6GuezrZHpHVmtIMOLiasDW+K4vSFElaAkUpH1W 7o4deOFOMy/+LnRBRHXXr/q8me3q6o900zSJ0u4zHpw3BlkRO7QYo9d/LMt0F4XSEtf1 8b7pm5Mgd+tvJhilUfDAC6h4e0IiQ7tr92FGj0Je/C6vuxuqZ+Nb2uAMgpkO6fSS2E1f PoM+6pn8SFi6S2IQvHO5k78NkkNoOOQCAn3/xPJexhPL7a+qfSbWtUFH9MpOMwXZTufk R/8hGXhC1V+3N/pWUZkvfAppZxvuI0/6MUeYPlTNOgPDEDmA5mtQ6tQ92ZMkx6o0qKL/ lWIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FbAh+aztF0zh2yPX+S7IKVelQO7NqMfexMVIl0szM/Q=; b=p1yxLe2AQ/sKb2t46N4aD5xrDWrRG7/kOglvU7C7zCNULoZ4qvIijxLy/5Uh+b1qT7 itq75rpk8xGTf0Iev0j2G3AQoAezJ2RrJKUsfONTll5DCDPRC+Hrs0d8iMwKxFogOgM/ Umt4ej7tjCxP540NADfK0IoayfBdvIREmkNdOz/ERIN44n7SgClR/UvE1a1stMr/UrVU PcOH1WA9XzF4CdBfjkiavscic8qcv27QvEgESFx4VVQE55Edg4rpR23BKKrUzFSBQz8K AJFPTbgVhm8DV4DY+RwXJc84q6zgL0ZExwig8tbLU13W47jdyrCg7/SSZtaiqn0elFje tf+w== X-Gm-Message-State: AOAM530TxuB1JoQrCdXxHWArMWHrKs/y8DYvoK1eiRdlRIL46XmpG3I+ JMg9au6ssP2sqO02zQuvcqilkw== X-Google-Smtp-Source: ABdhPJwuqcWCq5OtkKnnGu4FzRENuBcr3VIuVBqyCASUcE2XGA1oVULFg2sKZDvp1S0mXlH38p+wWw== X-Received: by 2002:a5d:6447:: with SMTP id d7mr34905244wrw.118.1637261216576; Thu, 18 Nov 2021 10:46:56 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id c1sm644533wrt.14.2021.11.18.10.46.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Nov 2021 10:46:54 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 490751FF98; Thu, 18 Nov 2021 18:46:50 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: kvm@vger.kernel.org Cc: idan.horowitz@gmail.com, qemu-arm@nongnu.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, christoffer.dall@arm.com, maz@kernel.org, =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [kvm-unit-tests PATCH v8 01/10] docs: mention checkpatch in the README Date: Thu, 18 Nov 2021 18:46:41 +0000 Message-Id: <20211118184650.661575-2-alex.bennee@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211118184650.661575-1-alex.bennee@linaro.org> References: <20211118184650.661575-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211118_104659_270761_30ED330E X-CRM114-Status: GOOD ( 10.35 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Signed-off-by: Alex Bennée Acked-by: Andrew Jones --- README.md | 2 ++ 1 file changed, 2 insertions(+) diff --git a/README.md b/README.md index b498aaf..5db48e5 100644 --- a/README.md +++ b/README.md @@ -182,3 +182,5 @@ the code files. We also start with common code and finish with unit test code. git-diff's orderFile feature allows us to specify the order in a file. The orderFile we use is `scripts/git.difforder`; adding the config with `git config diff.orderFile scripts/git.difforder` enables it. + +Please run the kernel's ./scripts/checkpatch.pl on new patches From patchwork Thu Nov 18 18:46:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 12693069 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B20EDC433F5 for ; Thu, 18 Nov 2021 18:48:45 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8315B61A0D for ; Thu, 18 Nov 2021 18:48:45 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 8315B61A0D Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=2u7Bv6G+3pQYisx0MhKHcfCKHk5zyGZ5LdbB972bHGI=; b=alNMjrD+P3PQQR 3nzpHhxg2uAZJmYY4EVz67CWjA66j0l7RAtO8TiVEA8UiuXIw1HanA2zaNLYuhWyC6dCBBOrswJmD LFUcSXc11v/BOnJexYZ2jh9NDVUnkVL7aAG6I10jzY8QaR03/aozwRArwhMHExzhDDk4kyvmLQjiE 5V8VY/ihQAcAbI3BjNY9mgjpzGWA2B9XLRqyKB9wNMibvcz8z/O59ins175HccDCeswT0Es4EyBvC Rp2YD9sy4hUSK//nA6Cn8HICsWeyFlOjITqTuaoF7pw6AZ3qJ1fa4+/XDymwUFXkvGp+kvPSXW7o+ TMzvHqRxt7A2PenVk+Ww==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mnmRP-008d2D-NO; Thu, 18 Nov 2021 18:47:23 +0000 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mnmQy-008ctE-J8 for linux-arm-kernel@lists.infradead.org; Thu, 18 Nov 2021 18:46:57 +0000 Received: by mail-wm1-x335.google.com with SMTP id o29so6256029wms.2 for ; Thu, 18 Nov 2021 10:46:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tOmySd5ZdC4WjR5pqWQluHQkWraboy7ZlqKYZZCFjto=; b=odLpz8EZ1vyqBAm0rFDZYV49GrwMKDvbxKQ+SyB2aLw0WE8TCSj/Bcy2Xe+Hmz9Yt3 LhghE7I8TGtpPFT7Sx+h6c0SFZZZqdRuXFVetqaah8ct5fZeP9NLx1w16f9tf5UHFOap Q6LFGeNlkOa9WLERkzmi4vtzJNU8HSygywuPF3ynjMS1c3lsHDwQQGA/QbdCC43OICgM MUBL/rYK2YWxE1utNrG4cJLqyQmNClwBwhzWgzZXcZTHVmqV9D0zmd5Qfqirl2QVqrks bJgSkgaPxF7pqt4M3r/afE2djzrsEJS4xQkH+3X9L76mX6e3eOJvbogjrENFed54AwbF /wEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tOmySd5ZdC4WjR5pqWQluHQkWraboy7ZlqKYZZCFjto=; b=6BhgOeq0XbaiCRBVYfi0WpK1TrlOPUM0YmwRKrO54x0LhMaBpZdUJ7AqSHdJ4WXAOF uB8zukTeS1BAqOGXTcuEZYDLZJ+ERe9fbWsEiwiCanHROgb+dTKU2qjNojKbchu1uSXc fJcDE1mLMFzPlPXYZaeLnWexpTUwHk3hjeDmJ0epREkv/7V5VbRt0pFR1tuML4wuM6hr uOIKNgRDgQkRmThyRsqM7zl1fL20EIX5SDU6useV3iXWaPXsSqf9R4Y5pY5tpC4Yc7lp MR2jAFTSS30lYAIjS5MqDK/tBhlOg5LQumG71xDuevaj/YBYBYNugcwU2SkJ9Tg6EiN1 G4Mw== X-Gm-Message-State: AOAM532qJrTTJ8T9fxaEYljp4A6dlmi7nYOe2hd+rImCgU4vwuMFgiOa 9ILLhJye/HHG6cdsj2LXQ4nMSA== X-Google-Smtp-Source: ABdhPJyHr89MEcvcKNNgqQkU7LLmSsVqr9xPkXN6m1nHufZRRPmyHO/j2xfEPRMZ4+sIHj9mgtlOow== X-Received: by 2002:a05:600c:4e01:: with SMTP id b1mr12398367wmq.109.1637261214762; Thu, 18 Nov 2021 10:46:54 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id n129sm464676wmn.36.2021.11.18.10.46.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Nov 2021 10:46:50 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 4A7EF1FF99; Thu, 18 Nov 2021 18:46:50 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: kvm@vger.kernel.org Cc: idan.horowitz@gmail.com, qemu-arm@nongnu.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, christoffer.dall@arm.com, maz@kernel.org, =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [kvm-unit-tests PATCH v8 02/10] arm/flat.lds: don't drop debug during link Date: Thu, 18 Nov 2021 18:46:42 +0000 Message-Id: <20211118184650.661575-3-alex.bennee@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211118184650.661575-1-alex.bennee@linaro.org> References: <20211118184650.661575-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211118_104656_662648_F48AEB62 X-CRM114-Status: GOOD ( 11.79 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org It is useful to keep the debug in the .elf file so we can debug and it doesn't get copied across to the final .flat file. Of course we still need to ensure we apply the offset when we load the symbols based on where QEMU decided to load the kernel. (gdb) symbol-file ./builds/arm64/arm/tlbflush-data.elf -o 0x40080000 Signed-off-by: Alex Bennée --- arm/flat.lds | 1 - 1 file changed, 1 deletion(-) diff --git a/arm/flat.lds b/arm/flat.lds index 6fb459e..47fcb64 100644 --- a/arm/flat.lds +++ b/arm/flat.lds @@ -62,7 +62,6 @@ SECTIONS /DISCARD/ : { *(.note*) *(.interp) - *(.debug*) *(.comment) *(.dynamic) } From patchwork Thu Nov 18 18:46:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 12693067 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CAF25C4332F for ; Thu, 18 Nov 2021 18:48:27 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9B35461101 for ; Thu, 18 Nov 2021 18:48:27 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 9B35461101 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=BWeDbDU9Dor+UCWn30WDAXzTg93Y4AeDAxZne3phTzc=; b=mzi3Eq+EXp4bs6 UVWH1ZsOfp2lHjtjFgdWE1X0z/9sMNdfj6hl+5HVkJw3HSQdtEXZ1Rqg8zpELpuI3lXOIY9+wFD8D l8G6xloalLrOl3sm7SUmqpsKS27s5jgFG1F5Cw644N1pfYxIiJQZ6jrUIG1NXZrnCdJgazMPv3i7E OSuZ1NoL9rlisJjCK/B4/lIat9TiPJs8DbpE7EQlnwdy4cfZKMoZaDih9orBrzNen4uLk4Dui47NL kPdpBJYHmmn7YtvVIBfr6vgB79QJrewUzcV2bYi1oC5eIeBwhlbcRA+vswsmrmJFqXVixT4cY6DD0 XsEc/1ySCCQOmar3+WZg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mnmR0-008cuO-EI; Thu, 18 Nov 2021 18:46:58 +0000 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mnmQx-008csu-8S for linux-arm-kernel@lists.infradead.org; Thu, 18 Nov 2021 18:46:56 +0000 Received: by mail-wm1-x331.google.com with SMTP id y196so6247162wmc.3 for ; Thu, 18 Nov 2021 10:46:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=N1TD+o6fA2jwMAGGm9K/LhqxPmEtAnkZjhJNXEULmUk=; b=OZ+0ycbkYM32+k3qsnQBx40UB+HQWYrf4ClPvT9L+GaXRo74oIjcfnG8tB2nzPRVUY MK0WqQiXpqYCXs+/HVInv8n6a3FB5TqhV55wnN8ET4JFpkolVeEHwW2rXqwADhwJyhQU dhkS7OnJKDDDDqhUuwZSW7rcWltcnbgqDhZsIHy+cBFzhXu90XSEB0kOSoFTwG87WC64 nwfj2Zlr8ySTd99Z/TSoNnKZJvpfd8BU3Vc+zhM3ucXjuJTUTsZnXy+6wSYVxUPuq3ms M2w2fwo+xzjA+7N3KUJ4j800daGm7Npqu8dt6FFkdR9ur3B6aauwHp1Hb6Ar7WympXyE R8OA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=N1TD+o6fA2jwMAGGm9K/LhqxPmEtAnkZjhJNXEULmUk=; b=iljvuB5V2g3mF0jZWAyUta1JWY/qWqNuTpiFHpdods8CgRbVswX4Vnc0L4O00wb8Ip JEnxZaZxC2J5WPya+rTsqvECoGk2tzOQgWBwZVWD4b1ZGhyqEh88OLxBd1LbnYuaMmX3 gj8D4oRCof7g8srlhdNhA1it1esNvSftrBwiG5BDo5FpTpI6dfUqyEmKIWIElYno0/wB ErzcnqEhu1vz6/T+o1cIJQIyi7XtqyMMCrNoW2PmQE2K3AZRt8pXGCleBks7hUVXTd1U aKj0guRY7ISr9R2HpSz/L6yJZ9b5T2ie5NWb3Lmo9aGXYMWE0BhOjTu+OINYmYvTvZhl pq6w== X-Gm-Message-State: AOAM5336qeWUMjg3K15iF5JAs5zS2WfZi5YIUNMM0RRodQABuz/VH3OL aJrlYoEvhI3Hf3Ypu5LwW4ssi5cw04v8Cw== X-Google-Smtp-Source: ABdhPJwla25wllkelCSuqSunInape1qck1sRu6PWmBGXbmmbMp7JZz+bf9KnvBlWv5Jc/4k8cdhsXg== X-Received: by 2002:a05:600c:1c20:: with SMTP id j32mr12131735wms.1.1637261212696; Thu, 18 Nov 2021 10:46:52 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id n1sm655518wmq.6.2021.11.18.10.46.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Nov 2021 10:46:50 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 56B171FF9A; Thu, 18 Nov 2021 18:46:50 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: kvm@vger.kernel.org Cc: idan.horowitz@gmail.com, qemu-arm@nongnu.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, christoffer.dall@arm.com, maz@kernel.org, =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [kvm-unit-tests PATCH v8 03/10] Makefile: add GNU global tags support Date: Thu, 18 Nov 2021 18:46:43 +0000 Message-Id: <20211118184650.661575-4-alex.bennee@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211118184650.661575-1-alex.bennee@linaro.org> References: <20211118184650.661575-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211118_104655_318428_96766167 X-CRM114-Status: GOOD ( 11.07 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org If you have ctags you might as well offer gtags as a target. Signed-off-by: Alex Bennée --- Makefile | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index b80c31f..0b7c03a 100644 --- a/Makefile +++ b/Makefile @@ -122,6 +122,9 @@ cscope: -name '*.[chsS]' -exec realpath --relative-base=$(CURDIR) {} \; | sort -u > ./cscope.files cscope -bk -.PHONY: tags +.PHONY: tags gtags tags: ctags -R + +gtags: + gtags From patchwork Thu Nov 18 18:46:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 12693071 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4EF25C433F5 for ; Thu, 18 Nov 2021 18:49:21 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1A53A61AD2 for ; Thu, 18 Nov 2021 18:49:21 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 1A53A61AD2 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=qPUTHjonPlOSVSPKzAimVpB8dqkSa65Pi+bQl8ePU80=; b=G2Fn7o23qhzAFi 8AjvRUlmuo+fsQhFy2Wm55VanIpt6Z1eDtC5LCk3l0F2sfvBirXlxo/yinU/02UMVSZLkigqSEUKT Q5NHttzlhVmekVHq7dpk+jor4lyVhkkTy+s7V7/dUUy5B8aV64Z0/5nS/eoGSIwUzpUqZkhmkEcIH zD4VGYdD2jSWo8RNU1cfRC+OzdqumfuTze2+YNhOzjb/CVWTYB0fRXIXZ8o3eiqgUOARafiZwj7gn OdYCkWsJ7zLHBM0blXU79C/76X3+vSVSBMOrfSAbW84XVr9itAj9T/EzPO9pF5ypzaZp7Bmu7Kzhp tFGErI5JZrCtUV5ekAvg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mnmRp-008d90-Md; Thu, 18 Nov 2021 18:47:49 +0000 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mnmR1-008cun-Iz for linux-arm-kernel@lists.infradead.org; Thu, 18 Nov 2021 18:47:01 +0000 Received: by mail-wm1-x32b.google.com with SMTP id n33-20020a05600c502100b0032fb900951eso8438205wmr.4 for ; Thu, 18 Nov 2021 10:46:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eaPUXaq41WZH/h6GYRFaezaVsEA4ttJDyJAW7JSISJY=; b=F2gHMH6vwR4xvqpoXWpgXJXoDksN1UxSEkEmbqmlD8hyupOtNFO3mGg1RFg2TX62I0 xaVKX0aL2NMGzFQ7eMYjleeolRXafF/TqwYxwneEasRcGVHXl9epK3WPRzqcTmi+iari 8D1slSEtOH3Kcb+9lMZCC5DUr/4MEXsoYBE5MKGETfA15XQ6FsHrOCcgkCH8hu/Ar5LW w+aYUP1y+h/3dKHWBAedUL1pTKEzA2KvVoU2gHvciE3OMO5GFXa9/4ysbEzpyvaNQaO/ BibROcRlDz9v5WAQZTmIZvB17dBLXL1BiGJytnG6W9zHQHW0EGbhak1/43tvnoirJFAe wCNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eaPUXaq41WZH/h6GYRFaezaVsEA4ttJDyJAW7JSISJY=; b=zIWRkbhVm+lBiPHoRaWl/tGp5L00burnN09OJl4OOUcJU3IbNJZ0SUQCdVdSUMbuKQ 0WGxccde4PRJ/XJhbpduJDR9f//KuolDKHWVChxpSUTAmJuKr1gGFYAgcbj5+I2yDr9q t3EAr+yc5JoAJHyPTbgc7XuwtqslsedPus0FdnSWeuLSw3UNqjXP0DuQZUnKTvhZpVow 8MepIeLDNmqEqityIoCdWfKsp4VhZnnWunmUiYZ1ugFBFdoKbEhzn6EiqdHc+PGprlyG 2S1EWSLT0H9ZecEaLCx3Gyr4lAZZbUCPwOQRWy1YhpfkeoXNbMXOdjMS+1OJofZ8Q1uG o4KQ== X-Gm-Message-State: AOAM531Ew5CCSiDxGYprlcglGo/TyAjcteo6lQ5PCziLqNyt78tO43eL lyTe9NEr3s0cbluVcpoV6PgkZA== X-Google-Smtp-Source: ABdhPJxi0gHTPCkCLhwz4sZpESe0ZsiFVHaJxtTlU8ot0566wwXQutX6kiYchOOZ+lORo2U9U57Iog== X-Received: by 2002:a1c:9a4f:: with SMTP id c76mr12329695wme.162.1637261217715; Thu, 18 Nov 2021 10:46:57 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id q26sm654555wrc.39.2021.11.18.10.46.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Nov 2021 10:46:54 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 583341FF9B; Thu, 18 Nov 2021 18:46:50 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: kvm@vger.kernel.org Cc: idan.horowitz@gmail.com, qemu-arm@nongnu.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, christoffer.dall@arm.com, maz@kernel.org, =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [kvm-unit-tests PATCH v8 04/10] run_tests.sh: add --config option for alt test set Date: Thu, 18 Nov 2021 18:46:44 +0000 Message-Id: <20211118184650.661575-5-alex.bennee@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211118184650.661575-1-alex.bennee@linaro.org> References: <20211118184650.661575-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211118_104659_652830_452A9D32 X-CRM114-Status: GOOD ( 11.99 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The upcoming MTTCG tests don't need to be run for normal KVM unit tests so lets add the facility to have a custom set of tests. Signed-off-by: Alex Bennée --- run_tests.sh | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/run_tests.sh b/run_tests.sh index 9f233c5..b1088d2 100755 --- a/run_tests.sh +++ b/run_tests.sh @@ -15,7 +15,7 @@ function usage() { cat < X-Patchwork-Id: 12693075 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19C8EC433F5 for ; Thu, 18 Nov 2021 18:51:28 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D44BC61AFD for ; Thu, 18 Nov 2021 18:51:27 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org D44BC61AFD Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=idPmB/juqLiHLX6MldLaT2E6a+67Nuc90KkWN09GIdc=; b=AYRfTV/yxNlNoO K537K0UE72gHr31CYkzQ5fGWgyh/yYWAJWeVMUd5vOzcI3mKsIARWp7P+l6RETmmHHkHt7Va2clfL uI2AQXnz27W7TnCdD8fGsCr7Rv9G+XLrTNrdSGOh1ZtS64QfnppXE59xtzBEgPOm5LwaqmDXYHzUN Vamo1H4SF7D28vRRXcWsyzRKzDtrIfdTc/6toZ0c+K5NmoP1Ee9xnZTB3Mi5PRUM4qLdWh/hmjJ2a mwkKfxcSMof0EuC5z8OfFNT5XDjRwzbSPhFYQN6Y/BdafQtKLtgQR6zE52MuRZ498cUDusAuMkvuA EFxYgBcz/MsEnajoul3A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mnmTk-008e3k-BE; Thu, 18 Nov 2021 18:49:48 +0000 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mnmR7-008cwy-7X for linux-arm-kernel@lists.infradead.org; Thu, 18 Nov 2021 18:47:07 +0000 Received: by mail-wm1-x32f.google.com with SMTP id p3-20020a05600c1d8300b003334fab53afso8451161wms.3 for ; Thu, 18 Nov 2021 10:47:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hk3bzlKoxpZyDrrCE6PtbaVaXFgnlPYcxwsdlufAHz0=; b=I43S0rspR+9J8s4VPXSwP0qyAG5XgbNXHbzEd835vMuI7wuTMavLxF7tWdRLqOMS0y e59iO9k++LXYhBppdh31y+jrY77McfWBpeFfblKi+SHAMwp3O9C6UfOFH2vWzw99n0W2 Fdw7EYaEqtfZtIObXsnYWMYOdEn3gM0oiW0glfAzGKRuEETBfs0Tx1h3d/14eoL0Ah5G FGAOyCY3DSA6KazwWqVGE8YkG9pPRxJ1OhHQDVURFTtMPz37nA1d3MZV7ZQOjebdFXu/ 2TNnrkru4w3C8CiMDUm+zUGlIZyl5WZpJOINtNhePY8GX7fsplROp928dF2Qr7yKuRlB IE/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hk3bzlKoxpZyDrrCE6PtbaVaXFgnlPYcxwsdlufAHz0=; b=Yaf/Un+Ye1yawPIrQwXp4U12J8iwa6jRSnkQ14auxpfF87wmBrfevaJ4hYGmRQkI42 Lu2QoyEc5gAbBXhpybaqWeGtAru9xBYkOvpPAjBBLIblJ/0JUzDosdoHTPKPxLHu/XKg 5cyyE31gABvfL4Kaluoxt66/F5YirrGjoZ1YESoeF9trrNuANF8PmiNeRjLasMKmYSF6 /xvv2EjiykM6U78gztL7N90jus90chxEgudAMkKuM3mEQ5xJYkRuq/tXXrSyZgDyszlB P6YmsR2ByHgc/3DP48CPoxoT3tAfEJ/7mp0woEk4hFzsreQOv55LU916gUV9PHBCEB6L A+NA== X-Gm-Message-State: AOAM530D89yYvuAlGAGXb6ziZFZDKk0rUBxnhHOQDOc83i1zUj8R0P0A 6geQZvjE9rF+H3zf3Mu2EWqufA== X-Google-Smtp-Source: ABdhPJwenmIb9vjZ9kptMGO/3EYwW5+5ywUMVFwd1C+3xnaj5wrhMgI/Yra/+F6z1kZFHXsAdH4uSw== X-Received: by 2002:a7b:c257:: with SMTP id b23mr12531384wmj.67.1637261223275; Thu, 18 Nov 2021 10:47:03 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id s8sm697055wra.9.2021.11.18.10.46.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Nov 2021 10:46:55 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 64ADB1FF9C; Thu, 18 Nov 2021 18:46:50 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: kvm@vger.kernel.org Cc: idan.horowitz@gmail.com, qemu-arm@nongnu.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, christoffer.dall@arm.com, maz@kernel.org, =?utf-8?q?Alex_Benn=C3=A9e?= , "Timothy B . Terriberry" , Andrew Jones Subject: [kvm-unit-tests PATCH v8 05/10] lib: add isaac prng library from CCAN Date: Thu, 18 Nov 2021 18:46:45 +0000 Message-Id: <20211118184650.661575-6-alex.bennee@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211118184650.661575-1-alex.bennee@linaro.org> References: <20211118184650.661575-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211118_104705_366645_49DF556D X-CRM114-Status: GOOD ( 25.08 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org It's often useful to introduce some sort of random variation when testing several racing CPU conditions. Instead of each test implementing some half-arsed PRNG bring in a a decent one which has good statistical randomness. Obviously it is deterministic for a given seed value which is likely the behaviour you want. I've pulled in the ISAAC library from CCAN: http://ccodearchive.net/info/isaac.html I shaved off the float related stuff which is less useful for unit testing and re-indented to fit the style. The original license was CC0 (Public Domain) which is compatible with the LGPL v2 of kvm-unit-tests. Signed-off-by: Alex Bennée CC: Timothy B. Terriberry Acked-by: Andrew Jones --- arm/Makefile.common | 1 + lib/prng.h | 82 ++++++++++++++++++++++ lib/prng.c | 162 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 245 insertions(+) create mode 100644 lib/prng.h create mode 100644 lib/prng.c diff --git a/arm/Makefile.common b/arm/Makefile.common index 38385e0..99bcf3f 100644 --- a/arm/Makefile.common +++ b/arm/Makefile.common @@ -44,6 +44,7 @@ cflatobjs += lib/pci-testdev.o cflatobjs += lib/virtio.o cflatobjs += lib/virtio-mmio.o cflatobjs += lib/chr-testdev.o +cflatobjs += lib/prng.o cflatobjs += lib/arm/io.o cflatobjs += lib/arm/setup.o cflatobjs += lib/arm/mmu.o diff --git a/lib/prng.h b/lib/prng.h new file mode 100644 index 0000000..bf5776d --- /dev/null +++ b/lib/prng.h @@ -0,0 +1,82 @@ +/* + * PRNG Header + */ +#ifndef __PRNG_H__ +#define __PRNG_H__ + +# include + + + +typedef struct isaac_ctx isaac_ctx; + + + +/*This value may be lowered to reduce memory usage on embedded platforms, at + the cost of reducing security and increasing bias. + Quoting Bob Jenkins: "The current best guess is that bias is detectable after + 2**37 values for [ISAAC_SZ_LOG]=3, 2**45 for 4, 2**53 for 5, 2**61 for 6, + 2**69 for 7, and 2**77 values for [ISAAC_SZ_LOG]=8."*/ +#define ISAAC_SZ_LOG (8) +#define ISAAC_SZ (1< +#include "prng.h" + +#define ISAAC_MASK (0xFFFFFFFFU) + +/* Extract ISAAC_SZ_LOG bits (starting at bit 2). */ +static inline uint32_t lower_bits(uint32_t x) +{ + return (x & ((ISAAC_SZ-1) << 2)) >> 2; +} + +/* Extract next ISAAC_SZ_LOG bits (starting at bit ISAAC_SZ_LOG+2). */ +static inline uint32_t upper_bits(uint32_t y) +{ + return (y >> (ISAAC_SZ_LOG+2)) & (ISAAC_SZ-1); +} + +static void isaac_update(isaac_ctx *_ctx){ + uint32_t *m; + uint32_t *r; + uint32_t a; + uint32_t b; + uint32_t x; + uint32_t y; + int i; + m=_ctx->m; + r=_ctx->r; + a=_ctx->a; + b=_ctx->b+(++_ctx->c); + for(i=0;i>6)+m[i+ISAAC_SZ/2]; + m[i]=y=m[lower_bits(x)]+a+b; + r[i]=b=m[upper_bits(y)]+x; + x=m[++i]; + a=(a^a<<2)+m[i+ISAAC_SZ/2]; + m[i]=y=m[lower_bits(x)]+a+b; + r[i]=b=m[upper_bits(y)]+x; + x=m[++i]; + a=(a^a>>16)+m[i+ISAAC_SZ/2]; + m[i]=y=m[lower_bits(x)]+a+b; + r[i]=b=m[upper_bits(y)]+x; + } + for(i=ISAAC_SZ/2;i>6)+m[i-ISAAC_SZ/2]; + m[i]=y=m[lower_bits(x)]+a+b; + r[i]=b=m[upper_bits(y)]+x; + x=m[++i]; + a=(a^a<<2)+m[i-ISAAC_SZ/2]; + m[i]=y=m[lower_bits(x)]+a+b; + r[i]=b=m[upper_bits(y)]+x; + x=m[++i]; + a=(a^a>>16)+m[i-ISAAC_SZ/2]; + m[i]=y=m[lower_bits(x)]+a+b; + r[i]=b=m[upper_bits(y)]+x; + } + _ctx->b=b; + _ctx->a=a; + _ctx->n=ISAAC_SZ; +} + +static void isaac_mix(uint32_t _x[8]){ + static const unsigned char SHIFT[8]={11,2,8,16,10,4,8,9}; + int i; + for(i=0;i<8;i++){ + _x[i]^=_x[(i+1)&7]<>SHIFT[i]; + _x[(i+3)&7]+=_x[i]; + _x[(i+1)&7]+=_x[(i+2)&7]; + } +} + + +void isaac_init(isaac_ctx *_ctx,const unsigned char *_seed,int _nseed){ + _ctx->a=_ctx->b=_ctx->c=0; + memset(_ctx->r,0,sizeof(_ctx->r)); + isaac_reseed(_ctx,_seed,_nseed); +} + +void isaac_reseed(isaac_ctx *_ctx,const unsigned char *_seed,int _nseed){ + uint32_t *m; + uint32_t *r; + uint32_t x[8]; + int i; + int j; + m=_ctx->m; + r=_ctx->r; + if(_nseed>ISAAC_SEED_SZ_MAX)_nseed=ISAAC_SEED_SZ_MAX; + for(i=0;i<_nseed>>2;i++){ + r[i]^=(uint32_t)_seed[i<<2|3]<<24|(uint32_t)_seed[i<<2|2]<<16| + (uint32_t)_seed[i<<2|1]<<8|_seed[i<<2]; + } + _nseed-=i<<2; + if(_nseed>0){ + uint32_t ri; + ri=_seed[i<<2]; + for(j=1;j<_nseed;j++)ri|=(uint32_t)_seed[i<<2|j]<<(j<<3); + r[i++]^=ri; + } + x[0]=x[1]=x[2]=x[3]=x[4]=x[5]=x[6]=x[7]=0x9E3779B9U; + for(i=0;i<4;i++)isaac_mix(x); + for(i=0;in)isaac_update(_ctx); + return _ctx->r[--_ctx->n]; +} + +uint32_t isaac_next_uint(isaac_ctx *_ctx,uint32_t _n){ + uint32_t r; + uint32_t v; + uint32_t d; + do{ + r=isaac_next_uint32(_ctx); + v=r%_n; + d=r-v; + } + while(((d+_n-1)&ISAAC_MASK) X-Patchwork-Id: 12693072 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E36B5C433EF for ; Thu, 18 Nov 2021 18:49:34 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A908961AFD for ; Thu, 18 Nov 2021 18:49:34 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org A908961AFD Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=kYjzGUS42l5oeHGyuZW93xqL+UUsD1RyNMmiBpdxD/g=; b=zxPR1QmJ74I19I TwKgtvG41pB5SHS69+nORERjufpwCL52+/M5y9Sqf272hhzgTLZ9pM+DgxMLRSJb2OJwly6X3jETl 8opMo/YRm0AXP0PnZwJuYfJr1vkIRZ3cgD+jd7++d53oYgJz8ysSQWrRSjwOyhMIkuMU975P97siP U8K1qPbipk3uaa1b6GcPMDOQAhj9shZ43pd4syTRpntJivFR82Vb4QNZV+tcY6D2nG4jRNojf/cbM UIMADWIZ35vURWvGxAUqy9G0XtcSHBqZFgkzaGYa2DyHEYK6TPp/9LAkUJysg0RCiIjYhBd5tt7SI 9BwtKfSrPjG+cq4Sx9uA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mnmS6-008dFa-A9; Thu, 18 Nov 2021 18:48:06 +0000 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mnmR2-008cvZ-Vp for linux-arm-kernel@lists.infradead.org; Thu, 18 Nov 2021 18:47:02 +0000 Received: by mail-wm1-x335.google.com with SMTP id 77-20020a1c0450000000b0033123de3425so8483591wme.0 for ; Thu, 18 Nov 2021 10:47:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xmjowUqqjsoP8AlfmYKLxnopZGHsSI/gJkyk5037USk=; b=dwUsDJypNTWzxb1xCgM9KxqhEwspTtdc1biqJsMlafe4KQ1f1qyY6m0l0Z0zHPQOsF d7enZDzFRQjVFro/FbUb7GXF2YQ2Zxv+nyIcw944ptCa5d5jXcOQtc3KLyyfneQN5pX0 fWqT2VYYD359OBstUPubP14iAhvDit6Pkg2L1WRSYKtv4HRgiuQzRQvUJmNkFzQS2R0d I8Vn9Z5+Yax2xgIxMTu5AYd9ddW5k5a75PSGL0uH0sc/qq3hGTdeNAWciRMDKPN77Myo Ee1Pzw1Jca5tEv1dN9YFT6ELo8PZ2aKiu6y1gOrIAwFnD0oplu1WfU1Ut0RN6kEaXHn6 pdZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xmjowUqqjsoP8AlfmYKLxnopZGHsSI/gJkyk5037USk=; b=zHZx+eVR+Q0EIi0HHytNAOddh7B3F6USXY9GYrknAXJ7l+88HckLKX+ZbS1IelW0mo IjPIyy6v8s+ndx+aV5iyt9D3UVtLIdIIEhAgfQPwxFsWvtfcjLNy3j6V9+hcu8sRHuWe 0uDMwMUq/+hIkpDjoEUisG4z0y8NrJo8oJCe+yyMQep9ax6Ne2vVmx5N5BwrgnLNAnLa Kgra/bxPDnhake7azZtkkVfzoRW3oDIltrjatOPHxG4rMppSKy6tB7GYlLP+WOV+lSNT HaCpie54ZAJ+ylJcjMyZG4viv/Oa8aLeXJsPD8A2sW1fz6xnlqTg8j/z5v6vktwpn86J 7I3A== X-Gm-Message-State: AOAM530N9fIV7jdC5N2zWD8jE0BVWRlJSEXnOJlWaworI4WgLE9g6BRO dfsz7emIu71vKQDyr9xvfALdBA== X-Google-Smtp-Source: ABdhPJzYwdTN3EnbaeoJv0JEGoIzLR7U4UyTyp2tmsc/2jx3IUjE2VKN+I4X+3k0ACY//b/8iKbVvQ== X-Received: by 2002:a05:600c:a05:: with SMTP id z5mr12420976wmp.73.1637261219751; Thu, 18 Nov 2021 10:46:59 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id g124sm9269456wme.28.2021.11.18.10.46.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Nov 2021 10:46:55 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 67B9E1FF9D; Thu, 18 Nov 2021 18:46:50 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: kvm@vger.kernel.org Cc: idan.horowitz@gmail.com, qemu-arm@nongnu.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, christoffer.dall@arm.com, maz@kernel.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Mark Rutland Subject: [kvm-unit-tests PATCH v8 06/10] arm/tlbflush-code: TLB flush during code execution Date: Thu, 18 Nov 2021 18:46:46 +0000 Message-Id: <20211118184650.661575-7-alex.bennee@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211118184650.661575-1-alex.bennee@linaro.org> References: <20211118184650.661575-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211118_104701_111437_F00ADBAC X-CRM114-Status: GOOD ( 27.86 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This adds a fairly brain dead torture test for TLB flushes intended for stressing the MTTCG QEMU build. It takes the usual -smp option for multiple CPUs. By default it CPU0 will do a TLBIALL flush after each cycle. You can pass options via -append to control additional aspects of the test: - "page" flush each page in turn (one per function) - "self" do the flush after each computation cycle - "verbose" report progress on each computation cycle Signed-off-by: Alex Bennée CC: Mark Rutland --- v2 - rename to tlbflush-test - made makefile changes cleaner - added self/other flush mode - create specific prefix - whitespace fixes v3 - using new SMP framework for test runing v4 - merge in the unitests.cfg v5 - max out at -smp 4 - printf fmtfix v7 - rename to tlbflush-code - int -> bool flags v8 - kernel style fixes - move to separate mttcgtests.cfg --- arm/Makefile.common | 1 + arm/tlbflush-code.c | 209 ++++++++++++++++++++++++++++++++++++++++++++ arm/mttcgtests.cfg | 30 +++++++ 3 files changed, 240 insertions(+) create mode 100644 arm/tlbflush-code.c create mode 100644 arm/mttcgtests.cfg diff --git a/arm/Makefile.common b/arm/Makefile.common index 99bcf3f..e3f04f2 100644 --- a/arm/Makefile.common +++ b/arm/Makefile.common @@ -12,6 +12,7 @@ tests-common += $(TEST_DIR)/gic.flat tests-common += $(TEST_DIR)/psci.flat tests-common += $(TEST_DIR)/sieve.flat tests-common += $(TEST_DIR)/pl031.flat +tests-common += $(TEST_DIR)/tlbflush-code.flat tests-all = $(tests-common) $(tests) all: directories $(tests-all) diff --git a/arm/tlbflush-code.c b/arm/tlbflush-code.c new file mode 100644 index 0000000..ca98c82 --- /dev/null +++ b/arm/tlbflush-code.c @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * TLB Flush Race Tests + * + * These tests are designed to test for incorrect TLB flush semantics + * under emulation. The initial CPU will set all the others working a + * compuation task and will then trigger TLB flushes across the + * system. It doesn't actually need to re-map anything but the flushes + * themselves will trigger QEMU's TCG self-modifying code detection + * which will invalidate any generated code causing re-translation. + * Eventually the code buffer will fill and a general tb_lush() will + * be triggered. + * + * Copyright (C) 2016-2021, Linaro, Alex Bennée + * + * This work is licensed under the terms of the GNU LGPL, version 2. + */ + +#include +#include +#include +#include +#include + +#define SEQ_LENGTH 10 +#define SEQ_HASH 0x7cd707fe + +static cpumask_t smp_test_complete; +static int flush_count = 1000000; +static bool flush_self; +static bool flush_page; +static bool flush_verbose; + +/* + * Work functions + * + * These work functions need to be: + * + * - page aligned, so we can flush one function at a time + * - have branches, so QEMU TCG generates multiple basic blocks + * - call across pages, so we exercise the TCG basic block slow path + */ + +/* Adler32 */ +__attribute__((aligned(PAGE_SIZE))) static +uint32_t hash_array(const void *buf, size_t buflen) +{ + const uint8_t *data = (uint8_t *) buf; + uint32_t s1 = 1; + uint32_t s2 = 0; + + for (size_t n = 0; n < buflen; n++) { + s1 = (s1 + data[n]) % 65521; + s2 = (s2 + s1) % 65521; + } + return (s2 << 16) | s1; +} + +__attribute__((aligned(PAGE_SIZE))) static +void create_fib_sequence(int length, unsigned int *array) +{ + int i; + + /* first two values */ + array[0] = 0; + array[1] = 1; + for (i = 2; i < length; i++) + array[i] = array[i-2] + array[i-1]; +} + +__attribute__((aligned(PAGE_SIZE))) static +unsigned long long factorial(unsigned int n) +{ + unsigned int i; + unsigned long long fac = 1; + + for (i = 1; i <= n; i++) + fac = fac * i; + return fac; +} + +__attribute__((aligned(PAGE_SIZE))) static +void factorial_array(unsigned int n, unsigned int *input, + unsigned long long *output) +{ + unsigned int i; + + for (i = 0; i < n; i++) + output[i] = factorial(input[i]); +} + +__attribute__((aligned(PAGE_SIZE))) static +unsigned int do_computation(void) +{ + unsigned int fib_array[SEQ_LENGTH]; + unsigned long long facfib_array[SEQ_LENGTH]; + uint32_t fib_hash, facfib_hash; + + create_fib_sequence(SEQ_LENGTH, &fib_array[0]); + fib_hash = hash_array(&fib_array[0], sizeof(fib_array)); + factorial_array(SEQ_LENGTH, &fib_array[0], &facfib_array[0]); + facfib_hash = hash_array(&facfib_array[0], sizeof(facfib_array)); + + return (fib_hash ^ facfib_hash); +} + +/* This provides a table of the work functions so we can flush each + * page individually + */ +static void *pages[] = {&hash_array, &create_fib_sequence, &factorial, + &factorial_array, &do_computation}; + +static void do_flush(int i) +{ + if (flush_page) + flush_tlb_page((unsigned long)pages[i % ARRAY_SIZE(pages)]); + else + flush_tlb_all(); +} + + +static void just_compute(void) +{ + int i, errors = 0; + int cpu = smp_processor_id(); + + uint32_t result; + + printf("CPU%d online\n", cpu); + + for (i = 0 ; i < flush_count; i++) { + result = do_computation(); + + if (result != SEQ_HASH) { + errors++; + printf("CPU%d: seq%d 0x%"PRIx32"!=0x%x\n", + cpu, i, result, SEQ_HASH); + } + + if (flush_verbose && (i % 1000) == 0) + printf("CPU%d: seq%d\n", cpu, i); + + if (flush_self) + do_flush(i); + } + + report(errors == 0, "CPU%d: Done - Errors: %d\n", cpu, errors); + + cpumask_set_cpu(cpu, &smp_test_complete); + if (cpu != 0) + halt(); +} + +static void just_flush(void) +{ + int cpu = smp_processor_id(); + int i = 0; + + /* + * Set our CPU as done, keep flushing until everyone else + * finished + */ + cpumask_set_cpu(cpu, &smp_test_complete); + + while (!cpumask_full(&smp_test_complete)) + do_flush(i++); + + report_info("CPU%d: Done - Triggered %d flushes\n", cpu, i); +} + +int main(int argc, char **argv) +{ + int cpu, i; + char prefix[100]; + + for (i = 0; i < argc; i++) { + char *arg = argv[i]; + + if (strcmp(arg, "page") == 0) + flush_page = true; + + if (strcmp(arg, "self") == 0) + flush_self = true; + + if (strcmp(arg, "verbose") == 0) + flush_verbose = true; + } + + snprintf(prefix, sizeof(prefix), "tlbflush_%s_%s", + flush_page?"page":"all", + flush_self?"self":"other"); + report_prefix_push(prefix); + + for_each_present_cpu(cpu) { + if (cpu == 0) + continue; + smp_boot_secondary(cpu, just_compute); + } + + if (flush_self) + just_compute(); + else + just_flush(); + + while (!cpumask_full(&smp_test_complete)) + cpu_relax(); + + return report_summary(); +} diff --git a/arm/mttcgtests.cfg b/arm/mttcgtests.cfg new file mode 100644 index 0000000..d3ff102 --- /dev/null +++ b/arm/mttcgtests.cfg @@ -0,0 +1,30 @@ +############################################################################## +# MTTCG unit tests configuration +# +# These are torture tests for QEMU's Multi-threaded TCG (MTTCG) which +# aim to trigger various races in its emulation code. You can run them +# on a real system if you like but they shouldn't fail. +# +# See unittests.cfg for the file format +############################################################################## + +# TLB Torture Tests +[tlbflush-code::all_other] +file = tlbflush-code.flat +smp = $(($MAX_SMP>4?4:$MAX_SMP)) + +[tlbflush-code::page_other] +file = tlbflush-code.flat +smp = $(($MAX_SMP>4?4:$MAX_SMP)) +extra_params = -append 'page' + +[tlbflush-code::all_self] +file = tlbflush-code.flat +smp = $(($MAX_SMP>4?4:$MAX_SMP)) +extra_params = -append 'self' + +[tlbflush-code::page_self] +file = tlbflush-code.flat +smp = $(($MAX_SMP>4?4:$MAX_SMP)) +extra_params = -append 'page self' + From patchwork Thu Nov 18 18:46:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 12693073 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22158C433EF for ; Thu, 18 Nov 2021 18:50:07 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E1AA761AFD for ; Thu, 18 Nov 2021 18:50:06 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org E1AA761AFD Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=PyAaiy4dRKI+t/f2ejC3bJipG6x53rRU97J3vpmLm/0=; b=OU9C7asV23elDA Q2FLTLCrSHIOYYc8R8VSLr8lv5/8wQwTnI+IyRNmF9P3VWg+15mSgwUlgeu2iQClgBSe3/5+D/Sk2 5rt+hv4zIeDDVVAYRZP8lECKFXOpT57dnUSVh7aaaXxgfwdOfi1mFLOb6CXmJX3OmNKP7VlSAtrM8 q2kTN3uyRRr6WhaHkpgPmgNqVDIcIog/ojSj6ADY3Jqo7LiNEujoOvcGj2mT4K17c74wzp1JjbgTw eu36YhfmuWHm+iEaVi3Qs9ACMToB6xvEhaFEqqeRJsdF3X9kY+DjcWSDFGZcEX5Xkrbqn0QHCL9Dc UteGldNaD3EdbVFL6ZrQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mnmSS-008dQL-Mt; Thu, 18 Nov 2021 18:48:28 +0000 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mnmR4-008cwG-KW for linux-arm-kernel@lists.infradead.org; Thu, 18 Nov 2021 18:47:04 +0000 Received: by mail-wm1-x334.google.com with SMTP id g191-20020a1c9dc8000000b0032fbf912885so5568472wme.4 for ; Thu, 18 Nov 2021 10:47:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WiAvd7aj2aH/vAg+yhCdjHnmYC+nkAXagIoObHJiQv8=; b=M1ZUn5T7KFEZkTDBtCm/vAX6Yol8u9RSG3g940sZtr/aSEdJSO7qY3Ow0txJSnqqz3 ufF1gfQm477ArATrlNF3uEYwsfDT1oEi9k5gwKjzz/FrbwIZ2AcVNAgRGKqu3v4/so8x 59GmduwgDq/mV5AwXPZUINwfB7W2uydqcm6/7ql46hUFlPz+3ckOqSVrwY4W1JFz3F0u AYwVHwep3WgPYDu+/C5EtcKzPNRjPF0UkaIhuVxy95yF/dUKJS9bgARDd8L29FeAWkFh FxQX69PbTZW8GoMf1tm2mREulsKoQtCbBWn7Ha6MqlvOmk2ZoaaxAezKKHC7tBUb2spS JDBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WiAvd7aj2aH/vAg+yhCdjHnmYC+nkAXagIoObHJiQv8=; b=NhqHKBDFTiJBAP5+VU3oxmbb40bL2Z/QAqcD7XHdLM78of1a33xnDasm8gGIyXpbyZ qK1kq/MwyWB0my9LcNg9SWsL/EsB23uG96WFTv4NCVZI8wPL/NejZoCFpFNb8k02cZm0 a5WVDRscHzjTEBs5Zx/4cR3IrkwGnNAXqpuad75xxHFZr+v9COh0Lpa40XYlWhLlyhQ7 7kyr37PLPOefpDYVRsWF0a+ogc6k1PN81fFstJWB+vrB9eXZHAgnne5GlgU5Ow2jGWoA 0D08zVCfeGdPruE+NUnHQ/LAFNzheD6eW/xoxpH/gN38u2aRLFk09bMq1Dm9Dk7EJfnV 6soQ== X-Gm-Message-State: AOAM533A1LJv/bFZ7CWWVI+XVvnU6xWlHlXWjEM/nq5mvSiqg4HiCJhW D2xcikTtkptfAnky+7SxzwG/+g== X-Google-Smtp-Source: ABdhPJyoOeBfLMmm5zXegCQd2cYXFTf5fHVLMYDF0hXHgyZbSYPhJBDdRKu6lmzxCWLgM6m+dLwxqQ== X-Received: by 2002:a1c:790d:: with SMTP id l13mr12912116wme.101.1637261220654; Thu, 18 Nov 2021 10:47:00 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id j40sm639481wms.16.2021.11.18.10.46.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Nov 2021 10:46:55 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 743DD1FF9E; Thu, 18 Nov 2021 18:46:50 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: kvm@vger.kernel.org Cc: idan.horowitz@gmail.com, qemu-arm@nongnu.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, christoffer.dall@arm.com, maz@kernel.org, =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [kvm-unit-tests PATCH v8 07/10] arm/locking-tests: add comprehensive locking test Date: Thu, 18 Nov 2021 18:46:47 +0000 Message-Id: <20211118184650.661575-8-alex.bennee@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211118184650.661575-1-alex.bennee@linaro.org> References: <20211118184650.661575-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211118_104702_721788_8644CA28 X-CRM114-Status: GOOD ( 34.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This test has been written mainly to stress multi-threaded TCG behaviour but will demonstrate failure by default on real hardware. The test takes the following parameters: - "lock" use GCC's locking semantics - "atomic" use GCC's __atomic primitives - "wfelock" use WaitForEvent sleep - "excl" use load/store exclusive semantics Also two more options allow the test to be tweaked - "noshuffle" disables the memory shuffling - "count=%ld" set your own per-CPU increment count Signed-off-by: Alex Bennée --- v2 - Don't use thumb style strexeq stuff - Add atomic and wfelock tests - Add count/noshuffle test controls - Move barrier tests to separate test file v4 - fix up unitests.cfg to use correct test name - move into "locking" group, remove barrier tests - use a table to add tests, mark which are expected to work - correctly report XFAIL v5 - max out at -smp 4 in unittest.cfg v7 - make test control flags bools - default the count to 100000 (so it doesn't timeout) v8 - rm spinlock test - fix checkpatch errors - fix report usage --- arm/Makefile.common | 2 +- arm/locking-test.c | 322 ++++++++++++++++++++++++++++++++++++++++++++ arm/spinlock-test.c | 87 ------------ arm/mttcgtests.cfg | 29 ++++ 4 files changed, 352 insertions(+), 88 deletions(-) create mode 100644 arm/locking-test.c delete mode 100644 arm/spinlock-test.c diff --git a/arm/Makefile.common b/arm/Makefile.common index e3f04f2..f905971 100644 --- a/arm/Makefile.common +++ b/arm/Makefile.common @@ -5,7 +5,6 @@ # tests-common = $(TEST_DIR)/selftest.flat -tests-common += $(TEST_DIR)/spinlock-test.flat tests-common += $(TEST_DIR)/pci-test.flat tests-common += $(TEST_DIR)/pmu.flat tests-common += $(TEST_DIR)/gic.flat @@ -13,6 +12,7 @@ tests-common += $(TEST_DIR)/psci.flat tests-common += $(TEST_DIR)/sieve.flat tests-common += $(TEST_DIR)/pl031.flat tests-common += $(TEST_DIR)/tlbflush-code.flat +tests-common += $(TEST_DIR)/locking-test.flat tests-all = $(tests-common) $(tests) all: directories $(tests-all) diff --git a/arm/locking-test.c b/arm/locking-test.c new file mode 100644 index 0000000..eab9497 --- /dev/null +++ b/arm/locking-test.c @@ -0,0 +1,322 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Locking Test + * + * This test allows us to stress the various atomic primitives of a VM + * guest. A number of methods are available that use various patterns + * to implement a lock. + * + * Copyright (C) 2017 Linaro + * Author: Alex Bennée + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#include + +#define MAX_CPUS 8 + +/* Test definition structure + * + * A simple structure that describes the test name, expected pass and + * increment function. + */ + +/* Function pointers for test */ +typedef void (*inc_fn)(int cpu); + +typedef struct { + const char *test_name; + bool should_pass; + inc_fn main_fn; +} test_descr_t; + +/* How many increments to do */ +static int increment_count = 1000000; +static bool do_shuffle = true; + +/* Shared value all the tests attempt to safely increment using + * various forms of atomic locking and exclusive behaviour. + */ +static unsigned int shared_value; + +/* PAGE_SIZE * uint32_t means we span several pages */ +__attribute__((aligned(PAGE_SIZE))) static uint32_t memory_array[PAGE_SIZE]; + +/* We use the alignment of the following to ensure accesses to locking + * and synchronisation primatives don't interfere with the page of the + * shared value + */ +__attribute__((aligned(PAGE_SIZE))) static unsigned int per_cpu_value[MAX_CPUS]; +__attribute__((aligned(PAGE_SIZE))) static cpumask_t smp_test_complete; +__attribute__((aligned(PAGE_SIZE))) struct isaac_ctx prng_context[MAX_CPUS]; + +/* Some of the approaches use a global lock to prevent contention. */ +static int global_lock; + +/* In any SMP setting this *should* fail due to cores stepping on + * each other updating the shared variable + */ +static void increment_shared(int cpu) +{ + (void)cpu; + + shared_value++; +} + +/* GCC __sync primitives are deprecated in favour of __atomic */ +static void increment_shared_with_lock(int cpu) +{ + (void)cpu; + + while (__sync_lock_test_and_set(&global_lock, 1)); + + shared_value++; + + __sync_lock_release(&global_lock); +} + +/* + * In practice even __ATOMIC_RELAXED uses ARM's ldxr/stex exclusive + * semantics + */ +static void increment_shared_with_atomic(int cpu) +{ + (void)cpu; + + __atomic_add_fetch(&shared_value, 1, __ATOMIC_SEQ_CST); +} + + +/* + * Load/store exclusive with WFE (wait-for-event) + * + * See ARMv8 ARM examples: + * Use of Wait For Event (WFE) and Send Event (SEV) with locks + */ + +static void increment_shared_with_wfelock(int cpu) +{ + (void)cpu; + +#if defined(__aarch64__) + asm volatile( + " mov w1, #1\n" + " sevl\n" + " prfm PSTL1KEEP, [%[lock]]\n" + "1: wfe\n" + " ldaxr w0, [%[lock]]\n" + " cbnz w0, 1b\n" + " stxr w0, w1, [%[lock]]\n" + " cbnz w0, 1b\n" + /* lock held */ + " ldr w0, [%[sptr]]\n" + " add w0, w0, #0x1\n" + " str w0, [%[sptr]]\n" + /* now release */ + " stlr wzr, [%[lock]]\n" + : /* out */ + : [lock] "r" (&global_lock), [sptr] "r" (&shared_value) /* in */ + : "w0", "w1", "cc"); +#else + asm volatile( + " mov r1, #1\n" + "1: ldrex r0, [%[lock]]\n" + " cmp r0, #0\n" + " wfene\n" + " strexeq r0, r1, [%[lock]]\n" + " cmpeq r0, #0\n" + " bne 1b\n" + " dmb\n" + /* lock held */ + " ldr r0, [%[sptr]]\n" + " add r0, r0, #0x1\n" + " str r0, [%[sptr]]\n" + /* now release */ + " mov r0, #0\n" + " dmb\n" + " str r0, [%[lock]]\n" + " dsb\n" + " sev\n" + : /* out */ + : [lock] "r" (&global_lock), [sptr] "r" (&shared_value) /* in */ + : "r0", "r1", "cc"); +#endif +} + + +/* + * Hand-written version of the load/store exclusive + */ +static void increment_shared_with_excl(int cpu) +{ + (void)cpu; + +#if defined(__aarch64__) + asm volatile( + "1: ldxr w0, [%[sptr]]\n" + " add w0, w0, #0x1\n" + " stxr w1, w0, [%[sptr]]\n" + " cbnz w1, 1b\n" + : /* out */ + : [sptr] "r" (&shared_value) /* in */ + : "w0", "w1", "cc"); +#else + asm volatile( + "1: ldrex r0, [%[sptr]]\n" + " add r0, r0, #0x1\n" + " strex r1, r0, [%[sptr]]\n" + " cmp r1, #0\n" + " bne 1b\n" + : /* out */ + : [sptr] "r" (&shared_value) /* in */ + : "r0", "r1", "cc"); +#endif +} + +/* Test array */ +static test_descr_t tests[] = { + { "none", false, increment_shared }, + { "lock", true, increment_shared_with_lock }, + { "atomic", true, increment_shared_with_atomic }, + { "wfelock", true, increment_shared_with_wfelock }, + { "excl", true, increment_shared_with_excl } +}; + +/* The idea of this is just to generate some random load/store + * activity which may or may not race with an un-barried incremented + * of the shared counter + */ +static void shuffle_memory(int cpu) +{ + int i; + uint32_t lspat = isaac_next_uint32(&prng_context[cpu]); + uint32_t seq = isaac_next_uint32(&prng_context[cpu]); + int count = seq & 0x1f; + uint32_t val = 0; + + seq >>= 5; + + for (i = 0; i < count; i++) { + int index = seq & ~PAGE_MASK; + + if (lspat & 1) + val ^= memory_array[index]; + else + memory_array[index] = val; + + seq >>= PAGE_SHIFT; + seq ^= lspat; + lspat >>= 1; + } + +} + +static inc_fn increment_function; + +static void do_increment(void) +{ + int i; + int cpu = smp_processor_id(); + + printf("CPU%d: online and ++ing\n", cpu); + + for (i = 0; i < increment_count; i++) { + per_cpu_value[cpu]++; + increment_function(cpu); + + if (do_shuffle) + shuffle_memory(cpu); + } + + printf("CPU%d: Done, %d incs\n", cpu, per_cpu_value[cpu]); + + cpumask_set_cpu(cpu, &smp_test_complete); + if (cpu != 0) + halt(); +} + +static void setup_and_run_test(test_descr_t *test) +{ + unsigned int i, sum = 0; + int cpu, cpu_cnt = 0; + + increment_function = test->main_fn; + + /* fill our random page */ + for (i = 0; i < PAGE_SIZE; i++) + memory_array[i] = isaac_next_uint32(&prng_context[0]); + + for_each_present_cpu(cpu) { + uint32_t seed2 = isaac_next_uint32(&prng_context[0]); + + cpu_cnt++; + if (cpu == 0) + continue; + + isaac_init(&prng_context[cpu], (unsigned char *) &seed2, sizeof(seed2)); + smp_boot_secondary(cpu, do_increment); + } + + do_increment(); + + while (!cpumask_full(&smp_test_complete)) + cpu_relax(); + + /* All CPUs done, do we add up */ + for_each_present_cpu(cpu) { + sum += per_cpu_value[cpu]; + } + + if (test->should_pass) + report(sum == shared_value, "total incs %d", shared_value); + else + report_xfail(true, sum == shared_value, "total incs %d", shared_value); +} + +int main(int argc, char **argv) +{ + static const unsigned char seed[] = "myseed"; + test_descr_t *test = &tests[0]; + int i; + unsigned int j; + + isaac_init(&prng_context[0], &seed[0], sizeof(seed)); + + for (i = 0; i < argc; i++) { + char *arg = argv[i]; + + /* Check for test name */ + for (j = 0; j < ARRAY_SIZE(tests); j++) { + if (strcmp(arg, tests[j].test_name) == 0) + test = &tests[j]; + } + + /* Test modifiers */ + if (strcmp(arg, "noshuffle") == 0) { + do_shuffle = false; + report_prefix_push("noshuffle"); + } else if (strstr(arg, "count=") != NULL) { + char *p = strstr(arg, "="); + + increment_count = atol(p+1); + } else { + isaac_reseed(&prng_context[0], (unsigned char *) arg, strlen(arg)); + } + } + + if (test) + setup_and_run_test(test); + else + report(false, "Unknown test"); + + return report_summary(); +} diff --git a/arm/spinlock-test.c b/arm/spinlock-test.c deleted file mode 100644 index 73aea76..0000000 --- a/arm/spinlock-test.c +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Spinlock test - * - * This code is based on code from the tcg_baremetal_tests. - * - * Copyright (C) 2015 Virtual Open Systems SAS - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include - -#define LOOP_SIZE 10000000 - -struct lock_ops { - void (*lock)(int *v); - void (*unlock)(int *v); -}; -static struct lock_ops lock_ops; - -static void gcc_builtin_lock(int *lock_var) -{ - while (__sync_lock_test_and_set(lock_var, 1)); -} -static void gcc_builtin_unlock(int *lock_var) -{ - __sync_lock_release(lock_var); -} -static void none_lock(int *lock_var) -{ - while (*(volatile int *)lock_var != 0); - *(volatile int *)lock_var = 1; -} -static void none_unlock(int *lock_var) -{ - *(volatile int *)lock_var = 0; -} - -static int global_a, global_b; -static int global_lock; - -static void test_spinlock(void *data __unused) -{ - int i, errors = 0; - int cpu = smp_processor_id(); - - printf("CPU%d online\n", cpu); - - for (i = 0; i < LOOP_SIZE; i++) { - - lock_ops.lock(&global_lock); - - if (global_a == (cpu + 1) % 2) { - global_a = 1; - global_b = 0; - } else { - global_a = 0; - global_b = 1; - } - - if (global_a == global_b) - errors++; - - lock_ops.unlock(&global_lock); - } - report(errors == 0, "CPU%d: Done - Errors: %d", cpu, errors); -} - -int main(int argc, char **argv) -{ - report_prefix_push("spinlock"); - if (argc > 1 && strcmp(argv[1], "bad") != 0) { - lock_ops.lock = gcc_builtin_lock; - lock_ops.unlock = gcc_builtin_unlock; - } else { - lock_ops.lock = none_lock; - lock_ops.unlock = none_unlock; - } - - on_cpus(test_spinlock, NULL); - - return report_summary(); -} diff --git a/arm/mttcgtests.cfg b/arm/mttcgtests.cfg index d3ff102..46fcb57 100644 --- a/arm/mttcgtests.cfg +++ b/arm/mttcgtests.cfg @@ -28,3 +28,32 @@ file = tlbflush-code.flat smp = $(($MAX_SMP>4?4:$MAX_SMP)) extra_params = -append 'page self' +# Locking tests +[locking::none] +file = locking-test.flat +smp = $(($MAX_SMP>4?4:$MAX_SMP)) +groups = locking + +[locking::lock] +file = locking-test.flat +smp = $(($MAX_SMP>4?4:$MAX_SMP)) +extra_params = -append 'lock' +groups = locking + +[locking::atomic] +file = locking-test.flat +smp = $(($MAX_SMP>4?4:$MAX_SMP)) +extra_params = -append 'atomic' +groups = locking + +[locking::wfelock] +file = locking-test.flat +smp = $(($MAX_SMP>4?4:$MAX_SMP)) +extra_params = -append 'wfelock' +groups = locking + +[locking::excl] +file = locking-test.flat +smp = $(($MAX_SMP>4?4:$MAX_SMP)) +extra_params = -append 'excl' +groups = locking From patchwork Thu Nov 18 18:46:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 12693074 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1C212C433EF for ; Thu, 18 Nov 2021 18:50:40 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DCBC861AFD for ; Thu, 18 Nov 2021 18:50:39 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org DCBC861AFD Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=kDLhPa9oaom2EpBAGY4FsDUvLtwolp0zhDWA1jp4foM=; b=AAvoPxiGHdeQ9j cLVSYPcG9BvMgqQb8+IyRfZxVJN4RzuiBzmNMbljBzD25LETDVTjFk0UWnuHdw2v642re11LHJ4fc yBdQHn5Gh6nIjWXauWHWIJwWW4GdELKIlabOlE3kiLW32OLG47xGsp42PvH7QSBcBJFKwtRL9kvS9 VLO5eC9ztdJG+shTxlTTFojeaTST/krs76fLuBUlxTl+qG1awhYh4PoaWAbyEo/WMSjmHZ1BgLXkj cTOKO/rIlYBoB9+ZlzdV6qRo1habkCa8zfylAoOQdrxeuGEmU4aqVqZZA3P+PXelhtCniepIsesCM VjT+h1fna+sBZYwijUZQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mnmT0-008dh2-7y; Thu, 18 Nov 2021 18:49:02 +0000 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mnmR6-008cwh-9c for linux-arm-kernel@lists.infradead.org; Thu, 18 Nov 2021 18:47:07 +0000 Received: by mail-wm1-x329.google.com with SMTP id y196so6247527wmc.3 for ; Thu, 18 Nov 2021 10:47:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=89AsjvVNV/Rc4mz/t7QuZ/hAkSNPw+08m1IGT1ip1xI=; b=YcUQsR9goVIG1cmb6wDmmWszFwkT6J/HHGiLzSBZCLy0uob/O1PfkIr4PpOwAx+KgW HaKAroxgCFxbwTMHiQA8IY6i96JGwbqkSqGRpXPvR5wscq7oNhSXr0odBxjpwa1mEryy IkZmujQJ9t9yD+iFr1IUEP2fYF/cpXP9ezCt/4vLX5zy0SslfxPs9A9Zv7vHCEXpA7OM YTseNLdkFx+mhqhIs21GMIbDAiW/FBICBHtsu4sl6G0kB7xs4g+u05l0aEoVbVGQmUTP fjdQFcnhCOD8rYSHGOqec7PMForlDrkFPb0bdfU04Rixd+W0UmVcOiBQGPhTL9a6hauU FLsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=89AsjvVNV/Rc4mz/t7QuZ/hAkSNPw+08m1IGT1ip1xI=; b=mo67+15WtM7wiD0nTBL2LjrPTyhB30G5W9q1C0dZFSmm5L9tZDRC7TPg9JDntIonuG v3rab5ZX0yGbtn0yIMtWY367hKgrfhJTU1YmY8un3LeFx19f1IgiSrz196pQf0r9CtMw LwgpxXDHeNhqIxutTcI+KjeClhNqSKPmoLSfkwN+pqPEvl2CpejDMJ77yV2CQZKhl/U3 pBVE53Y64Ku2zVCgSyxkNVi4teOp1iG1lcEQa5rVNTWMyxHTo7SO8vcm5VWFeb6eN2AM mThrekB6ULQ64f4jM5fz3uo97Yu3734eONNxXsaBOiz2aH1EXw7olsPUdtUh32LJA2Dl aP3w== X-Gm-Message-State: AOAM530A+RzRkrpkJm/4eE1eDS1DF5ESmLxQgguaN6I0Ca+JOfA5FOV+ pvvSRYUfUqxgmYTX2lQ/1nG6ig== X-Google-Smtp-Source: ABdhPJxtJMfw1VaJ9apSMOVnKg6iVLS/xnIsuT0Gx51E7pogEWTJyMokYRVchlu/236t/dIVufjhmA== X-Received: by 2002:a05:600c:4f02:: with SMTP id l2mr12707960wmq.26.1637261222298; Thu, 18 Nov 2021 10:47:02 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id b11sm9637580wmj.35.2021.11.18.10.46.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Nov 2021 10:46:55 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 78D701FF9F; Thu, 18 Nov 2021 18:46:50 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: kvm@vger.kernel.org Cc: idan.horowitz@gmail.com, qemu-arm@nongnu.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, christoffer.dall@arm.com, maz@kernel.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Will Deacon Subject: [kvm-unit-tests PATCH v8 08/10] arm/barrier-litmus-tests: add simple mp and sal litmus tests Date: Thu, 18 Nov 2021 18:46:48 +0000 Message-Id: <20211118184650.661575-9-alex.bennee@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211118184650.661575-1-alex.bennee@linaro.org> References: <20211118184650.661575-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211118_104704_397926_C07B45E4 X-CRM114-Status: GOOD ( 35.91 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This adds a framework for adding simple barrier litmus tests against ARM. The litmus tests aren't as comprehensive as the academic exercises which will attempt to do all sorts of things to keep racing CPUs synced up. These tests do honour the "sync" parameter to do a poor-mans equivalent. The two litmus tests are: - message passing - store-after-load They both have case that should fail (although won't on single-threaded TCG setups). If barriers aren't working properly the store-after-load test will fail even on an x86 backend as x86 allows re-ording of non aliased stores. I've imported a few more of the barrier primatives from the Linux source tree so we consistently use macros. The arm64 barrier primitives trip up on -Wstrict-aliasing so this is disabled in the Makefile. Signed-off-by: Alex Bennée CC: Will Deacon --- v8 - move to mttcgtests.cfg - fix checkpatch issues - fix report usage v7 - merge in store-after-load - clean-up sync-up code - use new counter api - fix xfail for sal test v6 - add a unittest.cfg - -fno-strict-aliasing --- arm/Makefile.common | 1 + lib/arm/asm/barrier.h | 61 ++++++ lib/arm64/asm/barrier.h | 50 +++++ arm/barrier-litmus-test.c | 450 ++++++++++++++++++++++++++++++++++++++ arm/mttcgtests.cfg | 33 +++ 5 files changed, 595 insertions(+) create mode 100644 arm/barrier-litmus-test.c diff --git a/arm/Makefile.common b/arm/Makefile.common index f905971..861e5c7 100644 --- a/arm/Makefile.common +++ b/arm/Makefile.common @@ -13,6 +13,7 @@ tests-common += $(TEST_DIR)/sieve.flat tests-common += $(TEST_DIR)/pl031.flat tests-common += $(TEST_DIR)/tlbflush-code.flat tests-common += $(TEST_DIR)/locking-test.flat +tests-common += $(TEST_DIR)/barrier-litmus-test.flat tests-all = $(tests-common) $(tests) all: directories $(tests-all) diff --git a/lib/arm/asm/barrier.h b/lib/arm/asm/barrier.h index 7f86831..2870080 100644 --- a/lib/arm/asm/barrier.h +++ b/lib/arm/asm/barrier.h @@ -8,6 +8,8 @@ * This work is licensed under the terms of the GNU GPL, version 2. */ +#include + #define sev() asm volatile("sev" : : : "memory") #define wfe() asm volatile("wfe" : : : "memory") #define wfi() asm volatile("wfi" : : : "memory") @@ -25,4 +27,63 @@ #define smp_rmb() smp_mb() #define smp_wmb() dmb(ishst) +extern void abort(void); + +static inline void __write_once_size(volatile void *p, void *res, int size) +{ + switch (size) { + case 1: *(volatile uint8_t *)p = *(uint8_t *)res; break; + case 2: *(volatile uint16_t *)p = *(uint16_t *)res; break; + case 4: *(volatile uint32_t *)p = *(uint32_t *)res; break; + case 8: *(volatile uint64_t *)p = *(uint64_t *)res; break; + default: + /* unhandled case */ + abort(); + } +} + +#define WRITE_ONCE(x, val) \ +({ \ + union { typeof(x) __val; char __c[1]; } __u = \ + { .__val = (typeof(x)) (val) }; \ + __write_once_size(&(x), __u.__c, sizeof(x)); \ + __u.__val; \ +}) + +#define smp_store_release(p, v) \ +do { \ + smp_mb(); \ + WRITE_ONCE(*p, v); \ +} while (0) + + +static inline +void __read_once_size(const volatile void *p, void *res, int size) +{ + switch (size) { + case 1: *(uint8_t *)res = *(volatile uint8_t *)p; break; + case 2: *(uint16_t *)res = *(volatile uint16_t *)p; break; + case 4: *(uint32_t *)res = *(volatile uint32_t *)p; break; + case 8: *(uint64_t *)res = *(volatile uint64_t *)p; break; + default: + /* unhandled case */ + abort(); + } +} + +#define READ_ONCE(x) \ +({ \ + union { typeof(x) __val; char __c[1]; } __u; \ + __read_once_size(&(x), __u.__c, sizeof(x)); \ + __u.__val; \ +}) + + +#define smp_load_acquire(p) \ +({ \ + typeof(*p) ___p1 = READ_ONCE(*p); \ + smp_mb(); \ + ___p1; \ +}) + #endif /* _ASMARM_BARRIER_H_ */ diff --git a/lib/arm64/asm/barrier.h b/lib/arm64/asm/barrier.h index 0e1904c..5e40519 100644 --- a/lib/arm64/asm/barrier.h +++ b/lib/arm64/asm/barrier.h @@ -24,4 +24,54 @@ #define smp_rmb() dmb(ishld) #define smp_wmb() dmb(ishst) +#define smp_store_release(p, v) \ +do { \ + switch (sizeof(*p)) { \ + case 1: \ + asm volatile ("stlrb %w1, %0" \ + : "=Q" (*p) : "r" (v) : "memory"); \ + break; \ + case 2: \ + asm volatile ("stlrh %w1, %0" \ + : "=Q" (*p) : "r" (v) : "memory"); \ + break; \ + case 4: \ + asm volatile ("stlr %w1, %0" \ + : "=Q" (*p) : "r" (v) : "memory"); \ + break; \ + case 8: \ + asm volatile ("stlr %1, %0" \ + : "=Q" (*p) : "r" (v) : "memory"); \ + break; \ + } \ +} while (0) + +#define smp_load_acquire(p) \ +({ \ + union { typeof(*p) __val; char __c[1]; } __u; \ + switch (sizeof(*p)) { \ + case 1: \ + asm volatile ("ldarb %w0, %1" \ + : "=r" (*(u8 *)__u.__c) \ + : "Q" (*p) : "memory"); \ + break; \ + case 2: \ + asm volatile ("ldarh %w0, %1" \ + : "=r" (*(u16 *)__u.__c) \ + : "Q" (*p) : "memory"); \ + break; \ + case 4: \ + asm volatile ("ldar %w0, %1" \ + : "=r" (*(u32 *)__u.__c) \ + : "Q" (*p) : "memory"); \ + break; \ + case 8: \ + asm volatile ("ldar %0, %1" \ + : "=r" (*(u64 *)__u.__c) \ + : "Q" (*p) : "memory"); \ + break; \ + } \ + __u.__val; \ +}) + #endif /* _ASMARM64_BARRIER_H_ */ diff --git a/arm/barrier-litmus-test.c b/arm/barrier-litmus-test.c new file mode 100644 index 0000000..e90f6dd --- /dev/null +++ b/arm/barrier-litmus-test.c @@ -0,0 +1,450 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * ARM Barrier Litmus Tests + * + * This test provides a framework for testing barrier conditions on + * the processor. It's simpler than the more involved barrier testing + * frameworks as we are looking for simple failures of QEMU's TCG not + * weird edge cases the silicon gets wrong. + */ + +#include +#include +#include +#include +#include + +#define MAX_CPUS 8 + +/* Array size and access controls */ +static int array_size = 100000; +static int wait_if_ahead; + +static cpumask_t cpu_mask; + +/* + * These test_array_* structures are a contiguous array modified by two or more + * competing CPUs. The padding is to ensure the variables do not share + * cache lines. + * + * All structures start zeroed. + */ + +typedef struct test_array { + volatile unsigned int x; + uint8_t dummy[64]; + volatile unsigned int y; + uint8_t dummy2[64]; + volatile unsigned int r[MAX_CPUS]; +} test_array; + +volatile test_array *array; + +/* Test definition structure + * + * The first function will always run on the primary CPU, it is + * usually the one that will detect any weirdness and trigger the + * failure of the test. + */ + +typedef void (*test_fn)(void); + +typedef struct { + const char *test_name; + bool should_pass; + test_fn main_fn; + test_fn secondary_fns[MAX_CPUS-1]; +} test_descr_t; + +/* Litmus tests */ + +static unsigned long sync_start(void) +{ + const unsigned long gate_mask = ~0x3ffff; + unsigned long gate, now; + + gate = get_cntvct() & gate_mask; + do { + now = get_cntvct(); + } while ((now & gate_mask) == gate); + + return now; +} + +/* Simple Message Passing + * + * x is the message data + * y is the flag to indicate the data is ready + * + * Reading x == 0 when y == 1 is a failure. + */ + +static void message_passing_write(void) +{ + int i; + + sync_start(); + for (i = 0; i < array_size; i++) { + volatile test_array *entry = &array[i]; + + entry->x = 1; + entry->y = 1; + } + + halt(); +} + +static void message_passing_read(void) +{ + int i; + int errors = 0, ready = 0; + + sync_start(); + for (i = 0; i < array_size; i++) { + volatile test_array *entry = &array[i]; + unsigned int x, y; + + y = entry->y; + x = entry->x; + + if (y && !x) + errors++; + ready += y; + } + + /* + * We expect this to fail but with STO backends you often get + * way with it. Fudge xfail if we did actually pass. + */ + report_xfail(errors == 0 ? false : true, errors == 0, + "mp: %d errors, %d ready", errors, ready); +} + +/* Simple Message Passing with barriers */ +static void message_passing_write_barrier(void) +{ + int i; + + sync_start(); + for (i = 0; i < array_size; i++) { + volatile test_array *entry = &array[i]; + + entry->x = 1; + smp_wmb(); + entry->y = 1; + } + + halt(); +} + +static void message_passing_read_barrier(void) +{ + int i; + int errors = 0, ready = 0, not_ready = 0; + + sync_start(); + for (i = 0; i < array_size; i++) { + volatile test_array *entry = &array[i]; + unsigned int x, y; + + y = entry->y; + smp_rmb(); + x = entry->x; + + if (y && !x) + errors++; + + if (y) { + ready++; + } else { + not_ready++; + + if (not_ready > 2) { + entry = &array[i+1]; + do { + not_ready = 0; + } while (wait_if_ahead && !entry->y); + } + } + } + + report(errors == 0, "mp barrier: %d errors, %d ready", errors, ready); +} + +/* Simple Message Passing with Acquire/Release */ +static void message_passing_write_release(void) +{ + int i; + + for (i = 0; i < array_size; i++) { + volatile test_array *entry = &array[i]; + + entry->x = 1; + smp_store_release(&entry->y, 1); + } + + halt(); +} + +static void message_passing_read_acquire(void) +{ + int i; + int errors = 0, ready = 0, not_ready = 0; + + for (i = 0; i < array_size; i++) { + volatile test_array *entry = &array[i]; + unsigned int x, y; + + y = smp_load_acquire(&entry->y); + x = entry->x; + + if (y && !x) + errors++; + + if (y) { + ready++; + } else { + not_ready++; + + if (not_ready > 2) { + entry = &array[i+1]; + do { + not_ready = 0; + } while (wait_if_ahead && !entry->y); + } + } + } + + report(errors == 0, "mp acqrel: %d errors, %d ready", errors, ready); +} + +/* + * Store after load + * + * T1: write 1 to x, load r from y + * T2: write 1 to y, load r from x + * + * Without memory fence r[0] && r[1] == 0 + * With memory fence both == 0 should be impossible + */ + +static void check_store_and_load_results(const char *name, int thread, + bool xfail, unsigned long start, + unsigned long end) +{ + int i; + int neither = 0; + int only_first = 0; + int only_second = 0; + int both = 0; + + for ( i= 0; i < array_size; i++) { + volatile test_array *entry = &array[i]; + + if (entry->r[0] == 0 && + entry->r[1] == 0) + neither++; + else if (entry->r[0] && + entry->r[1]) + both++; + else if (entry->r[0]) + only_first++; + else + only_second++; + } + + printf("T%d: %08lx->%08lx neither=%d only_t1=%d only_t2=%d both=%d\n", thread, + start, end, neither, only_first, only_second, both); + + if (thread == 1) + report_xfail(xfail, neither==0, "%s: errors=%d", name, neither); + +} + +/* + * This attempts to synchronise the start of both threads to roughly + * the same time. On real hardware there is a little latency as the + * secondary vCPUs are powered up however this effect it much more + * exaggerated on a TCG host. + * + * Busy waits until the we pass a future point in time, returns final + * start time. + */ + +static void store_and_load_1(void) +{ + int i; + unsigned long start, end; + + start = sync_start(); + for (i = 0; i < array_size; i++) { + volatile test_array *entry = &array[i]; + unsigned int r; + + entry->x = 1; + r = entry->y; + entry->r[0] = r; + } + end = get_cntvct(); + + smp_mb(); + + while (!cpumask_test_cpu(1, &cpu_mask)) + cpu_relax(); + + check_store_and_load_results("sal", 1, true, start, end); +} + +static void store_and_load_2(void) +{ + int i; + unsigned long start, end; + + start = sync_start(); + for (i = 0; i < array_size; i++) { + volatile test_array *entry = &array[i]; + unsigned int r; + + entry->y = 1; + r = entry->x; + entry->r[1] = r; + } + end = get_cntvct(); + + check_store_and_load_results("sal", 2, true, start, end); + + cpumask_set_cpu(1, &cpu_mask); + + halt(); +} + +static void store_and_load_barrier_1(void) +{ + int i; + unsigned long start, end; + + start = sync_start(); + for (i = 0; i < array_size; i++) { + volatile test_array *entry = &array[i]; + unsigned int r; + + entry->x = 1; + smp_mb(); + r = entry->y; + entry->r[0] = r; + } + end = get_cntvct(); + + smp_mb(); + + while (!cpumask_test_cpu(1, &cpu_mask)) + cpu_relax(); + + check_store_and_load_results("sal_barrier", 1, false, start, end); +} + +static void store_and_load_barrier_2(void) +{ + int i; + unsigned long start, end; + + start = sync_start(); + for (i = 0; i < array_size; i++) { + volatile test_array *entry = &array[i]; + unsigned int r; + + entry->y = 1; + smp_mb(); + r = entry->x; + entry->r[1] = r; + } + end = get_cntvct(); + + check_store_and_load_results("sal_barrier", 2, false, start, end); + + cpumask_set_cpu(1, &cpu_mask); + + halt(); +} + + +/* Test array */ +static test_descr_t tests[] = { + + { "mp", false, + message_passing_read, + { message_passing_write } + }, + + { "mp_barrier", true, + message_passing_read_barrier, + { message_passing_write_barrier } + }, + + { "mp_acqrel", true, + message_passing_read_acquire, + { message_passing_write_release } + }, + + { "sal", false, + store_and_load_1, + { store_and_load_2 } + }, + + { "sal_barrier", true, + store_and_load_barrier_1, + { store_and_load_barrier_2 } + }, +}; + + +static void setup_and_run_litmus(test_descr_t *test) +{ + array = calloc(array_size, sizeof(test_array)); + + if (array) { + int i = 0; + + printf("Allocated test array @ %p\n", array); + + while (test->secondary_fns[i]) { + smp_boot_secondary(i+1, test->secondary_fns[i]); + i++; + } + + test->main_fn(); + } else + report(false, "%s: failed to allocate memory", test->test_name); +} + +int main(int argc, char **argv) +{ + int i; + unsigned int j; + test_descr_t *test = NULL; + + for (i = 0; i < argc; i++) { + char *arg = argv[i]; + + for (j = 0; j < ARRAY_SIZE(tests); j++) { + if (strcmp(arg, tests[j].test_name) == 0) + test = &tests[j]; + } + + /* Test modifiers */ + if (strstr(arg, "count=") != NULL) { + char *p = strstr(arg, "="); + + array_size = atol(p+1); + } else if (strcmp(arg, "wait") == 0) { + wait_if_ahead = 1; + } + } + + if (test) + setup_and_run_litmus(test); + else + report(false, "Unknown test"); + + return report_summary(); +} diff --git a/arm/mttcgtests.cfg b/arm/mttcgtests.cfg index 46fcb57..2b46756 100644 --- a/arm/mttcgtests.cfg +++ b/arm/mttcgtests.cfg @@ -57,3 +57,36 @@ file = locking-test.flat smp = $(($MAX_SMP>4?4:$MAX_SMP)) extra_params = -append 'excl' groups = locking + +# Barrier Litmus tests +[barrier-litmus::mp] +file = barrier-litmus-test.flat +smp = 2 +extra_params = -append 'mp' +groups = barrier + +[barrier-litmus::mp-barrier] +file = barrier-litmus-test.flat +smp = 2 +extra_params = -append 'mp_barrier' +groups = barrier + +[barrier-litmus::mp-acqrel] +file = barrier-litmus-test.flat +smp = 2 +extra_params = -append 'mp_acqrel' +groups = barrier + +[barrier-litmus::sal] +file = barrier-litmus-test.flat +smp = 2 +extra_params = -append 'sal' +groups = barrier +accel = tcg + +[barrier-litmus::sal-barrier] +file = barrier-litmus-test.flat +smp = 2 +extra_params = -append 'sal_barrier' +groups = barrier + From patchwork Thu Nov 18 18:46:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 12693076 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9A836C433EF for ; Thu, 18 Nov 2021 18:51:54 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6B6FB61AD2 for ; Thu, 18 Nov 2021 18:51:54 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 6B6FB61AD2 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=lGMck0TPdshn/G7bAEyQVu5TFzqb+9bXoA8o9ITtycY=; b=rPY7HrTgBA/WGG 44Kwf6kkiNVpSJWDaGSKMbl1QMyQCPTMyFJf8UHSy6GUzsbx8hiDRGGmo0qXJecqV18lAIaz3a7ki cSb4amqa3imor6I+ep71wOf3i3KFrDq6VZC2U+gllyR8ozt9ihaZUKecT5PRzXZIX+koLfShvaCNj qRaQNoXmg71R91CiD/ieikR/NbboiuSWdzcngJ7UuWiCUENUtuggSHMMJQjoEhguoNPxRdCUSUV3o asyXOaXrbO+JITPf+W7qT5ZVsJbT/4eGA9GSmkz9s1WeF3pkK52WA64Jg9Cn1XdpdfdZbPR0xWAWb rBGfZqMTtUNYw5AEQLIA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mnmUG-008eOa-2g; Thu, 18 Nov 2021 18:50:21 +0000 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mnmR8-008cy9-SD for linux-arm-kernel@lists.infradead.org; Thu, 18 Nov 2021 18:47:08 +0000 Received: by mail-wr1-x42e.google.com with SMTP id t30so13394638wra.10 for ; Thu, 18 Nov 2021 10:47:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4ZUZgHuD8NGUtXmK8AnZStWJy8xmbLtZriXcWFhy400=; b=tPWuwxoTarEuAMs1Cr0K1Krqok8qufGx6RqHKdovs46l6HbP+r9r+bOksExQa0YZDG AsoaKRil8lZWbPR012ZeNS/eQgdcSSwBTND/DHsfkJinAESipF/l47RgYCK7D9yD4Aio T8Y6P6sbDUNwqrn8MTUeJG7y6AvFCKD712kKLPvPaWNNtvKuinZplyk7fjbgm3kZsqRJ N3v3Jwa1Mfhb2Zk6CWQ2MOZQdSA3rbX5NknoDw2paAGO4VWketi0gk3I3DnClywHpIkE dGDdijAlG9Mj05jaZ8QvkdqOixKg8+Bx2d5lVU+Dt2aHvZ+f0HRxD75WSkOJoV62yoac BBGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4ZUZgHuD8NGUtXmK8AnZStWJy8xmbLtZriXcWFhy400=; b=OB3GnuVRhM8zyXzxRiHG8CDq/TMsRBOlvginMIv9MXoBHKCH3YuCO5FixZMZBlTgZK c4K4OG30w9r8Q4eUZpB0eX9WC4cY6u8R2AC0MFCTlSqZEwAG1ejOwpXProha1t38mwXg A70Y0a/lMygmQ3+TH5CCLkScyRqlZSnNFxBqDEUKcCrAZNMFAAFiR+05JbTPt8NyAmmj F1PM0+BCCPqP5L48UQPNY4RW3m/r9uQQNAEKtcC9koqPMGsUI7k280ECOhSu4UPPq2/z jSglzILRFxV+GLm2QZT/oIDN0Zzg4pXAQqY5G+dbNQ6/YJqHw4vD7WH+HRfuNsTbtBdn fpYA== X-Gm-Message-State: AOAM532wfHcrKR1YV2rnE6FMy0Bw+DM8nwRyX44TYMB8U5lEyDaRtac4 7BMMeUuiArkAeVuiafYPDuDS3Q== X-Google-Smtp-Source: ABdhPJwrdug8tImztTIg3ZfiYXxvh9yFWUBC2psfMHONmasEUnH8rpbLxJaonSmjf5pZLT3W2NFuZw== X-Received: by 2002:a05:6000:2a3:: with SMTP id l3mr34560244wry.415.1637261225009; Thu, 18 Nov 2021 10:47:05 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id y142sm458082wmc.40.2021.11.18.10.46.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Nov 2021 10:47:04 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 8504A1FFA5; Thu, 18 Nov 2021 18:46:50 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: kvm@vger.kernel.org Cc: idan.horowitz@gmail.com, qemu-arm@nongnu.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, christoffer.dall@arm.com, maz@kernel.org, =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [kvm-unit-tests PATCH v8 09/10] arm/run: use separate --accel form Date: Thu, 18 Nov 2021 18:46:49 +0000 Message-Id: <20211118184650.661575-10-alex.bennee@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211118184650.661575-1-alex.bennee@linaro.org> References: <20211118184650.661575-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211118_104706_938610_CBF8A5C5 X-CRM114-Status: GOOD ( 10.48 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This will allow TCG tests to alter things such as tb-size. Signed-off-by: Alex Bennée --- arm/run | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arm/run b/arm/run index a390ca5..73c6c83 100755 --- a/arm/run +++ b/arm/run @@ -58,8 +58,8 @@ if $qemu $M -device '?' 2>&1 | grep pci-testdev > /dev/null; then pci_testdev="-device pci-testdev" fi -M+=",accel=$ACCEL" -command="$qemu -nodefaults $M -cpu $processor $chr_testdev $pci_testdev" +A="-accel $ACCEL" +command="$qemu -nodefaults $M $A -cpu $processor $chr_testdev $pci_testdev" command+=" -display none -serial stdio -kernel" command="$(migration_cmd) $(timeout_cmd) $command" From patchwork Thu Nov 18 18:46:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 12693077 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD14DC433F5 for ; Thu, 18 Nov 2021 18:52:52 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 93CDF61A8A for ; Thu, 18 Nov 2021 18:52:52 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 93CDF61A8A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=CyfDW6+1rxD6HLpizwm1ocZAaL7UvdHVm5295HpJrMY=; b=BNx3oHeVSDTcHU 4twWlLYWvswwYd/ztA8AW5FcZmwF6+x4qlUVBKkmjFpRnfeiPWASytOOXRhpIL75Zr98fEOv/kF1b EzdKoguJUKjLc/bZBr6WUsBi6fjBLroRSdbOOaUhH8sNPsXFX4uFGeKwVNZZ2fFb9zjbe2p2ug9g9 me2OutFfRG7P7l5SRfdu3und6yeHr/FM1hHjxD6uYtpHiay3HuTRBmgQFnYJVUEu3wf9WRLlEPgBh 2MO8zv5vaelfnadSvrLIkUhUckqq/81GkMzIoaPBuMaL2i0Q0ToJ+ucGixPSWf3IGZk23mjX6FJz0 2mDPgqigbm+59xcaVL3Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mnmUt-008ekD-FN; Thu, 18 Nov 2021 18:51:00 +0000 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mnmRA-008cyr-15 for linux-arm-kernel@lists.infradead.org; Thu, 18 Nov 2021 18:47:10 +0000 Received: by mail-wr1-x42f.google.com with SMTP id d24so13499762wra.0 for ; Thu, 18 Nov 2021 10:47:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TeU0MZFr7GmLIe9/vyMfDVB2g60J2veSoHkG35ZbNRU=; b=Pd/DPYoZYGK6uFSc9H3U7K9hIQHjZYDFGKvzgclPl5DPJTFJduZkFHxkmqN0Q0XVt0 olajLeeHI5UwCkb0zJPcWDdWWZDbTPtD3wcdYmSOMnsUuptkWs3YhGRjmrHUh7leXPgi Pxpoyl7z40zimiERppRyHD/OhSekltv6UZDAkxcqCFGoeY677nqcQS3ArwhBnt8zAl+x VF7gnJvvDCnGXNM9cYFlx2GqUAlIe1JGZc3z0PB+b7qAfGGb52SX9QofuY2i7UmTmH3S 0/+TqS5gao/1ItCgFek6FkU8mP4hZ578ua5WVUzrO5sp+Cd3xf0teZhXkE8h4wah0mtx 6SOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TeU0MZFr7GmLIe9/vyMfDVB2g60J2veSoHkG35ZbNRU=; b=nMDL0PGoDqHAY185+9rI5E2ZpIvBIzFP4ENAASTlQk2VNgfa+Z3K3lfcgfnai5MnbX Bq4IAxul2tkF375WV9BhprPltcEbcjWQmJ7QzGdVUXS9oUcUBjgH1Ce52OmupjpgDzQF mdw526ozvfUvKfhJlGGZB1jK8ckeseZwD6gYWKCBkO5iCIQx57I6kXsJfMi39yZVTtJn lr4JHBVuwruW1kfignqr2zhgJhsNkIQjpysCkPiN8dtfKbksi2AKFs3VkdpsdVcxCHfK 8UvfrhWP0KoRNFTBEzSq8OmVJH8nc7P1Tyrz5/AqSN2fJ1maEKHdSFUOSTLKulqjpxlc 2Onw== X-Gm-Message-State: AOAM533VXyxfbUFx08LB1wpJlKz3GL5r8/iV+yQqS1tx01/BKGlB76F9 v7bb0/Zuoi7uWTg/uThX/7600w== X-Google-Smtp-Source: ABdhPJyi4lZaV7tRL7lIlmxYB1gYsRbfsC01Ue6vCZmf4ZgD1grz5/bZa1hgQf17fiTmeFj5lxx75w== X-Received: by 2002:a5d:5504:: with SMTP id b4mr34601005wrv.307.1637261225964; Thu, 18 Nov 2021 10:47:05 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id n32sm537042wms.42.2021.11.18.10.46.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Nov 2021 10:47:04 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 877EA1FFA6; Thu, 18 Nov 2021 18:46:50 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: kvm@vger.kernel.org Cc: idan.horowitz@gmail.com, qemu-arm@nongnu.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, christoffer.dall@arm.com, maz@kernel.org, =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [kvm-unit-tests PATCH v8 10/10] arm/tcg-test: some basic TCG exercising tests Date: Thu, 18 Nov 2021 18:46:50 +0000 Message-Id: <20211118184650.661575-11-alex.bennee@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211118184650.661575-1-alex.bennee@linaro.org> References: <20211118184650.661575-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211118_104708_140573_332D30AB X-CRM114-Status: GOOD ( 28.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org These tests are not really aimed at KVM at all but exist to stretch QEMU's TCG code generator. In particular these exercise the ability of the TCG to: * Chain TranslationBlocks together (tight) * Handle heavy usage of the tb_jump_cache (paged) * Pathological case of computed local jumps (computed) In addition the tests can be varied by adding IPI IRQs or SMC sequences into the mix to stress the tcg_exit and invalidation mechanisms. To explicitly stress the tb_flush() mechanism you can use the mod/rounds parameters to force more frequent tb invalidation. Combined with setting -tb-size 1 in QEMU to limit the code generation buffer size. Signed-off-by: Alex Bennée --- v5 - added armv8 version of the tcg tests - max out at -smp 4 in unittests.cfg - add up IRQs sent and delivered for PASS/FAIL - take into account error count - add "rounds=" parameter - tweak smc to tb-size=1 - printf fmt fix v7 - merged in IRQ numerology - updated to latest IRQ API v8 - fix report usage - fix checkpatch errors --- arm/Makefile.arm | 2 + arm/Makefile.arm64 | 2 + arm/Makefile.common | 1 + arm/tcg-test-asm.S | 171 ++++++++++++++++++++++ arm/tcg-test-asm64.S | 170 ++++++++++++++++++++++ arm/tcg-test.c | 338 +++++++++++++++++++++++++++++++++++++++++++ arm/mttcgtests.cfg | 84 +++++++++++ 7 files changed, 768 insertions(+) create mode 100644 arm/tcg-test-asm.S create mode 100644 arm/tcg-test-asm64.S create mode 100644 arm/tcg-test.c diff --git a/arm/Makefile.arm b/arm/Makefile.arm index 3a4cc6b..05e47f1 100644 --- a/arm/Makefile.arm +++ b/arm/Makefile.arm @@ -31,4 +31,6 @@ tests = include $(SRCDIR)/$(TEST_DIR)/Makefile.common +$(TEST_DIR)/tcg-test.elf: $(cstart.o) $(TEST_DIR)/tcg-test.o $(TEST_DIR)/tcg-test-asm.o + arch_clean: arm_clean diff --git a/arm/Makefile.arm64 b/arm/Makefile.arm64 index e8a38d7..ac94f8e 100644 --- a/arm/Makefile.arm64 +++ b/arm/Makefile.arm64 @@ -34,5 +34,7 @@ tests += $(TEST_DIR)/cache.flat include $(SRCDIR)/$(TEST_DIR)/Makefile.common +$(TEST_DIR)/tcg-test.elf: $(cstart.o) $(TEST_DIR)/tcg-test.o $(TEST_DIR)/tcg-test-asm64.o + arch_clean: arm_clean $(RM) lib/arm64/.*.d diff --git a/arm/Makefile.common b/arm/Makefile.common index 861e5c7..abb6948 100644 --- a/arm/Makefile.common +++ b/arm/Makefile.common @@ -14,6 +14,7 @@ tests-common += $(TEST_DIR)/pl031.flat tests-common += $(TEST_DIR)/tlbflush-code.flat tests-common += $(TEST_DIR)/locking-test.flat tests-common += $(TEST_DIR)/barrier-litmus-test.flat +tests-common += $(TEST_DIR)/tcg-test.flat tests-all = $(tests-common) $(tests) all: directories $(tests-all) diff --git a/arm/tcg-test-asm.S b/arm/tcg-test-asm.S new file mode 100644 index 0000000..4ec4978 --- /dev/null +++ b/arm/tcg-test-asm.S @@ -0,0 +1,171 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * TCG Test assembler functions for armv7 tests. + * + * Copyright (C) 2016, Linaro Ltd, Alex Bennée + * + * This work is licensed under the terms of the GNU LGPL, version 2. + * + * These helper functions are written in pure asm to control the size + * of the basic blocks and ensure they fit neatly into page + * aligned chunks. The pattern of branches they follow is determined by + * the 32 bit seed they are passed. It should be the same for each set. + * + * Calling convention + * - r0, iterations + * - r1, jump pattern + * - r2-r3, scratch + * + * Returns r0 + */ + +.arm + +.section .text + +/* Tight - all blocks should quickly be patched and should run + * very fast unless irqs or smc gets in the way + */ + +.global tight_start +tight_start: + subs r0, r0, #1 + beq tight_end + + ror r1, r1, #1 + tst r1, #1 + beq tightA + b tight_start + +tightA: + subs r0, r0, #1 + beq tight_end + + ror r1, r1, #1 + tst r1, #1 + beq tightB + b tight_start + +tightB: + subs r0, r0, #1 + beq tight_end + + ror r1, r1, #1 + tst r1, #1 + beq tight_start + b tightA + +.global tight_end +tight_end: + mov pc, lr + +/* + * Computed jumps cannot be hardwired into the basic blocks so each one + * will cause an exit for the main execution loop to look up the next block. + * + * There is some caching which should ameliorate the cost a little. + */ + + /* Align << 13 == 4096 byte alignment */ + .align 13 + .global computed_start +computed_start: + subs r0, r0, #1 + beq computed_end + + /* Jump table */ + ror r1, r1, #1 + and r2, r1, #1 + adr r3, computed_jump_table + ldr r2, [r3, r2, lsl #2] + mov pc, r2 + + b computed_err + +computed_jump_table: + .word computed_start + .word computedA + +computedA: + subs r0, r0, #1 + beq computed_end + + /* Jump into code */ + ror r1, r1, #1 + and r2, r1, #1 + adr r3, 1f + add r3, r2, lsl #2 + mov pc, r3 +1: b computed_start + b computedB + + b computed_err + + +computedB: + subs r0, r0, #1 + beq computed_end + ror r1, r1, #1 + + /* Conditional register load */ + adr r3, computedA + tst r1, #1 + adreq r3, computed_start + mov pc, r3 + + b computed_err + +computed_err: + mov r0, #1 + .global computed_end +computed_end: + mov pc, lr + + +/* + * Page hoping + * + * Each block is in a different page, hence the blocks never get joined + */ + /* Align << 13 == 4096 byte alignment */ + .align 13 + .global paged_start +paged_start: + subs r0, r0, #1 + beq paged_end + + ror r1, r1, #1 + tst r1, #1 + beq pagedA + b paged_start + + /* Align << 13 == 4096 byte alignment */ + .align 13 +pagedA: + subs r0, r0, #1 + beq paged_end + + ror r1, r1, #1 + tst r1, #1 + beq pagedB + b paged_start + + /* Align << 13 == 4096 byte alignment */ + .align 13 +pagedB: + subs r0, r0, #1 + beq paged_end + + ror r1, r1, #1 + tst r1, #1 + beq paged_start + b pagedA + + /* Align << 13 == 4096 byte alignment */ + .align 13 +.global paged_end +paged_end: + mov pc, lr + +.global test_code_end +test_code_end: diff --git a/arm/tcg-test-asm64.S b/arm/tcg-test-asm64.S new file mode 100644 index 0000000..2781eeb --- /dev/null +++ b/arm/tcg-test-asm64.S @@ -0,0 +1,170 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * TCG Test assembler functions for armv8 tests. + * + * Copyright (C) 2016, Linaro Ltd, Alex Bennée + * + * This work is licensed under the terms of the GNU LGPL, version 2. + * + * These helper functions are written in pure asm to control the size + * of the basic blocks and ensure they fit neatly into page + * aligned chunks. The pattern of branches they follow is determined by + * the 32 bit seed they are passed. It should be the same for each set. + * + * Calling convention + * - x0, iterations + * - x1, jump pattern + * - x2-x3, scratch + * + * Returns x0 + */ + +.section .text + +/* Tight - all blocks should quickly be patched and should run + * very fast unless irqs or smc gets in the way + */ + +.global tight_start +tight_start: + subs x0, x0, #1 + beq tight_end + + ror x1, x1, #1 + tst x1, #1 + beq tightA + b tight_start + +tightA: + subs x0, x0, #1 + beq tight_end + + ror x1, x1, #1 + tst x1, #1 + beq tightB + b tight_start + +tightB: + subs x0, x0, #1 + beq tight_end + + ror x1, x1, #1 + tst x1, #1 + beq tight_start + b tightA + +.global tight_end +tight_end: + ret + +/* + * Computed jumps cannot be hardwired into the basic blocks so each one + * will cause an exit for the main execution loop to look up the next block. + * + * There is some caching which should ameliorate the cost a little. + */ + + /* Align << 13 == 4096 byte alignment */ + .align 13 + .global computed_start +computed_start: + subs x0, x0, #1 + beq computed_end + + /* Jump table */ + ror x1, x1, #1 + and x2, x1, #1 + adr x3, computed_jump_table + ldr x2, [x3, x2, lsl #3] + br x2 + + b computed_err + +computed_jump_table: + .quad computed_start + .quad computedA + +computedA: + subs x0, x0, #1 + beq computed_end + + /* Jump into code */ + ror x1, x1, #1 + and x2, x1, #1 + adr x3, 1f + add x3, x3, x2, lsl #2 + br x3 +1: b computed_start + b computedB + + b computed_err + + +computedB: + subs x0, x0, #1 + beq computed_end + ror x1, x1, #1 + + /* Conditional register load */ + adr x2, computedA + adr x3, computed_start + tst x1, #1 + csel x2, x3, x2, eq + br x2 + + b computed_err + +computed_err: + mov x0, #1 + .global computed_end +computed_end: + ret + + +/* + * Page hoping + * + * Each block is in a different page, hence the blocks never get joined + */ + /* Align << 13 == 4096 byte alignment */ + .align 13 + .global paged_start +paged_start: + subs x0, x0, #1 + beq paged_end + + ror x1, x1, #1 + tst x1, #1 + beq pagedA + b paged_start + + /* Align << 13 == 4096 byte alignment */ + .align 13 +pagedA: + subs x0, x0, #1 + beq paged_end + + ror x1, x1, #1 + tst x1, #1 + beq pagedB + b paged_start + + /* Align << 13 == 4096 byte alignment */ + .align 13 +pagedB: + subs x0, x0, #1 + beq paged_end + + ror x1, x1, #1 + tst x1, #1 + beq paged_start + b pagedA + + /* Align << 13 == 4096 byte alignment */ + .align 13 +.global paged_end +paged_end: + ret + +.global test_code_end +test_code_end: diff --git a/arm/tcg-test.c b/arm/tcg-test.c new file mode 100644 index 0000000..fddab7b --- /dev/null +++ b/arm/tcg-test.c @@ -0,0 +1,338 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * ARM TCG Tests + * + * These tests are explicitly aimed at stretching the QEMU TCG engine. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#define MAX_CPUS 8 + +/* These entry points are in the assembly code */ +extern int tight_start(uint32_t count, uint32_t pattern); +extern int computed_start(uint32_t count, uint32_t pattern); +extern int paged_start(uint32_t count, uint32_t pattern); +extern uint32_t tight_end; +extern uint32_t computed_end; +extern uint32_t paged_end; +extern unsigned long test_code_end; + +typedef int (*test_fn)(uint32_t count, uint32_t pattern); + +typedef struct { + const char *test_name; + bool should_pass; + test_fn start_fn; + uint32_t *code_end; +} test_descr_t; + +/* Test array */ +static test_descr_t tests[] = { + /* + * Tight chain. + * + * These are a bunch of basic blocks that have fixed branches in + * a page aligned space. The branches taken are decided by a + * psuedo-random bitmap for each CPU. + * + * Once the basic blocks have been chained together by the TCG they + * should run until they reach their block count. This will be the + * most efficient mode in which generated code is run. The only other + * exits will be caused by interrupts or TB invalidation. + */ + { "tight", true, tight_start, &tight_end }, + /* + * Computed jumps. + * + * A bunch of basic blocks which just do computed jumps so the basic + * block is never chained but they are all within a page (maybe not + * required). This will exercise the cache lookup but not the new + * generation. + */ + { "computed", true, computed_start, &computed_end }, + /* + * Page ping pong. + * + * Have the blocks are separated by PAGE_SIZE so they can never + * be chained together. + * + */ + { "paged", true, paged_start, &paged_end} +}; + +static test_descr_t *test; + +static int iterations = 1000000; +static int rounds = 1000; +static int mod_freq = 5; +static uint32_t pattern[MAX_CPUS]; + +/* control flags */ +static int smc; +static int irq; +static int check_irq; + +/* IRQ accounting */ +#define MAX_IRQ_IDS 16 +static int irqv; +static unsigned long irq_sent_ts[MAX_CPUS][MAX_CPUS][MAX_IRQ_IDS]; + +static int irq_recv[MAX_CPUS]; +static int irq_sent[MAX_CPUS]; +static int irq_overlap[MAX_CPUS]; /* if ts > now, i.e a race */ +static int irq_slow[MAX_CPUS]; /* if delay > threshold */ +static unsigned long irq_latency[MAX_CPUS]; /* cumulative time */ + +static int errors[MAX_CPUS]; + +static cpumask_t smp_test_complete; + +static cpumask_t ready; + +static void wait_on_ready(void) +{ + cpumask_set_cpu(smp_processor_id(), &ready); + while (!cpumask_full(&ready)) + cpu_relax(); +} + +/* This triggers TCGs SMC detection by writing values to the executing + * code pages. We are not actually modifying the instructions and the + * underlying code will remain unchanged. However this should trigger + * invalidation of the Translation Blocks + */ + +static void trigger_smc_detection(uint32_t *start, uint32_t *end) +{ + volatile uint32_t *ptr = start; + + while (ptr < end) { + uint32_t inst = *ptr; + *ptr++ = inst; + } +} + +/* Handler for receiving IRQs */ + +static void irq_handler(struct pt_regs *regs __unused) +{ + unsigned long then, now = get_cntvct(); + int cpu = smp_processor_id(); + u32 irqstat = gic_read_iar(); + u32 irqnr = gic_iar_irqnr(irqstat); + + if (irqnr != GICC_INT_SPURIOUS) { + unsigned int src_cpu = (irqstat >> 10) & 0x7; + + gic_write_eoir(irqstat); + irq_recv[cpu]++; + + then = irq_sent_ts[src_cpu][cpu][irqnr]; + + if (then > now) { + irq_overlap[cpu]++; + } else { + unsigned long latency = (now - then); + + if (latency > 30000) + irq_slow[cpu]++; + else + irq_latency[cpu] += latency; + } + } +} + +/* This triggers cross-CPU IRQs. Each IRQ should cause the basic block + * execution to finish the main run-loop get entered again. + */ +static int send_cross_cpu_irqs(int this_cpu, int irq) +{ + int cpu, sent = 0; + cpumask_t mask; + + cpumask_copy(&mask, &cpu_present_mask); + + for_each_present_cpu(cpu) { + if (cpu != this_cpu) { + irq_sent_ts[this_cpu][cpu][irq] = get_cntvct(); + cpumask_clear_cpu(cpu, &mask); + sent++; + } + } + + gic_ipi_send_mask(irq, &mask); + + return sent; +} + +static void do_test(void) +{ + int cpu = smp_processor_id(); + int i, irq_id = 0; + + printf("CPU%d: online and setting up with pattern 0x%"PRIx32"\n", + cpu, pattern[cpu]); + + if (irq) { + gic_enable_defaults(); +#ifdef __arm__ + install_exception_handler(EXCPTN_IRQ, irq_handler); +#else + install_irq_handler(EL1H_IRQ, irq_handler); +#endif + local_irq_enable(); + + wait_on_ready(); + } + + for (i = 0; i < rounds; i++) { + /* Enter the blocks */ + errors[cpu] += test->start_fn(iterations, pattern[cpu]); + + if ((i + cpu) % mod_freq == 0) { + if (smc) + trigger_smc_detection((uint32_t *) test->start_fn, + test->code_end); + + if (irq) { + irq_sent[cpu] += send_cross_cpu_irqs(cpu, irq_id); + irq_id++; + irq_id = irq_id % 15; + } + } + } + + /* ensure everything complete before we finish */ + smp_wmb(); + + cpumask_set_cpu(cpu, &smp_test_complete); + if (cpu != 0) + halt(); +} + +static void report_irq_stats(int cpu) +{ + int recv = irq_recv[cpu]; + int race = irq_overlap[cpu]; + int slow = irq_slow[cpu]; + + unsigned long avg_latency = irq_latency[cpu] / (recv - (race + slow)); + + printf("CPU%d: %d irqs (%d races, %d slow, %ld ticks avg latency)\n", + cpu, recv, race, slow, avg_latency); +} + + +static void setup_and_run_tcg_test(void) +{ + static const unsigned char seed[] = "tcg-test"; + struct isaac_ctx prng_context; + int cpu; + int total_err = 0, total_sent = 0, total_recv = 0; + + isaac_init(&prng_context, &seed[0], sizeof(seed)); + + /* boot other CPUs */ + for_each_present_cpu(cpu) { + pattern[cpu] = isaac_next_uint32(&prng_context); + + if (cpu == 0) + continue; + + smp_boot_secondary(cpu, do_test); + } + + do_test(); + + while (!cpumask_full(&smp_test_complete)) + cpu_relax(); + + /* Ensure everything completes before we check the data */ + smp_mb(); + + /* Now total up errors and irqs */ + for_each_present_cpu(cpu) { + total_err += errors[cpu]; + total_sent += irq_sent[cpu]; + total_recv += irq_recv[cpu]; + + if (check_irq) + report_irq_stats(cpu); + } + + if (check_irq) + report(total_sent == total_recv && total_err == 0, + "%d IRQs sent, %d received, %d errors\n", + total_sent, total_recv, total_err == 0); + else + report(total_err == 0, "%d errors, IRQs not checked", total_err); +} + +int main(int argc, char **argv) +{ + int i; + unsigned int j; + + for (i = 0; i < argc; i++) { + char *arg = argv[i]; + + for (j = 0; j < ARRAY_SIZE(tests); j++) { + if (strcmp(arg, tests[j].test_name) == 0) + test = &tests[j]; + } + + /* Test modifiers */ + if (strstr(arg, "mod=") != NULL) { + char *p = strstr(arg, "="); + + mod_freq = atol(p+1); + } + + if (strstr(arg, "rounds=") != NULL) { + char *p = strstr(arg, "="); + + rounds = atol(p+1); + } + + if (strcmp(arg, "smc") == 0) { + unsigned long test_start = (unsigned long) &tight_start; + unsigned long test_end = (unsigned long) &test_code_end; + + smc = 1; + mmu_set_range_ptes(mmu_idmap, test_start, test_start, test_end, + __pgprot(PTE_WBWA)); + + report_prefix_push("smc"); + } + + if (strcmp(arg, "irq") == 0) { + irq = 1; + if (!gic_init()) + report_abort("No supported gic present!"); + irqv = gic_version(); + report_prefix_push("irq"); + } + + if (strcmp(arg, "check_irq") == 0) + check_irq = 1; + } + + if (test) { + /* ensure args visible to all cores */ + smp_mb(); + setup_and_run_tcg_test(); + } else { + report(false, "Unknown test"); + } + + return report_summary(); +} diff --git a/arm/mttcgtests.cfg b/arm/mttcgtests.cfg index 2b46756..046a59c 100644 --- a/arm/mttcgtests.cfg +++ b/arm/mttcgtests.cfg @@ -90,3 +90,87 @@ smp = 2 extra_params = -append 'sal_barrier' groups = barrier +# TCG Tests +[tcg::tight] +file = tcg-test.flat +smp = $(($MAX_SMP>4?4:$MAX_SMP)) +extra_params = -append 'tight' +groups = tcg +accel = tcg + +[tcg::tight-smc] +file = tcg-test.flat +smp = $(($MAX_SMP>4?4:$MAX_SMP)) +extra_params = -append 'tight smc' -accel tcg,tb-size=1 +groups = tcg +accel = tcg + +[tcg::tight-irq] +file = tcg-test.flat +smp = $(($MAX_SMP>4?4:$MAX_SMP)) +extra_params = -append 'tight irq' +groups = tcg +accel = tcg + +[tcg::tight-smc-irq] +file = tcg-test.flat +smp = $(($MAX_SMP>4?4:$MAX_SMP)) +extra_params = -append 'tight smc irq' +groups = tcg +accel = tcg + +[tcg::computed] +file = tcg-test.flat +smp = $(($MAX_SMP>4?4:$MAX_SMP)) +extra_params = -append 'computed' +groups = tcg +accel = tcg + +[tcg::computed-smc] +file = tcg-test.flat +smp = $(($MAX_SMP>4?4:$MAX_SMP)) +extra_params = -append 'computed smc' +groups = tcg +accel = tcg + +[tcg::computed-irq] +file = tcg-test.flat +smp = $(($MAX_SMP>4?4:$MAX_SMP)) +extra_params = -append 'computed irq' +groups = tcg +accel = tcg + +[tcg::computed-smc-irq] +file = tcg-test.flat +smp = $(($MAX_SMP>4?4:$MAX_SMP)) +extra_params = -append 'computed smc irq' +groups = tcg +accel = tcg + +[tcg::paged] +file = tcg-test.flat +smp = $(($MAX_SMP>4?4:$MAX_SMP)) +extra_params = -append 'paged' +groups = tcg +accel = tcg + +[tcg::paged-smc] +file = tcg-test.flat +smp = $(($MAX_SMP>4?4:$MAX_SMP)) +extra_params = -append 'paged smc' +groups = tcg +accel = tcg + +[tcg::paged-irq] +file = tcg-test.flat +smp = $(($MAX_SMP>4?4:$MAX_SMP)) +extra_params = -append 'paged irq' +groups = tcg +accel = tcg + +[tcg::paged-smc-irq] +file = tcg-test.flat +smp = $(($MAX_SMP>4?4:$MAX_SMP)) +extra_params = -append 'paged smc irq' +groups = tcg +accel = tcg