From patchwork Tue Nov 23 21:01:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver Upton X-Patchwork-Id: 12693501 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2A11BC433F5 for ; Tue, 23 Nov 2021 21:03:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=Qu6jn552Y09Hi5wug5Hv479l7tZkaNcXznCPQNLnyL4=; b=p2uigk9kJpGp3I4dCakX5k+LM/ Q6eeF4u2YWwu4kvuSalqEpU+Q7Y6/CMsnpawnETeD8lq2yyA1r5BYsGL7V4qkmAUTMpZD/hV5uXnM UBpjrZ7iKRvBuBFJXJdsN/k63bARIpbjbB+fM8AUYXm0EbqgJH/jN7lrMhYdljOM6bbrE12dGzS5E nvSTxlIM9JOoePtyCETvZD8vGKGBp4fwd0F9a1+ppH5YuvQar1dUm7zGluSPVllElE58EZqBYd4nL lyu2WN5fP+xnKcfBMfl1dipoHAbaBme2sUYzLgMNXQK2aETo9TlJBtWlkVi90qGIg6Xq1eI9HuJCy 2a9fS5tw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mpcuo-003Ske-JI; Tue, 23 Nov 2021 21:01:22 +0000 Received: from mail-io1-xd49.google.com ([2607:f8b0:4864:20::d49]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mpcuj-003SiE-Vd for linux-arm-kernel@lists.infradead.org; Tue, 23 Nov 2021 21:01:19 +0000 Received: by mail-io1-xd49.google.com with SMTP id h16-20020a056602155000b005ec7daa8de5so134723iow.16 for ; Tue, 23 Nov 2021 13:01:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=zz/xhPyoPXicYUMo26iz+W4ztk9QLIUECi8yH0EE7Hg=; b=FPW2vvMEF0DWDy4pjYuYom7O9yhLArCXJ1IIIMafjH4l9SQfuEz8J6FSjgPKgvHDaK DeBp6PeziJvrhgneRyz+rm+FkgN/NezBffwxGMpDfggznwqV99WmAWiZCD8N2DgV1bS8 r2QDDazxIzsxwyPXvSZihMTMmtbjUrPbY83UArR2T/PZBc1y88t0Sc7je51Z/CSxSHai ZRcYz8NU/ysUeWm25rP3blxxgU8VDJdjei2+qBFGiFDtkXqyuiogjzH82aK/MyhahMWb 4LPyjD+RYSfQeNq7mCdSe6sIs/C0e/fUK+K8PkaIOIWtK73aljR+R1fxD0uS0UQ/jq0U 7Tpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=zz/xhPyoPXicYUMo26iz+W4ztk9QLIUECi8yH0EE7Hg=; b=AOJ5dwnys3/n0vbgIk4yRITRNON8apKL8gg1iJCIBvsWv54WgbQNAeq0Y9/ZJqLn4o 3EiVJ225JNjiB5UFxTGTQ6/TYbB2MSDZ4XKT+35rIMloVQ6Eg5PUMtp3tQbwHtHRb0MF g90MkaolB0WrzKoLu0veEW5CFmS8CQdBQMNjnnlBfY4EIimiQlmVbnDcEj7XG3dY9P1/ QQx1jUgVICcxg9ve6TB6IKmEIEFh2qQsYJiTw83eUu/qURXd9uItBSoejzhy94YyKj60 bNs0OsKy528sWtWAbCyh/75GyeGcr2opvJj04HCBHCbLB3WHV1+hmw4rPBKPlQyODqZa ze+g== X-Gm-Message-State: AOAM530Be8vtUlgrS5FoEurdAzJmaVe7QJNmlH/r7l534cJE/wDj2Gd7 zJ1rjTkx+YyPqOJcGevSo37CfPKtVkU= X-Google-Smtp-Source: ABdhPJx+by8JvSWhwxRKIldPBbHOsPDBS6NTTo+dJ01tZHkK4K1KEKpOIEbd3eNqZtzCQs9wCBQyxE4E9+Y= X-Received: from oupton.c.googlers.com ([fda3:e722:ac3:cc00:2b:ff92:c0a8:404]) (user=oupton job=sendgmr) by 2002:a05:6602:2b10:: with SMTP id p16mr9105121iov.2.1637701277092; Tue, 23 Nov 2021 13:01:17 -0800 (PST) Date: Tue, 23 Nov 2021 21:01:04 +0000 In-Reply-To: <20211123210109.1605642-1-oupton@google.com> Message-Id: <20211123210109.1605642-2-oupton@google.com> Mime-Version: 1.0 References: <20211123210109.1605642-1-oupton@google.com> X-Mailer: git-send-email 2.34.0.rc2.393.gf8c9666880-goog Subject: [PATCH v3 1/6] KVM: arm64: Correctly treat writes to OSLSR_EL1 as undefined From: Oliver Upton To: kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, Marc Zyngier , James Morse , Alexandru Elisei , Suzuki K Poulose , linux-arm-kernel@lists.infradead.org, Andrew Jones , Peter Shier , Ricardo Koller , Reiji Watanabe , Oliver Upton X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211123_130118_066798_2AF1F577 X-CRM114-Status: GOOD ( 12.23 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Any valid implementation of the architecture should generate an undefined exception for writes to a read-only register, such as OSLSR_EL1. Nonetheless, the KVM handler actually implements write-ignore behavior. Align the trap handler for OSLSR_EL1 with hardware behavior. If such a write ever traps to EL2, inject an undef into the guest and print a warning. Reviewed-by: Reiji Watanabe Signed-off-by: Oliver Upton --- arch/arm64/kvm/sys_regs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index e3ec1a44f94d..11b4212c2036 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -292,7 +292,7 @@ static bool trap_oslsr_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) { if (p->is_write) { - return ignore_write(vcpu, p); + return write_to_read_only(vcpu, p, r); } else { p->regval = (1 << 3); return true; From patchwork Tue Nov 23 21:01:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver Upton X-Patchwork-Id: 12693503 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C6B00C433FE for ; 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Tue, 23 Nov 2021 21:01:54 +0000 Received: from mail-il1-x149.google.com ([2607:f8b0:4864:20::149]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mpcul-003Sj9-Lw for linux-arm-kernel@lists.infradead.org; Tue, 23 Nov 2021 21:01:21 +0000 Received: by mail-il1-x149.google.com with SMTP id d8-20020a928748000000b0027585828bc3so229968ilm.7 for ; Tue, 23 Nov 2021 13:01:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=3r/HSQlSMaGqGuO6qlyByqylj4w37aYh03CWLKihWyE=; b=I8o6vjAywpa6ruSUYX/8rdQEeBmRUvrZry6knOs03Fgu95sSJgIAGoEOAm5r52PDyM OPUu6j2D962rPDVnZCg/PcPaiRpKDm27kqyLUztlCTLwup2hcjFYHG7RZ4r4CJHzjpjo 47XmcQns0NFxIW4y+Tam+CSpz0of/dHbWg06/kEztW/6TQd9Jtg184l9TrwZiJG22i8G Ya24YTmfCQKVw8J7RVMbFS7QOLYgstBAxVflKJRtxOBJKbsWMs2c3RD6WxijeZUXsOTA k0aYjkpMBXtBcwytCiuXiX9UvwE4imWn/KbfC7lMdFNzMHklDMH/bAN/hYO5xQ3AAg4g 2e2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=3r/HSQlSMaGqGuO6qlyByqylj4w37aYh03CWLKihWyE=; b=6A/Nu0xzCtHu2t9HkFnsfKqD7UzygDdJ8/Nj6+BuD6o/0rgs89No9NjUgEae/0Lu3s KtrQLjNutDd7HlNsU4fDK/LBa5HN+mfMgDXWPqn1bLA8XG61oZKUc2QyLwCKiOI9mEEm SLltaxoBzMINlogFnM556e/KvI63TRRA2E6IE6ON9oEgcvSoXRSAaGOvxCtS3taX458C SoH5m0qTb5pjK3cH2PdYvvjkA/C0IJji6lyZXiyZcoPrVEeTTdbWO90xY+r9mRyQ317W cvT4NYFwOg8yktcM98E7ROzKarAH2lfzt+HU/X92N8dBZKsHtCnriGaAYxfrYjoLoViR iyFw== X-Gm-Message-State: AOAM531qEc9CpHhiH3VjheH49b59LqbEHK6xT+0FwwDzD5bIzUDbFIvT 8VnHGmIhKUzNuo2BtpapO4GbZiJfCrw= X-Google-Smtp-Source: ABdhPJyC0nmrb9p3Fph5PiHQgzCf4XqAVV9qwdGI+BZkjpGMX0GXawApszVLVF40+DN93mTIiNXihq0S8Bg= X-Received: from oupton.c.googlers.com ([fda3:e722:ac3:cc00:2b:ff92:c0a8:404]) (user=oupton job=sendgmr) by 2002:a05:6e02:2146:: with SMTP id d6mr7996051ilv.45.1637701278015; Tue, 23 Nov 2021 13:01:18 -0800 (PST) Date: Tue, 23 Nov 2021 21:01:05 +0000 In-Reply-To: <20211123210109.1605642-1-oupton@google.com> Message-Id: <20211123210109.1605642-3-oupton@google.com> Mime-Version: 1.0 References: <20211123210109.1605642-1-oupton@google.com> X-Mailer: git-send-email 2.34.0.rc2.393.gf8c9666880-goog Subject: [PATCH v3 2/6] KVM: arm64: Stash OSLSR_EL1 in the cpu context From: Oliver Upton To: kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, Marc Zyngier , James Morse , Alexandru Elisei , Suzuki K Poulose , linux-arm-kernel@lists.infradead.org, Andrew Jones , Peter Shier , Ricardo Koller , Reiji Watanabe , Oliver Upton X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211123_130119_746533_D90E06AB X-CRM114-Status: GOOD ( 14.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org An upcoming change to KVM will context switch the OS Lock status between guest/host. Add OSLSR_EL1 to the cpu context and handle guest reads using the stored value. Wire up a custom handler for writes from userspace and prevent any of the invariant bits from changing. Reviewed-by: Reiji Watanabe Signed-off-by: Oliver Upton --- arch/arm64/include/asm/kvm_host.h | 2 ++ arch/arm64/kvm/sys_regs.c | 31 ++++++++++++++++++++++++------- 2 files changed, 26 insertions(+), 7 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 2a5f7f38006f..53fc8a6eaf1c 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -172,8 +172,10 @@ enum vcpu_sysreg { PAR_EL1, /* Physical Address Register */ MDSCR_EL1, /* Monitor Debug System Control Register */ MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */ + OSLSR_EL1, /* OS Lock Status Register */ DISR_EL1, /* Deferred Interrupt Status Register */ + /* Performance Monitors Registers */ PMCR_EL0, /* Control Register */ PMSELR_EL0, /* Event Counter Selection Register */ diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 11b4212c2036..7bf350b3d9cd 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -291,12 +291,28 @@ static bool trap_oslsr_el1(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) { - if (p->is_write) { + if (p->is_write) return write_to_read_only(vcpu, p, r); - } else { - p->regval = (1 << 3); - return true; - } + + p->regval = __vcpu_sys_reg(vcpu, r->reg); + return true; +} + +static int set_oslsr_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, + const struct kvm_one_reg *reg, void __user *uaddr) +{ + u64 id = sys_reg_to_index(rd); + u64 val; + int err; + + err = reg_from_user(&val, uaddr, id); + if (err) + return err; + + if (val != rd->val) + return -EINVAL; + + return 0; } static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu, @@ -1448,7 +1464,8 @@ static const struct sys_reg_desc sys_reg_descs[] = { { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi }, { SYS_DESC(SYS_OSLAR_EL1), trap_raz_wi }, - { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1 }, + { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_val, OSLSR_EL1, 0x00000008, + .set_user = set_oslsr_el1, }, { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi }, { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi }, { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi }, @@ -1923,7 +1940,7 @@ static const struct sys_reg_desc cp14_regs[] = { { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi }, DBGBXVR(1), /* DBGOSLSR */ - { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1 }, + { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1, NULL, OSLSR_EL1 }, DBGBXVR(2), DBGBXVR(3), /* DBGOSDLR */ From patchwork Tue Nov 23 21:01:06 2021 Content-Type: text/plain; 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Tue, 23 Nov 2021 13:01:19 -0800 (PST) Date: Tue, 23 Nov 2021 21:01:06 +0000 In-Reply-To: <20211123210109.1605642-1-oupton@google.com> Message-Id: <20211123210109.1605642-4-oupton@google.com> Mime-Version: 1.0 References: <20211123210109.1605642-1-oupton@google.com> X-Mailer: git-send-email 2.34.0.rc2.393.gf8c9666880-goog Subject: [PATCH v3 3/6] KVM: arm64: Allow guest to set the OSLK bit From: Oliver Upton To: kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, Marc Zyngier , James Morse , Alexandru Elisei , Suzuki K Poulose , linux-arm-kernel@lists.infradead.org, Andrew Jones , Peter Shier , Ricardo Koller , Reiji Watanabe , Oliver Upton X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211123_130120_481035_E7F75D01 X-CRM114-Status: GOOD ( 15.66 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Allow writes to OSLAR and forward the OSLK bit to OSLSR. Do nothing with the value for now. Reviewed-by: Reiji Watanabe Signed-off-by: Oliver Upton --- arch/arm64/include/asm/sysreg.h | 6 ++++++ arch/arm64/kvm/sys_regs.c | 33 ++++++++++++++++++++++++++------- 2 files changed, 32 insertions(+), 7 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 16b3f1a1d468..9fad61a82047 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -129,7 +129,13 @@ #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7) #define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0) #define SYS_OSLAR_EL1 sys_reg(2, 0, 1, 0, 4) + +#define SYS_OSLAR_OSLK BIT(0) + #define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4) + +#define SYS_OSLSR_OSLK BIT(1) + #define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4) #define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4) #define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 7bf350b3d9cd..5dbdb45d6d44 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -44,6 +44,10 @@ * 64bit interface. */ +static int reg_from_user(u64 *val, const void __user *uaddr, u64 id); +static int reg_to_user(void __user *uaddr, const u64 *val, u64 id); +static u64 sys_reg_to_index(const struct sys_reg_desc *reg); + static bool read_from_write_only(struct kvm_vcpu *vcpu, struct sys_reg_params *params, const struct sys_reg_desc *r) @@ -287,6 +291,24 @@ static bool trap_loregion(struct kvm_vcpu *vcpu, return trap_raz_wi(vcpu, p, r); } +static bool trap_oslar_el1(struct kvm_vcpu *vcpu, + struct sys_reg_params *p, + const struct sys_reg_desc *r) +{ + u64 oslsr; + + if (!p->is_write) + return read_from_write_only(vcpu, p, r); + + /* Forward the OSLK bit to OSLSR */ + oslsr = __vcpu_sys_reg(vcpu, OSLSR_EL1) & ~SYS_OSLSR_OSLK; + if (p->regval & SYS_OSLAR_OSLK) + oslsr |= SYS_OSLSR_OSLK; + + __vcpu_sys_reg(vcpu, OSLSR_EL1) = oslsr; + return true; +} + static bool trap_oslsr_el1(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) @@ -309,9 +331,10 @@ static int set_oslsr_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, if (err) return err; - if (val != rd->val) + if ((val & ~SYS_OSLSR_OSLK) != rd->val) return -EINVAL; + __vcpu_sys_reg(vcpu, rd->reg) = val; return 0; } @@ -1180,10 +1203,6 @@ static bool access_raz_id_reg(struct kvm_vcpu *vcpu, return __access_id_reg(vcpu, p, r, true); } -static int reg_from_user(u64 *val, const void __user *uaddr, u64 id); -static int reg_to_user(void __user *uaddr, const u64 *val, u64 id); -static u64 sys_reg_to_index(const struct sys_reg_desc *reg); - /* Visibility overrides for SVE-specific control registers */ static unsigned int sve_visibility(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd) @@ -1463,7 +1482,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { DBG_BCR_BVR_WCR_WVR_EL1(15), { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi }, - { SYS_DESC(SYS_OSLAR_EL1), trap_raz_wi }, + { SYS_DESC(SYS_OSLAR_EL1), trap_oslar_el1 }, { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_val, OSLSR_EL1, 0x00000008, .set_user = set_oslsr_el1, }, { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi }, @@ -1937,7 +1956,7 @@ static const struct sys_reg_desc cp14_regs[] = { DBGBXVR(0), /* DBGOSLAR */ - { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi }, + { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_oslar_el1 }, DBGBXVR(1), /* DBGOSLSR */ { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1, NULL, OSLSR_EL1 }, From patchwork Tue Nov 23 21:01:07 2021 Content-Type: text/plain; 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Tue, 23 Nov 2021 13:01:19 -0800 (PST) Date: Tue, 23 Nov 2021 21:01:07 +0000 In-Reply-To: <20211123210109.1605642-1-oupton@google.com> Message-Id: <20211123210109.1605642-5-oupton@google.com> Mime-Version: 1.0 References: <20211123210109.1605642-1-oupton@google.com> X-Mailer: git-send-email 2.34.0.rc2.393.gf8c9666880-goog Subject: [PATCH v3 4/6] KVM: arm64: Emulate the OS Lock From: Oliver Upton To: kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, Marc Zyngier , James Morse , Alexandru Elisei , Suzuki K Poulose , linux-arm-kernel@lists.infradead.org, Andrew Jones , Peter Shier , Ricardo Koller , Reiji Watanabe , Oliver Upton X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211123_130121_081040_1B73A2A1 X-CRM114-Status: GOOD ( 19.80 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The OS lock blocks all debug exceptions at every EL. To date, KVM has not implemented the OS lock for its guests, despite the fact that it is mandatory per the architecture. Simple context switching between the guest and host is not appropriate, as its effects are not constrained to the guest context. Emulate the OS Lock by clearing MDE and SS in MDSCR_EL1, thereby blocking all but software breakpoint instructions. To handle breakpoint instructions, trap debug exceptions to EL2 and skip the instruction. Signed-off-by: Oliver Upton --- arch/arm64/include/asm/kvm_host.h | 4 ++++ arch/arm64/kvm/debug.c | 27 +++++++++++++++++++++++---- arch/arm64/kvm/sys_regs.c | 6 +++--- 3 files changed, 30 insertions(+), 7 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 53fc8a6eaf1c..e5a06ff1cba6 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -726,6 +726,10 @@ void kvm_arm_vcpu_init_debug(struct kvm_vcpu *vcpu); void kvm_arm_setup_debug(struct kvm_vcpu *vcpu); void kvm_arm_clear_debug(struct kvm_vcpu *vcpu); void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu); + +#define kvm_vcpu_os_lock_enabled(vcpu) \ + (!!(__vcpu_sys_reg(vcpu, OSLSR_EL1) & SYS_OSLSR_OSLK)) + int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr); int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu, diff --git a/arch/arm64/kvm/debug.c b/arch/arm64/kvm/debug.c index db9361338b2a..7835c76347ce 100644 --- a/arch/arm64/kvm/debug.c +++ b/arch/arm64/kvm/debug.c @@ -53,6 +53,14 @@ static void restore_guest_debug_regs(struct kvm_vcpu *vcpu) vcpu_read_sys_reg(vcpu, MDSCR_EL1)); } +/* + * Returns true if the host needs to use the debug registers. + */ +static inline bool host_using_debug_regs(struct kvm_vcpu *vcpu) +{ + return vcpu->guest_debug || kvm_vcpu_os_lock_enabled(vcpu); +} + /** * kvm_arm_init_debug - grab what we need for debug * @@ -105,9 +113,11 @@ static void kvm_arm_setup_mdcr_el2(struct kvm_vcpu *vcpu) * - Userspace is using the hardware to debug the guest * (KVM_GUESTDBG_USE_HW is set). * - The guest is not using debug (KVM_ARM64_DEBUG_DIRTY is clear). + * - The guest has enabled the OS Lock (debug exceptions are blocked). */ if ((vcpu->guest_debug & KVM_GUESTDBG_USE_HW) || - !(vcpu->arch.flags & KVM_ARM64_DEBUG_DIRTY)) + !(vcpu->arch.flags & KVM_ARM64_DEBUG_DIRTY) || + kvm_vcpu_os_lock_enabled(vcpu)) vcpu->arch.mdcr_el2 |= MDCR_EL2_TDA; trace_kvm_arm_set_dreg32("MDCR_EL2", vcpu->arch.mdcr_el2); @@ -160,8 +170,10 @@ void kvm_arm_setup_debug(struct kvm_vcpu *vcpu) kvm_arm_setup_mdcr_el2(vcpu); - /* Is Guest debugging in effect? */ - if (vcpu->guest_debug) { + /* + * Check if we need to use the debug registers. + */ + if (host_using_debug_regs(vcpu)) { /* Save guest debug state */ save_guest_debug_regs(vcpu); @@ -223,6 +235,10 @@ void kvm_arm_setup_debug(struct kvm_vcpu *vcpu) trace_kvm_arm_set_regset("WAPTS", get_num_wrps(), &vcpu->arch.debug_ptr->dbg_wcr[0], &vcpu->arch.debug_ptr->dbg_wvr[0]); + } else if (kvm_vcpu_os_lock_enabled(vcpu)) { + mdscr = vcpu_read_sys_reg(vcpu, MDSCR_EL1); + mdscr &= ~DBG_MDSCR_MDE; + vcpu_write_sys_reg(vcpu, mdscr, MDSCR_EL1); } } @@ -244,7 +260,10 @@ void kvm_arm_clear_debug(struct kvm_vcpu *vcpu) { trace_kvm_arm_clear_debug(vcpu->guest_debug); - if (vcpu->guest_debug) { + /* + * Restore the guest's debug registers if we were using them. + */ + if (host_using_debug_regs(vcpu)) { restore_guest_debug_regs(vcpu); /* diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 5dbdb45d6d44..1346906f5c46 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1453,9 +1453,9 @@ static unsigned int mte_visibility(const struct kvm_vcpu *vcpu, * Debug handling: We do trap most, if not all debug related system * registers. The implementation is good enough to ensure that a guest * can use these with minimal performance degradation. The drawback is - * that we don't implement any of the external debug, none of the - * OSlock protocol. This should be revisited if we ever encounter a - * more demanding guest... + * that we don't implement any of the external debug architecture. + * This should be revisited if we ever encounter a more demanding + * guest... */ static const struct sys_reg_desc sys_reg_descs[] = { { SYS_DESC(SYS_DC_ISW), access_dcsw }, From patchwork Tue Nov 23 21:01:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver Upton X-Patchwork-Id: 12693506 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 140F5C433EF for ; Tue, 23 Nov 2021 21:04:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=9wHmrZpJ+I4Xhwx01vrqOH06TZN1Pfvbg/fg4TnRbhQ=; b=pIaRudVXfKxc/EGdZR4HP+lnYh xL8zqg2mSRrLV9Sg9Qd+aONrnetPrXSCTA0UvLohv3CrbA96cuoWa2YSw4ARmsJUMIA8J711Qgqew sGjDOGR2J4NQumhEsLJuHQoECdPXcpVyIDSNLwUEQrg7ZIOjVhJR9jW/JGvtuVTMpuzwEJe/OBr6+ l6UmrVufuKEf1au8zOMPTftVpQdwK49NYIoDd4m85624g/eCEsv5ybk5Z38eKP9Fx9JnX42kQBHGD 6+nlaJ7xTgQtC/xlZtlRPuzrzSLj5+fTmgHzqDmtk5Y+1hzczpyc8lBkbnGMZh7jvjT91SAx+iesf +AlT2c4A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mpcvv-003Syx-UN; Tue, 23 Nov 2021 21:02:32 +0000 Received: from mail-io1-xd49.google.com ([2607:f8b0:4864:20::d49]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mpcuo-003Skg-7C for linux-arm-kernel@lists.infradead.org; Tue, 23 Nov 2021 21:01:23 +0000 Received: by mail-io1-xd49.google.com with SMTP id d12-20020a0566022d4c00b005ebda1035b1so158796iow.7 for ; Tue, 23 Nov 2021 13:01:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=BwedrBbB5HTyTT2p4mXfIz5QYgjh9yNsR4b4hzDoNcc=; b=Qaaf+qNAHsw9kOiocwlPyQ0uu8vL8UJhBqb8PdL3yfi+rhltZxP2GUdFo8KKxXIF2y 6IZ/uxBz0Ahn+4GR5yWfCfWrL5FHSvGty4CvmlOR4qAkUXmWWSnW2VS4HHgxJF3nAYup 8230IweKBYk0p9mch3LGMraTTxEIO/uKA/L4wA8eXpXuoz23U2AkmV39GFksQQCQ8DhE WnE0rEBRBf4zorX53WPARK1svet5e8XOn3nqGqDjANt/uI7PgRy/KuUil9dGh1ZiLL9D IZnfjhI6ieihzJ92jh8EwquSdmAAvY8mdCwlu/6dhLJundiUSd5Dy3HfdQnBwv7ny618 ZOIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=BwedrBbB5HTyTT2p4mXfIz5QYgjh9yNsR4b4hzDoNcc=; b=uBCbNR+Rtuvcp9wK1IYm6iZhnawikjCKkMnzkw+0C0Mz8hNc1wSCsGx6OZU2bdG/Hf ELseZnSW2nAC4WpcuxOK7XIyVBCNccyp//R4AsWWht3odd6Z74oPJXY6H34px4b+5P1e mPkti/hsPjonpUeOD+UydKO4yg4wBkPeN9403Nu6uTJcv8nFl7r1KiXwdGDU1sCz+sM1 s893S+3x2XH2u7RsztWOApu+T/xNFxliGQQK4WkyqQMbXBvLGnRZ2V3QAL377ZNQUzOE Yk3m2zUXqbgAW73122xTJgDDDxpJiFYIX9Jw2MeaMHCA+IaymxpAHRiKdPYkYFiZjXRj Y6xg== X-Gm-Message-State: AOAM531qi/ph939AB6XB3vn1rE+v953cYk0VPiXkUW8vM697DhSHjN64 pEZeQGQUtuSRm581WkY+4mk4i9fyqUg= X-Google-Smtp-Source: ABdhPJzaYhRodYov80jU9UDbdbd9k79+gVGKWsjAcZxXmdtDiHN7YN7VKm1c4GS5SZfFz37xFHlrrmZumXw= X-Received: from oupton.c.googlers.com ([fda3:e722:ac3:cc00:2b:ff92:c0a8:404]) (user=oupton job=sendgmr) by 2002:a6b:8bc2:: with SMTP id n185mr8931449iod.174.1637701281216; Tue, 23 Nov 2021 13:01:21 -0800 (PST) Date: Tue, 23 Nov 2021 21:01:08 +0000 In-Reply-To: <20211123210109.1605642-1-oupton@google.com> Message-Id: <20211123210109.1605642-6-oupton@google.com> Mime-Version: 1.0 References: <20211123210109.1605642-1-oupton@google.com> X-Mailer: git-send-email 2.34.0.rc2.393.gf8c9666880-goog Subject: [PATCH v3 5/6] selftests: KVM: Add OSLSR_EL1 to the list of blessed regs From: Oliver Upton To: kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, Marc Zyngier , James Morse , Alexandru Elisei , Suzuki K Poulose , linux-arm-kernel@lists.infradead.org, Andrew Jones , Peter Shier , Ricardo Koller , Reiji Watanabe , Oliver Upton X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211123_130122_291713_ACC83770 X-CRM114-Status: UNSURE ( 9.65 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org OSLSR_EL1 is now part of the visible system register state. Add it to the get-reg-list selftest to ensure we keep it that way. Signed-off-by: Oliver Upton --- tools/testing/selftests/kvm/aarch64/get-reg-list.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/testing/selftests/kvm/aarch64/get-reg-list.c b/tools/testing/selftests/kvm/aarch64/get-reg-list.c index cc898181faab..0c7c39a16b3f 100644 --- a/tools/testing/selftests/kvm/aarch64/get-reg-list.c +++ b/tools/testing/selftests/kvm/aarch64/get-reg-list.c @@ -761,6 +761,7 @@ static __u64 base_regs[] = { ARM64_SYS_REG(2, 0, 0, 15, 6), ARM64_SYS_REG(2, 0, 0, 15, 7), ARM64_SYS_REG(2, 4, 0, 7, 0), /* DBGVCR32_EL2 */ + ARM64_SYS_REG(2, 0, 1, 1, 4), /* OSLSR_EL1 */ ARM64_SYS_REG(3, 0, 0, 0, 5), /* MPIDR_EL1 */ ARM64_SYS_REG(3, 0, 0, 1, 0), /* ID_PFR0_EL1 */ ARM64_SYS_REG(3, 0, 0, 1, 1), /* ID_PFR1_EL1 */ From patchwork Tue Nov 23 21:01:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver Upton X-Patchwork-Id: 12693507 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1B198C433EF for ; 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c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=QovEQZReWLCATlIewYReLSWnyKrpm0FAX1JqfLYj0ZU=; b=i0O2Cg0Yr4/3SYlG0hf5iBigGORCFv0Tw/bLobWrDsyuyouw2XRUCTEuoCrRADKMlv Ob8cyACH4Tic0gWR6QUcqWNAK7hAf3Jl0NBZf0w1YpaQU2Wfnk2Ot6qYol9WZy/PsF+3 ZY8rjzX9ke0494ggWpF/2Cq4F4+7YsmjUed2uGykbk3yCSWwYFVtI73rJpLRvz7AkJ6u xzZ5NqS46PZvCsb6GXpmAQUrelfAKpw4iqZUWffPD+jBE53v9Xp8Lhf/2IPuPNYos56E 577j0ifMGm7/YHo4/T0C0b62P1quSNzGGXfCcXj5sNybTP3TGjBDG+n9bUriZ+pCMfxI Du5A== X-Gm-Message-State: AOAM532fCFwDx9URohw1pIDMkFJrHL+3WxxQ/Do4K7rQeO+km57Pn4PM C+U4zyimvKGzRmQ6cnnQXHhUwg2I0nM= X-Google-Smtp-Source: ABdhPJwTgu9XjIzS0u9PqlLGX0GOMfjHnkXYfd2F5tiYZIseel2tjBlN9HerYxahKvrn7lMiFo9d0WYzcmE= X-Received: from oupton.c.googlers.com ([fda3:e722:ac3:cc00:2b:ff92:c0a8:404]) (user=oupton job=sendgmr) by 2002:a02:ba8b:: with SMTP id g11mr9410034jao.128.1637701282229; Tue, 23 Nov 2021 13:01:22 -0800 (PST) Date: Tue, 23 Nov 2021 21:01:09 +0000 In-Reply-To: <20211123210109.1605642-1-oupton@google.com> Message-Id: <20211123210109.1605642-7-oupton@google.com> Mime-Version: 1.0 References: <20211123210109.1605642-1-oupton@google.com> X-Mailer: git-send-email 2.34.0.rc2.393.gf8c9666880-goog Subject: [PATCH v3 6/6] selftests: KVM: Test OS lock behavior From: Oliver Upton To: kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, Marc Zyngier , James Morse , Alexandru Elisei , Suzuki K Poulose , linux-arm-kernel@lists.infradead.org, Andrew Jones , Peter Shier , Ricardo Koller , Reiji Watanabe , Oliver Upton X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211123_130124_043788_4112E294 X-CRM114-Status: GOOD ( 12.00 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org KVM now correctly handles the OS Lock for its guests. When set, KVM blocks all debug exceptions originating from the guest. Add test cases to the debug-exceptions test to assert that software breakpoint, hardware breakpoint, watchpoint, and single-step exceptions are in fact blocked. Signed-off-by: Oliver Upton --- .../selftests/kvm/aarch64/debug-exceptions.c | 58 ++++++++++++++++++- 1 file changed, 56 insertions(+), 2 deletions(-) diff --git a/tools/testing/selftests/kvm/aarch64/debug-exceptions.c b/tools/testing/selftests/kvm/aarch64/debug-exceptions.c index ea189d83abf7..63b2178210c4 100644 --- a/tools/testing/selftests/kvm/aarch64/debug-exceptions.c +++ b/tools/testing/selftests/kvm/aarch64/debug-exceptions.c @@ -23,7 +23,7 @@ #define SPSR_D (1 << 9) #define SPSR_SS (1 << 21) -extern unsigned char sw_bp, hw_bp, bp_svc, bp_brk, hw_wp, ss_start; +extern unsigned char sw_bp, sw_bp2, hw_bp, hw_bp2, bp_svc, bp_brk, hw_wp, ss_start; static volatile uint64_t sw_bp_addr, hw_bp_addr; static volatile uint64_t wp_addr, wp_data_addr; static volatile uint64_t svc_addr; @@ -47,6 +47,14 @@ static void reset_debug_state(void) isb(); } +static void enable_os_lock(void) +{ + write_sysreg(1, oslar_el1); + isb(); + + GUEST_ASSERT(read_sysreg(oslsr_el1) & 2); +} + static void install_wp(uint64_t addr) { uint32_t wcr; @@ -99,6 +107,7 @@ static void guest_code(void) GUEST_SYNC(0); /* Software-breakpoint */ + reset_debug_state(); asm volatile("sw_bp: brk #0"); GUEST_ASSERT_EQ(sw_bp_addr, PC(sw_bp)); @@ -152,6 +161,51 @@ static void guest_code(void) GUEST_ASSERT_EQ(ss_addr[1], PC(ss_start) + 4); GUEST_ASSERT_EQ(ss_addr[2], PC(ss_start) + 8); + GUEST_SYNC(6); + + /* OS Lock does not block software-breakpoint */ + reset_debug_state(); + enable_os_lock(); + sw_bp_addr = 0; + asm volatile("sw_bp2: brk #0"); + GUEST_ASSERT_EQ(sw_bp_addr, PC(sw_bp2)); + + GUEST_SYNC(7); + + /* OS Lock blocking hardware-breakpoint */ + reset_debug_state(); + enable_os_lock(); + install_hw_bp(PC(hw_bp2)); + hw_bp_addr = 0; + asm volatile("hw_bp2: nop"); + GUEST_ASSERT_EQ(hw_bp_addr, 0); + + GUEST_SYNC(8); + + /* OS Lock blocking watchpoint */ + reset_debug_state(); + enable_os_lock(); + write_data = '\0'; + wp_data_addr = 0; + install_wp(PC(write_data)); + write_data = 'x'; + GUEST_ASSERT_EQ(write_data, 'x'); + GUEST_ASSERT_EQ(wp_data_addr, 0); + + GUEST_SYNC(9); + + /* OS Lock blocking single-step */ + reset_debug_state(); + enable_os_lock(); + ss_addr[0] = 0; + install_ss(); + ss_idx = 0; + asm volatile("mrs x0, esr_el1\n\t" + "add x0, x0, #1\n\t" + "msr daifset, #8\n\t" + : : : "x0"); + GUEST_ASSERT_EQ(ss_addr[0], 0); + GUEST_DONE(); } @@ -223,7 +277,7 @@ int main(int argc, char *argv[]) vm_install_sync_handler(vm, VECTOR_SYNC_CURRENT, ESR_EC_SVC64, guest_svc_handler); - for (stage = 0; stage < 7; stage++) { + for (stage = 0; stage < 11; stage++) { vcpu_run(vm, VCPU_ID); switch (get_ucall(vm, VCPU_ID, &uc)) {