From patchwork Tue Dec 14 13:32:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 12696073 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AA236C433EF for ; Tue, 14 Dec 2021 13:34:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=D/76ZnRJUdpNUEZX5Oan3ps/4AREp6c/wMHDmlany1I=; b=GwqbjZ2+lW2Isr bNsoI7OD8zmfDdR+tQ6iDROP05eeAZue/11UDeRGmTCzthy7tePttiTZhuo2f+nc6N2lnPP6vRKvZ vGY+wEkUDPqOOQ+auEG6Onnb2/CcDLxg26YUuOmEo5R3+7Jy6Xrpm53WoNBRZ0FUXqBdQhgG8OTrB ZdVZ7AbP2IL+Lijr7SvI0kTQ+za4YONu/UHmDg5HWwdwK+gtAMGz9EJTRWVHHv7SyrEbUYiiXq8cp I1Pw2MBlZKK2j65rPbBfUDRdETd4IFwcIpQUWc/sxP43y7reFcyDRflY+gW4gCNmyC4p0eJaTeoZW iYzCYAIOd1Ovyi30KvnA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mx7vB-00EAyi-JX; Tue, 14 Dec 2021 13:32:45 +0000 Received: from mga01.intel.com ([192.55.52.88]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mx7v7-00EAy0-KR for linux-arm-kernel@lists.infradead.org; Tue, 14 Dec 2021 13:32:43 +0000 X-IronPort-AV: E=McAfee;i="6200,9189,10197"; a="263116503" X-IronPort-AV: E=Sophos;i="5.88,205,1635231600"; d="scan'208";a="263116503" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Dec 2021 05:32:41 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,205,1635231600"; d="scan'208";a="752980367" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga006.fm.intel.com with ESMTP; 14 Dec 2021 05:32:39 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id 8995B15C; Tue, 14 Dec 2021 15:32:46 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Andrew Lunn , Sebastian Hesselbarth , Gregory Clement , Russell King Subject: [PATCH v1 1/1] ARM: orion/gpio: Get rid of unused first parameter in orion_gpio_init() Date: Tue, 14 Dec 2021 15:32:43 +0200 Message-Id: <20211214133243.53199-1-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.33.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211214_053241_743580_3D32DA06 X-CRM114-Status: GOOD ( 14.80 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The OF node pointer is always NULL, get rid of unused parameter in orion_gpio_init(). As a side effect it will allow to switch GPIO library to the fwnode API, as well as in case of resurrecting it here it should be fwnode_handle anyways. Signed-off-by: Andy Shevchenko --- arch/arm/mach-dove/irq.c | 11 +++-------- arch/arm/mach-mv78xx0/irq.c | 3 +-- arch/arm/mach-orion5x/irq.c | 3 +-- arch/arm/plat-orion/gpio.c | 8 ++------ arch/arm/plat-orion/include/plat/orion-gpio.h | 3 +-- 5 files changed, 8 insertions(+), 20 deletions(-) diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c index 31ccbcee2627..c7ad6e5c37b0 100644 --- a/arch/arm/mach-dove/irq.c +++ b/arch/arm/mach-dove/irq.c @@ -73,12 +73,7 @@ void __init dove_init_irq(void) /* * Initialize gpiolib for GPIOs 0-71. */ - orion_gpio_init(NULL, 0, 32, DOVE_GPIO_LO_VIRT_BASE, 0, - IRQ_DOVE_GPIO_START, gpio0_irqs); - - orion_gpio_init(NULL, 32, 32, DOVE_GPIO_HI_VIRT_BASE, 0, - IRQ_DOVE_GPIO_START + 32, gpio1_irqs); - - orion_gpio_init(NULL, 64, 8, DOVE_GPIO2_VIRT_BASE, 0, - IRQ_DOVE_GPIO_START + 64, gpio2_irqs); + orion_gpio_init(0, 32, DOVE_GPIO_LO_VIRT_BASE, 0, IRQ_DOVE_GPIO_START, gpio0_irqs); + orion_gpio_init(32, 32, DOVE_GPIO_HI_VIRT_BASE, 0, IRQ_DOVE_GPIO_START + 32, gpio1_irqs); + orion_gpio_init(64, 8, DOVE_GPIO2_VIRT_BASE, 0, IRQ_DOVE_GPIO_START + 64, gpio2_irqs); } diff --git a/arch/arm/mach-mv78xx0/irq.c b/arch/arm/mach-mv78xx0/irq.c index 788569e960e1..0b5f055ca1c3 100644 --- a/arch/arm/mach-mv78xx0/irq.c +++ b/arch/arm/mach-mv78xx0/irq.c @@ -67,7 +67,6 @@ void __init mv78xx0_init_irq(void) * registers for core #1 are at an offset of 0x18 from those of * core #0.) */ - orion_gpio_init(NULL, 0, 32, GPIO_VIRT_BASE, - mv78xx0_core_index() ? 0x18 : 0, + orion_gpio_init(0, 32, GPIO_VIRT_BASE, mv78xx0_core_index() ? 0x18 : 0, IRQ_MV78XX0_GPIO_START, gpio0_irqs); } diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c index ac4af2283bef..62d0f4877b2a 100644 --- a/arch/arm/mach-orion5x/irq.c +++ b/arch/arm/mach-orion5x/irq.c @@ -49,6 +49,5 @@ void __init orion5x_init_irq(void) /* * Initialize gpiolib for GPIOs 0-31. */ - orion_gpio_init(NULL, 0, 32, GPIO_VIRT_BASE, 0, - IRQ_ORION5X_GPIO_START, gpio0_irqs); + orion_gpio_init(0, 32, GPIO_VIRT_BASE, 0, IRQ_ORION5X_GPIO_START, gpio0_irqs); } diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c index 734f0be4f14a..3ef9ecdd6343 100644 --- a/arch/arm/plat-orion/gpio.c +++ b/arch/arm/plat-orion/gpio.c @@ -516,8 +516,7 @@ static void orion_gpio_mask_irq(struct irq_data *d) irq_gc_unlock(gc); } -void __init orion_gpio_init(struct device_node *np, - int gpio_base, int ngpio, +void __init orion_gpio_init(int gpio_base, int ngpio, void __iomem *base, int mask_offset, int secondary_irq_base, int irqs[4]) @@ -545,9 +544,6 @@ void __init orion_gpio_init(struct device_node *np, ochip->chip.base = gpio_base; ochip->chip.ngpio = ngpio; ochip->chip.can_sleep = 0; -#ifdef CONFIG_OF - ochip->chip.of_node = np; -#endif ochip->chip.dbg_show = orion_gpio_dbg_show; spin_lock_init(&ochip->lock); @@ -605,7 +601,7 @@ void __init orion_gpio_init(struct device_node *np, IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE); /* Setup irq domain on top of the generic chip. */ - ochip->domain = irq_domain_add_legacy(np, + ochip->domain = irq_domain_add_legacy(NULL, ochip->chip.ngpio, ochip->secondary_irq_base, ochip->secondary_irq_base, diff --git a/arch/arm/plat-orion/include/plat/orion-gpio.h b/arch/arm/plat-orion/include/plat/orion-gpio.h index e856b073a9c8..25a2963e0e0f 100644 --- a/arch/arm/plat-orion/include/plat/orion-gpio.h +++ b/arch/arm/plat-orion/include/plat/orion-gpio.h @@ -30,8 +30,7 @@ int orion_gpio_led_blink_set(struct gpio_desc *desc, int state, void orion_gpio_set_valid(unsigned pin, int mode); /* Initialize gpiolib. */ -void __init orion_gpio_init(struct device_node *np, - int gpio_base, int ngpio, +void __init orion_gpio_init(int gpio_base, int ngpio, void __iomem *base, int mask_offset, int secondary_irq_base, int irq[4]);