From patchwork Tue Dec 14 17:28:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver Upton X-Patchwork-Id: 12696097 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7E0C5C433F5 for ; Tue, 14 Dec 2021 17:29:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=v5l/uIJJZuMy/zvlHpv9UOy0RjGsuY0zqD4UcVjwY0Y=; b=jyfSd3hebAWGs5IAsB4srzkVL0 PTx6y5DolKg+ItUjjcxGv/GjR5iwiZFkhoG2/XaAqc1x3wMQgH+6PTEUKPre1ywCfAmy4uZB7wM2j 8XS+pAWQ5un9Wlai1iG55I15AViYwVThAdL/8DDDxAUn2jJ8ETLAS4PniZLvSNI+C6N3nNfDQQFcf X+c7Fgw4zjDI1/sOLh5VSmWo9oiQG+Wkd456P5529n7MKKRxiCYKqxfBgADLH9e2SjbyNUYDOEywc dsxze2Hdlso4mHXVd1PS+F7hAqPapZmShRAULSfMii/D/nfdcfiltHrcopgPSnki1u13XZbaJuqY+ IBY/SsQA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mxBbO-00F6b6-N9; Tue, 14 Dec 2021 17:28:34 +0000 Received: from mail-il1-x149.google.com ([2607:f8b0:4864:20::149]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mxBbA-00F6UZ-2O for linux-arm-kernel@lists.infradead.org; Tue, 14 Dec 2021 17:28:21 +0000 Received: by mail-il1-x149.google.com with SMTP id g14-20020a92c7ce000000b002b1e78da1f9so594125ilk.21 for ; Tue, 14 Dec 2021 09:28:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=EylPoIwJHu5cp6KovczhslrKEkEYeADu9LS/s52w9YE=; b=WptfY3NUSXg/+ge/bSycAdDXNGBatjC9Ty3fRvRO/naZtajLtOnCel1J92sJl+ffyB gn+26lozgkVnDFQXpBa6gsCcYi+iyY4OuU7RAGOitBJmuO5NpueNu8HQNe2wJsQlV6mb s7HQwUbg5T382xCMHMjdkKxRgEijgNNkXxlDoC+ukK9aQYxusDSDlIbvu7hlEhqY3DzV PXKES3uS5RaC0dZXWqfEbw+aUVIHfHv1KsCCPV6Bv9GfSPLPIO74l8okr9dVLvECSxr6 aLA1+JI2wnVQl0R+IFRqmZ5wRbK2MPHwT1vTHXV+IlorXhALZmCfzJ++Gt7rw6BYo9I0 i7tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=EylPoIwJHu5cp6KovczhslrKEkEYeADu9LS/s52w9YE=; b=acGWxDpv3OXPdqhlvkc2WbsCyBm2tdzIBEQ6XpcypNngsxjwPtZZqgEHFtNpILrTwc ZQamLvFUzyYduXbG+YLt8wn0WKayr6CS3dctwBJSBm7A9r1FfVqU8eqSsXtQ1MCOwcEP gEnmtIf+Pxp04MM/vGben0sYD7xTbkBVTIFa/TVuxEmmofP0Rzw6lVCPrVOa61WsvL7Q OZNyJL8mPWrESH+pAeRjNY6/BDBfZ++060J7kTkN+pnQb1R/LWPo+fxgiKBG4oaaGBCw 7YR0vLj3uGh2Wi5ZxLYAFTGa4OnnuabyIk80y0qnocZHWSjRphQksyrtC6+tjMUNBS6V kEGw== X-Gm-Message-State: AOAM532vmOWHUIMK/z41g3ciHB/MpMFgR9FZU4n6zIdBc+aZAaDqBVpl LH2STtBSd3g7WCmum7wkxECGmBnOA3g= X-Google-Smtp-Source: ABdhPJxlHuYVYQeqSWOyzJfDt70mmril4aeZVLx8iWFQhBCjg4s0ijgzuxjSVPZcN3dObuSd5rcGMlUpWSY= X-Received: from oupton.c.googlers.com ([fda3:e722:ac3:cc00:2b:ff92:c0a8:404]) (user=oupton job=sendgmr) by 2002:a05:6602:2d84:: with SMTP id k4mr4567077iow.168.1639502898040; Tue, 14 Dec 2021 09:28:18 -0800 (PST) Date: Tue, 14 Dec 2021 17:28:07 +0000 In-Reply-To: <20211214172812.2894560-1-oupton@google.com> Message-Id: <20211214172812.2894560-2-oupton@google.com> Mime-Version: 1.0 References: <20211214172812.2894560-1-oupton@google.com> X-Mailer: git-send-email 2.34.1.173.g76aa8bc2d0-goog Subject: [PATCH v4 1/6] KVM: arm64: Correctly treat writes to OSLSR_EL1 as undefined From: Oliver Upton To: kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, Marc Zyngier , James Morse , Alexandru Elisei , Suzuki K Poulose , linux-arm-kernel@lists.infradead.org, Andrew Jones , Peter Shier , Ricardo Koller , Reiji Watanabe , Oliver Upton X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211214_092820_137213_98BAE5ED X-CRM114-Status: GOOD ( 11.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Any valid implementation of the architecture should generate an undefined exception for writes to a read-only register, such as OSLSR_EL1. Nonetheless, the KVM handler actually implements write-ignore behavior. Align the trap handler for OSLSR_EL1 with hardware behavior. If such a write ever traps to EL2, inject an undef into the guest and print a warning. Reviewed-by: Reiji Watanabe Signed-off-by: Oliver Upton Reviewed-by: Mark Rutland --- arch/arm64/kvm/sys_regs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index e3ec1a44f94d..11b4212c2036 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -292,7 +292,7 @@ static bool trap_oslsr_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) { if (p->is_write) { - return ignore_write(vcpu, p); + return write_to_read_only(vcpu, p, r); } else { p->regval = (1 << 3); return true; From patchwork Tue Dec 14 17:28:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver Upton X-Patchwork-Id: 12696098 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5BF48C433F5 for ; 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Tue, 14 Dec 2021 17:28:46 +0000 Received: from mail-il1-x14a.google.com ([2607:f8b0:4864:20::14a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mxBbB-00F6Uv-3c for linux-arm-kernel@lists.infradead.org; Tue, 14 Dec 2021 17:28:22 +0000 Received: by mail-il1-x14a.google.com with SMTP id u8-20020a056e021a4800b002a1ec0f08afso18356112ilv.7 for ; Tue, 14 Dec 2021 09:28:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=dkE80KJZU2BKakse2hQ7jV87ahQ5YomadoMUm+qJz2M=; b=TOAhrySHSGJuV+NGGLD4vDz6yAho4RCIclHYD49tWwn5F2L4+vnHDhRvePecRxm+BE soyKilcS3/H742ylFOr0Lt/Ip1YdlLudQRguDLHR2utNKT0tkobG3pV9QpdLmk9YLR2m xt2MpJeDyyoxICHRQBjAurQ2Be/tQAniONeA6mwSpykAdKOK5U+B6t+RUolDLvbTFyEJ YcgbfutesxYsPYSGrQTZM/Z8ixvO4A1Xia9MpchQkmxbMvwKmftpg69WzwD4KtQGM0kX venbV1JsmylOzQoiBNtufwRRrGTahtV44gKDeOumxuL1OnKu8Ao2ZrcfW1zZlPvY1Asl hrrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=dkE80KJZU2BKakse2hQ7jV87ahQ5YomadoMUm+qJz2M=; b=0xu0h9ELpmt9RBMDho1Zt4Lb6xnCxxmeVpZZgCLZ+Qh8iBtN1TYQOEgI5Z8RfH30le LocWpV9PHs4Pf239TYWSvwInu/crAIT2zC2osMFzhr2YfqWeomYeR4v/4Rh1V2shWhmC a4DjQW5eQXiinVSAMtzjlJa21oNiOU1qjou90zDLajELdcCZjWaP0LA3RlglEj5pvMWW Q4mb/2rw0reIpZmOJY6OafXqXG9H50zAGaCTWdjtDnijiwlVFQyCiMrtRhRMUIwlcZ6g XgEDR1Q3kff+isVq0jB+qu2xQGL005qr1ClYyR1C+wEuxotkRJv0sG49o9SLNS0/pmpr 4bXg== X-Gm-Message-State: AOAM531k0SIimnSpHCi/jJ3Kx8jRWZbvcGCMwAmlBnOtZIt6P2Gx3lLD 3EccOErGYzv5KT5AieGCri70qOEDYFg= X-Google-Smtp-Source: ABdhPJwlx+badFHXeudBOY0/DTEsOaO58kXH+u/oQcvLDqtXYpjKkq51uR0VlpbCCin+GDh54GlcWnJ4Q1k= X-Received: from oupton.c.googlers.com ([fda3:e722:ac3:cc00:2b:ff92:c0a8:404]) (user=oupton job=sendgmr) by 2002:a05:6602:1484:: with SMTP id a4mr4544883iow.35.1639502899090; Tue, 14 Dec 2021 09:28:19 -0800 (PST) Date: Tue, 14 Dec 2021 17:28:08 +0000 In-Reply-To: <20211214172812.2894560-1-oupton@google.com> Message-Id: <20211214172812.2894560-3-oupton@google.com> Mime-Version: 1.0 References: <20211214172812.2894560-1-oupton@google.com> X-Mailer: git-send-email 2.34.1.173.g76aa8bc2d0-goog Subject: [PATCH v4 2/6] KVM: arm64: Stash OSLSR_EL1 in the cpu context From: Oliver Upton To: kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, Marc Zyngier , James Morse , Alexandru Elisei , Suzuki K Poulose , linux-arm-kernel@lists.infradead.org, Andrew Jones , Peter Shier , Ricardo Koller , Reiji Watanabe , Oliver Upton X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211214_092821_174321_0F41CC8B X-CRM114-Status: GOOD ( 14.25 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org An upcoming change to KVM will context switch the OS Lock status between guest/host. Add OSLSR_EL1 to the cpu context and handle guest reads using the stored value. Wire up a custom handler for writes from userspace and prevent any of the invariant bits from changing. Reviewed-by: Reiji Watanabe Signed-off-by: Oliver Upton --- arch/arm64/include/asm/kvm_host.h | 2 ++ arch/arm64/kvm/sys_regs.c | 31 ++++++++++++++++++++++++------- 2 files changed, 26 insertions(+), 7 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 2a5f7f38006f..53fc8a6eaf1c 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -172,8 +172,10 @@ enum vcpu_sysreg { PAR_EL1, /* Physical Address Register */ MDSCR_EL1, /* Monitor Debug System Control Register */ MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */ + OSLSR_EL1, /* OS Lock Status Register */ DISR_EL1, /* Deferred Interrupt Status Register */ + /* Performance Monitors Registers */ PMCR_EL0, /* Control Register */ PMSELR_EL0, /* Event Counter Selection Register */ diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 11b4212c2036..7bf350b3d9cd 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -291,12 +291,28 @@ static bool trap_oslsr_el1(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) { - if (p->is_write) { + if (p->is_write) return write_to_read_only(vcpu, p, r); - } else { - p->regval = (1 << 3); - return true; - } + + p->regval = __vcpu_sys_reg(vcpu, r->reg); + return true; +} + +static int set_oslsr_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, + const struct kvm_one_reg *reg, void __user *uaddr) +{ + u64 id = sys_reg_to_index(rd); + u64 val; + int err; + + err = reg_from_user(&val, uaddr, id); + if (err) + return err; + + if (val != rd->val) + return -EINVAL; + + return 0; } static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu, @@ -1448,7 +1464,8 @@ static const struct sys_reg_desc sys_reg_descs[] = { { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi }, { SYS_DESC(SYS_OSLAR_EL1), trap_raz_wi }, - { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1 }, + { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_val, OSLSR_EL1, 0x00000008, + .set_user = set_oslsr_el1, }, { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi }, { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi }, { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi }, @@ -1923,7 +1940,7 @@ static const struct sys_reg_desc cp14_regs[] = { { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi }, DBGBXVR(1), /* DBGOSLSR */ - { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1 }, + { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1, NULL, OSLSR_EL1 }, DBGBXVR(2), DBGBXVR(3), /* DBGOSDLR */ From patchwork Tue Dec 14 17:28:09 2021 Content-Type: text/plain; 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Tue, 14 Dec 2021 09:28:20 -0800 (PST) Date: Tue, 14 Dec 2021 17:28:09 +0000 In-Reply-To: <20211214172812.2894560-1-oupton@google.com> Message-Id: <20211214172812.2894560-4-oupton@google.com> Mime-Version: 1.0 References: <20211214172812.2894560-1-oupton@google.com> X-Mailer: git-send-email 2.34.1.173.g76aa8bc2d0-goog Subject: [PATCH v4 3/6] KVM: arm64: Allow guest to set the OSLK bit From: Oliver Upton To: kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, Marc Zyngier , James Morse , Alexandru Elisei , Suzuki K Poulose , linux-arm-kernel@lists.infradead.org, Andrew Jones , Peter Shier , Ricardo Koller , Reiji Watanabe , Oliver Upton X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211214_092822_464595_3EE7B7A0 X-CRM114-Status: GOOD ( 17.33 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Allow writes to OSLAR and forward the OSLK bit to OSLSR. Do nothing with the value for now. Reviewed-by: Reiji Watanabe Signed-off-by: Oliver Upton --- arch/arm64/include/asm/sysreg.h | 9 ++++++++ arch/arm64/kvm/sys_regs.c | 39 ++++++++++++++++++++++++++------- 2 files changed, 40 insertions(+), 8 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 16b3f1a1d468..46f800bda045 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -129,7 +129,16 @@ #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7) #define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0) #define SYS_OSLAR_EL1 sys_reg(2, 0, 1, 0, 4) + +#define SYS_OSLAR_OSLK BIT(0) + #define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4) + +#define SYS_OSLSR_OSLK BIT(1) + +#define SYS_OSLSR_OSLM_MASK (BIT(3) | BIT(0)) +#define SYS_OSLSR_OSLM BIT(3) + #define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4) #define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4) #define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 7bf350b3d9cd..5188a74095e3 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -44,6 +44,10 @@ * 64bit interface. */ +static int reg_from_user(u64 *val, const void __user *uaddr, u64 id); +static int reg_to_user(void __user *uaddr, const u64 *val, u64 id); +static u64 sys_reg_to_index(const struct sys_reg_desc *reg); + static bool read_from_write_only(struct kvm_vcpu *vcpu, struct sys_reg_params *params, const struct sys_reg_desc *r) @@ -287,6 +291,24 @@ static bool trap_loregion(struct kvm_vcpu *vcpu, return trap_raz_wi(vcpu, p, r); } +static bool trap_oslar_el1(struct kvm_vcpu *vcpu, + struct sys_reg_params *p, + const struct sys_reg_desc *r) +{ + u64 oslsr; + + if (!p->is_write) + return read_from_write_only(vcpu, p, r); + + /* Forward the OSLK bit to OSLSR */ + oslsr = __vcpu_sys_reg(vcpu, OSLSR_EL1) & ~SYS_OSLSR_OSLK; + if (p->regval & SYS_OSLAR_OSLK) + oslsr |= SYS_OSLSR_OSLK; + + __vcpu_sys_reg(vcpu, OSLSR_EL1) = oslsr; + return true; +} + static bool trap_oslsr_el1(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) @@ -309,9 +331,14 @@ static int set_oslsr_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, if (err) return err; - if (val != rd->val) + /* + * The only modifiable bit is the OSLK bit. Refuse the write if + * userspace attempts to change any other bit in the register. + */ + if ((val & ~SYS_OSLSR_OSLK) != SYS_OSLSR_OSLM) return -EINVAL; + __vcpu_sys_reg(vcpu, rd->reg) = val; return 0; } @@ -1180,10 +1207,6 @@ static bool access_raz_id_reg(struct kvm_vcpu *vcpu, return __access_id_reg(vcpu, p, r, true); } -static int reg_from_user(u64 *val, const void __user *uaddr, u64 id); -static int reg_to_user(void __user *uaddr, const u64 *val, u64 id); -static u64 sys_reg_to_index(const struct sys_reg_desc *reg); - /* Visibility overrides for SVE-specific control registers */ static unsigned int sve_visibility(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd) @@ -1463,8 +1486,8 @@ static const struct sys_reg_desc sys_reg_descs[] = { DBG_BCR_BVR_WCR_WVR_EL1(15), { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi }, - { SYS_DESC(SYS_OSLAR_EL1), trap_raz_wi }, - { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_val, OSLSR_EL1, 0x00000008, + { SYS_DESC(SYS_OSLAR_EL1), trap_oslar_el1 }, + { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_val, OSLSR_EL1, SYS_OSLSR_OSLM, .set_user = set_oslsr_el1, }, { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi }, { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi }, @@ -1937,7 +1960,7 @@ static const struct sys_reg_desc cp14_regs[] = { DBGBXVR(0), /* DBGOSLAR */ - { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi }, + { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_oslar_el1 }, DBGBXVR(1), /* DBGOSLSR */ { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1, NULL, OSLSR_EL1 }, From patchwork Tue Dec 14 17:28:10 2021 Content-Type: text/plain; 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Tue, 14 Dec 2021 09:28:20 -0800 (PST) Date: Tue, 14 Dec 2021 17:28:10 +0000 In-Reply-To: <20211214172812.2894560-1-oupton@google.com> Message-Id: <20211214172812.2894560-5-oupton@google.com> Mime-Version: 1.0 References: <20211214172812.2894560-1-oupton@google.com> X-Mailer: git-send-email 2.34.1.173.g76aa8bc2d0-goog Subject: [PATCH v4 4/6] KVM: arm64: Emulate the OS Lock From: Oliver Upton To: kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, Marc Zyngier , James Morse , Alexandru Elisei , Suzuki K Poulose , linux-arm-kernel@lists.infradead.org, Andrew Jones , Peter Shier , Ricardo Koller , Reiji Watanabe , Oliver Upton X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211214_092822_314706_C57C222A X-CRM114-Status: GOOD ( 19.85 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The OS lock blocks all debug exceptions at every EL. To date, KVM has not implemented the OS lock for its guests, despite the fact that it is mandatory per the architecture. Simple context switching between the guest and host is not appropriate, as its effects are not constrained to the guest context. Emulate the OS Lock by clearing MDE and SS in MDSCR_EL1, thereby blocking all but software breakpoint instructions. Signed-off-by: Oliver Upton --- arch/arm64/include/asm/kvm_host.h | 4 ++++ arch/arm64/kvm/debug.c | 26 ++++++++++++++++++++++---- arch/arm64/kvm/sys_regs.c | 6 +++--- 3 files changed, 29 insertions(+), 7 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 53fc8a6eaf1c..e5a06ff1cba6 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -726,6 +726,10 @@ void kvm_arm_vcpu_init_debug(struct kvm_vcpu *vcpu); void kvm_arm_setup_debug(struct kvm_vcpu *vcpu); void kvm_arm_clear_debug(struct kvm_vcpu *vcpu); void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu); + +#define kvm_vcpu_os_lock_enabled(vcpu) \ + (!!(__vcpu_sys_reg(vcpu, OSLSR_EL1) & SYS_OSLSR_OSLK)) + int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr); int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu, diff --git a/arch/arm64/kvm/debug.c b/arch/arm64/kvm/debug.c index db9361338b2a..4fd5c216c4bb 100644 --- a/arch/arm64/kvm/debug.c +++ b/arch/arm64/kvm/debug.c @@ -105,9 +105,11 @@ static void kvm_arm_setup_mdcr_el2(struct kvm_vcpu *vcpu) * - Userspace is using the hardware to debug the guest * (KVM_GUESTDBG_USE_HW is set). * - The guest is not using debug (KVM_ARM64_DEBUG_DIRTY is clear). + * - The guest has enabled the OS Lock (debug exceptions are blocked). */ if ((vcpu->guest_debug & KVM_GUESTDBG_USE_HW) || - !(vcpu->arch.flags & KVM_ARM64_DEBUG_DIRTY)) + !(vcpu->arch.flags & KVM_ARM64_DEBUG_DIRTY) || + kvm_vcpu_os_lock_enabled(vcpu)) vcpu->arch.mdcr_el2 |= MDCR_EL2_TDA; trace_kvm_arm_set_dreg32("MDCR_EL2", vcpu->arch.mdcr_el2); @@ -160,8 +162,8 @@ void kvm_arm_setup_debug(struct kvm_vcpu *vcpu) kvm_arm_setup_mdcr_el2(vcpu); - /* Is Guest debugging in effect? */ - if (vcpu->guest_debug) { + /* Check if we need to use the debug registers. */ + if (vcpu->guest_debug || kvm_vcpu_os_lock_enabled(vcpu)) { /* Save guest debug state */ save_guest_debug_regs(vcpu); @@ -223,6 +225,19 @@ void kvm_arm_setup_debug(struct kvm_vcpu *vcpu) trace_kvm_arm_set_regset("WAPTS", get_num_wrps(), &vcpu->arch.debug_ptr->dbg_wcr[0], &vcpu->arch.debug_ptr->dbg_wvr[0]); + + /* + * The OS Lock blocks debug exceptions in all ELs when it is + * enabled. If the guest has enabled the OS Lock, constrain its + * effects to the guest. Emulate the behavior by clearing + * MDSCR_EL1.MDE. In so doing, we ensure that host debug + * exceptions are unaffected by guest configuration of the OS + * Lock. + */ + } else if (kvm_vcpu_os_lock_enabled(vcpu)) { + mdscr = vcpu_read_sys_reg(vcpu, MDSCR_EL1); + mdscr &= ~DBG_MDSCR_MDE; + vcpu_write_sys_reg(vcpu, mdscr, MDSCR_EL1); } } @@ -244,7 +259,10 @@ void kvm_arm_clear_debug(struct kvm_vcpu *vcpu) { trace_kvm_arm_clear_debug(vcpu->guest_debug); - if (vcpu->guest_debug) { + /* + * Restore the guest's debug registers if we were using them. + */ + if (vcpu->guest_debug || kvm_vcpu_os_lock_enabled(vcpu)) { restore_guest_debug_regs(vcpu); /* diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 5188a74095e3..50a6966aab1b 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1457,9 +1457,9 @@ static unsigned int mte_visibility(const struct kvm_vcpu *vcpu, * Debug handling: We do trap most, if not all debug related system * registers. The implementation is good enough to ensure that a guest * can use these with minimal performance degradation. The drawback is - * that we don't implement any of the external debug, none of the - * OSlock protocol. This should be revisited if we ever encounter a - * more demanding guest... + * that we don't implement any of the external debug architecture. + * This should be revisited if we ever encounter a more demanding + * guest... */ static const struct sys_reg_desc sys_reg_descs[] = { { SYS_DESC(SYS_DC_ISW), access_dcsw }, From patchwork Tue Dec 14 17:28:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver Upton X-Patchwork-Id: 12696101 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CBC12C433F5 for ; Tue, 14 Dec 2021 17:30:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=fi8cc7/Q37S6y5Kge7jI1aX7yFThK2ZX7zDbq/Jznko=; b=ZO2nj6wDqraI7a+lxnbGlGjyoZ YX3t91+7jcgCevih2ra8SLiFnEaXwZWHeFQk1lVTe8TAhy55QGV7CrdOGM12aEbfAcNJlPdKI9EKj 5/wGINkP2jvBzBelvqfpIg4GLNHvWf9grAaQTqZKtlayoC98BL6ihFafhWEj4rindPZb+muRnCYbq lc3oWkf49atM11BGRiFYlf65Jslqqx1AyZYpQYwu1aQ0mOnJlTNSdUS4mXH5U0LQIIb6Gm8qLsEwg z2gmh2WFTLY/U2mtzetGJzKhkCnxiq1MtRGbsr7CzUBenr4QZa2tOob6y3D1az1GwajQHa3k8P/0K XETWxI4g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mxBcD-00F6rQ-Rr; Tue, 14 Dec 2021 17:29:26 +0000 Received: from mail-il1-x149.google.com ([2607:f8b0:4864:20::149]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mxBbD-00F6Vw-I4 for linux-arm-kernel@lists.infradead.org; Tue, 14 Dec 2021 17:28:25 +0000 Received: by mail-il1-x149.google.com with SMTP id t5-20020a056e02160500b002aee18dcf60so4121204ilu.11 for ; Tue, 14 Dec 2021 09:28:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=1Jwvt2jUDR/UART7D/evy6xX8nTOg9MzOLHWtI9aqPs=; b=SzpEesm+Mh2jg4QGy8qBWU5SuQUrhFLEHQSQshWM9fM4hoZ9A7wBdjrOY5vU7OIJ2h G3Ye+hM9b1QwZJvy9WGZyTpicP54IeYAVoMLcvcY2NYRkOVUvIILLL7dsfh0DbRNj/Wk LNfobwMekfHZuTNXHlaMmu+WlD2KONk+nM3s8drKYTagGFa/Mnpx1MhsVA9gyz2DxpsB A10VPKejwxiLgNvOm0pvoxY+xDNSPbwsxeDlIQYKhTl52zX5PoJsoIUx+od9VJELicAp IZYShzHylChaqzxJhRTArPhpSQxSRA6cbYBn7l+GjtDdkfZtQKph6JvnXFjoDiScnQpx 2csg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=1Jwvt2jUDR/UART7D/evy6xX8nTOg9MzOLHWtI9aqPs=; b=o6ZFqlC66W93Qjqvb3v/bQVcYTlj0ItQ7a7MtM3BvAbCN+5DBA97RH+PDvhSEcPlg7 ryPCsjqyC6b7xNImUBfgwIgWSgc8E1TnGv5idlgcmK3h6Tk13D6rlcW7/oYJwukJptYI GzfFTzkeDuO3JnmFC3JKCSSpklD6VRNEF4EihYNA8UPdnVXi+TAFKIdN34KOPOUYdBPB +qSCKRDp48Ndru4tePNAit6bLJWNZvNiDQ56bXHg8UJnepymtJl2l2/Koj9gQdZ7fa6B zqsC5KM6EfudiuvT2gw2r9n7qIiieFpHH/HNHR9rLqe7HKuTIlyKUtALEW63Q7j+qiMS /OQw== X-Gm-Message-State: AOAM530LF6d9cjpx5R2RTyt6Thh4eWfxcXIwxbLJVXTqVjzmoiByn+Bo hqIe3xM91UIbfqwi0d3cHXJ1dX04hSE= X-Google-Smtp-Source: ABdhPJy18yNyWrBFa7EmeTStINtjn7maODxM/UjDHu9TWrMLPrCpYH3fBbsImp3Jixp6csA+szHEYxhmlG0= X-Received: from oupton.c.googlers.com ([fda3:e722:ac3:cc00:2b:ff92:c0a8:404]) (user=oupton job=sendgmr) by 2002:a05:6602:1604:: with SMTP id x4mr4626833iow.84.1639502901988; Tue, 14 Dec 2021 09:28:21 -0800 (PST) Date: Tue, 14 Dec 2021 17:28:11 +0000 In-Reply-To: <20211214172812.2894560-1-oupton@google.com> Message-Id: <20211214172812.2894560-6-oupton@google.com> Mime-Version: 1.0 References: <20211214172812.2894560-1-oupton@google.com> X-Mailer: git-send-email 2.34.1.173.g76aa8bc2d0-goog Subject: [PATCH v4 5/6] selftests: KVM: Add OSLSR_EL1 to the list of blessed regs From: Oliver Upton To: kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, Marc Zyngier , James Morse , Alexandru Elisei , Suzuki K Poulose , linux-arm-kernel@lists.infradead.org, Andrew Jones , Peter Shier , Ricardo Koller , Reiji Watanabe , Oliver Upton X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211214_092823_631879_E690D053 X-CRM114-Status: UNSURE ( 9.27 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org OSLSR_EL1 is now part of the visible system register state. Add it to the get-reg-list selftest to ensure we keep it that way. Signed-off-by: Oliver Upton --- tools/testing/selftests/kvm/aarch64/get-reg-list.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/testing/selftests/kvm/aarch64/get-reg-list.c b/tools/testing/selftests/kvm/aarch64/get-reg-list.c index cc898181faab..0c7c39a16b3f 100644 --- a/tools/testing/selftests/kvm/aarch64/get-reg-list.c +++ b/tools/testing/selftests/kvm/aarch64/get-reg-list.c @@ -761,6 +761,7 @@ static __u64 base_regs[] = { ARM64_SYS_REG(2, 0, 0, 15, 6), ARM64_SYS_REG(2, 0, 0, 15, 7), ARM64_SYS_REG(2, 4, 0, 7, 0), /* DBGVCR32_EL2 */ + ARM64_SYS_REG(2, 0, 1, 1, 4), /* OSLSR_EL1 */ ARM64_SYS_REG(3, 0, 0, 0, 5), /* MPIDR_EL1 */ ARM64_SYS_REG(3, 0, 0, 1, 0), /* ID_PFR0_EL1 */ ARM64_SYS_REG(3, 0, 0, 1, 1), /* ID_PFR1_EL1 */ From patchwork Tue Dec 14 17:28:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver Upton X-Patchwork-Id: 12696102 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F086DC433F5 for ; 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When set, KVM blocks all debug exceptions originating from the guest. Add test cases to the debug-exceptions test to assert that software breakpoint, hardware breakpoint, watchpoint, and single-step exceptions are in fact blocked. Signed-off-by: Oliver Upton --- .../selftests/kvm/aarch64/debug-exceptions.c | 58 ++++++++++++++++++- 1 file changed, 56 insertions(+), 2 deletions(-) diff --git a/tools/testing/selftests/kvm/aarch64/debug-exceptions.c b/tools/testing/selftests/kvm/aarch64/debug-exceptions.c index ea189d83abf7..63b2178210c4 100644 --- a/tools/testing/selftests/kvm/aarch64/debug-exceptions.c +++ b/tools/testing/selftests/kvm/aarch64/debug-exceptions.c @@ -23,7 +23,7 @@ #define SPSR_D (1 << 9) #define SPSR_SS (1 << 21) -extern unsigned char sw_bp, hw_bp, bp_svc, bp_brk, hw_wp, ss_start; +extern unsigned char sw_bp, sw_bp2, hw_bp, hw_bp2, bp_svc, bp_brk, hw_wp, ss_start; static volatile uint64_t sw_bp_addr, hw_bp_addr; static volatile uint64_t wp_addr, wp_data_addr; static volatile uint64_t svc_addr; @@ -47,6 +47,14 @@ static void reset_debug_state(void) isb(); } +static void enable_os_lock(void) +{ + write_sysreg(1, oslar_el1); + isb(); + + GUEST_ASSERT(read_sysreg(oslsr_el1) & 2); +} + static void install_wp(uint64_t addr) { uint32_t wcr; @@ -99,6 +107,7 @@ static void guest_code(void) GUEST_SYNC(0); /* Software-breakpoint */ + reset_debug_state(); asm volatile("sw_bp: brk #0"); GUEST_ASSERT_EQ(sw_bp_addr, PC(sw_bp)); @@ -152,6 +161,51 @@ static void guest_code(void) GUEST_ASSERT_EQ(ss_addr[1], PC(ss_start) + 4); GUEST_ASSERT_EQ(ss_addr[2], PC(ss_start) + 8); + GUEST_SYNC(6); + + /* OS Lock does not block software-breakpoint */ + reset_debug_state(); + enable_os_lock(); + sw_bp_addr = 0; + asm volatile("sw_bp2: brk #0"); + GUEST_ASSERT_EQ(sw_bp_addr, PC(sw_bp2)); + + GUEST_SYNC(7); + + /* OS Lock blocking hardware-breakpoint */ + reset_debug_state(); + enable_os_lock(); + install_hw_bp(PC(hw_bp2)); + hw_bp_addr = 0; + asm volatile("hw_bp2: nop"); + GUEST_ASSERT_EQ(hw_bp_addr, 0); + + GUEST_SYNC(8); + + /* OS Lock blocking watchpoint */ + reset_debug_state(); + enable_os_lock(); + write_data = '\0'; + wp_data_addr = 0; + install_wp(PC(write_data)); + write_data = 'x'; + GUEST_ASSERT_EQ(write_data, 'x'); + GUEST_ASSERT_EQ(wp_data_addr, 0); + + GUEST_SYNC(9); + + /* OS Lock blocking single-step */ + reset_debug_state(); + enable_os_lock(); + ss_addr[0] = 0; + install_ss(); + ss_idx = 0; + asm volatile("mrs x0, esr_el1\n\t" + "add x0, x0, #1\n\t" + "msr daifset, #8\n\t" + : : : "x0"); + GUEST_ASSERT_EQ(ss_addr[0], 0); + GUEST_DONE(); } @@ -223,7 +277,7 @@ int main(int argc, char *argv[]) vm_install_sync_handler(vm, VECTOR_SYNC_CURRENT, ESR_EC_SVC64, guest_svc_handler); - for (stage = 0; stage < 7; stage++) { + for (stage = 0; stage < 11; stage++) { vcpu_run(vm, VCPU_ID); switch (get_ucall(vm, VCPU_ID, &uc)) {