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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; Received: from SATLEXMB03.amd.com (165.204.84.17) by BN8NAM11FT039.mail.protection.outlook.com (10.13.177.169) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4823.18 via Frontend Transport; Tue, 28 Dec 2021 20:06:31 +0000 Received: from yaz-ethanolx.amd.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 28 Dec 2021 14:06:31 -0600 From: Yazen Ghannam To: CC: , , , , , , , , "Yazen Ghannam" Subject: [PATCH v3 1/2] EDAC/amd64: Set memory type per DIMM Date: Tue, 28 Dec 2021 20:06:14 +0000 Message-ID: <20211228200615.412999-2-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211228200615.412999-1-yazen.ghannam@amd.com> References: <20211228200615.412999-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB03.amd.com (10.181.40.144) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 360f4765-3d77-4431-2314-08d9ca3d8ac0 X-MS-TrafficTypeDiagnostic: MW3PR12MB4412:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:576; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Dec 2021 20:06:31.8830 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 360f4765-3d77-4431-2314-08d9ca3d8ac0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT039.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4412 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Current AMD systems allow mixing of DIMM types within a system. However, DIMMs within a channel, i.e. managed by a single Unified Memory Controller (UMC), must be of the same type. Handle this possible configuration by checking and setting the memory type for each individual EDAC "DIMM" structure. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20211215155309.2711917-2-yazen.ghannam@amd.com v2->v3: * Change patch to properly handle systems with different DIMM types. v1->v2: * Was patch 3 in v1. * Update commit message. drivers/edac/amd64_edac.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index fba609ada0e6..4db92c77276f 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1616,19 +1616,23 @@ static void read_dct_base_mask(struct amd64_pvt *pvt) } } +static enum mem_type determine_memory_type_df(struct amd64_umc *umc) +{ + if (umc->dimm_cfg & BIT(5)) + return MEM_LRDDR4; + + if (umc->dimm_cfg & BIT(4)) + return MEM_RDDR4; + + return MEM_DDR4; +} + static void determine_memory_type(struct amd64_pvt *pvt) { u32 dram_ctrl, dcsm; - if (pvt->umc) { - if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(5)) - pvt->dram_type = MEM_LRDDR4; - else if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(4)) - pvt->dram_type = MEM_RDDR4; - else - pvt->dram_type = MEM_DDR4; + if (pvt->umc) return; - } switch (pvt->fam) { case 0xf: @@ -3547,8 +3551,8 @@ static int init_csrows_df(struct mem_ctl_info *mci) edac_dbg(1, "MC node: %d, csrow: %d\n", pvt->mc_node_id, cs); + dimm->mtype = determine_memory_type_df(&pvt->umc[umc]); dimm->nr_pages = get_csrow_nr_pages(pvt, umc, cs); - dimm->mtype = pvt->dram_type; dimm->edac_mode = edac_mode; dimm->dtype = dev_type; dimm->grain = 64; From patchwork Tue Dec 28 20:06:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12700587 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53827C433FE for ; Tue, 28 Dec 2021 20:06:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237248AbhL1UGh (ORCPT ); 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Tue, 28 Dec 2021 14:06:32 -0600 From: Yazen Ghannam To: CC: , , , , , , , , "Yazen Ghannam" Subject: [PATCH v3 2/2] EDAC/amd64: Add new register offset support and related changes Date: Tue, 28 Dec 2021 20:06:15 +0000 Message-ID: <20211228200615.412999-3-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211228200615.412999-1-yazen.ghannam@amd.com> References: <20211228200615.412999-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB03.amd.com (10.181.40.144) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 3c81223c-aa00-4882-1583-08d9ca3d8b99 X-MS-TrafficTypeDiagnostic: CY4PR1201MB0184:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7219; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: xdNGZosRns15Eay1JZ29UwCDsyhO/+NDt160mlYiUaggOQJkaPhhMqSCAIZQbKVEn/HHUWdHBLo1GlOcOZ65cCenIP/NYG3dBouocax++0zHPZwxo2HYLTMsOhqEVle1oVAmrpCfwat8rS68qRCKn6C+LC/pAUYmYj4l9V+w/sZoo+PdkabiasRl+BlGu65T9tYAoL7n0v8Psj+/NFY82lChPoWmOGgobCMOMsF/P+2Cu/U3DsvApilZBitemnLDRWUeA2SypaKGTkSjRTl55jloUNFWUxtyIzFvbJoY1xpj8fDjdMsDzzTVG/S2N/k2W9Y6AZ+Gt1VzwEogRVVAQbRTcODcAUGqr5sil4iQURaYWbZ04xaGcb9k4YfxzvbUlB+y944PGEZMNKHsfaHOd/XhZh45SRC6WJiKRDgH1WFDp9kM8Snf2+JpNeJFMxJmygaafH2Ibm/JY1vh7tbQTZ6En8/R+NWPrcRB3Q8ug/wbUJUN3wVqWkgy3ToocxCIOxhGxwvFlvbbxYPzuM6AxwnUCe3zwxdAYvfoSod+zPWEATtjjHVj8uPZayqGettII+DqQSndvT56LAiWyrYE90Z1W6QDbwJd58Ij7P783v/fMFYu4dZ00gmie5hkLUr8Xxwei55KDoI8SPpKMigKWGIbRqhxjg81ALnoctAcS09x8VSb1+I9skCLaXJTE0OQ+VcE9Bwwp2elJaMyIXG23L+RkyYjg8DSiCDrZLQJkk1YfItKbBIwOWk5TshyBHq4fmqx9k5D9EhOFdJw18Lv5BmyNZy2EJyFrnLThLTwZfW3Yuk/9zLu7iH/pcjzADXqq+YzsNaXUNbslVqFESP51kQgJ9sjsFmy3bBLflkAj/aw5CZz9kSb6xlCYp6v7y6J X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(40470700002)(46966006)(36840700001)(1076003)(2616005)(40460700001)(6666004)(186003)(70206006)(83380400001)(82310400004)(36860700001)(336012)(316002)(426003)(6916009)(70586007)(54906003)(47076005)(36756003)(86362001)(7696005)(44832011)(356005)(26005)(81166007)(8676002)(8936002)(4326008)(2906002)(5660300002)(966005)(508600001)(16526019)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Dec 2021 20:06:33.3048 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3c81223c-aa00-4882-1583-08d9ca3d8b99 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT039.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR1201MB0184 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Introduce a "family flags" bitmask that can be used to indicate any special behavior needed on a per-family basis. Add a flag to indicate a system uses the new register offsets introduced with Family 19h Model 10h. Use this flag to account for register offset changes, a new bitfield indicating DDR5 use on a memory controller, and to set the proper number of chip select masks. Rework f17_addr_mask_to_cs_size() to properly handle the change in chip select masks. And update code comments to reflect the updated Chip Select, DIMM, and Mask relationships. Signed-off-by: Yazen Ghannam Reported-by: kernel test robot --- Link: https://lkml.kernel.org/r/20211215155309.2711917-3-yazen.ghannam@amd.com v2->v3: * Adjust variable names to explicitly show what they represent. * Update code comment to give more detail on CS/MASK/DIMM layout. v1->v2: * Was patch 4 in v1. * Change "has_ddr5" flag to "zn_regs_v2". * Drop flag check helper function. * Update determine_memory_type() to check bitfield for DDR5. * Update code comments. drivers/edac/amd64_edac.c | 79 +++++++++++++++++++++++++++++++++------ drivers/edac/amd64_edac.h | 14 +++++++ 2 files changed, 82 insertions(+), 11 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 4db92c77276f..a299c361a904 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -15,6 +15,31 @@ static struct msr __percpu *msrs; static struct amd64_family_type *fam_type; +/* Family flag helpers */ +static inline u64 get_addr_cfg(void) +{ + if (fam_type->flags.zn_regs_v2) + return UMCCH_ADDR_CFG_DDR5; + + return UMCCH_ADDR_CFG; +} + +static inline u64 get_addr_mask_sec(void) +{ + if (fam_type->flags.zn_regs_v2) + return UMCCH_ADDR_MASK_SEC_DDR5; + + return UMCCH_ADDR_MASK_SEC; +} + +static inline u64 get_dimm_cfg(void) +{ + if (fam_type->flags.zn_regs_v2) + return UMCCH_DIMM_CFG_DDR5; + + return UMCCH_DIMM_CFG; +} + /* Per-node stuff */ static struct ecc_settings **ecc_stngs; @@ -1429,8 +1454,10 @@ static void __dump_misc_regs_df(struct amd64_pvt *pvt) edac_dbg(1, "UMC%d x16 DIMMs present: %s\n", i, (umc->dimm_cfg & BIT(7)) ? "yes" : "no"); - if (pvt->dram_type == MEM_LRDDR4) { - amd_smn_read(pvt->mc_node_id, umc_base + UMCCH_ADDR_CFG, &tmp); + if (pvt->dram_type == MEM_LRDDR4 || pvt->dram_type == MEM_LRDDR5) { + amd_smn_read(pvt->mc_node_id, + umc_base + get_addr_cfg(), + &tmp); edac_dbg(1, "UMC%d LRDIMM %dx rank multiply\n", i, 1 << ((tmp >> 4) & 0x3)); } @@ -1505,7 +1532,7 @@ static void prep_chip_selects(struct amd64_pvt *pvt) for_each_umc(umc) { pvt->csels[umc].b_cnt = 4; - pvt->csels[umc].m_cnt = 2; + pvt->csels[umc].m_cnt = fam_type->flags.zn_regs_v2 ? 4 : 2; } } else { @@ -1545,7 +1572,7 @@ static void read_umc_base_mask(struct amd64_pvt *pvt) } umc_mask_reg = get_umc_base(umc) + UMCCH_ADDR_MASK; - umc_mask_reg_sec = get_umc_base(umc) + UMCCH_ADDR_MASK_SEC; + umc_mask_reg_sec = get_umc_base(umc) + get_addr_mask_sec(); for_each_chip_select_mask(cs, umc, pvt) { mask = &pvt->csels[umc].csmasks[cs]; @@ -1618,6 +1645,20 @@ static void read_dct_base_mask(struct amd64_pvt *pvt) static enum mem_type determine_memory_type_df(struct amd64_umc *umc) { + /* + * Check if the system supports the "DDR Type" field in UMC Config + * and has DDR5 DIMMs in use. + */ + if (fam_type->flags.zn_regs_v2 && ((umc->umc_cfg & GENMASK(2, 0)) == 0x1)) { + if (umc->dimm_cfg & BIT(5)) + return MEM_LRDDR5; + + if (umc->dimm_cfg & BIT(4)) + return MEM_RDDR5; + + return MEM_DDR5; + } + if (umc->dimm_cfg & BIT(5)) return MEM_LRDDR4; @@ -2153,6 +2194,7 @@ static int f17_addr_mask_to_cs_size(struct amd64_pvt *pvt, u8 umc, { u32 addr_mask_orig, addr_mask_deinterleaved; u32 msb, weight, num_zero_bits; + int cs_mask_nr = csrow_nr; int dimm, size = 0; /* No Chip Selects are enabled. */ @@ -2168,17 +2210,31 @@ static int f17_addr_mask_to_cs_size(struct amd64_pvt *pvt, u8 umc, return size; /* - * There is one mask per DIMM, and two Chip Selects per DIMM. - * CS0 and CS1 -> DIMM0 - * CS2 and CS3 -> DIMM1 + * Family 17h introduced systems with one mask per DIMM, + * and two Chip Selects per DIMM. + * + * CS0 and CS1 -> MASK0 / DIMM0 + * CS2 and CS3 -> MASK1 / DIMM1 + * + * Family 19h Model 10h introduced systems with one mask per Chip Select, + * and two Chip Selects per DIMM. + * + * CS0 -> MASK0 -> DIMM0 + * CS1 -> MASK1 -> DIMM0 + * CS2 -> MASK2 -> DIMM1 + * CS3 -> MASK3 -> DIMM1 + * + * Keep the mask number equal to the Chip Select number for newer systems, + * and shift the mask number for older systems. */ - dimm = csrow_nr >> 1; + if (!fam_type->flags.zn_regs_v2) + cs_mask_nr >>= 1; /* Asymmetric dual-rank DIMM support. */ if ((csrow_nr & 1) && (cs_mode & CS_ODD_SECONDARY)) - addr_mask_orig = pvt->csels[umc].csmasks_sec[dimm]; + addr_mask_orig = pvt->csels[umc].csmasks_sec[cs_mask_nr]; else - addr_mask_orig = pvt->csels[umc].csmasks[dimm]; + addr_mask_orig = pvt->csels[umc].csmasks[cs_mask_nr]; /* * The number of zero bits in the mask is equal to the number of bits @@ -2934,6 +2990,7 @@ static struct amd64_family_type family_types[] = { .f0_id = PCI_DEVICE_ID_AMD_19H_M10H_DF_F0, .f6_id = PCI_DEVICE_ID_AMD_19H_M10H_DF_F6, .max_mcs = 12, + .flags.zn_regs_v2 = 1, .ops = { .early_channel_count = f17_early_channel_count, .dbam_to_cs = f17_addr_mask_to_cs_size, @@ -3372,7 +3429,7 @@ static void __read_mc_regs_df(struct amd64_pvt *pvt) umc_base = get_umc_base(i); umc = &pvt->umc[i]; - amd_smn_read(nid, umc_base + UMCCH_DIMM_CFG, &umc->dimm_cfg); + amd_smn_read(nid, umc_base + get_dimm_cfg(), &umc->dimm_cfg); amd_smn_read(nid, umc_base + UMCCH_UMC_CFG, &umc->umc_cfg); amd_smn_read(nid, umc_base + UMCCH_SDP_CTRL, &umc->sdp_ctrl); amd_smn_read(nid, umc_base + UMCCH_ECC_CTRL, &umc->ecc_ctrl); diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h index 352bda9803f6..4598a5cd0361 100644 --- a/drivers/edac/amd64_edac.h +++ b/drivers/edac/amd64_edac.h @@ -273,8 +273,11 @@ #define UMCCH_BASE_ADDR_SEC 0x10 #define UMCCH_ADDR_MASK 0x20 #define UMCCH_ADDR_MASK_SEC 0x28 +#define UMCCH_ADDR_MASK_SEC_DDR5 0x30 #define UMCCH_ADDR_CFG 0x30 +#define UMCCH_ADDR_CFG_DDR5 0x40 #define UMCCH_DIMM_CFG 0x80 +#define UMCCH_DIMM_CFG_DDR5 0x90 #define UMCCH_UMC_CFG 0x100 #define UMCCH_SDP_CTRL 0x104 #define UMCCH_ECC_CTRL 0x14C @@ -480,11 +483,22 @@ struct low_ops { unsigned cs_mode, int cs_mask_nr); }; +struct amd64_family_flags { + /* + * Indicates that the system supports the new register offsets, etc. + * first introduced with Family 19h Model 10h. + */ + __u64 zn_regs_v2 : 1, + + __reserved : 63; +}; + struct amd64_family_type { const char *ctl_name; u16 f0_id, f1_id, f2_id, f6_id; /* Maximum number of memory controllers per die/node. */ u8 max_mcs; + struct amd64_family_flags flags; struct low_ops ops; };