From patchwork Mon Jan 3 15:30:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 12702603 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AC48DC433EF for ; Mon, 3 Jan 2022 15:32:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=YyfMu5JWPxbpM9Gvu4vRuyfLwY402JNlm0ko7bRboB8=; b=BhsTBcUfFckXo6 sjJb4eCrfAm4I8bPG2Wfr7eEbVBZhm6dHjSOv/MaKIHEU5lbw3Nl7TsCeB9NUGkLHIAdGxgI7ZAvn pRG3A6LqpHJgpR3Ekzv/MirGKmDqI5hegu5lthvaGkFSWp7zDPlP+NVOi36GyepTLZY57Cwf2Skfr oKjz/7y2ZxF8al+P/7uT9xnFrpKjUm+IAdePcdcMXCH5wKsob/Kj2ApPOEpkK8Wsj/Gg/TOe9mE11 BwTqKFjcVA5QJDG5vmEChE+TeO0cO0lqBbr9Ccus++iRwlzI3OwlVE0NCwJ/hJJFxJvTMeR4bMIt3 5Vu2t1m5k3bJ/+8QVVpQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n4PJo-009LZz-2F; Mon, 03 Jan 2022 15:32:16 +0000 Received: from bhuna.collabora.co.uk ([2a00:1098:0:82:1000:25:2eeb:e3e3]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1n4PIb-009L2I-V4; Mon, 03 Jan 2022 15:31:05 +0000 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: kholk11) with ESMTPSA id E08201F42531 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1641223860; bh=OCATAr76pxucOWHqX8fcBcrgOZAy/R1mrCCO8GiW+uY=; h=From:To:Cc:Subject:Date:From; b=kggixzlZaAY5HMlTEAQw68iKWoWdyYCyn+ZUlgGGKNJrz5c8KR4vDX1m2ed1xJn/x kWiPQhkN76wQgEpeVLmGjoYt/GdjIXBBvV9qBcBd/8Uo5Tj31diRaLJCqvu2ytQ/Jz kA2vZT4fSrLnHVs5fueI/tkub13ug0H5809sVx+3NsMZixWgoP2Hh0som2tgW9LAI4 tbCfJuecAdxlSRqtx76ywoFDLNj2/L5G6Y/iR2tp+KGXMw/qE7Cr2f4S+9XpKtThoL QkOzymMYXSiATaWnyCkwPTsOcppRasR8xBIEvJXMTTnXoS7ZjvGRfZ/uZsrozFSc4V CdXjPVSQ8OicQ== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, chunfeng.yun@mediatek.com, kishon@ti.com, vkoul@kernel.org, matthias.bgg@gmail.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, AngeloGioacchino Del Regno Subject: [PATCH 1/4] phy: mediatek: phy-mtk-hdmi: Switch to regmap for mmio access Date: Mon, 3 Jan 2022 16:30:52 +0100 Message-Id: <20220103153055.50473-1-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.33.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220103_073102_307573_1ABF4649 X-CRM114-Status: GOOD ( 10.26 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Switch to using the generic regmap API instead of calls to readl/writel for MMIO register access, removing custom crafted update/set/clear_bits functions and also allowing us to reduce code size. Signed-off-by: AngeloGioacchino Del Regno --- drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c | 165 ++++++++++----------- drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c | 126 ++++++++-------- drivers/phy/mediatek/phy-mtk-hdmi.c | 51 ++----- drivers/phy/mediatek/phy-mtk-hdmi.h | 9 +- 4 files changed, 158 insertions(+), 193 deletions(-) diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c b/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c index b74c65a1762c..09e0dd7499d8 100644 --- a/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c +++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c @@ -69,19 +69,19 @@ static int mtk_hdmi_pll_prepare(struct clk_hw *hw) { struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS); + regmap_set_bits(hdmi_phy->regmap, HDMI_CON7, RG_HTPLL_AUTOK_EN); + regmap_clear_bits(hdmi_phy->regmap, HDMI_CON6, RG_HTPLL_RLH_EN); + regmap_set_bits(hdmi_phy->regmap, HDMI_CON6, RG_HTPLL_POSDIV_MASK); + regmap_set_bits(hdmi_phy->regmap, HDMI_CON2, RG_HDMITX_EN_MBIAS); usleep_range(80, 100); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK); + regmap_set_bits(hdmi_phy->regmap, HDMI_CON6, RG_HTPLL_EN); + regmap_set_bits(hdmi_phy->regmap, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO); + regmap_set_bits(hdmi_phy->regmap, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK); usleep_range(80, 100); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK); + regmap_set_bits(hdmi_phy->regmap, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN); + regmap_set_bits(hdmi_phy->regmap, HDMI_CON0, RG_HDMITX_EN_SER_MASK); + regmap_set_bits(hdmi_phy->regmap, HDMI_CON0, RG_HDMITX_EN_PRED_MASK); + regmap_set_bits(hdmi_phy->regmap, HDMI_CON0, RG_HDMITX_EN_DRV_MASK); usleep_range(80, 100); return 0; } @@ -90,19 +90,19 @@ static void mtk_hdmi_pll_unprepare(struct clk_hw *hw) { struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN); + regmap_clear_bits(hdmi_phy->regmap, HDMI_CON0, RG_HDMITX_EN_DRV_MASK); + regmap_clear_bits(hdmi_phy->regmap, HDMI_CON0, RG_HDMITX_EN_PRED_MASK); + regmap_clear_bits(hdmi_phy->regmap, HDMI_CON0, RG_HDMITX_EN_SER_MASK); + regmap_clear_bits(hdmi_phy->regmap, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN); usleep_range(80, 100); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN); + regmap_clear_bits(hdmi_phy->regmap, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK); + regmap_clear_bits(hdmi_phy->regmap, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO); + regmap_clear_bits(hdmi_phy->regmap, HDMI_CON6, RG_HTPLL_EN); usleep_range(80, 100); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN); + regmap_clear_bits(hdmi_phy->regmap, HDMI_CON2, RG_HDMITX_EN_MBIAS); + regmap_clear_bits(hdmi_phy->regmap, HDMI_CON6, RG_HTPLL_POSDIV_MASK); + regmap_clear_bits(hdmi_phy->regmap, HDMI_CON6, RG_HTPLL_RLH_EN); + regmap_clear_bits(hdmi_phy->regmap, HDMI_CON7, RG_HTPLL_AUTOK_EN); usleep_range(80, 100); } @@ -125,37 +125,34 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate, else pos_div = 1; - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_PREDIV_MASK); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_POSDIV); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_IC), - RG_HTPLL_IC_MASK); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_IR), - RG_HTPLL_IR_MASK); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON2, (pos_div << RG_HDMITX_TX_POSDIV), - RG_HDMITX_TX_POSDIV_MASK); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (1 << RG_HTPLL_FBKSEL), - RG_HTPLL_FBKSEL_MASK); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (19 << RG_HTPLL_FBKDIV), - RG_HTPLL_FBKDIV_MASK); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON7, (0x2 << RG_HTPLL_DIVEN), - RG_HTPLL_DIVEN_MASK); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0xc << RG_HTPLL_BP), - RG_HTPLL_BP_MASK); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x2 << RG_HTPLL_BC), - RG_HTPLL_BC_MASK); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_BR), - RG_HTPLL_BR_MASK); - - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PRED_IMP); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, (0x3 << RG_HDMITX_PRED_IBIAS), - RG_HDMITX_PRED_IBIAS_MASK); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_IMP_MASK); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, (0x28 << RG_HDMITX_DRV_IMP), - RG_HDMITX_DRV_IMP_MASK); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4, 0x28, RG_HDMITX_RESERVE_MASK); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, (0xa << RG_HDMITX_DRV_IBIAS), - RG_HDMITX_DRV_IBIAS_MASK); + regmap_set_bits(hdmi_phy->regmap, HDMI_CON6, RG_HTPLL_PREDIV_MASK); + regmap_set_bits(hdmi_phy->regmap, HDMI_CON6, RG_HTPLL_POSDIV_MASK); + regmap_set_bits(hdmi_phy->regmap, HDMI_CON2, RG_HDMITX_EN_TX_POSDIV); + regmap_update_bits(hdmi_phy->regmap, HDMI_CON6, RG_HTPLL_IC_MASK, BIT(RG_HTPLL_IC)); + regmap_update_bits(hdmi_phy->regmap, HDMI_CON6, RG_HTPLL_IR_MASK, BIT(RG_HTPLL_IR)); + regmap_update_bits(hdmi_phy->regmap, HDMI_CON2, RG_HDMITX_TX_POSDIV_MASK, + (pos_div << RG_HDMITX_TX_POSDIV)); + regmap_update_bits(hdmi_phy->regmap, HDMI_CON6, RG_HTPLL_FBKSEL_MASK, + (1 << RG_HTPLL_FBKSEL)); + regmap_update_bits(hdmi_phy->regmap, HDMI_CON6, RG_HTPLL_FBKDIV_MASK, + (19 << RG_HTPLL_FBKDIV)); + regmap_update_bits(hdmi_phy->regmap, HDMI_CON7, RG_HTPLL_DIVEN_MASK, + (0x2 << RG_HTPLL_DIVEN)); + regmap_update_bits(hdmi_phy->regmap, HDMI_CON6, RG_HTPLL_BP_MASK, + (0xc << RG_HTPLL_BP)); + regmap_update_bits(hdmi_phy->regmap, HDMI_CON6, RG_HTPLL_BC_MASK, + (0x2 << RG_HTPLL_BC)); + regmap_update_bits(hdmi_phy->regmap, HDMI_CON6, RG_HTPLL_BR_MASK, BIT(RG_HTPLL_BR)); + + regmap_clear_bits(hdmi_phy->regmap, HDMI_CON1, RG_HDMITX_PRED_IMP); + regmap_update_bits(hdmi_phy->regmap, HDMI_CON1, RG_HDMITX_PRED_IBIAS_MASK, + (0x3 << RG_HDMITX_PRED_IBIAS)); + regmap_clear_bits(hdmi_phy->regmap, HDMI_CON0, RG_HDMITX_EN_IMP_MASK); + regmap_update_bits(hdmi_phy->regmap, HDMI_CON1, RG_HDMITX_DRV_IMP_MASK, + (0x28 << RG_HDMITX_DRV_IMP)); + regmap_update_bits(hdmi_phy->regmap, HDMI_CON4, RG_HDMITX_RESERVE_MASK, 0x28); + regmap_update_bits(hdmi_phy->regmap, HDMI_CON0, RG_HDMITX_DRV_IBIAS_MASK, + (0xa << RG_HDMITX_DRV_IBIAS)); return 0; } @@ -163,10 +160,11 @@ static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); - unsigned long out_rate, val; + unsigned long out_rate; + u32 val; - val = (readl(hdmi_phy->regs + HDMI_CON6) - & RG_HTPLL_PREDIV_MASK) >> RG_HTPLL_PREDIV; + regmap_read(hdmi_phy->regmap, HDMI_CON6, &val); + val = (val & RG_HTPLL_PREDIV_MASK) >> RG_HTPLL_PREDIV; switch (val) { case 0x00: out_rate = parent_rate; @@ -179,14 +177,15 @@ static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw, break; } - val = (readl(hdmi_phy->regs + HDMI_CON6) - & RG_HTPLL_FBKDIV_MASK) >> RG_HTPLL_FBKDIV; + regmap_read(hdmi_phy->regmap, HDMI_CON6, &val); + val = (val & RG_HTPLL_FBKDIV_MASK) >> RG_HTPLL_FBKDIV; out_rate *= (val + 1) * 2; - val = (readl(hdmi_phy->regs + HDMI_CON2) - & RG_HDMITX_TX_POSDIV_MASK); + regmap_read(hdmi_phy->regmap, HDMI_CON2, &val); + val &= RG_HDMITX_TX_POSDIV_MASK; out_rate >>= (val >> RG_HDMITX_TX_POSDIV); - if (readl(hdmi_phy->regs + HDMI_CON2) & RG_HDMITX_EN_TX_POSDIV) + regmap_read(hdmi_phy->regmap, HDMI_CON2, &val); + if (val & RG_HDMITX_EN_TX_POSDIV) out_rate /= 5; return out_rate; @@ -202,37 +201,37 @@ static const struct clk_ops mtk_hdmi_phy_pll_ops = { static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy) { - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS); + regmap_set_bits(hdmi_phy->regmap, HDMI_CON7, RG_HTPLL_AUTOK_EN); + regmap_clear_bits(hdmi_phy->regmap, HDMI_CON6, RG_HTPLL_RLH_EN); + regmap_set_bits(hdmi_phy->regmap, HDMI_CON6, RG_HTPLL_POSDIV_MASK); + regmap_set_bits(hdmi_phy->regmap, HDMI_CON2, RG_HDMITX_EN_MBIAS); usleep_range(80, 100); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK); + regmap_set_bits(hdmi_phy->regmap, HDMI_CON6, RG_HTPLL_EN); + regmap_set_bits(hdmi_phy->regmap, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO); + regmap_set_bits(hdmi_phy->regmap, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK); usleep_range(80, 100); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK); + regmap_set_bits(hdmi_phy->regmap, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN); + regmap_set_bits(hdmi_phy->regmap, HDMI_CON0, RG_HDMITX_EN_SER_MASK); + regmap_set_bits(hdmi_phy->regmap, HDMI_CON0, RG_HDMITX_EN_PRED_MASK); + regmap_set_bits(hdmi_phy->regmap, HDMI_CON0, RG_HDMITX_EN_DRV_MASK); usleep_range(80, 100); } static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy) { - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN); + regmap_clear_bits(hdmi_phy->regmap, HDMI_CON0, RG_HDMITX_EN_DRV_MASK); + regmap_clear_bits(hdmi_phy->regmap, HDMI_CON0, RG_HDMITX_EN_PRED_MASK); + regmap_clear_bits(hdmi_phy->regmap, HDMI_CON0, RG_HDMITX_EN_SER_MASK); + regmap_clear_bits(hdmi_phy->regmap, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN); usleep_range(80, 100); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN); + regmap_clear_bits(hdmi_phy->regmap, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK); + regmap_clear_bits(hdmi_phy->regmap, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO); + regmap_clear_bits(hdmi_phy->regmap, HDMI_CON6, RG_HTPLL_EN); usleep_range(80, 100); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN); + regmap_clear_bits(hdmi_phy->regmap, HDMI_CON2, RG_HDMITX_EN_MBIAS); + regmap_clear_bits(hdmi_phy->regmap, HDMI_CON6, RG_HTPLL_POSDIV_MASK); + regmap_clear_bits(hdmi_phy->regmap, HDMI_CON6, RG_HTPLL_RLH_EN); + regmap_clear_bits(hdmi_phy->regmap, HDMI_CON7, RG_HTPLL_AUTOK_EN); usleep_range(80, 100); } diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c b/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c index 6cdfdf5a698a..e317bf4a9db9 100644 --- a/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c +++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c @@ -111,15 +111,15 @@ static int mtk_hdmi_pll_prepare(struct clk_hw *hw) { struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, RG_HDMITX_MHLCK_EN); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_EN); + regmap_set_bits(hdmi_phy->regmap, HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN); + regmap_set_bits(hdmi_phy->regmap, HDMI_CON0, RG_HDMITX_PLL_POSDIV); + regmap_clear_bits(hdmi_phy->regmap, HDMI_CON3, RG_HDMITX_MHLCK_EN); + regmap_set_bits(hdmi_phy->regmap, HDMI_CON1, RG_HDMITX_PLL_BIAS_EN); usleep_range(100, 150); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_EN); + regmap_set_bits(hdmi_phy->regmap, HDMI_CON0, RG_HDMITX_PLL_EN); usleep_range(100, 150); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN); + regmap_set_bits(hdmi_phy->regmap, HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN); + regmap_set_bits(hdmi_phy->regmap, HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN); return 0; } @@ -128,14 +128,14 @@ static void mtk_hdmi_pll_unprepare(struct clk_hw *hw) { struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN); + regmap_clear_bits(hdmi_phy->regmap, HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN); + regmap_clear_bits(hdmi_phy->regmap, HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN); usleep_range(100, 150); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_EN); + regmap_clear_bits(hdmi_phy->regmap, HDMI_CON0, RG_HDMITX_PLL_EN); usleep_range(100, 150); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_EN); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN); + regmap_clear_bits(hdmi_phy->regmap, HDMI_CON1, RG_HDMITX_PLL_BIAS_EN); + regmap_clear_bits(hdmi_phy->regmap, HDMI_CON0, RG_HDMITX_PLL_POSDIV); + regmap_clear_bits(hdmi_phy->regmap, HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN); usleep_range(100, 150); } @@ -177,65 +177,59 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate, div = 1; } - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, - (pre_div << PREDIV_SHIFT), RG_HDMITX_PLL_PREDIV); - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, - (0x1 << PLL_IC_SHIFT) | (0x1 << PLL_IR_SHIFT), - RG_HDMITX_PLL_IC | RG_HDMITX_PLL_IR); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, - (div << PLL_TXDIV_SHIFT), RG_HDMITX_PLL_TXDIV); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, - (0x1 << PLL_FBKSEL_SHIFT) | (19 << PLL_FBKDIV_SHIFT), - RG_HDMITX_PLL_FBKSEL | RG_HDMITX_PLL_FBKDIV); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, - (0x2 << PLL_DIVEN_SHIFT), RG_HDMITX_PLL_DIVEN); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, - (0xc << PLL_BP_SHIFT) | (0x2 << PLL_BC_SHIFT) | - (0x1 << PLL_BR_SHIFT), - RG_HDMITX_PLL_BP | RG_HDMITX_PLL_BC | - RG_HDMITX_PLL_BR); + regmap_update_bits(hdmi_phy->regmap, HDMI_CON0, RG_HDMITX_PLL_PREDIV, + (pre_div << PREDIV_SHIFT)); + regmap_set_bits(hdmi_phy->regmap, HDMI_CON0, RG_HDMITX_PLL_POSDIV); + regmap_update_bits(hdmi_phy->regmap, HDMI_CON0, + RG_HDMITX_PLL_IC | RG_HDMITX_PLL_IR, + BIT(PLL_IC_SHIFT) | BIT(PLL_IR_SHIFT)); + regmap_update_bits(hdmi_phy->regmap, HDMI_CON1, RG_HDMITX_PLL_TXDIV, + (div << PLL_TXDIV_SHIFT)); + regmap_update_bits(hdmi_phy->regmap, HDMI_CON0, + RG_HDMITX_PLL_FBKSEL | RG_HDMITX_PLL_FBKDIV, + BIT(PLL_FBKSEL_SHIFT) | (19 << PLL_FBKDIV_SHIFT)); + regmap_update_bits(hdmi_phy->regmap, HDMI_CON1, RG_HDMITX_PLL_DIVEN, + (0x2 << PLL_DIVEN_SHIFT)); + regmap_update_bits(hdmi_phy->regmap, HDMI_CON0, + RG_HDMITX_PLL_BP | RG_HDMITX_PLL_BC | RG_HDMITX_PLL_BR, + (0xc << PLL_BP_SHIFT) | (0x2 << PLL_BC_SHIFT) | + (0x1 << PLL_BR_SHIFT)); if (rate < 165000000) { - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, + regmap_clear_bits(hdmi_phy->regmap, HDMI_CON3, RG_HDMITX_PRD_IMP_EN); pre_ibias = 0x3; imp_en = 0x0; hdmi_ibias = hdmi_phy->ibias; } else { - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3, + regmap_set_bits(hdmi_phy->regmap, HDMI_CON3, RG_HDMITX_PRD_IMP_EN); pre_ibias = 0x6; imp_en = 0xf; hdmi_ibias = hdmi_phy->ibias_up; } - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4, - (pre_ibias << PRD_IBIAS_CLK_SHIFT) | - (pre_ibias << PRD_IBIAS_D2_SHIFT) | - (pre_ibias << PRD_IBIAS_D1_SHIFT) | - (pre_ibias << PRD_IBIAS_D0_SHIFT), - RG_HDMITX_PRD_IBIAS_CLK | - RG_HDMITX_PRD_IBIAS_D2 | - RG_HDMITX_PRD_IBIAS_D1 | - RG_HDMITX_PRD_IBIAS_D0); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3, - (imp_en << DRV_IMP_EN_SHIFT), - RG_HDMITX_DRV_IMP_EN); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, - (hdmi_phy->drv_imp_clk << DRV_IMP_CLK_SHIFT) | - (hdmi_phy->drv_imp_d2 << DRV_IMP_D2_SHIFT) | - (hdmi_phy->drv_imp_d1 << DRV_IMP_D1_SHIFT) | - (hdmi_phy->drv_imp_d0 << DRV_IMP_D0_SHIFT), - RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 | - RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0); - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5, - (hdmi_ibias << DRV_IBIAS_CLK_SHIFT) | - (hdmi_ibias << DRV_IBIAS_D2_SHIFT) | - (hdmi_ibias << DRV_IBIAS_D1_SHIFT) | - (hdmi_ibias << DRV_IBIAS_D0_SHIFT), - RG_HDMITX_DRV_IBIAS_CLK | - RG_HDMITX_DRV_IBIAS_D2 | - RG_HDMITX_DRV_IBIAS_D1 | - RG_HDMITX_DRV_IBIAS_D0); + regmap_update_bits(hdmi_phy->regmap, HDMI_CON4, + RG_HDMITX_PRD_IBIAS_CLK | RG_HDMITX_PRD_IBIAS_D2 | + RG_HDMITX_PRD_IBIAS_D1 | RG_HDMITX_PRD_IBIAS_D0, + (pre_ibias << PRD_IBIAS_CLK_SHIFT) | + (pre_ibias << PRD_IBIAS_D2_SHIFT) | + (pre_ibias << PRD_IBIAS_D1_SHIFT) | + (pre_ibias << PRD_IBIAS_D0_SHIFT)); + regmap_update_bits(hdmi_phy->regmap, HDMI_CON3, RG_HDMITX_DRV_IMP_EN, + (imp_en << DRV_IMP_EN_SHIFT)); + regmap_update_bits(hdmi_phy->regmap, HDMI_CON6, + RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 | + RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0, + (hdmi_phy->drv_imp_clk << DRV_IMP_CLK_SHIFT) | + (hdmi_phy->drv_imp_d2 << DRV_IMP_D2_SHIFT) | + (hdmi_phy->drv_imp_d1 << DRV_IMP_D1_SHIFT) | + (hdmi_phy->drv_imp_d0 << DRV_IMP_D0_SHIFT)); + regmap_update_bits(hdmi_phy->regmap, HDMI_CON5, + RG_HDMITX_DRV_IBIAS_CLK | RG_HDMITX_DRV_IBIAS_D2 | + RG_HDMITX_DRV_IBIAS_D1 | RG_HDMITX_DRV_IBIAS_D0, + (hdmi_ibias << DRV_IBIAS_CLK_SHIFT) | + (hdmi_ibias << DRV_IBIAS_D2_SHIFT) | + (hdmi_ibias << DRV_IBIAS_D1_SHIFT) | + (hdmi_ibias << DRV_IBIAS_D0_SHIFT)); return 0; } @@ -257,17 +251,15 @@ static const struct clk_ops mtk_hdmi_phy_pll_ops = { static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy) { - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3, - RG_HDMITX_SER_EN | RG_HDMITX_PRD_EN | - RG_HDMITX_DRV_EN); + regmap_set_bits(hdmi_phy->regmap, HDMI_CON3, + RG_HDMITX_SER_EN | RG_HDMITX_PRD_EN | RG_HDMITX_DRV_EN); usleep_range(100, 150); } static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy) { - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, - RG_HDMITX_DRV_EN | RG_HDMITX_PRD_EN | - RG_HDMITX_SER_EN); + regmap_clear_bits(hdmi_phy->regmap, HDMI_CON3, + RG_HDMITX_DRV_EN | RG_HDMITX_PRD_EN | RG_HDMITX_SER_EN); } struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf = { diff --git a/drivers/phy/mediatek/phy-mtk-hdmi.c b/drivers/phy/mediatek/phy-mtk-hdmi.c index 5fb4217fb8e0..707e90691e6e 100644 --- a/drivers/phy/mediatek/phy-mtk-hdmi.c +++ b/drivers/phy/mediatek/phy-mtk-hdmi.c @@ -15,39 +15,6 @@ static const struct phy_ops mtk_hdmi_phy_dev_ops = { .owner = THIS_MODULE, }; -void mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset, - u32 bits) -{ - void __iomem *reg = hdmi_phy->regs + offset; - u32 tmp; - - tmp = readl(reg); - tmp &= ~bits; - writel(tmp, reg); -} - -void mtk_hdmi_phy_set_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset, - u32 bits) -{ - void __iomem *reg = hdmi_phy->regs + offset; - u32 tmp; - - tmp = readl(reg); - tmp |= bits; - writel(tmp, reg); -} - -void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset, - u32 val, u32 mask) -{ - void __iomem *reg = hdmi_phy->regs + offset; - u32 tmp; - - tmp = readl(reg); - tmp = (tmp & ~mask) | (val & mask); - writel(tmp, reg); -} - inline struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw) { return container_of(hw, struct mtk_hdmi_phy, pll_hw); @@ -96,6 +63,13 @@ static void mtk_hdmi_phy_clk_get_data(struct mtk_hdmi_phy *hdmi_phy, clk_init->ops = hdmi_phy->conf->hdmi_phy_clk_ops; } +static const struct regmap_config mtk_hdmi_phy_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .disable_locking = true, +}; + static int mtk_hdmi_phy_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -109,15 +83,20 @@ static int mtk_hdmi_phy_probe(struct platform_device *pdev) struct phy *phy; struct phy_provider *phy_provider; + void __iomem *regs; int ret; hdmi_phy = devm_kzalloc(dev, sizeof(*hdmi_phy), GFP_KERNEL); if (!hdmi_phy) return -ENOMEM; - hdmi_phy->regs = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(hdmi_phy->regs)) - return PTR_ERR(hdmi_phy->regs); + regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(regs)) + return PTR_ERR(regs); + + hdmi_phy->regmap = devm_regmap_init_mmio(dev, regs, &mtk_hdmi_phy_regmap_config); + if (IS_ERR(hdmi_phy->regmap)) + return PTR_ERR(hdmi_phy->regmap); ref_clk = devm_clk_get(dev, "pll_ref"); if (IS_ERR(ref_clk)) { diff --git a/drivers/phy/mediatek/phy-mtk-hdmi.h b/drivers/phy/mediatek/phy-mtk-hdmi.h index dcf9bb13699b..a0571271d730 100644 --- a/drivers/phy/mediatek/phy-mtk-hdmi.h +++ b/drivers/phy/mediatek/phy-mtk-hdmi.h @@ -15,6 +15,7 @@ #include #include #include +#include #include struct mtk_hdmi_phy; @@ -28,7 +29,7 @@ struct mtk_hdmi_phy_conf { }; struct mtk_hdmi_phy { - void __iomem *regs; + struct regmap *regmap; struct device *dev; struct mtk_hdmi_phy_conf *conf; struct clk *pll; @@ -42,12 +43,6 @@ struct mtk_hdmi_phy { unsigned int ibias_up; }; -void mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset, - u32 bits); -void mtk_hdmi_phy_set_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset, - u32 bits); -void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset, - u32 val, u32 mask); struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw); extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf; From patchwork Mon Jan 3 15:30:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 12702602 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 709B3C433EF for ; Mon, 3 Jan 2022 15:31:19 +0000 (UTC) DKIM-Signature: v=1; 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Mon, 03 Jan 2022 15:31:04 +0000 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: kholk11) with ESMTPSA id B3B5E1F42536 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1641223861; bh=ufpjK9obNzMvAWdLd5nIOYsHY/3E6VwId5SApV+NWmY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IxrxphPRJeH6xoKd3/7H4lUO1e6wRNNj0KJ/Zlho65Hs5+j/ZlkHzo0vV+XG3mNQm tW5ZmzFM83RZPEDnb3H9hRssaNZ+1t2YPEI3LLEBuqtlgFokb4edV6w2+/hJR9PZPj gkyvg1MV0ddmx8DS5Q/HlP3BsxkkAAIos7S3Un7ghBMGhw0tFeLgXbp7t+vbz/XUDm TFnMXx5v04qo1DWwjFZDoYlOqRcl3ycrCNZx6kCxJdD41bGJoW6oNvRkab1o8aqugl d5Qe3H91vrbFrG+J636lwLZ0sgVOWTg52czd/4k0eYrAQ8+R/lBgeGPiAh32clLuZ2 iULNNllkTd7VQ== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, chunfeng.yun@mediatek.com, kishon@ti.com, vkoul@kernel.org, matthias.bgg@gmail.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, AngeloGioacchino Del Regno Subject: [PATCH 2/4] phy: mediatek: phy-mtk-hdmi: Reorder to remove forward declarations Date: Mon, 3 Jan 2022 16:30:53 +0100 Message-Id: <20220103153055.50473-2-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220103153055.50473-1-angelogioacchino.delregno@collabora.com> References: <20220103153055.50473-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220103_073102_748255_E07961CB X-CRM114-Status: UNSURE ( 8.28 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Forward declarations for mtk_hdmi_power_{on,off} aren't necessary: move mtk_hdmi_phy_dev_ops down to remove forward declarations. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chunfeng Yun --- drivers/phy/mediatek/phy-mtk-hdmi.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/drivers/phy/mediatek/phy-mtk-hdmi.c b/drivers/phy/mediatek/phy-mtk-hdmi.c index 707e90691e6e..b4193cb4e4e3 100644 --- a/drivers/phy/mediatek/phy-mtk-hdmi.c +++ b/drivers/phy/mediatek/phy-mtk-hdmi.c @@ -6,15 +6,6 @@ #include "phy-mtk-hdmi.h" -static int mtk_hdmi_phy_power_on(struct phy *phy); -static int mtk_hdmi_phy_power_off(struct phy *phy); - -static const struct phy_ops mtk_hdmi_phy_dev_ops = { - .power_on = mtk_hdmi_phy_power_on, - .power_off = mtk_hdmi_phy_power_off, - .owner = THIS_MODULE, -}; - inline struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw) { return container_of(hw, struct mtk_hdmi_phy, pll_hw); @@ -43,6 +34,12 @@ static int mtk_hdmi_phy_power_off(struct phy *phy) return 0; } +static const struct phy_ops mtk_hdmi_phy_dev_ops = { + .power_on = mtk_hdmi_phy_power_on, + .power_off = mtk_hdmi_phy_power_off, + .owner = THIS_MODULE, +}; + static const struct phy_ops * mtk_hdmi_phy_dev_get_ops(const struct mtk_hdmi_phy *hdmi_phy) { From patchwork Mon Jan 3 15:30:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 12702604 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DCB2BC433F5 for ; Mon, 3 Jan 2022 15:32:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=OlJrcOjo9Kv58R/QdevXq43KCXu29keU9D1Qf/769Gk=; b=mCKkYI+r99GoK4 y8wuaHzjY8j4T+NTk+QG3YIT5x4DfFqSi6rxCdOerh9NPJsU6BznYqjU8kNC1pDK81K2U13g6IjQM 64/yQ4WPLjGhIogCHIDoQLafl0BhBBhMPo0Qd3Vrf5mTyJUlXK1cD0/CQSbWBW1nHI/ioXN5BD5cu +AifKdIW2EMbweHbACvnnJNPEb0MPsLf14bHUOt5mqtAzhjRP6qUbUxmfxAxDmqSMoZJBlzDS3R9R Oot5EebWPS4/djIgVlI2iwYFEON+467lS4bn0aRzbc10QpjIATHpQGOyMDKKfEIwBAGysue2FioHf 4AFt936oqzNbLpLGEgxw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n4PJq-009LbF-4k; Mon, 03 Jan 2022 15:32:18 +0000 Received: from bhuna.collabora.co.uk ([46.235.227.227]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1n4PId-009L2y-F2; Mon, 03 Jan 2022 15:31:05 +0000 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: kholk11) with ESMTPSA id 8249F1F4254C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1641223862; bh=sEDq2d+5/abLrttz8U18JMOJJuSHWVdlfX/N3MRUvHk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fQ1z/nL8jFTbNjKYRB+PMQyIzYsFu8sg0pylMTuCTroCVbNbcK8gxDvbw3InCv3Eo APnlC7ub0pkwb6wX2AeUIbRQ62kF+tJ5KgGt7vk7Iy3736YtYuXAx77SH5Qz7sLyS3 kTQpo+2Z1D9+0f1IHN7S8bsHtGS8CVEMlQqUpTi6ol54LYyMraQbMLQbuqFvs3XlWz h2w8qP3AuUSe5CCDPg5SMKKfpgftvNQIximMZiuS7EKyHe49z6RCSGDrSg01FwDG0q 9n9ZLhC31266uN1touKYVJfUA2OUlxFOJtMMIJg4eujsjfVs2bpChzdaFlbgbT/MKG kzSzetjsZVD3g== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, chunfeng.yun@mediatek.com, kishon@ti.com, vkoul@kernel.org, matthias.bgg@gmail.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, AngeloGioacchino Del Regno Subject: [PATCH 3/4] phy: mediatek: phy-mtk-hdmi: Reorder and stop implicit header inclusion Date: Mon, 3 Jan 2022 16:30:54 +0100 Message-Id: <20220103153055.50473-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220103153055.50473-1-angelogioacchino.delregno@collabora.com> References: <20220103153055.50473-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220103_073103_654940_358B02E5 X-CRM114-Status: UNSURE ( 9.10 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org All the headers for phy-mtk-{hdmi,hdmi-mt2701,hdmi-mt8183}.c were included from phy-mtk-mipi-dsi.h, but this isn't optimal: in order to increase readability and sensibly reduce build times, the inclusions should be done per-file, also avoiding to include unused headers and should not be implicit. For this reason, move the inclusions to each file and remove unused ones. Signed-off-by: AngeloGioacchino Del Regno --- drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c | 5 +++++ drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c | 5 +++++ drivers/phy/mediatek/phy-mtk-hdmi.c | 8 ++++++++ drivers/phy/mediatek/phy-mtk-hdmi.h | 10 +--------- 4 files changed, 19 insertions(+), 9 deletions(-) diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c b/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c index 09e0dd7499d8..270c5f538483 100644 --- a/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c +++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c @@ -4,6 +4,11 @@ * Author: Chunhui Dai */ +#include +#include +#include +#include +#include #include "phy-mtk-hdmi.h" #define HDMI_CON0 0x00 diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c b/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c index e317bf4a9db9..87ba9a3687b7 100644 --- a/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c +++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c @@ -4,6 +4,11 @@ * Author: Jie Qiu */ +#include +#include +#include +#include +#include #include "phy-mtk-hdmi.h" #define HDMI_CON0 0x00 diff --git a/drivers/phy/mediatek/phy-mtk-hdmi.c b/drivers/phy/mediatek/phy-mtk-hdmi.c index b4193cb4e4e3..e037fa89696c 100644 --- a/drivers/phy/mediatek/phy-mtk-hdmi.c +++ b/drivers/phy/mediatek/phy-mtk-hdmi.c @@ -4,6 +4,14 @@ * Author: Jie Qiu */ +#include +#include +#include +#include +#include +#include +#include +#include #include "phy-mtk-hdmi.h" inline struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw) diff --git a/drivers/phy/mediatek/phy-mtk-hdmi.h b/drivers/phy/mediatek/phy-mtk-hdmi.h index a0571271d730..ef81e44a235d 100644 --- a/drivers/phy/mediatek/phy-mtk-hdmi.h +++ b/drivers/phy/mediatek/phy-mtk-hdmi.h @@ -6,17 +6,9 @@ #ifndef _MTK_HDMI_PHY_H #define _MTK_HDMI_PHY_H -#include + #include -#include -#include -#include -#include -#include -#include -#include #include -#include struct mtk_hdmi_phy; From patchwork Mon Jan 3 15:30:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 12702605 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 81285C433FE for ; Mon, 3 Jan 2022 15:32:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fir+ujfJNM05YaXg9OVuXrjYsLYFWjcKntoB2ehQIIVsZVcVvTixYQhHYdMcCPd3o pGtSFthvJDCddnv1LQHqYQuMx3UoOC1XxDunBT58INR3fxfvsdZ+UsSwY2wGhcqKpk hcFEomrqtwycnN2JZ8UQcyvOVTg/f6+JUQJgWF2yXGXyQGjnEIZKo7taa9zvyuR0dg 9Tnkbq+KjiTxIZcCBHY7BUoj2utD4tUWbMSu1l15B1kagsMnOqAX5SWXYn2QmIGquD JwYDjJq/guagELnXkvTJ7Es1Ke7mDHVN62es6uF+O1UXpfkD6le76NKZFpuWw4MQzO FGi3fvaxMrcNw== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, chunfeng.yun@mediatek.com, kishon@ti.com, vkoul@kernel.org, matthias.bgg@gmail.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, AngeloGioacchino Del Regno Subject: [PATCH 4/4] phy: mediatek: phy-mtk-hdmi: Simplify with dev_err_probe() Date: Mon, 3 Jan 2022 16:30:55 +0100 Message-Id: <20220103153055.50473-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220103153055.50473-1-angelogioacchino.delregno@collabora.com> References: <20220103153055.50473-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220103_073104_331356_42B36F30 X-CRM114-Status: UNSURE ( 9.76 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Use the dev_err_probe() helper to simplify error handling during probe. Signed-off-by: AngeloGioacchino Del Regno --- drivers/phy/mediatek/phy-mtk-hdmi.c | 50 +++++++++++------------------ 1 file changed, 19 insertions(+), 31 deletions(-) diff --git a/drivers/phy/mediatek/phy-mtk-hdmi.c b/drivers/phy/mediatek/phy-mtk-hdmi.c index e037fa89696c..4f40a6eea004 100644 --- a/drivers/phy/mediatek/phy-mtk-hdmi.c +++ b/drivers/phy/mediatek/phy-mtk-hdmi.c @@ -104,20 +104,16 @@ static int mtk_hdmi_phy_probe(struct platform_device *pdev) return PTR_ERR(hdmi_phy->regmap); ref_clk = devm_clk_get(dev, "pll_ref"); - if (IS_ERR(ref_clk)) { - ret = PTR_ERR(ref_clk); - dev_err(&pdev->dev, "Failed to get PLL reference clock: %d\n", - ret); - return ret; - } + if (IS_ERR(ref_clk)) + return dev_err_probe(dev, PTR_ERR(ref_clk), + "Failed to get PLL reference clock\n"); + ref_clk_name = __clk_get_name(ref_clk); ret = of_property_read_string(dev->of_node, "clock-output-names", &clk_init.name); - if (ret < 0) { - dev_err(dev, "Failed to read clock-output-names: %d\n", ret); - return ret; - } + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to read clock-output-names\n"); hdmi_phy->dev = dev; hdmi_phy->conf = @@ -125,25 +121,19 @@ static int mtk_hdmi_phy_probe(struct platform_device *pdev) mtk_hdmi_phy_clk_get_data(hdmi_phy, &clk_init); hdmi_phy->pll_hw.init = &clk_init; hdmi_phy->pll = devm_clk_register(dev, &hdmi_phy->pll_hw); - if (IS_ERR(hdmi_phy->pll)) { - ret = PTR_ERR(hdmi_phy->pll); - dev_err(dev, "Failed to register PLL: %d\n", ret); - return ret; - } + if (IS_ERR(hdmi_phy->pll)) + return dev_err_probe(dev, PTR_ERR(hdmi_phy->pll), + "Failed to register PLL\n"); ret = of_property_read_u32(dev->of_node, "mediatek,ibias", &hdmi_phy->ibias); - if (ret < 0) { - dev_err(&pdev->dev, "Failed to get ibias: %d\n", ret); - return ret; - } + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to get ibias\n"); ret = of_property_read_u32(dev->of_node, "mediatek,ibias_up", &hdmi_phy->ibias_up); - if (ret < 0) { - dev_err(&pdev->dev, "Failed to get ibias up: %d\n", ret); - return ret; - } + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to get ibias_up\n"); dev_info(dev, "Using default TX DRV impedance: 4.2k/36\n"); hdmi_phy->drv_imp_clk = 0x30; @@ -152,17 +142,15 @@ static int mtk_hdmi_phy_probe(struct platform_device *pdev) hdmi_phy->drv_imp_d0 = 0x30; phy = devm_phy_create(dev, NULL, mtk_hdmi_phy_dev_get_ops(hdmi_phy)); - if (IS_ERR(phy)) { - dev_err(dev, "Failed to create HDMI PHY\n"); - return PTR_ERR(phy); - } + if (IS_ERR(phy)) + return dev_err_probe(dev, PTR_ERR(phy), "Cannot create HDMI PHY\n"); + phy_set_drvdata(phy, hdmi_phy); phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); - if (IS_ERR(phy_provider)) { - dev_err(dev, "Failed to register HDMI PHY\n"); - return PTR_ERR(phy_provider); - } + if (IS_ERR(phy_provider)) + return dev_err_probe(dev, PTR_ERR(phy_provider), + "Failed to register HDMI PHY\n"); if (hdmi_phy->conf->pll_default_off) hdmi_phy->conf->hdmi_phy_disable_tmds(hdmi_phy);