From patchwork Wed Jan 5 03:08:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 12704004 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3BC73C433EF for ; Wed, 5 Jan 2022 03:17:39 +0000 (UTC) Received: from localhost ([::1]:52698 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n4wny-0008I2-4H for qemu-devel@archiver.kernel.org; Tue, 04 Jan 2022 22:17:38 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60374) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n4wfZ-00070d-O4; Tue, 04 Jan 2022 22:08:57 -0500 Received: from [2607:f8b0:4864:20::102a] (port=35575 helo=mail-pj1-x102a.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n4wfY-0001we-6E; Tue, 04 Jan 2022 22:08:57 -0500 Received: by mail-pj1-x102a.google.com with SMTP id r16-20020a17090a0ad000b001b276aa3aabso2028722pje.0; Tue, 04 Jan 2022 19:08:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9sdvt0SCvD2QSOMHtz/9igRF47GFOyS9Q4ZZZNZ/yIc=; b=obB03EIcWsiKFsUdcQ1O8JyaigoZu5ZHQpBKINBnEnOGC9fksk47Lniz5OYoLpfenR oF8IrOQM18hYSzSqcIWt/+rarvuaEYrCdesSaDjIZgJrFa8pbX2hbbe0nnjEQeCskc/S qYMP9NLkc+nQ/WZ+4byE2wPPhhzfKXIhmrHtkd+StHbnNcFEqhqVI2LFEnuWThhn+gfF 4rN7KxfaQpKNx7d4SNfh/L1MU+ZNtRgp0v0X3Vu3doDGtg4ga2Q2U/wQ/Vmy7X1kDq2N Mhe/OfHHOh7PfRZ5Km1q160ek4hgJRQ17GWWtNh6JRQ0Mh2oFa+WAhpFZIYHpbmkQi52 ymQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9sdvt0SCvD2QSOMHtz/9igRF47GFOyS9Q4ZZZNZ/yIc=; b=B8RJLJ/jL8j4yQrjMAU0hJJYGkEcvo1JE1yBZiuz7Z0O3o7OCH4m67KI9nXUmj7MbB FW91eTz5YkH6Q+kLSxCFFvKSHHfXe7X079HhoGhANeayVMi18KX+iHIif4Wv7aYpkSSO e8Bw/bg9LWdKAWV+vGwMqz+m47RDuNzELeBIwXdgtOzToJUCo/kQWbQQhaHCGX0/lLsR 51nmWRpVP1HbHNS3RMVL6IE800zO9oAVFlSzfC20t1lI/RoMzy3Z9/EXWb+z+1rAJCLV rzlDzOjvXeB0Vm7LTvrlwCBQxl/XVQ7uN3bS3Q7pYYktPOAS2le9Ys9zGPYlxL6eLQpt XyuQ== X-Gm-Message-State: AOAM530+kGX4XhAip/IwuMLVKNPUbDXdzM+cfzs10jT0Op2FjggpcPMM Tp8z36TJkJm9wQ8lkluAy+E= X-Google-Smtp-Source: ABdhPJxoA/J60/Lo8PZcxUMLjVYU4ba3ALv5iSM4fySF7//Ep/pQkBSZFoDaUba4qeLgtO7iyB0JVQ== X-Received: by 2002:a17:902:eaca:b0:148:c78e:3064 with SMTP id p10-20020a170902eaca00b00148c78e3064mr52573116pld.53.1641352134727; Tue, 04 Jan 2022 19:08:54 -0800 (PST) Received: from pek-vx-bsp2.wrs.com (unknown-176-192.windriver.com. [147.11.176.192]) by smtp.gmail.com with ESMTPSA id t191sm36206889pgd.3.2022.01.04.19.08.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jan 2022 19:08:54 -0800 (PST) From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RESEND PATCH v3 2/7] target/riscv: machine: Add debug state description Date: Wed, 5 Jan 2022 11:08:39 +0800 Message-Id: <20220105030844.780642-3-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220105030844.780642-1-bmeng.cn@gmail.com> References: <20220105030844.780642-1-bmeng.cn@gmail.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102a (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x102a.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Alistair Francis Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Add a subsection to machine.c to migrate debug CSR state. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- (no changes since v2) Changes in v2: - new patch: add debug state description target/riscv/machine.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/target/riscv/machine.c b/target/riscv/machine.c index ad8248ebfd..25aa3b38f7 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -164,6 +164,38 @@ static const VMStateDescription vmstate_pointermasking = { } }; +static bool debug_needed(void *opaque) +{ + RISCVCPU *cpu = opaque; + CPURISCVState *env = &cpu->env; + + return riscv_feature(env, RISCV_FEATURE_DEBUG); +} + +static const VMStateDescription vmstate_debug_type2 = { + .name = "cpu/debug/type2", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINTTL(mcontrol, trigger_type2_t), + VMSTATE_UINTTL(maddress, trigger_type2_t), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_debug = { + .name = "cpu/debug", + .version_id = 1, + .minimum_version_id = 1, + .needed = debug_needed, + .fields = (VMStateField[]) { + VMSTATE_UINTTL(env.trigger_cur, RISCVCPU), + VMSTATE_STRUCT_ARRAY(env.trigger_type2, RISCVCPU, TRIGGER_TYPE2_NUM, + 0, vmstate_debug_type2, trigger_type2_t), + VMSTATE_END_OF_LIST() + } +}; + const VMStateDescription vmstate_riscv_cpu = { .name = "cpu", .version_id = 3, @@ -218,6 +250,7 @@ const VMStateDescription vmstate_riscv_cpu = { &vmstate_hyper, &vmstate_vector, &vmstate_pointermasking, + &vmstate_debug, NULL } }; From patchwork Wed Jan 5 03:08:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 12704005 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E3AB7C433F5 for ; Wed, 5 Jan 2022 03:20:13 +0000 (UTC) Received: from localhost ([::1]:56946 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n4wqS-0002jP-L9 for qemu-devel@archiver.kernel.org; Tue, 04 Jan 2022 22:20:12 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60506) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n4wfr-0007Zg-Px; Tue, 04 Jan 2022 22:09:15 -0500 Received: from [2607:f8b0:4864:20::633] (port=46746 helo=mail-pl1-x633.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n4wfb-0001xL-4n; Tue, 04 Jan 2022 22:09:15 -0500 Received: by mail-pl1-x633.google.com with SMTP id w7so27833460plp.13; Tue, 04 Jan 2022 19:08:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eOAJlfpeviuZxpZ870fiG0a+l02uIRJcq4Xs27O408E=; b=XidnIAcDnn8cTOGGXL0/IJzkIh+umffhd618+yNwZxysB3sf6r0PRi3JlKdHFNawqT 6i8r7PTH/nTtVR9TFVur06C8Hmau9/I67v06XXjSJaIOIOIO+CSv+LbTY2rvegq0pz6d 6TYNjl/txy1vJ1hnSAlRON4U3vV9H3aAdaExMs38kBhv8eFCUZ+D2CZXgjYcZUZ4UUbe 1FZY6Xo9KbSEBXxJ+90+ZwVpWkvRB7lXqPnxEm4SHgLrYCSdvgfylOOV9U88hZMB+rXY 9Vm9VhU4D/SWjhpVHcl+iN9iT4XIzfHOlxeEh+bHivMi2fTiWhfUgj65CfABsQ5099vx zJBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eOAJlfpeviuZxpZ870fiG0a+l02uIRJcq4Xs27O408E=; b=22LR5O4QoXWpBH7gGNiHQ5j4K0UJjQcCYgTbF36d/FJMFwSoY7rmz+IC7lzGe871yN pccPON0xnIaLXI0mcRAINZTgTWwSdus7DYwyN4w8gx4fLBk2pCLWZ2ooAa1+7dhwvMms 4NvcpTZyj8AGMGEaES5hq4UP5EfkDcPoBEFjvm/NCR02Xu/YYdYstSeVLn5I0a4FdfVi ie0da7e7oVMZrfpPpeEvWi+WDG0dPRA9tiHvdXzBUL9kaWDmZGht9L3r4bhQV8xXJiSw Tq5m7uxDpam1TjKF5hZQzjv6QbG1GxNM+BMXBF/smj8wgU2GHCGqmoZ9WRCmrS9Iy3L4 Fu0g== X-Gm-Message-State: AOAM531hGgbzQnPy337HWM3auZLPobnGIfDQs2ebti43JmFDDwGpSK2t mDkdUKk5qocCZzJfkCqmg7I= X-Google-Smtp-Source: ABdhPJxPqIgeiyLs6eat/aVkPC7pFVGFAR3d6sIbdR3GvzY+iMwjb166L7A/QELLilZKo1Hvl6tr9A== X-Received: by 2002:a17:90b:3143:: with SMTP id ip3mr1730931pjb.58.1641352137580; Tue, 04 Jan 2022 19:08:57 -0800 (PST) Received: from pek-vx-bsp2.wrs.com (unknown-176-192.windriver.com. [147.11.176.192]) by smtp.gmail.com with ESMTPSA id t191sm36206889pgd.3.2022.01.04.19.08.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jan 2022 19:08:57 -0800 (PST) From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RESEND PATCH v3 3/7] target/riscv: debug: Implement debug related TCGCPUOps Date: Wed, 5 Jan 2022 11:08:40 +0800 Message-Id: <20220105030844.780642-4-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220105030844.780642-1-bmeng.cn@gmail.com> References: <20220105030844.780642-1-bmeng.cn@gmail.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::633 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=bmeng.cn@gmail.com; helo=mail-pl1-x633.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Alistair Francis Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Implement .debug_excp_handler, .debug_check_{breakpoint, watchpoint} TCGCPUOps and hook them into riscv_tcg_ops. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- (no changes since v2) Changes in v2: - use 0 instead of GETPC() target/riscv/debug.h | 4 +++ target/riscv/cpu.c | 3 ++ target/riscv/debug.c | 75 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 82 insertions(+) diff --git a/target/riscv/debug.h b/target/riscv/debug.h index 0a3fda6c72..d0f63e2414 100644 --- a/target/riscv/debug.h +++ b/target/riscv/debug.h @@ -105,4 +105,8 @@ void tselect_csr_write(CPURISCVState *env, target_ulong val); target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index); void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val); +void riscv_cpu_debug_excp_handler(CPUState *cs); +bool riscv_cpu_debug_check_breakpoint(CPUState *cs); +bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); + #endif /* RISCV_DEBUG_H */ diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6ef3314bce..3aa07bc019 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -705,6 +705,9 @@ static const struct TCGCPUOps riscv_tcg_ops = { .do_interrupt = riscv_cpu_do_interrupt, .do_transaction_failed = riscv_cpu_do_transaction_failed, .do_unaligned_access = riscv_cpu_do_unaligned_access, + .debug_excp_handler = riscv_cpu_debug_excp_handler, + .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, + .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, #endif /* !CONFIG_USER_ONLY */ }; diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 530e030007..7760c4611f 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -337,3 +337,78 @@ void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val) return write_func(env, env->trigger_cur, tdata_index, val); } + +void riscv_cpu_debug_excp_handler(CPUState *cs) +{ + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + + if (cs->watchpoint_hit) { + if (cs->watchpoint_hit->flags & BP_CPU) { + cs->watchpoint_hit = NULL; + riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, 0); + } + } else { + if (cpu_breakpoint_test(cs, env->pc, BP_CPU)) { + riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, 0); + } + } +} + +bool riscv_cpu_debug_check_breakpoint(CPUState *cs) +{ + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + CPUBreakpoint *bp; + target_ulong ctrl; + target_ulong pc; + int i; + + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { + for (i = 0; i < TRIGGER_TYPE2_NUM; i++) { + ctrl = env->trigger_type2[i].mcontrol; + pc = env->trigger_type2[i].maddress; + + if ((ctrl & TYPE2_EXEC) && (bp->pc == pc)) { + /* check U/S/M bit against current privilege level */ + if ((ctrl >> 3) & BIT(env->priv)) { + return true; + } + } + } + } + + return false; +} + +bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) +{ + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + target_ulong ctrl; + target_ulong addr; + int flags; + int i; + + for (i = 0; i < TRIGGER_TYPE2_NUM; i++) { + ctrl = env->trigger_type2[i].mcontrol; + addr = env->trigger_type2[i].maddress; + flags = 0; + + if (ctrl & TYPE2_LOAD) { + flags |= BP_MEM_READ; + } + if (ctrl & TYPE2_STORE) { + flags |= BP_MEM_WRITE; + } + + if ((wp->flags & flags) && (wp->vaddr == addr)) { + /* check U/S/M bit against current privilege level */ + if ((ctrl >> 3) & BIT(env->priv)) { + return true; + } + } + } + + return false; +} From patchwork Wed Jan 5 03:08:41 2022 Content-Type: text/plain; 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[147.11.176.192]) by smtp.gmail.com with ESMTPSA id t191sm36206889pgd.3.2022.01.04.19.08.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jan 2022 19:09:00 -0800 (PST) From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RESEND PATCH v3 4/7] target/riscv: cpu: Add a config option for native debug Date: Wed, 5 Jan 2022 11:08:41 +0800 Message-Id: <20220105030844.780642-5-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220105030844.780642-1-bmeng.cn@gmail.com> References: <20220105030844.780642-1-bmeng.cn@gmail.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1034 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x1034.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Alistair Francis Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Add a config option to enable support for native M-mode debug. This is disabled by default and can be enabled with 'debug=true'. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- (no changes since v2) Changes in v2: - change the config option to 'disabled' by default target/riscv/cpu.h | 2 ++ target/riscv/cpu.c | 5 +++++ 2 files changed, 7 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0f3b3a4219..35445bbc86 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -75,6 +75,7 @@ enum { RISCV_FEATURE_MMU, RISCV_FEATURE_PMP, RISCV_FEATURE_EPMP, + RISCV_FEATURE_DEBUG, RISCV_FEATURE_MISA }; @@ -332,6 +333,7 @@ struct RISCVCPU { bool mmu; bool pmp; bool epmp; + bool debug; uint64_t resetvec; } cfg; }; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3aa07bc019..d36c31ce9a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -448,6 +448,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } } + if (cpu->cfg.debug) { + set_feature(env, RISCV_FEATURE_DEBUG); + } + set_resetvec(env, cpu->cfg.resetvec); /* Validate that MISA_MXL is set properly. */ @@ -634,6 +638,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), + DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, false), DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), From patchwork Wed Jan 5 03:08:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 12704002 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ABC4CC433F5 for ; Wed, 5 Jan 2022 03:16:08 +0000 (UTC) Received: from localhost ([::1]:50442 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n4wmV-0006ZQ-EK for qemu-devel@archiver.kernel.org; Tue, 04 Jan 2022 22:16:07 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60456) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n4wfj-0007Mb-BY; Tue, 04 Jan 2022 22:09:07 -0500 Received: from [2607:f8b0:4864:20::102e] (port=53820 helo=mail-pj1-x102e.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n4wfg-0001yJ-Fv; Tue, 04 Jan 2022 22:09:05 -0500 Received: by mail-pj1-x102e.google.com with SMTP id m13so466754pji.3; Tue, 04 Jan 2022 19:09:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fwTz88tSj2yC6sh3Uadzhxd84PIM0JrnBO97AFjz0So=; b=iVx67tHs3ljy60HweEa/rtTxJen1Cs4z8G7U+9gnSrvUdReHd7ff3HmbvfkPZAa23z C0Svp6IVfIM9pf5WVajM5S03MAMOrso1OuvV+DKaRInompnTyrcYg6xCOZy4E+SxMfk7 fljK1ZwlrvJh/Yj2vgMEhYoN4CfTcOpxwllInTMZpqi6Nr/1/jL932RxqKbcdmPbVYJx cAGnSsQ1gYlU0H9FXzqMkH8Ld7jwYmlUUiL9slY+2ozgzeJLdaxvvrCVHtu8ed06ZIfZ +3Y5F6BQAX6IOL8AWDOZoNh1Cw6tG4sZOGiePXFwxSUS/yIcodlUl64lHHVvyQli3x2X X0Dg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fwTz88tSj2yC6sh3Uadzhxd84PIM0JrnBO97AFjz0So=; b=gWgWEaXQo9FKnD/0NrnWJ/M5ZCgJcfnaDuMdQbbPPtDkUioS5klTvg2C82N6QXkReP iwj4nONoniAAjaWmk6f+62w1XqDSSG/lSJ2lCrwIJ+Nhf98c/BQD6VM4Mxxd9knHICh1 hH+4FfZmkbliQPiKy7byMizw+dP9JAckJ/7gix8gmyVIwsS8eypSmvFgmA3NiaIMWUEK AyocucoGTioy6+Q7qSKg0eWyutF9zSd6E0Aw8VyFO6Hl1MZWehwTC4W6Aeyo9bzvkpO7 dFKwqpT0YHsrR25YcActqYRL6PVHNa3Ec595W7HLMMM47qWnbQfYgoRCNLidT4W2JxGh 6MDg== X-Gm-Message-State: AOAM533DP8sPhqikR1EXVzJGxai9QkzMizwKfGnIT6/QBfF+j6WFuFJg 27Hu69PzLWHluFAKblq5esQ= X-Google-Smtp-Source: ABdhPJwAgQrrlwKOkTkXw1hpYFlyTGKqOk3sKYnpC5mQl2dvd+F0zCw/O0egNbbDgmjKbz3ypoys0w== X-Received: by 2002:a17:90a:7e8a:: with SMTP id j10mr1720882pjl.13.1641352142956; Tue, 04 Jan 2022 19:09:02 -0800 (PST) Received: from pek-vx-bsp2.wrs.com (unknown-176-192.windriver.com. [147.11.176.192]) by smtp.gmail.com with ESMTPSA id t191sm36206889pgd.3.2022.01.04.19.09.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jan 2022 19:09:02 -0800 (PST) From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RESEND PATCH v3 5/7] target/riscv: csr: Hook debug CSR read/write Date: Wed, 5 Jan 2022 11:08:42 +0800 Message-Id: <20220105030844.780642-6-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220105030844.780642-1-bmeng.cn@gmail.com> References: <20220105030844.780642-1-bmeng.cn@gmail.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102e (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x102e.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng This adds debug CSR read/write support to the RISC-V CSR RW table. Signed-off-by: Bin Meng --- Changes in v3: - add riscv_trigger_init(), moved from patch #1 to this patch target/riscv/debug.h | 2 ++ target/riscv/cpu.c | 6 +++++ target/riscv/csr.c | 57 ++++++++++++++++++++++++++++++++++++++++++++ target/riscv/debug.c | 27 +++++++++++++++++++++ 4 files changed, 92 insertions(+) diff --git a/target/riscv/debug.h b/target/riscv/debug.h index d0f63e2414..f4da2db35d 100644 --- a/target/riscv/debug.h +++ b/target/riscv/debug.h @@ -109,4 +109,6 @@ void riscv_cpu_debug_excp_handler(CPUState *cs); bool riscv_cpu_debug_check_breakpoint(CPUState *cs); bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); +void riscv_trigger_init(CPURISCVState *env); + #endif /* RISCV_DEBUG_H */ diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d36c31ce9a..17dcc3c14f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -575,6 +575,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) riscv_cpu_register_gdb_regs_for_features(cs); +#ifndef CONFIG_USER_ONLY + if (riscv_feature(env, RISCV_FEATURE_DEBUG)) { + riscv_trigger_init(env); + } +#endif + qemu_init_vcpu(cs); cpu_reset(cs); diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 146447eac5..189b9cc8c6 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -220,6 +220,15 @@ static RISCVException epmp(CPURISCVState *env, int csrno) return RISCV_EXCP_ILLEGAL_INST; } + +static RISCVException debug(CPURISCVState *env, int csrno) +{ + if (riscv_feature(env, RISCV_FEATURE_DEBUG)) { + return RISCV_EXCP_NONE; + } + + return RISCV_EXCP_ILLEGAL_INST; +} #endif /* User Floating-Point CSRs */ @@ -1464,6 +1473,48 @@ static RISCVException write_pmpaddr(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } +static RISCVException read_tselect(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val = tselect_csr_read(env); + return RISCV_EXCP_NONE; +} + +static RISCVException write_tselect(CPURISCVState *env, int csrno, + target_ulong val) +{ + tselect_csr_write(env, val); + return RISCV_EXCP_NONE; +} + +static RISCVException read_tdata(CPURISCVState *env, int csrno, + target_ulong *val) +{ + /* return 0 in tdata1 to end the trigger enumeration */ + if (env->trigger_cur >= TRIGGER_NUM && csrno == CSR_TDATA1) { + *val = 0; + return RISCV_EXCP_NONE; + } + + if (!tdata_available(env, csrno - CSR_TDATA1)) { + return RISCV_EXCP_ILLEGAL_INST; + } + + *val = tdata_csr_read(env, csrno - CSR_TDATA1); + return RISCV_EXCP_NONE; +} + +static RISCVException write_tdata(CPURISCVState *env, int csrno, + target_ulong val) +{ + if (!tdata_available(env, csrno - CSR_TDATA1)) { + return RISCV_EXCP_ILLEGAL_INST; + } + + tdata_csr_write(env, csrno - CSR_TDATA1, val); + return RISCV_EXCP_NONE; +} + /* * Functions to access Pointer Masking feature registers * We have to check if current priv lvl could modify @@ -1962,6 +2013,12 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_PMPADDR14] = { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr }, [CSR_PMPADDR15] = { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr }, + /* Debug CSRs */ + [CSR_TSELECT] = { "tselect", debug, read_tselect, write_tselect }, + [CSR_TDATA1] = { "tdata1", debug, read_tdata, write_tdata }, + [CSR_TDATA2] = { "tdata2", debug, read_tdata, write_tdata }, + [CSR_TDATA3] = { "tdata3", debug, read_tdata, write_tdata }, + /* User Pointer Masking */ [CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte }, [CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask, write_upmmask }, diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 7760c4611f..041a0d3a89 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -412,3 +412,30 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) return false; } + +void riscv_trigger_init(CPURISCVState *env) +{ + target_ulong type2 = trigger_type(env, TRIGGER_TYPE_AD_MATCH); + int i; + + /* type 2 triggers */ + for (i = 0; i < TRIGGER_TYPE2_NUM; i++) { + /* + * type = TRIGGER_TYPE_AD_MATCH + * dmode = 0 (both debug and M-mode can write tdata) + * maskmax = 0 (unimplemented, always 0) + * sizehi = 0 (match against any size, RV64 only) + * hit = 0 (unimplemented, always 0) + * select = 0 (always 0, perform match on address) + * timing = 0 (always 0, trigger before instruction) + * sizelo = 0 (match against any size) + * action = 0 (always 0, raise a breakpoint exception) + * chain = 0 (unimplemented, always 0) + * match = 0 (always 0, when any compare value equals tdata2) + */ + env->trigger_type2[i].mcontrol = type2; + env->trigger_type2[i].maddress = 0; + env->trigger_type2[i].bp = NULL; + env->trigger_type2[i].wp = NULL; + } +} From patchwork Wed Jan 5 03:08:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 12704009 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C03A5C433EF for ; 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[147.11.176.192]) by smtp.gmail.com with ESMTPSA id t191sm36206889pgd.3.2022.01.04.19.09.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jan 2022 19:09:05 -0800 (PST) From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RESEND PATCH v3 6/7] target/riscv: cpu: Enable native debug feature Date: Wed, 5 Jan 2022 11:08:43 +0800 Message-Id: <20220105030844.780642-7-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220105030844.780642-1-bmeng.cn@gmail.com> References: <20220105030844.780642-1-bmeng.cn@gmail.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102d (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x102d.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Turn on native debug feature by default for all CPUs. Signed-off-by: Bin Meng --- Changes in v3: - enable debug feature by default for all CPUs target/riscv/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 17dcc3c14f..17444b458f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -644,7 +644,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), - DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, false), + DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), From patchwork Wed Jan 5 03:08:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 12704010 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ACF16C433EF for ; Wed, 5 Jan 2022 03:31:41 +0000 (UTC) Received: from localhost ([::1]:42028 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n4x1Y-0003re-KO for qemu-devel@archiver.kernel.org; Tue, 04 Jan 2022 22:31:40 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60496) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n4wfp-0007Xc-Tl; Tue, 04 Jan 2022 22:09:13 -0500 Received: from [2607:f8b0:4864:20::1031] (port=37735 helo=mail-pj1-x1031.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n4wfm-0001yr-IX; Tue, 04 Jan 2022 22:09:12 -0500 Received: by mail-pj1-x1031.google.com with SMTP id y16-20020a17090a6c9000b001b13ffaa625so1990196pjj.2; Tue, 04 Jan 2022 19:09:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=k03hqsrN3r2DAcpcEZo3Qmaha1XCoOaXcqqhAGM9cU0=; b=Tr9AjbeEaky53mDQSY0wD7+6h8s3i+xcQR7q9E3hepQL6Q7pL5tNXGKinC7KDbwgSI 0mKdLmmkpimmq84uOQwnbgjB43s0WLB26s6jyUZT0uCW/IGhVU78BHIATYbp2wxB1EaE jzHrZw8nS1zxg9dIdhLXsfFwV+nYxoPEdI7EjyNwkJObS76zDvr6LtqKNBtd0Sqy/QQo /hgrU4L2V75iaL9ueHy35RTTZC7Yd7ql6dM+pm2G7mdd8IpFzBSyFaqn+5l1krWba1t0 eKyeRVXGr6SrFoQ7E9XwvTyb1w825QdUpPi0ffYod94efzTxX2py4iF/ULxYJqL+LuuW biZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=k03hqsrN3r2DAcpcEZo3Qmaha1XCoOaXcqqhAGM9cU0=; b=bRkcVEHlt5W+84u5a7jorcUxGmnaybNMAC0fdqHv7BP/n5tDCyE5k0aghupXFruRqN nncC7vMdcIDkbNlazsxloNlWlSPbZXMo8Mdlqk68rX4yTxfAS5BlK4bol5YG0DibWjjB J2bv4fdGvDP+ksIciiKRucAFJUg1sAiLoY5+iEFHQVtk79IMhTUT7NXXqeYgD/vrP262 QzYpetoYO7e/O/IhA+AVDcMHcxxZ0Nu/dzdwUqEfgaFljs+vpC2d+i22V7xjoPwKYfcO g8pjRSf+KL4u8ZN7f4KN8j/xX8r0u0DkbOt8bkZoFBWMJmhPNVirkRqR4/WoZAy12dpI fqgQ== X-Gm-Message-State: AOAM53069sYk69BbFnWevm/Q1uDB5fdZFj9pdY1N1EjHicXDuN8K7sFJ 3pByUI5Yxuo9ISe5BTfFe70= X-Google-Smtp-Source: ABdhPJwc3QNQFKCJX/Ztbmrulq67knl8h6bBIESHheRutsnwxXXBDjCGXdwjBU7Le1ciJjIvjVKxvg== X-Received: by 2002:a17:90b:4017:: with SMTP id ie23mr1702040pjb.109.1641352149224; Tue, 04 Jan 2022 19:09:09 -0800 (PST) Received: from pek-vx-bsp2.wrs.com (unknown-176-192.windriver.com. [147.11.176.192]) by smtp.gmail.com with ESMTPSA id t191sm36206889pgd.3.2022.01.04.19.09.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jan 2022 19:09:08 -0800 (PST) From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RESEND PATCH v3 7/7] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint() Date: Wed, 5 Jan 2022 11:08:44 +0800 Message-Id: <20220105030844.780642-8-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220105030844.780642-1-bmeng.cn@gmail.com> References: <20220105030844.780642-1-bmeng.cn@gmail.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1031 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x1031.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Bin Meng , Richard Henderson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng This is now used by RISC-V as well. Update the comments. Signed-off-by: Bin Meng Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- (no changes since v1) include/hw/core/tcg-cpu-ops.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index e13898553a..f98671ff32 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -90,6 +90,7 @@ struct TCGCPUOps { /** * @debug_check_watchpoint: return true if the architectural * watchpoint whose address has matched should really fire, used by ARM + * and RISC-V */ bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);