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[198.145.64.163]) by smtp.gmail.com with ESMTPSA id k9sm23343pgr.47.2022.01.07.15.27.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jan 2022 15:27:48 -0800 (PST) From: Kees Cook To: Will Deacon Cc: Kees Cook , Peter Zijlstra , Boqun Feng , Catalin Marinas , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-hardening@vger.kernel.org Subject: [PATCH] arm64: atomics: Dereference matching size Date: Fri, 7 Jan 2022 15:27:46 -0800 Message-Id: <20220107232746.1540130-1-keescook@chromium.org> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3016; h=from:subject; bh=47ond1j5oGNg2bOUtQPmTXc41W+OJBUy48YiocxEN4U=; b=owEBbQKS/ZANAwAKAYly9N/cbcAmAcsmYgBh2MxxvccpCaBRI64wFu4HGOYd1RAGYXBxjWnsjXy5 R2rn/yGJAjMEAAEKAB0WIQSlw/aPIp3WD3I+bhOJcvTf3G3AJgUCYdjMcQAKCRCJcvTf3G3AJryvD/ 9sp7vs3pCbVfOzxQ7kLuD+kKELqKNUVCexpGQpaRgthUhlpLMkl4o/uCUdhMl/8vFmoj+trO/gg2ri U2nAztuCZRepyX55YXnD9oP9a91Lj0yUuEC+QBdFqEpzf4vZpWtuzSlVSdvCs0m687FxhhDoOAGrRb DwQeZsnpHSHKCYSr4TXVqXWN/+sU/QjOYShyGXirFcDyJc2oiqfmfwtTcIfjqHHJmWVh2g5bszWkca JJ+8tfXnb25k5CfBP6CX32ltb2OfTUZA5k6PGODdLQoGyR/wstI5izT3Nj6K2CJBLcxiMoxYCzk+jw M1rj0lO4940pou6msREP+yejU4zsqF6asUmFTSDEzr8gSRVyB0ucovrkAwwcd5NA//o2VloyJEgOLz Ie7sP0j0Zo1VAzOGCPOmASBHEGLRHi6yqC9bAsdLLUNCcAArW0M8XKyTptmjQKf3O7nCKh4DrDqyiy KmACPWY5vP6j3FdK94iaYm7JO9QoGbpSLAZ3LQ9L0eOcCmpv29zvGQ7pP2UGCIofiq9my6R+y6WbED 3t0uJb6Ssgy8Y8XVwmakBhmIvA8D2zUuQi80BZcdAO33q9bZDLTSnnoUTDdIESOPH7FqR+9dacRaUF IDbsjMCLcE1xplrSEuaxzIdXt0/59nKJdJaAPohTH59jmZE3FOkOeKr6arEw== X-Developer-Key: i=keescook@chromium.org; a=openpgp; fpr=A5C3F68F229DD60F723E6E138972F4DFDC6DC026 Precedence: bulk List-ID: X-Mailing-List: linux-hardening@vger.kernel.org When building with -Warray-bounds (which is desired to be enabled globally), the following warning is generated: In file included from ./arch/arm64/include/asm/lse.h:16, from ./arch/arm64/include/asm/cmpxchg.h:14, from ./arch/arm64/include/asm/atomic.h:16, from ./include/linux/atomic.h:7, from ./include/asm-generic/bitops/atomic.h:5, from ./arch/arm64/include/asm/bitops.h:25, from ./include/linux/bitops.h:33, from ./include/linux/kernel.h:22, from kernel/printk/printk.c:22: ./arch/arm64/include/asm/atomic_lse.h:247:9: warning: array subscript 'long unsigned int[0]' is partly outside array bounds of 'atomic_t[1]' [-Warray-bounds] 247 | asm volatile( \ | ^~~ ./arch/arm64/include/asm/atomic_lse.h:266:1: note: in expansion of macro '__CMPXCHG_CASE' 266 | __CMPXCHG_CASE(w, , acq_, 32, a, "memory") | ^~~~~~~~~~~~~~ kernel/printk/printk.c:3606:17: note: while referencing 'printk_cpulock_owner' 3606 | static atomic_t printk_cpulock_owner = ATOMIC_INIT(-1); | ^~~~~~~~~~~~~~~~~~~~ This is due to the compiler seeing an unsigned long * cast against something (atomic_t) that is int sized. Replace the cast with the matching size cast. This results in no change in binary output. Cc: Will Deacon Cc: Peter Zijlstra Cc: Boqun Feng Cc: Catalin Marinas Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Kees Cook Acked-by: Ard Biesheuvel Acked-by: Mark Rutland --- arch/arm64/include/asm/atomic_lse.h | 2 +- arch/arm64/include/asm/cmpxchg.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/atomic_lse.h b/arch/arm64/include/asm/atomic_lse.h index d955ade5df7c..5d460f6b7675 100644 --- a/arch/arm64/include/asm/atomic_lse.h +++ b/arch/arm64/include/asm/atomic_lse.h @@ -249,7 +249,7 @@ __lse__cmpxchg_case_##name##sz(volatile void *ptr, \ " mov %" #w "[tmp], %" #w "[old]\n" \ " cas" #mb #sfx "\t%" #w "[tmp], %" #w "[new], %[v]\n" \ " mov %" #w "[ret], %" #w "[tmp]" \ - : [ret] "+r" (x0), [v] "+Q" (*(unsigned long *)ptr), \ + : [ret] "+r" (x0), [v] "+Q" (*(u##sz *)ptr), \ [tmp] "=&r" (tmp) \ : [old] "r" (x1), [new] "r" (x2) \ : cl); \ diff --git a/arch/arm64/include/asm/cmpxchg.h b/arch/arm64/include/asm/cmpxchg.h index f9bef42c1411..497acf134d99 100644 --- a/arch/arm64/include/asm/cmpxchg.h +++ b/arch/arm64/include/asm/cmpxchg.h @@ -243,7 +243,7 @@ static inline void __cmpwait_case_##sz(volatile void *ptr, \ " cbnz %" #w "[tmp], 1f\n" \ " wfe\n" \ "1:" \ - : [tmp] "=&r" (tmp), [v] "+Q" (*(unsigned long *)ptr) \ + : [tmp] "=&r" (tmp), [v] "+Q" (*(u##sz *)ptr) \ : [val] "r" (val)); \ }