From patchwork Fri Jan 7 23:53:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brian Norris X-Patchwork-Id: 12707137 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7C27AC4332F for ; Fri, 7 Jan 2022 23:54:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=EnqpASP7w/S1PQp9nXUYw9WJgbBx6j5sKO3B+ToFLB4=; b=qWohKiMrA/oyez Fml1HaIREUDFEh1mZ1yQhtc6b+h/lpajxAB4F1Xb79zHIhC5GK6qnRfYl6RYd+MjlxVWb7xQmv3sF ekMQR3C4AE7nkBi+v5gWL80gL1HNvnV1p4UZHhVh0VkfVRAov4NXmbpqrWmvv7TVssu4CEqiVG0c6 9RcLk+A9uTBZf93T9aAxij+ga0Iymuhji00YqnMaDRsiDkMlx9QOF0YHSeQQvgqXYetCljELPtZvp EK770Wl9YHGP587RLLQNL10/rXcNlxvvDKwheybiGITAqFxah2UJKQMtGhDYBrEhra83kaX4kgW6K xq/uF69XVOyKeasph3Rw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n5z3V-005YyV-DM; Fri, 07 Jan 2022 23:53:57 +0000 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1n5z36-005Yje-Cy for linux-rockchip@lists.infradead.org; Fri, 07 Jan 2022 23:53:36 +0000 Received: by mail-pj1-x1034.google.com with SMTP id oa15so5643052pjb.4 for ; Fri, 07 Jan 2022 15:53:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lpsTogdRjDeDJloO2kyX0qqWiyNV3lg2YpOQTAMx7l8=; b=lKPJVa0IFdFHs/i+zvVYxD425wd3c2s7LtqrcZK9g/929bdiTa/P17fu/StVbzL5U/ AeGqGNXBCHkIx7njE804v8nEY+/ICVhHExna2x/+3L8TAsJ8EZiidXUNnVPFMZ7fLi/O geeiPGcq61Oi4yTo4Wx/dZTt4uFCMIP7D54bc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lpsTogdRjDeDJloO2kyX0qqWiyNV3lg2YpOQTAMx7l8=; b=oyPKxRzSOjTGdalGslyoiYY1AJ7gK/7quRVj2KkY6ENqnZUnStjHaCGYA89qBOzS98 F7e4EOWZXJqBsfJQ14ogZOxB8zpSpAJ9GkTV1J912uc7Fx02G0u4/hHG/dfGljH/CNoQ Z0rV+ZGKT8cR7ETJNin/J/LNSBzrcaKs9X4BO8B8z4dlMs0rBPb2Je5mPT6qy3wN7oyZ eWOR4fkDlgcJfH4LDhHcitX8sONbByVA/1ItQAO20EKquMoEmbWMX0qFXZPVq05ccNAj 1XEXh94jm2wOyNhebHW8jScxLTszql7CfC3enhIdGVAQEUaNqzH6u8LbS8hNH796Oz8H 4+Ow== X-Gm-Message-State: AOAM532ZvGDF3oW6339yvKQnqPA8ROK8tKjLDZSyLCrfSTmnkDWc7Szs 1ehI4UCyUuVn3vxC3l7tu1Gs0w== X-Google-Smtp-Source: ABdhPJzMJ9SDIkdNkKcc/h7iuwp64taJWRgmoWP7OHOhhkDRzpaVgNe/jw5quX0PnQtkDPeSfJBW0w== X-Received: by 2002:a17:902:b110:b0:14a:197:dfea with SMTP id q16-20020a170902b11000b0014a0197dfeamr6437725plr.142.1641599611397; Fri, 07 Jan 2022 15:53:31 -0800 (PST) Received: from localhost ([2620:15c:202:201:db:1c60:693f:c24e]) by smtp.gmail.com with UTF8SMTPSA id t7sm47571pfj.168.2022.01.07.15.53.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 07 Jan 2022 15:53:31 -0800 (PST) From: Brian Norris To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring Cc: Heiko Stuebner , linux-arm-kernel@lists.infradead.org, Lin Huang , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-pm@vger.kernel.org, Derek Basehore , linux-kernel@vger.kernel.org, Brian Norris Subject: [PATCH 01/10] dt-bindings: devfreq: rk3399_dmc: Convert to YAML Date: Fri, 7 Jan 2022 15:53:11 -0800 Message-Id: <20220107155215.1.I875ab8f28c5155a7d2f103316191954d4b07ac13@changeid> X-Mailer: git-send-email 2.34.1.575.g55b058a8bb-goog In-Reply-To: <20220107235320.965497-1-briannorris@chromium.org> References: <20220107235320.965497-1-briannorris@chromium.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220107_155332_483644_7F274054 X-CRM114-Status: GOOD ( 25.40 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org I want to add, deprecate, and bugfix some properties, as well as add the first users. This is easier with a proper schema. The transformation is mostly straightforward, plus a few notable tweaks: * Renamed rockchip,dram_speed_bin to rockchip,ddr3_speed_bin. The driver code and the example matched, but the description was different. I went with the implementation. * Drop upthreshold and downdifferential properties from the example. These were undocumented (so, wouldn't pass validation), but were representing software properties (governor tweaks). I drop them from the driver in subsequent patches. * Rename clock from pclk_ddr_mon to dmc_clk. The driver, DT example, and all downstream users matched -- the binding definition was the exception. Anyway, "dmc_clk" is a more appropriately generic name. Signed-off-by: Brian Norris --- .../bindings/devfreq/rk3399_dmc.txt | 212 ------------- .../bindings/devfreq/rk3399_dmc.yaml | 297 ++++++++++++++++++ 2 files changed, 297 insertions(+), 212 deletions(-) delete mode 100644 Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt create mode 100644 Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt deleted file mode 100644 index 58fc8a6cebc7..000000000000 --- a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt +++ /dev/null @@ -1,212 +0,0 @@ -* Rockchip rk3399 DMC (Dynamic Memory Controller) device - -Required properties: -- compatible: Must be "rockchip,rk3399-dmc". -- devfreq-events: Node to get DDR loading, Refer to - Documentation/devicetree/bindings/devfreq/event/ - rockchip-dfi.txt -- clocks: Phandles for clock specified in "clock-names" property -- clock-names : The name of clock used by the DFI, must be - "pclk_ddr_mon"; -- operating-points-v2: Refer to Documentation/devicetree/bindings/opp/opp-v2.yaml - for details. -- center-supply: DMC supply node. -- status: Marks the node enabled/disabled. -- rockchip,pmu: Phandle to the syscon managing the "PMU general register - files". - -Optional properties: -- interrupts: The CPU interrupt number. The interrupt specifier - format depends on the interrupt controller. - It should be a DCF interrupt. When DDR DVFS finishes - a DCF interrupt is triggered. -- rockchip,pmu: Phandle to the syscon managing the "PMU general register - files". - -Following properties relate to DDR timing: - -- rockchip,dram_speed_bin : Value reference include/dt-bindings/clock/rk3399-ddr.h, - it selects the DDR3 cl-trp-trcd type. It must be - set according to "Speed Bin" in DDR3 datasheet, - DO NOT use a smaller "Speed Bin" than specified - for the DDR3 being used. - -- rockchip,pd_idle : Configure the PD_IDLE value. Defines the - power-down idle period in which memories are - placed into power-down mode if bus is idle - for PD_IDLE DFI clock cycles. - -- rockchip,sr_idle : Configure the SR_IDLE value. Defines the - self-refresh idle period in which memories are - placed into self-refresh mode if bus is idle - for SR_IDLE * 1024 DFI clock cycles (DFI - clocks freq is half of DRAM clock), default - value is "0". - -- rockchip,sr_mc_gate_idle : Defines the memory self-refresh and controller - clock gating idle period. Memories are placed - into self-refresh mode and memory controller - clock arg gating started if bus is idle for - sr_mc_gate_idle*1024 DFI clock cycles. - -- rockchip,srpd_lite_idle : Defines the self-refresh power down idle - period in which memories are placed into - self-refresh power down mode if bus is idle - for srpd_lite_idle * 1024 DFI clock cycles. - This parameter is for LPDDR4 only. - -- rockchip,standby_idle : Defines the standby idle period in which - memories are placed into self-refresh mode. - The controller, pi, PHY and DRAM clock will - be gated if bus is idle for standby_idle * DFI - clock cycles. - -- rockchip,dram_dll_dis_freq : Defines the DDR3 DLL bypass frequency in MHz. - When DDR frequency is less than DRAM_DLL_DISB_FREQ, - DDR3 DLL will be bypassed. Note: if DLL was bypassed, - the odt will also stop working. - -- rockchip,phy_dll_dis_freq : Defines the PHY dll bypass frequency in - MHz (Mega Hz). When DDR frequency is less than - DRAM_DLL_DISB_FREQ, PHY DLL will be bypassed. - Note: PHY DLL and PHY ODT are independent. - -- rockchip,ddr3_odt_dis_freq : When the DRAM type is DDR3, this parameter defines - the ODT disable frequency in MHz (Mega Hz). - when the DDR frequency is less then ddr3_odt_dis_freq, - the ODT on the DRAM side and controller side are - both disabled. - -- rockchip,ddr3_drv : When the DRAM type is DDR3, this parameter defines - the DRAM side driver strength in ohms. Default - value is 40. - -- rockchip,ddr3_odt : When the DRAM type is DDR3, this parameter defines - the DRAM side ODT strength in ohms. Default value - is 120. - -- rockchip,phy_ddr3_ca_drv : When the DRAM type is DDR3, this parameter defines - the phy side CA line (incluing command line, - address line and clock line) driver strength. - Default value is 40. - -- rockchip,phy_ddr3_dq_drv : When the DRAM type is DDR3, this parameter defines - the PHY side DQ line (including DQS/DQ/DM line) - driver strength. Default value is 40. - -- rockchip,phy_ddr3_odt : When the DRAM type is DDR3, this parameter defines - the PHY side ODT strength. Default value is 240. - -- rockchip,lpddr3_odt_dis_freq : When the DRAM type is LPDDR3, this parameter defines - then ODT disable frequency in MHz (Mega Hz). - When DDR frequency is less then ddr3_odt_dis_freq, - the ODT on the DRAM side and controller side are - both disabled. - -- rockchip,lpddr3_drv : When the DRAM type is LPDDR3, this parameter defines - the DRAM side driver strength in ohms. Default - value is 34. - -- rockchip,lpddr3_odt : When the DRAM type is LPDDR3, this parameter defines - the DRAM side ODT strength in ohms. Default value - is 240. - -- rockchip,phy_lpddr3_ca_drv : When the DRAM type is LPDDR3, this parameter defines - the PHY side CA line (including command line, - address line and clock line) driver strength. - Default value is 40. - -- rockchip,phy_lpddr3_dq_drv : When the DRAM type is LPDDR3, this parameter defines - the PHY side DQ line (including DQS/DQ/DM line) - driver strength. Default value is 40. - -- rockchip,phy_lpddr3_odt : When dram type is LPDDR3, this parameter define - the phy side odt strength, default value is 240. - -- rockchip,lpddr4_odt_dis_freq : When the DRAM type is LPDDR4, this parameter - defines the ODT disable frequency in - MHz (Mega Hz). When the DDR frequency is less then - ddr3_odt_dis_freq, the ODT on the DRAM side and - controller side are both disabled. - -- rockchip,lpddr4_drv : When the DRAM type is LPDDR4, this parameter defines - the DRAM side driver strength in ohms. Default - value is 60. - -- rockchip,lpddr4_dq_odt : When the DRAM type is LPDDR4, this parameter defines - the DRAM side ODT on DQS/DQ line strength in ohms. - Default value is 40. - -- rockchip,lpddr4_ca_odt : When the DRAM type is LPDDR4, this parameter defines - the DRAM side ODT on CA line strength in ohms. - Default value is 40. - -- rockchip,phy_lpddr4_ca_drv : When the DRAM type is LPDDR4, this parameter defines - the PHY side CA line (including command address - line) driver strength. Default value is 40. - -- rockchip,phy_lpddr4_ck_cs_drv : When the DRAM type is LPDDR4, this parameter defines - the PHY side clock line and CS line driver - strength. Default value is 80. - -- rockchip,phy_lpddr4_dq_drv : When the DRAM type is LPDDR4, this parameter defines - the PHY side DQ line (including DQS/DQ/DM line) - driver strength. Default value is 80. - -- rockchip,phy_lpddr4_odt : When the DRAM type is LPDDR4, this parameter defines - the PHY side ODT strength. Default value is 60. - -Example: - dmc_opp_table: dmc_opp_table { - compatible = "operating-points-v2"; - - opp00 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <900000>; - }; - opp01 { - opp-hz = /bits/ 64 <666000000>; - opp-microvolt = <900000>; - }; - }; - - dmc: dmc { - compatible = "rockchip,rk3399-dmc"; - devfreq-events = <&dfi>; - interrupts = ; - clocks = <&cru SCLK_DDRC>; - clock-names = "dmc_clk"; - operating-points-v2 = <&dmc_opp_table>; - center-supply = <&ppvar_centerlogic>; - upthreshold = <15>; - downdifferential = <10>; - rockchip,ddr3_speed_bin = <21>; - rockchip,pd_idle = <0x40>; - rockchip,sr_idle = <0x2>; - rockchip,sr_mc_gate_idle = <0x3>; - rockchip,srpd_lite_idle = <0x4>; - rockchip,standby_idle = <0x2000>; - rockchip,dram_dll_dis_freq = <300>; - rockchip,phy_dll_dis_freq = <125>; - rockchip,auto_pd_dis_freq = <666>; - rockchip,ddr3_odt_dis_freq = <333>; - rockchip,ddr3_drv = <40>; - rockchip,ddr3_odt = <120>; - rockchip,phy_ddr3_ca_drv = <40>; - rockchip,phy_ddr3_dq_drv = <40>; - rockchip,phy_ddr3_odt = <240>; - rockchip,lpddr3_odt_dis_freq = <333>; - rockchip,lpddr3_drv = <34>; - rockchip,lpddr3_odt = <240>; - rockchip,phy_lpddr3_ca_drv = <40>; - rockchip,phy_lpddr3_dq_drv = <40>; - rockchip,phy_lpddr3_odt = <240>; - rockchip,lpddr4_odt_dis_freq = <333>; - rockchip,lpddr4_drv = <60>; - rockchip,lpddr4_dq_odt = <40>; - rockchip,lpddr4_ca_odt = <40>; - rockchip,phy_lpddr4_ca_drv = <40>; - rockchip,phy_lpddr4_ck_cs_drv = <80>; - rockchip,phy_lpddr4_dq_drv = <80>; - rockchip,phy_lpddr4_odt = <60>; - }; diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml new file mode 100644 index 000000000000..f12f34d93378 --- /dev/null +++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml @@ -0,0 +1,297 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# %YAML 1.2 +--- +$id: http://devicetree.org/schemas/devfreq/rk3399_dmc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip rk3399 DMC (Dynamic Memory Controller) device + +maintainers: + - Brian Norris + +required: + - compatible + - devfreq-events + - clocks + - clock-names + - operating-points-v2 + - center-supply + +properties: + compatible: + enum: + - rockchip,rk3399-dmc + + devfreq-events: + $ref: /schemas/types.yaml#/definitions/phandle-array + minItems: 1 + description: + Node to get DDR loading. Refer to + Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt. + + clocks: + maxItems: 1 + + clock-names: + items: + - const: dmc_clk + + operating-points-v2: + description: + Refer to Documentation/devicetree/bindings/opp/opp-v2.yaml for details. + + center-supply: + description: + DMC regulator supply. + + rockchip,pmu: + $ref: /schemas/types.yaml#/definitions/phandle + maxItems: 1 + description: + Phandle to the syscon managing the "PMU general register files". + + interrupts: + maxItems: 1 + description: + The CPU interrupt number. The interrupt specifier format depends on the + interrupt controller. It should be a DCF interrupt. When DDR DVFS + finishes a DCF interrupt is triggered. + + rockchip,ddr3_speed_bin: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + For values, reference include/dt-bindings/clock/rk3399-ddr.h. Selects the + DDR3 cl-trp-trcd type. It must be set according to "Speed Bin" in DDR3 + datasheet; DO NOT use a smaller "Speed Bin" than specified for the DDR3 + being used. + + rockchip,pd_idle: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Configure the PD_IDLE value. Defines the power-down idle period in which + memories are placed into power-down mode if bus is idle for PD_IDLE DFI + clock cycles. + + rockchip,sr_idle: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Configure the SR_IDLE value. Defines the self-refresh idle period in + which memories are placed into self-refresh mode if bus is idle for + SR_IDLE * 1024 DFI clock cycles (DFI clocks freq is half of DRAM clock), + default value is "0". + + rockchip,sr_mc_gate_idle: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Defines the memory self-refresh and controller clock gating idle period. + Memories are placed into self-refresh mode and memory controller clock + arg gating started if bus is idle for sr_mc_gate_idle*1024 DFI clock + cycles. + + rockchip,srpd_lite_idle: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Defines the self-refresh power down idle period in which memories are + placed into self-refresh power down mode if bus is idle for + srpd_lite_idle * 1024 DFI clock cycles. This parameter is for LPDDR4 + only. + + rockchip,standby_idle: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Defines the standby idle period in which memories are placed into + self-refresh mode. The controller, pi, PHY and DRAM clock will be gated + if bus is idle for standby_idle * DFI clock cycles. + + rockchip,dram_dll_dis_freq: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Defines the DDR3 DLL bypass frequency in MHz. When DDR frequency is less + than DRAM_DLL_DISB_FREQ, DDR3 DLL will be bypassed. + Note: if DLL was bypassed, the odt will also stop working. + + rockchip,phy_dll_dis_freq: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Defines the PHY dll bypass frequency in MHz (Mega Hz). When DDR frequency + is less than DRAM_DLL_DISB_FREQ, PHY DLL will be bypassed. + Note: PHY DLL and PHY ODT are independent. + + rockchip,auto_pd_dis_freq: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Defines the auto PD disable frequency in MHz. + + rockchip,ddr3_odt_dis_freq: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is DDR3, this parameter defines the ODT disable + frequency in MHz (Mega Hz). When the DDR frequency is less then + ddr3_odt_dis_freq, the ODT on the DRAM side and controller side are both + disabled. + + rockchip,ddr3_drv: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is DDR3, this parameter defines the DRAM side drive + strength in ohms. Default value is 40. + + rockchip,ddr3_odt: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is DDR3, this parameter defines the DRAM side ODT + strength in ohms. Default value is 120. + + rockchip,phy_ddr3_ca_drv: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is DDR3, this parameter defines the phy side CA line + (incluing command line, address line and clock line) drive strength. + Default value is 40. + + rockchip,phy_ddr3_dq_drv: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is DDR3, this parameter defines the PHY side DQ line + (including DQS/DQ/DM line) drive strength. Default value is 40. + + rockchip,phy_ddr3_odt: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is DDR3, this parameter defines the PHY side ODT + strength. Default value is 240. + + rockchip,lpddr3_odt_dis_freq: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is LPDDR3, this parameter defines then ODT disable + frequency in MHz (Mega Hz). When DDR frequency is less then + ddr3_odt_dis_freq, the ODT on the DRAM side and controller side are both + disabled. + + rockchip,lpddr3_drv: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is LPDDR3, this parameter defines the DRAM side drive + strength in ohms. Default value is 34. + + rockchip,lpddr3_odt: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is LPDDR3, this parameter defines the DRAM side ODT + strength in ohms. Default value is 240. + + rockchip,phy_lpddr3_ca_drv: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is LPDDR3, this parameter defines the PHY side CA line + (including command line, address line and clock line) drive strength. + Default value is 40. + + rockchip,phy_lpddr3_dq_drv: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is LPDDR3, this parameter defines the PHY side DQ line + (including DQS/DQ/DM line) drive strength. Default value is 40. + + rockchip,phy_lpddr3_odt: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When dram type is LPDDR3, this parameter define the phy side odt + strength, default value is 240. + + rockchip,lpddr4_odt_dis_freq: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is LPDDR4, this parameter defines the ODT disable + frequency in MHz (Mega Hz). When the DDR frequency is less then + ddr3_odt_dis_freq, the ODT on the DRAM side and controller side are both + disabled. + + rockchip,lpddr4_drv: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is LPDDR4, this parameter defines the DRAM side drive + strength in ohms. Default value is 60. + + rockchip,lpddr4_dq_odt: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on + DQS/DQ line strength in ohms. Default value is 40. + + rockchip,lpddr4_ca_odt: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on + CA line strength in ohms. Default value is 40. + + rockchip,phy_lpddr4_ca_drv: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is LPDDR4, this parameter defines the PHY side CA line + (including command address line) drive strength. Default value is 40. + + rockchip,phy_lpddr4_ck_cs_drv: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is LPDDR4, this parameter defines the PHY side clock + line and CS line drive strength. Default value is 80. + + rockchip,phy_lpddr4_dq_drv: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is LPDDR4, this parameter defines the PHY side DQ line + (including DQS/DQ/DM line) drive strength. Default value is 80. + + rockchip,phy_lpddr4_odt: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is LPDDR4, this parameter defines the PHY side ODT + strength. Default value is 60. + +additionalProperties: false + +examples: + - | + #include + #include + dmc: dmc { + compatible = "rockchip,rk3399-dmc"; + devfreq-events = <&dfi>; + rockchip,pmu = <&pmu>; + interrupts = ; + clocks = <&cru SCLK_DDRC>; + clock-names = "dmc_clk"; + operating-points-v2 = <&dmc_opp_table>; + center-supply = <&ppvar_centerlogic>; + rockchip,ddr3_speed_bin = <21>; + rockchip,pd_idle = <0x40>; + rockchip,sr_idle = <0x2>; + rockchip,sr_mc_gate_idle = <0x3>; + rockchip,srpd_lite_idle = <0x4>; + rockchip,standby_idle = <0x2000>; + rockchip,dram_dll_dis_freq = <300>; + rockchip,phy_dll_dis_freq = <125>; + rockchip,auto_pd_dis_freq = <666>; + rockchip,ddr3_odt_dis_freq = <333>; + rockchip,ddr3_drv = <40>; + rockchip,ddr3_odt = <120>; + rockchip,phy_ddr3_ca_drv = <40>; + rockchip,phy_ddr3_dq_drv = <40>; + rockchip,phy_ddr3_odt = <240>; + rockchip,lpddr3_odt_dis_freq = <333>; + rockchip,lpddr3_drv = <34>; + rockchip,lpddr3_odt = <240>; + rockchip,phy_lpddr3_ca_drv = <40>; + rockchip,phy_lpddr3_dq_drv = <40>; + rockchip,phy_lpddr3_odt = <240>; + rockchip,lpddr4_odt_dis_freq = <333>; + rockchip,lpddr4_drv = <60>; + rockchip,lpddr4_dq_odt = <40>; + rockchip,lpddr4_ca_odt = <40>; + rockchip,phy_lpddr4_ca_drv = <40>; + rockchip,phy_lpddr4_ck_cs_drv = <80>; + rockchip,phy_lpddr4_dq_drv = <80>; + rockchip,phy_lpddr4_odt = <60>; + }; From patchwork Fri Jan 7 23:53:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brian Norris X-Patchwork-Id: 12707138 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 70B96C433EF for ; Fri, 7 Jan 2022 23:54:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=xbL1v5pDLATLclWATJ7dVQE+5zSAFQgvn+o5OefBCnI=; b=bDy7zhj8jS4oIe Mjheo1KTg6nVqhWOep80gYqPE2laA5y/6DclhhBe5Wp09z9iY23KebAyqH+op4PF+VWkproxL+6Gn 62clHt/0lU+Oz0UUAo5jXfL+LKDgByNmnKKA7tmxtd8Oz89e0/m1UUj1i13q1YabGV7xJ4himxLSr zieYinhfatEI6NTHTCJxMYGCw3hPz3N4rtAjV9WonSejB1iSobf3WmzSHX2mjOysHdLHFYeF9wuv0 GtiOq0rD8U6reqYRDGePNOHlkfYFapC0L5dYhJYwurtH4gg+vz4Z2R98khJZSNYT7Xk2tpAQF/yND oqTMdj+Db1rNCFrgS93w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n5z3j-005Z5Y-OE; Fri, 07 Jan 2022 23:54:11 +0000 Received: from mail-pg1-x532.google.com ([2607:f8b0:4864:20::532]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1n5z38-005Ykt-IO for linux-rockchip@lists.infradead.org; Fri, 07 Jan 2022 23:53:37 +0000 Received: by mail-pg1-x532.google.com with SMTP id v25so7029843pge.2 for ; Fri, 07 Jan 2022 15:53:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EC6Yy1tAZPwKkwKJYGHE/vqhf31r7sL2lK9QflxCMkc=; b=l6MDdTSWAeTxNGvEd93nFWHohs6kDg+tWO7s+yzY75uQRjE/BUZL1kjNK+KjgI9a9t aPx/i6Iaen1SS2wobC8fW5PqQBGs6sokNQFaN+A0zHsO5gxsScGMZ1kAu4i9Dn7irHmw FyyZCrIBRJwc3h2FllmUT1etPGBlGUa7w0YSk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EC6Yy1tAZPwKkwKJYGHE/vqhf31r7sL2lK9QflxCMkc=; b=Ny5IMfqG0cyEgnYkDgukdIR9J3f6kxC4gANEqJAoM1/6MPromgdIpPNHdMuUFs7Oif QSOLmpvDnLM4AnDBbVs2p48WrxX4n6m8OIqGOeDtKQT+ABj9A26dntHHt88HnCDLBSRm rUvhGALwwwULG/vg7dRmUImTFBoXQD8m2/ZT2EjCu9VHgtYhrzO4s0JM9d7HezjQG6wX Z+pWIlE/QDszcskTe5qwkKeafdynrvnU8S5VF1z5ohW5q/thH44k1ZK6Sxa5rerUPStu +AGWmi/aGlQFYc01zE11fYC7Uqsu/MHtWnLOLanM1jOLyAUgMUkcITKTscALY84u3hRV LsEQ== X-Gm-Message-State: AOAM530r6c4J1mGEitn30Dzgd4kuzSiG6ZKe+Q+ESYkBIL+9eU3FXdg8 O6wc5pAsD+J0n92ZuFRJxCf0Rg== X-Google-Smtp-Source: ABdhPJz/zuh06SfcYdI8C2pwHxKqrqYVX1iKu5qlgzfHoSrOLowcEYEFERoS9ljANAwquYdmLD+jnQ== X-Received: by 2002:aa7:9799:0:b0:4bd:49ce:8bb1 with SMTP id o25-20020aa79799000000b004bd49ce8bb1mr555903pfp.74.1641599613569; Fri, 07 Jan 2022 15:53:33 -0800 (PST) Received: from localhost ([2620:15c:202:201:db:1c60:693f:c24e]) by smtp.gmail.com with UTF8SMTPSA id s12sm43682pfk.220.2022.01.07.15.53.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 07 Jan 2022 15:53:33 -0800 (PST) From: Brian Norris To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring Cc: Heiko Stuebner , linux-arm-kernel@lists.infradead.org, Lin Huang , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-pm@vger.kernel.org, Derek Basehore , linux-kernel@vger.kernel.org, Brian Norris Subject: [PATCH 02/10] dt-bindings: devfreq: rk3399_dmc: Deprecate unused/redundant properties Date: Fri, 7 Jan 2022 15:53:12 -0800 Message-Id: <20220107155215.2.I5ba582cd678d34c03d647e5500db8e33b7524d66@changeid> X-Mailer: git-send-email 2.34.1.575.g55b058a8bb-goog In-Reply-To: <20220107235320.965497-1-briannorris@chromium.org> References: <20220107235320.965497-1-briannorris@chromium.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220107_155334_707960_50276F2A X-CRM114-Status: GOOD ( 12.19 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org These DRAM configuration properties are all handled in ARM Trusted Firmware (and have been since the early days of this SoC), and there are no in-tree users of the DMC binding yet. It's better to just defer to firmware instead of maintaining this large list of properties. There's also some confusion about units: many of these are specified in MHz, but the downstream users and driver code are treating them as Hz, I believe. Rather than straighten all that out, I just drop them. Signed-off-by: Brian Norris Reviewed-by: Rob Herring --- .../bindings/devfreq/rk3399_dmc.yaml | 42 +++++++++---------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml index f12f34d93378..6bb411dddb7b 100644 --- a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml +++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml @@ -58,6 +58,7 @@ properties: finishes a DCF interrupt is triggered. rockchip,ddr3_speed_bin: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: For values, reference include/dt-bindings/clock/rk3399-ddr.h. Selects the @@ -104,6 +105,7 @@ properties: if bus is idle for standby_idle * DFI clock cycles. rockchip,dram_dll_dis_freq: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: | Defines the DDR3 DLL bypass frequency in MHz. When DDR frequency is less @@ -111,6 +113,7 @@ properties: Note: if DLL was bypassed, the odt will also stop working. rockchip,phy_dll_dis_freq: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: | Defines the PHY dll bypass frequency in MHz (Mega Hz). When DDR frequency @@ -118,6 +121,7 @@ properties: Note: PHY DLL and PHY ODT are independent. rockchip,auto_pd_dis_freq: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: Defines the auto PD disable frequency in MHz. @@ -131,18 +135,21 @@ properties: disabled. rockchip,ddr3_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is DDR3, this parameter defines the DRAM side drive strength in ohms. Default value is 40. rockchip,ddr3_odt: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is DDR3, this parameter defines the DRAM side ODT strength in ohms. Default value is 120. rockchip,phy_ddr3_ca_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is DDR3, this parameter defines the phy side CA line @@ -150,12 +157,14 @@ properties: Default value is 40. rockchip,phy_ddr3_dq_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is DDR3, this parameter defines the PHY side DQ line (including DQS/DQ/DM line) drive strength. Default value is 40. rockchip,phy_ddr3_odt: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is DDR3, this parameter defines the PHY side ODT @@ -170,18 +179,21 @@ properties: disabled. rockchip,lpddr3_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR3, this parameter defines the DRAM side drive strength in ohms. Default value is 34. rockchip,lpddr3_odt: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR3, this parameter defines the DRAM side ODT strength in ohms. Default value is 240. rockchip,phy_lpddr3_ca_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR3, this parameter defines the PHY side CA line @@ -189,12 +201,14 @@ properties: Default value is 40. rockchip,phy_lpddr3_dq_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR3, this parameter defines the PHY side DQ line (including DQS/DQ/DM line) drive strength. Default value is 40. rockchip,phy_lpddr3_odt: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When dram type is LPDDR3, this parameter define the phy side odt @@ -209,42 +223,49 @@ properties: disabled. rockchip,lpddr4_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR4, this parameter defines the DRAM side drive strength in ohms. Default value is 60. rockchip,lpddr4_dq_odt: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on DQS/DQ line strength in ohms. Default value is 40. rockchip,lpddr4_ca_odt: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on CA line strength in ohms. Default value is 40. rockchip,phy_lpddr4_ca_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR4, this parameter defines the PHY side CA line (including command address line) drive strength. Default value is 40. rockchip,phy_lpddr4_ck_cs_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR4, this parameter defines the PHY side clock line and CS line drive strength. Default value is 80. rockchip,phy_lpddr4_dq_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR4, this parameter defines the PHY side DQ line (including DQS/DQ/DM line) drive strength. Default value is 80. rockchip,phy_lpddr4_odt: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR4, this parameter defines the PHY side ODT @@ -265,33 +286,12 @@ examples: clock-names = "dmc_clk"; operating-points-v2 = <&dmc_opp_table>; center-supply = <&ppvar_centerlogic>; - rockchip,ddr3_speed_bin = <21>; rockchip,pd_idle = <0x40>; rockchip,sr_idle = <0x2>; rockchip,sr_mc_gate_idle = <0x3>; rockchip,srpd_lite_idle = <0x4>; rockchip,standby_idle = <0x2000>; - rockchip,dram_dll_dis_freq = <300>; - rockchip,phy_dll_dis_freq = <125>; - rockchip,auto_pd_dis_freq = <666>; rockchip,ddr3_odt_dis_freq = <333>; - rockchip,ddr3_drv = <40>; - rockchip,ddr3_odt = <120>; - rockchip,phy_ddr3_ca_drv = <40>; - rockchip,phy_ddr3_dq_drv = <40>; - rockchip,phy_ddr3_odt = <240>; rockchip,lpddr3_odt_dis_freq = <333>; - rockchip,lpddr3_drv = <34>; - rockchip,lpddr3_odt = <240>; - rockchip,phy_lpddr3_ca_drv = <40>; - rockchip,phy_lpddr3_dq_drv = <40>; - rockchip,phy_lpddr3_odt = <240>; rockchip,lpddr4_odt_dis_freq = <333>; - rockchip,lpddr4_drv = <60>; - rockchip,lpddr4_dq_odt = <40>; - rockchip,lpddr4_ca_odt = <40>; - rockchip,phy_lpddr4_ca_drv = <40>; - rockchip,phy_lpddr4_ck_cs_drv = <80>; - rockchip,phy_lpddr4_dq_drv = <80>; - rockchip,phy_lpddr4_odt = <60>; }; From patchwork Fri Jan 7 23:53:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brian Norris X-Patchwork-Id: 12707140 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DACB4C433F5 for ; Fri, 7 Jan 2022 23:54:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=FYj4vgy0WAnMf2ix7dGlzg7fP54TZty1m1k9KO87/x0=; b=Q5Tw49oE7/gl9J bU42eyNrddPhIfihHYQV420cuBMo5MzxNepjVd3X2E6hOIIwdE6YjRPUlVyNzyjZ8gkV9BrZ8uu5S kgQCRI3vdmBEHYM88QQJFJ0RWVBlolA4sfMJMvY2wxTOdENhVBJx6/2To20G0WWUd7R2Wly6GRjTN ps21mOGTR03BRYVP5R0CUtIq74yg9TKGw0+3UK/1e8YGGIBXWkSEkgS3Z3K5gDAZCvlkjcMEK8ePE 1waF579vb8DgtmwILhr61VfKuTuYRVxtDCerdZKD0sL1PVe144TVJ1u6/+CsnQ3MbfqrYRerX9I2m MefEbmq1B2ukL8vPamBw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n5z4I-005ZNx-Lt; Fri, 07 Jan 2022 23:54:46 +0000 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1n5z3A-005Ylh-GQ for linux-rockchip@lists.infradead.org; Fri, 07 Jan 2022 23:53:39 +0000 Received: by mail-pf1-x432.google.com with SMTP id s15so6519204pfk.6 for ; Fri, 07 Jan 2022 15:53:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1suEizrMvGP6y4nHTdrMBY8Z/9qqxnd7nZ3EYSd9DWU=; b=A+81pitwf4PEew7O1yF2AVQH4hy4VElUERoh0lH7dAt9CYBcL5IVQGqu0ocnzLyfVa rawQWefahy0AB4l3rc/7qRAZyb/cZwqfd34NwkWymbSSwBzlg0JFQVn87jFdU+jctCp6 uw+4WcHpToLNhSrZp/fpUJf/SS87jmUaM3cG4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1suEizrMvGP6y4nHTdrMBY8Z/9qqxnd7nZ3EYSd9DWU=; b=coqiwBtz8xo107Obc78TRStSTe3zMAxKiZ0BGTJyFfMEEIhzqqI45fimX0d+YnmH2z vJnIYVNWsJV0zyDK+gZTKtfIa8A/v8i6v6xqzvTOhj15x9HUwSWfFs8rNzMTWOpV5kKg NJLUH0WAb4iiYe+jqXm6L9KoeV5aGhlSiV3E7RCplWFfHu2PKdmRm0lve7jOZJptwXrA +wOY3l1wKv2MKcfOUrlvMGxWFWQJ3MM9zV3ZhOREsIzFYcDLBOtqu/S29bqgb9NIoBbY dJnEENUOvAoRHSUo40cWDGiPE/VUSAPD62WTZ1O4GApzUtAlh2M/wQfSbHsUl4j4OYXj OV5g== X-Gm-Message-State: AOAM5312SaRDTYkjw3ZN+52PnVqo4nw5sqOQM+zZEJ+7T5ini9qU18BO /X/XrmY71bmUYc5t3Ek+wgQ+Tg== X-Google-Smtp-Source: ABdhPJxds0fohPEqyTNsNoc8pOn/hFT5GWdvhrX8aPm+onPVVfGwVlzNPUBPKSNLxkkrxA9o00AxHg== X-Received: by 2002:a63:7d0a:: with SMTP id y10mr4111864pgc.533.1641599615668; Fri, 07 Jan 2022 15:53:35 -0800 (PST) Received: from localhost ([2620:15c:202:201:db:1c60:693f:c24e]) by smtp.gmail.com with UTF8SMTPSA id h15sm59512pfq.0.2022.01.07.15.53.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 07 Jan 2022 15:53:35 -0800 (PST) From: Brian Norris To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring Cc: Heiko Stuebner , linux-arm-kernel@lists.infradead.org, Lin Huang , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-pm@vger.kernel.org, Derek Basehore , linux-kernel@vger.kernel.org, Brian Norris Subject: [PATCH 03/10] dt-bindings: devfreq: rk3399_dmc: Fix Hz units Date: Fri, 7 Jan 2022 15:53:13 -0800 Message-Id: <20220107155215.3.I9341269171c114d0e04e41d48037fd32816e2d8c@changeid> X-Mailer: git-send-email 2.34.1.575.g55b058a8bb-goog In-Reply-To: <20220107235320.965497-1-briannorris@chromium.org> References: <20220107235320.965497-1-briannorris@chromium.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220107_155336_661251_71CB9955 X-CRM114-Status: GOOD ( 13.09 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org The driver and all downstream device trees [1] are using Hz units, but the document claims MHz. DRAM frequency for these systems can't possibly exceed 2^32-1 Hz, so the choice of unit doesn't really matter than much. Rather than add unnecessary risk in getting the units wrong, let's just go with the unofficial convention and make the docs match reality. A sub-1MHz frequency is extremely unlikely, so include a minimum in the schema, to help catch anybody who might have believed this was MHz. [1] And notably, also those trying to upstream them: https://lore.kernel.org/lkml/20210308233858.24741-3-daniel.lezcano@linaro.org/ Signed-off-by: Brian Norris Reviewed-by: Rob Herring --- .../bindings/devfreq/rk3399_dmc.yaml | 24 +++++++++---------- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml index 6bb411dddb7b..2c871c57fd97 100644 --- a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml +++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml @@ -128,11 +128,11 @@ properties: rockchip,ddr3_odt_dis_freq: $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1000000 # In case anyone thought this was MHz. description: When the DRAM type is DDR3, this parameter defines the ODT disable - frequency in MHz (Mega Hz). When the DDR frequency is less then - ddr3_odt_dis_freq, the ODT on the DRAM side and controller side are both - disabled. + frequency in Hz. When the DDR frequency is less then ddr3_odt_dis_freq, + the ODT on the DRAM side and controller side are both disabled. rockchip,ddr3_drv: deprecated: true @@ -172,11 +172,11 @@ properties: rockchip,lpddr3_odt_dis_freq: $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1000000 # In case anyone thought this was MHz. description: When the DRAM type is LPDDR3, this parameter defines then ODT disable - frequency in MHz (Mega Hz). When DDR frequency is less then - ddr3_odt_dis_freq, the ODT on the DRAM side and controller side are both - disabled. + frequency in Hz. When DDR frequency is less then ddr3_odt_dis_freq, the + ODT on the DRAM side and controller side are both disabled. rockchip,lpddr3_drv: deprecated: true @@ -216,11 +216,11 @@ properties: rockchip,lpddr4_odt_dis_freq: $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1000000 # In case anyone thought this was MHz. description: When the DRAM type is LPDDR4, this parameter defines the ODT disable - frequency in MHz (Mega Hz). When the DDR frequency is less then - ddr3_odt_dis_freq, the ODT on the DRAM side and controller side are both - disabled. + frequency in Hz. When the DDR frequency is less then ddr3_odt_dis_freq, + the ODT on the DRAM side and controller side are both disabled. rockchip,lpddr4_drv: deprecated: true @@ -291,7 +291,7 @@ examples: rockchip,sr_mc_gate_idle = <0x3>; rockchip,srpd_lite_idle = <0x4>; rockchip,standby_idle = <0x2000>; - rockchip,ddr3_odt_dis_freq = <333>; - rockchip,lpddr3_odt_dis_freq = <333>; - rockchip,lpddr4_odt_dis_freq = <333>; + rockchip,ddr3_odt_dis_freq = <333000000>; + rockchip,lpddr3_odt_dis_freq = <333000000>; + rockchip,lpddr4_odt_dis_freq = <333000000>; }; From patchwork Fri Jan 7 23:53:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brian Norris X-Patchwork-Id: 12707139 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0139CC433EF for ; Fri, 7 Jan 2022 23:54:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=P6WEx68QeFtPGKxXHxOuesE5xCW8XfBdh5qOXe9US1w=; b=2ISUlIUkLt24px Sa3a8EVbS6KjOocpbqj0LOqAshnLHWUl/YN1h5vob3UzsqHyGcWvUDPVkyqHZwUqvT+SzgFIK5zMT 9+BsFohHhcCQXTq9uupnijUFmCUB+fvTckB1TkiVxJMPw7RX8y+HOZwBrGAP5ZLnj8auhuQV4AZxq u4+qhfX9772UeUgczMFxOJBwMBvAsZp+WvDJouipIdFxMOfsWkiLB50kpgzRdGyDWhud55iOa5pwo 171l+OEl504qa2B8apwd06Kd31Fy30WhtW7TujEL1kOHT9je69e3nLRb85tRNdfFAig1wxd8jQhvX a1+1Z3Z1H5A/TcGQwJhA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n5z4J-005ZOO-JM; Fri, 07 Jan 2022 23:54:47 +0000 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1n5z3C-005YnJ-HM for linux-rockchip@lists.infradead.org; Fri, 07 Jan 2022 23:53:40 +0000 Received: by mail-pj1-x1030.google.com with SMTP id iy13so6482076pjb.5 for ; Fri, 07 Jan 2022 15:53:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uqA2vTRTwCd5lb+1bpw59I8A4YOj+PxA4CFZWdTkSiE=; b=KjQjjOwC8d4WeVLXIzAl5ZiDLmf1td57rlGuw1GCTyOix4NbWz87jaIU3GPeaHkhs2 +aKtbG6eMTbXncBI8DqE362s9f/7hyyLlEFnDyCIssQVbVjfuNX3Ig4LPvwuuJx9CHy3 4H3ahd/fdtvy4tK0RwPpQ0oebhP89pSmGlBC0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uqA2vTRTwCd5lb+1bpw59I8A4YOj+PxA4CFZWdTkSiE=; b=uFM0Ixn3qAPNQXy6eJ17tC57fAaz5x7/Du+zuLASLp5HWWYUr6m9U2JpbpMA9Zr7Xk QN1DPAXwtaA7HYl9qvhmMOKsjLrzf17DtmVAmhG/A5qA9feqTMvJncj1bPRt+1BOjiZp 5YYb5ne2HJFIEbsCDVD7FhWTONjks32+3TMxR0XO9cQQgdTVmbTfRYRgXk4mHi7gEJLO CTspV5betBGAxXOpp90F92nq/fNkhEVGrwXtoxCEMrRmTqJzBkihosGcf4YqN9n6sVac 3RELDJUYeIaT3O0OdtfN/h6UMHXYar1gIhGl57Q0vTzGEWlaZfGGMnrhW26bNlBn2A5j /lUg== X-Gm-Message-State: AOAM531StaS+ip4/9PrK6Pmd68nsi+ybbK1aX4jpfkpf8z9b1zcvNo6f V2CJw24IzK64sOv9OS4/s7GhxQ== X-Google-Smtp-Source: ABdhPJwIGLUJ4870oxOMvvNEBPUvoGuIBVIO34djfW+MF+nHRtQ6skGcluLNSZvfeaLmcwPvyDn+Tw== X-Received: by 2002:a17:90a:df04:: with SMTP id gp4mr2131418pjb.148.1641599617740; Fri, 07 Jan 2022 15:53:37 -0800 (PST) Received: from localhost ([2620:15c:202:201:db:1c60:693f:c24e]) by smtp.gmail.com with UTF8SMTPSA id h19sm57446pfh.30.2022.01.07.15.53.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 07 Jan 2022 15:53:37 -0800 (PST) From: Brian Norris To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring Cc: Heiko Stuebner , linux-arm-kernel@lists.infradead.org, Lin Huang , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-pm@vger.kernel.org, Derek Basehore , linux-kernel@vger.kernel.org, Brian Norris Subject: [PATCH 04/10] dt-bindings: devfreq: rk3399_dmc: Add more disable-freq properties Date: Fri, 7 Jan 2022 15:53:14 -0800 Message-Id: <20220107155215.4.I382d4de737198ea52deb118c9bdc4d93d76e009e@changeid> X-Mailer: git-send-email 2.34.1.575.g55b058a8bb-goog In-Reply-To: <20220107235320.965497-1-briannorris@chromium.org> References: <20220107235320.965497-1-briannorris@chromium.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220107_155338_632014_53937217 X-CRM114-Status: GOOD ( 11.88 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org DDR DVFS tuning has found that several power-saving features don't have good tradeoffs at higher frequencies -- at higher frequencies, we'll see glitches or other errors. Provide tuning controls so these can be disabled at higher OPPs, and left active only at the lower ones. Signed-off-by: Brian Norris --- .../bindings/devfreq/rk3399_dmc.yaml | 42 +++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml index 2c871c57fd97..357d07c5a3df 100644 --- a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml +++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml @@ -271,6 +271,43 @@ properties: When the DRAM type is LPDDR4, this parameter defines the PHY side ODT strength. Default value is 60. + rockchip,pd_idle_dis_freq: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Defines the power-down idle disable frequency in Hz. When the DDR + frequency is greater than pd_idle_dis_freq, power-down idle is disabled. + See also rockchip,pd_idle. + + rockchip,sr_idle_dis_freq: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Defines the self-refresh idle disable frequency in Hz. When the DDR + frequency is greater than sr_idle_dis_freq, self-refresh idle is + disabled. See also rockchip,sr_idle. + + rockchip,sr_mc_gate_idle_dis_freq: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Defines the self-refresh and memory-controller clock gating disable + frequency in Hz. When the DDR frequency is greater than + sr_mc_gate_idle_dis_freq, the clock will not be gated when idle. See also + rockchip,sr_mc_gate_idle. + + rockchip,srpd_lite_idle_dis_freq: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Defines the self-refresh power down idle disable frequency in Hz. When + the DDR frequency is greater than srpd_lite_idle_dis_freq, memory will + not be placed into self-refresh power down mode when idle. See also + rockchip,srpd_lite_idle. + + rockchip,standby_idle_dis_freq: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Defines the standby idle disable frequency in Hz. When the DDR frequency + is greater than standby_idle_dis_freq, standby idle is disabled. See also + rockchip,standby_idle. + additionalProperties: false examples: @@ -294,4 +331,9 @@ examples: rockchip,ddr3_odt_dis_freq = <333000000>; rockchip,lpddr3_odt_dis_freq = <333000000>; rockchip,lpddr4_odt_dis_freq = <333000000>; + rockchip,pd_idle_dis_freq = <1000000000>; + rockchip,sr_idle_dis_freq = <1000000000>; + rockchip,sr_mc_gate_idle_dis_freq = <1000000000>; + rockchip,srpd_lite_idle_dis_freq = <0>; + rockchip,standby_idle_dis_freq = <928000000>; }; From patchwork Fri Jan 7 23:53:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brian Norris X-Patchwork-Id: 12707141 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1A619C433F5 for ; Fri, 7 Jan 2022 23:55:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=v2e877OM1dmaz4hEToqb1vA5149wJBvQN3bUq51Hkgw=; b=2mz2qacB6b/kIP ZylDT8rzGR6QFgrBbPbgArDLKnUAbWAYHt208ZAFUECLaiYK3XeIVnhgPV4TtDmbxJKk2P8YYvDKd H4SzdKsyrG/rnAHNZLCw43le/eGeheW3klAzmQ2JQVShBhKViZyxJgHAodXT57bvaKZMQJauOVakw ONCYuC4DZNyPtDuTUqKZ8vI8tbqhmSI58cT4oFcEd/J1zN2XR+vUQ6SBIEf2iI4HwC9ROUI+EM0av Zo1p5XqZuvXEsnvlz8Padizve+SqeUGSEpkJuBSNpv1SM6zAlk/oble3qqwxLcJ3qG4W74jAR34oN BG0YSIxQ7VSd5VKXMICQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n5z4k-005Zfe-G0; Fri, 07 Jan 2022 23:55:14 +0000 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1n5z3F-005Yoc-0D for linux-rockchip@lists.infradead.org; Fri, 07 Jan 2022 23:53:42 +0000 Received: by mail-pf1-x42a.google.com with SMTP id 196so6500038pfw.10 for ; Fri, 07 Jan 2022 15:53:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BwZYnZ40KbeJ7AlpMWe+FaFD9GCv+xkqOCr7TXF+b3A=; b=cq+rL39e2SuXbNV4R/NBEY/tbIQC2k7A03THZsAhtXI3Wkr8/JpilReV4Fghu8TgMh 1CPQXkneJkFGvUaCOvkxRZDzc9HZiFk6Z/hla3uQPk99FB914B4StlrYZfVj5SfSKuPS OYB+Ql1tjc1P7xattSY46D3sLwnAwQA49pMeA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BwZYnZ40KbeJ7AlpMWe+FaFD9GCv+xkqOCr7TXF+b3A=; b=orYVFB9aVgmFoN038TuPzaTEZlIhHK7WCm3fSzA2N66OAqNyL/Egk2oqYceYsWOAOz 6pdep6yJ0JyXoO7jIlht/9m9Ne18qxB+fc+lkQdc9JkcLjJFPHt0LNEQaEb/FpKerhbr A0ft5HgqNy3vsownJx5wEZsb7h8z8oXDHf+f7v5W2UYwCDEOMi4x3GYFRTkO6kshEkzC X2M+4DHTNtt7V3zdyHtMlALINroa6qWut9VjYQ+ecQcIzBu0ASSZd4j+ABjgBT5ZtYfK tcRPNPi+aODEetLPCSBHYUWPYqaBkPbUwAiMqA+YKKclOrGzQfNMS+yujn4TFIXI56VI TKfQ== X-Gm-Message-State: AOAM532626sG1FpkhUH2ZS2os932rce+rkbYiqZGdudeTSwezuzbyFY6 Z2LSx9HhNVEeB8K2ATIYX07grg== X-Google-Smtp-Source: ABdhPJwXb0FrFN8WR31ai2WKeI7DfmoehFLv8X/wr7YuQYumhseqi7xnA6sbbMiM/sFeYOdpRZa9iA== X-Received: by 2002:a63:914c:: with SMTP id l73mr3103999pge.471.1641599620106; Fri, 07 Jan 2022 15:53:40 -0800 (PST) Received: from localhost ([2620:15c:202:201:db:1c60:693f:c24e]) by smtp.gmail.com with UTF8SMTPSA id p16sm55372pfh.88.2022.01.07.15.53.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 07 Jan 2022 15:53:39 -0800 (PST) From: Brian Norris To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring Cc: Heiko Stuebner , linux-arm-kernel@lists.infradead.org, Lin Huang , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-pm@vger.kernel.org, Derek Basehore , linux-kernel@vger.kernel.org, Brian Norris Subject: [PATCH 05/10] PM / devfreq: rk3399_dmc: Drop undocumented ondemand DT props Date: Fri, 7 Jan 2022 15:53:15 -0800 Message-Id: <20220107155215.5.I4bd77eb751d5bfce8346bfed576bcacb28e4550f@changeid> X-Mailer: git-send-email 2.34.1.575.g55b058a8bb-goog In-Reply-To: <20220107235320.965497-1-briannorris@chromium.org> References: <20220107235320.965497-1-briannorris@chromium.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220107_155341_081592_BA4C397C X-CRM114-Status: GOOD ( 11.63 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org These properties are: * undocumented * directly representing software properties, not hardware properties * unused (no in-tree users, yet; this IP block has so far only been used in downstream kernels) Let's just stick the values that downstream users have been using directly in the driver and call it a day. Signed-off-by: Brian Norris --- drivers/devfreq/rk3399_dmc.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/devfreq/rk3399_dmc.c b/drivers/devfreq/rk3399_dmc.c index 293857ebfd75..e982862f6ac2 100644 --- a/drivers/devfreq/rk3399_dmc.c +++ b/drivers/devfreq/rk3399_dmc.c @@ -430,10 +430,8 @@ static int rk3399_dmcfreq_probe(struct platform_device *pdev) goto err_edev; } - of_property_read_u32(np, "upthreshold", - &data->ondemand_data.upthreshold); - of_property_read_u32(np, "downdifferential", - &data->ondemand_data.downdifferential); + data->ondemand_data.upthreshold = 25; + data->ondemand_data.downdifferential = 15; data->rate = clk_get_rate(data->dmc_clk); From patchwork Fri Jan 7 23:53:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brian Norris X-Patchwork-Id: 12707142 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4E547C433F5 for ; Fri, 7 Jan 2022 23:56:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=etQys2XLgmwqNn2IX9znU3/I+iBEEX7/yMqTFn+7+Co=; b=QhtcwwxEZRjWP4 uzl0Mupah2ane578GS5pU80PAlLDfCpARhU6Vv4RAna0YqQiKcrD/RZrDOpflHYfa09xZoZmvbbd+ UastbJKqEOoL00jWmGdq3WKRC0Bc1KnlM5W9SZiB7DrvCjT7hBP7vG8UrZsRyCHnMZ6oJawUWx8n9 evlQdHFYcb2Bk+hLz+6Mi3WCbYdvc9Rd+Y0BfeXK70s3YqwyujKRye0zQoyIxGU8W/uA18D2Jy8o1 dhNFjGYvIzRbvQvKIvxaYleDp2lHtZDk+mgBNBhE9ubHc0FZ8cqabEXZrI1iNOvptJ3GEHNUOa6wA +ZumhG1MWhC8/C9W4dkA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n5z5Z-005aB7-1R; Fri, 07 Jan 2022 23:56:05 +0000 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1n5z3H-005YqA-7t for linux-rockchip@lists.infradead.org; Fri, 07 Jan 2022 23:53:46 +0000 Received: by mail-pj1-x1029.google.com with SMTP id l10-20020a17090a384a00b001b22190e075so13799382pjf.3 for ; Fri, 07 Jan 2022 15:53:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fo7MtS17rkUvmbaM/Uvg709jlFSobNAPiAMJh0FigaM=; b=fSm7J0uiwb17KOSyzyl61f+8mwrl0o5hL7QEjeyMf7wS5AmQDhfBg9xblIB5W9moOJ 4DkkZ99h02NPOvtMt8kNaJpyUX7qzNJ4A5sGcVgS+fW5rXzix2v0ztiZfhC91pNL9haA pz1zbyFqf20YGMkR8dh0gFcF2EQXmzR0xWlVo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fo7MtS17rkUvmbaM/Uvg709jlFSobNAPiAMJh0FigaM=; b=A/ivh4pD69zv0jEVedQJ7BHtlGGrTwiUvhlSGHCSGpzuBr3pngvwq1YaJjv8GfAhcX Cci7KGSQKcajbcld9pw26FoFbRV+KQr5a93KyusTf63V4Lrak7o6k04SS8eFGV00iaaW C/fWA18FjeqiwGYLT/sU5y3jng3lkKKKh1earN1r6R8EFH4Fn8UM5SL/TjT4gob8Sin1 abzRco2LfXw3HPVocTMhjqSV8cum+POxOlmVJgLYcRolo0Uk4g0xAK0ouxNdTFTjHywO vDLYXhyoeFSGT+yusatm2KLZleXdOrhf/Bf9lT71QGiskf/cGYd3nUbNBEqQBIIqSlUN UNMQ== X-Gm-Message-State: AOAM532fy5jhL9tOxG6vcOACl21KmF3WevlD5vhJ4nmlDDHEgt8bSH7t BPX0xTfa5pqRPy7/ci1a78rtIw== X-Google-Smtp-Source: ABdhPJzb90L7hROlDUtE7Sn6Ih+ihkNKTqcbGYvSCEKak9WB1KlTMVy28l/ZxdhjcDndIARS2jNjCw== X-Received: by 2002:a17:90b:1d07:: with SMTP id on7mr18400843pjb.177.1641599622416; Fri, 07 Jan 2022 15:53:42 -0800 (PST) Received: from localhost ([2620:15c:202:201:db:1c60:693f:c24e]) by smtp.gmail.com with UTF8SMTPSA id c10sm45878pfl.200.2022.01.07.15.53.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 07 Jan 2022 15:53:41 -0800 (PST) From: Brian Norris To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring Cc: Heiko Stuebner , linux-arm-kernel@lists.infradead.org, Lin Huang , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-pm@vger.kernel.org, Derek Basehore , linux-kernel@vger.kernel.org, Brian Norris Subject: [PATCH 06/10] PM / devfreq: rk3399_dmc: Drop excess timing properties Date: Fri, 7 Jan 2022 15:53:16 -0800 Message-Id: <20220107155215.6.Ia0f7d6168a71ba4a4fd0519972a8dfd4c681fc25@changeid> X-Mailer: git-send-email 2.34.1.575.g55b058a8bb-goog In-Reply-To: <20220107235320.965497-1-briannorris@chromium.org> References: <20220107235320.965497-1-briannorris@chromium.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220107_155343_335624_B48B1127 X-CRM114-Status: GOOD ( 20.92 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org All of these properties are initialized by ARM Trusted Firmware, and have been since the early days of this chip. It's redundant (and possibly wrong) to do this here now. What's more, there seems to be some confusion about the units and some of the definitions of this timing struct: the DT docs say MHz for many of these, but downstream users were in Hz (and therefore, the ATF interface was Hz). Also, the in-driver usage for some of these (e.g., for comparing to target frequency) were in Hz too. So doubly wrong. We can avoid thinking about who got the right units by dropping the unnecessary code and properties. They are marked deprecated in the binding schema. Signed-off-by: Brian Norris --- drivers/devfreq/rk3399_dmc.c | 144 +++++++---------------------------- 1 file changed, 29 insertions(+), 115 deletions(-) diff --git a/drivers/devfreq/rk3399_dmc.c b/drivers/devfreq/rk3399_dmc.c index e982862f6ac2..8f447217303f 100644 --- a/drivers/devfreq/rk3399_dmc.c +++ b/drivers/devfreq/rk3399_dmc.c @@ -23,38 +23,6 @@ #include #include -struct dram_timing { - unsigned int ddr3_speed_bin; - unsigned int pd_idle; - unsigned int sr_idle; - unsigned int sr_mc_gate_idle; - unsigned int srpd_lite_idle; - unsigned int standby_idle; - unsigned int auto_pd_dis_freq; - unsigned int dram_dll_dis_freq; - unsigned int phy_dll_dis_freq; - unsigned int ddr3_odt_dis_freq; - unsigned int ddr3_drv; - unsigned int ddr3_odt; - unsigned int phy_ddr3_ca_drv; - unsigned int phy_ddr3_dq_drv; - unsigned int phy_ddr3_odt; - unsigned int lpddr3_odt_dis_freq; - unsigned int lpddr3_drv; - unsigned int lpddr3_odt; - unsigned int phy_lpddr3_ca_drv; - unsigned int phy_lpddr3_dq_drv; - unsigned int phy_lpddr3_odt; - unsigned int lpddr4_odt_dis_freq; - unsigned int lpddr4_drv; - unsigned int lpddr4_dq_odt; - unsigned int lpddr4_ca_odt; - unsigned int phy_lpddr4_ca_drv; - unsigned int phy_lpddr4_ck_cs_drv; - unsigned int phy_lpddr4_dq_drv; - unsigned int phy_lpddr4_odt; -}; - struct rk3399_dmcfreq { struct device *dev; struct devfreq *devfreq; @@ -62,13 +30,21 @@ struct rk3399_dmcfreq { struct clk *dmc_clk; struct devfreq_event_dev *edev; struct mutex lock; - struct dram_timing timing; struct regulator *vdd_center; struct regmap *regmap_pmu; unsigned long rate, target_rate; unsigned long volt, target_volt; unsigned int odt_dis_freq; int odt_pd_arg0, odt_pd_arg1; + + unsigned int pd_idle; + unsigned int sr_idle; + unsigned int sr_mc_gate_idle; + unsigned int srpd_lite_idle; + unsigned int standby_idle; + unsigned int ddr3_odt_dis_freq; + unsigned int lpddr3_odt_dis_freq; + unsigned int lpddr4_odt_dis_freq; }; static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq, @@ -238,69 +214,27 @@ static __maybe_unused int rk3399_dmcfreq_resume(struct device *dev) static SIMPLE_DEV_PM_OPS(rk3399_dmcfreq_pm, rk3399_dmcfreq_suspend, rk3399_dmcfreq_resume); -static int of_get_ddr_timings(struct dram_timing *timing, - struct device_node *np) +static int rk3399_dmcfreq_of_props(struct rk3399_dmcfreq *data, + struct device_node *np) { int ret = 0; - ret = of_property_read_u32(np, "rockchip,ddr3_speed_bin", - &timing->ddr3_speed_bin); ret |= of_property_read_u32(np, "rockchip,pd_idle", - &timing->pd_idle); + &data->pd_idle); ret |= of_property_read_u32(np, "rockchip,sr_idle", - &timing->sr_idle); + &data->sr_idle); ret |= of_property_read_u32(np, "rockchip,sr_mc_gate_idle", - &timing->sr_mc_gate_idle); + &data->sr_mc_gate_idle); ret |= of_property_read_u32(np, "rockchip,srpd_lite_idle", - &timing->srpd_lite_idle); + &data->srpd_lite_idle); ret |= of_property_read_u32(np, "rockchip,standby_idle", - &timing->standby_idle); - ret |= of_property_read_u32(np, "rockchip,auto_pd_dis_freq", - &timing->auto_pd_dis_freq); - ret |= of_property_read_u32(np, "rockchip,dram_dll_dis_freq", - &timing->dram_dll_dis_freq); - ret |= of_property_read_u32(np, "rockchip,phy_dll_dis_freq", - &timing->phy_dll_dis_freq); + &data->standby_idle); ret |= of_property_read_u32(np, "rockchip,ddr3_odt_dis_freq", - &timing->ddr3_odt_dis_freq); - ret |= of_property_read_u32(np, "rockchip,ddr3_drv", - &timing->ddr3_drv); - ret |= of_property_read_u32(np, "rockchip,ddr3_odt", - &timing->ddr3_odt); - ret |= of_property_read_u32(np, "rockchip,phy_ddr3_ca_drv", - &timing->phy_ddr3_ca_drv); - ret |= of_property_read_u32(np, "rockchip,phy_ddr3_dq_drv", - &timing->phy_ddr3_dq_drv); - ret |= of_property_read_u32(np, "rockchip,phy_ddr3_odt", - &timing->phy_ddr3_odt); + &data->ddr3_odt_dis_freq); ret |= of_property_read_u32(np, "rockchip,lpddr3_odt_dis_freq", - &timing->lpddr3_odt_dis_freq); - ret |= of_property_read_u32(np, "rockchip,lpddr3_drv", - &timing->lpddr3_drv); - ret |= of_property_read_u32(np, "rockchip,lpddr3_odt", - &timing->lpddr3_odt); - ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_ca_drv", - &timing->phy_lpddr3_ca_drv); - ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_dq_drv", - &timing->phy_lpddr3_dq_drv); - ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_odt", - &timing->phy_lpddr3_odt); + &data->lpddr3_odt_dis_freq); ret |= of_property_read_u32(np, "rockchip,lpddr4_odt_dis_freq", - &timing->lpddr4_odt_dis_freq); - ret |= of_property_read_u32(np, "rockchip,lpddr4_drv", - &timing->lpddr4_drv); - ret |= of_property_read_u32(np, "rockchip,lpddr4_dq_odt", - &timing->lpddr4_dq_odt); - ret |= of_property_read_u32(np, "rockchip,lpddr4_ca_odt", - &timing->lpddr4_ca_odt); - ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_ca_drv", - &timing->phy_lpddr4_ca_drv); - ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_ck_cs_drv", - &timing->phy_lpddr4_ck_cs_drv); - ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_dq_drv", - &timing->phy_lpddr4_dq_drv); - ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_odt", - &timing->phy_lpddr4_odt); + &data->lpddr4_odt_dis_freq); return ret; } @@ -311,8 +245,7 @@ static int rk3399_dmcfreq_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct device_node *np = pdev->dev.of_node, *node; struct rk3399_dmcfreq *data; - int ret, index, size; - uint32_t *timing; + int ret; struct dev_pm_opp *opp; u32 ddr_type; u32 val; @@ -343,26 +276,7 @@ static int rk3399_dmcfreq_probe(struct platform_device *pdev) return ret; } - /* - * Get dram timing and pass it to arm trust firmware, - * the dram driver in arm trust firmware will get these - * timing and to do dram initial. - */ - if (!of_get_ddr_timings(&data->timing, np)) { - timing = &data->timing.ddr3_speed_bin; - size = sizeof(struct dram_timing) / 4; - for (index = 0; index < size; index++) { - arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, *timing++, index, - ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM, - 0, 0, 0, 0, &res); - if (res.a0) { - dev_err(dev, "Failed to set dram param: %ld\n", - res.a0); - ret = -EINVAL; - goto err_edev; - } - } - } + rk3399_dmcfreq_of_props(data, np); node = of_parse_phandle(np, "rockchip,pmu", 0); if (!node) @@ -381,13 +295,13 @@ static int rk3399_dmcfreq_probe(struct platform_device *pdev) switch (ddr_type) { case RK3399_PMUGRF_DDRTYPE_DDR3: - data->odt_dis_freq = data->timing.ddr3_odt_dis_freq; + data->odt_dis_freq = data->ddr3_odt_dis_freq; break; case RK3399_PMUGRF_DDRTYPE_LPDDR3: - data->odt_dis_freq = data->timing.lpddr3_odt_dis_freq; + data->odt_dis_freq = data->lpddr3_odt_dis_freq; break; case RK3399_PMUGRF_DDRTYPE_LPDDR4: - data->odt_dis_freq = data->timing.lpddr4_odt_dis_freq; + data->odt_dis_freq = data->lpddr4_odt_dis_freq; break; default: ret = -EINVAL; @@ -414,11 +328,11 @@ static int rk3399_dmcfreq_probe(struct platform_device *pdev) * arg2: * bit[0] : odt enable */ - data->odt_pd_arg0 = (data->timing.sr_idle & 0xff) | - ((data->timing.sr_mc_gate_idle & 0xff) << 8) | - ((data->timing.standby_idle & 0xffff) << 16); - data->odt_pd_arg1 = (data->timing.pd_idle & 0xfff) | - ((data->timing.srpd_lite_idle & 0xfff) << 16); + data->odt_pd_arg0 = (data->sr_idle & 0xff) | + ((data->sr_mc_gate_idle & 0xff) << 8) | + ((data->standby_idle & 0xffff) << 16); + data->odt_pd_arg1 = (data->pd_idle & 0xfff) | + ((data->srpd_lite_idle & 0xfff) << 16); /* * We add a devfreq driver to our parent since it has a device tree node From patchwork Fri Jan 7 23:53:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brian Norris X-Patchwork-Id: 12707143 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DD08DC433EF for ; Fri, 7 Jan 2022 23:56:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=VO9xhVLxecJW3Q4fBmZ4iBH+Ej52FftWhzb8Sr3EJy8=; b=2p7KuPilf8Qo3o NPvMSxLQJrsV6Hgh7Nff/Q6vQUwvtulslBFkg/vZQZZOMbJxy43KhAWyl7G+8dWFrhWz6kzexOr6A TA21aVUTLpmTNaYSjvPB+UlEmkgYqRYu82XcIwJd1pOiXRKIycp9hSVpQUyUst1SSgHv/nXGDXGT1 k0mE02TE6Y00tCCHO8Stf7DNFHTaaI1kAgOwkCNlnrOtwVGmmrUiqcyu76vWSOyepcIn4FiUKUQAT 1RiI/nJhCf2Up2Mr4Y1mkRS9OPKpJ0H6NBTOCas4y1UMjVZEoeQbFegINvCIGjpFypEE6taWgoKNW GqszOuzWpziXM9ZwNfUQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n5z65-005aTG-UT; Fri, 07 Jan 2022 23:56:38 +0000 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1n5z3J-005Yrk-1r for linux-rockchip@lists.infradead.org; Fri, 07 Jan 2022 23:53:48 +0000 Received: by mail-pj1-x102e.google.com with SMTP id l10-20020a17090a384a00b001b22190e075so13799533pjf.3 for ; Fri, 07 Jan 2022 15:53:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vnBEku22nFoYufV2aPCfVzGav/5qYcDVrSLes2E+zqw=; b=Ewu1LJLRf0snQq2dRiaVC6pWWngphFRDTOpkQ8Bi+K49SuQz9c3wIFTwLMNaGYBomH yNxIWv1Kx0I0nutVfCLkOhxETOv6wOcC10qsfblc4uzqdjWaEC9/Yqp38vSsDee7t9aA ilbHQYrt/zmhGPyyze+kyxSVuFvYHNn0WUafk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vnBEku22nFoYufV2aPCfVzGav/5qYcDVrSLes2E+zqw=; b=HBZkCny4RwcWX1fyQrM2vc9DkFjASKGb00tSuMEfaEHcb3JxoBjsOSZSKtNdwFvFWf S+xSU5IQJ+4gCqxPsntWZKnbdOZuLufktGUdj6ouEiyuIzY64Y84fDLFAjhWu55Hr8A+ sXzITAFEtTFKp3ZfIqoYzKC3YhjDd09MEA8Agv0xQKg6b+3S3UDFFpdO+2FgA5G3VqF4 xJNGI1/0hZUx0F9Rtruz4Ao2Z4ZWY2AxuSgcRwtKkqBmg4RAAeC4UEM5ohaJHsHFIp6u yiwVTa/v5At7j+oAcqTfHcaU5wXff7eM+67XtTv+GLOyVu4al7XE1lJ3e8+imf8QxHnI o/lA== X-Gm-Message-State: AOAM531bAaE13apz2OxwPY507tR8mXHSHs0fsjMCbaxcXCBaxWY7hd5U 9PsCUTMSan8uIf/7c3JfbHXQMA== X-Google-Smtp-Source: ABdhPJxSHaaq8+P1tjYNngGlMiqekaJ7/jtLTJDL6m/k3iyhZZNI45qDgrBzPEQ7Lddq74fCrB4/Lw== X-Received: by 2002:a17:90b:4c06:: with SMTP id na6mr17972774pjb.236.1641599624512; Fri, 07 Jan 2022 15:53:44 -0800 (PST) Received: from localhost ([2620:15c:202:201:db:1c60:693f:c24e]) by smtp.gmail.com with UTF8SMTPSA id q19sm48610pfk.153.2022.01.07.15.53.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 07 Jan 2022 15:53:44 -0800 (PST) From: Brian Norris To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring Cc: Heiko Stuebner , linux-arm-kernel@lists.infradead.org, Lin Huang , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-pm@vger.kernel.org, Derek Basehore , linux-kernel@vger.kernel.org, Brian Norris Subject: [PATCH 07/10] PM / devfreq: rk3399_dmc: Use bitfield macro definitions for ODT_PD Date: Fri, 7 Jan 2022 15:53:17 -0800 Message-Id: <20220107155215.7.I0f36da588afd01d0dc9ce5866240efa34bd91e21@changeid> X-Mailer: git-send-email 2.34.1.575.g55b058a8bb-goog In-Reply-To: <20220107235320.965497-1-briannorris@chromium.org> References: <20220107235320.965497-1-briannorris@chromium.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220107_155345_193146_61EF7834 X-CRM114-Status: GOOD ( 16.80 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org We're going to add new usages, and it's cleaner to work with macros instead of comments and magic numbers. Signed-off-by: Brian Norris --- drivers/devfreq/rk3399_dmc.c | 43 ++++++++++++++++++++---------------- 1 file changed, 24 insertions(+), 19 deletions(-) diff --git a/drivers/devfreq/rk3399_dmc.c b/drivers/devfreq/rk3399_dmc.c index 8f447217303f..c4efbc15cbb1 100644 --- a/drivers/devfreq/rk3399_dmc.c +++ b/drivers/devfreq/rk3399_dmc.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include @@ -23,6 +24,15 @@ #include #include +#define RK3399_SET_ODT_PD_0_SR_IDLE GENMASK(7, 0) +#define RK3399_SET_ODT_PD_0_SR_MC_GATE_IDLE GENMASK(15, 8) +#define RK3399_SET_ODT_PD_0_STANDBY_IDLE GENMASK(31, 16) + +#define RK3399_SET_ODT_PD_1_PD_IDLE GENMASK(11, 0) +#define RK3399_SET_ODT_PD_1_SRPD_LITE_IDLE GENMASK(27, 16) + +#define RK3399_SET_ODT_PD_2_ODT_ENABLE BIT(0) + struct rk3399_dmcfreq { struct device *dev; struct devfreq *devfreq; @@ -55,7 +65,6 @@ static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq, unsigned long old_clk_rate = dmcfreq->rate; unsigned long target_volt, target_rate; struct arm_smccc_res res; - bool odt_enable = false; int err; opp = devfreq_recommended_opp(dev, freq, flags); @@ -72,8 +81,10 @@ static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq, mutex_lock(&dmcfreq->lock); if (dmcfreq->regmap_pmu) { + unsigned int odt_pd_arg2 = 0; + if (target_rate >= dmcfreq->odt_dis_freq) - odt_enable = true; + odt_pd_arg2 |= RK3399_SET_ODT_PD_2_ODT_ENABLE; /* * This makes a SMC call to the TF-A to set the DDR PD @@ -83,7 +94,7 @@ static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq, arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, dmcfreq->odt_pd_arg0, dmcfreq->odt_pd_arg1, ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD, - odt_enable, 0, 0, 0, &res); + odt_pd_arg2, 0, 0, 0, &res); } /* @@ -316,23 +327,17 @@ static int rk3399_dmcfreq_probe(struct platform_device *pdev) /* * In TF-A there is a platform SIP call to set the PD (power-down) * timings and to enable or disable the ODT (on-die termination). - * This call needs three arguments as follows: - * - * arg0: - * bit[0-7] : sr_idle - * bit[8-15] : sr_mc_gate_idle - * bit[16-31] : standby idle - * arg1: - * bit[0-11] : pd_idle - * bit[16-27] : srpd_lite_idle - * arg2: - * bit[0] : odt enable */ - data->odt_pd_arg0 = (data->sr_idle & 0xff) | - ((data->sr_mc_gate_idle & 0xff) << 8) | - ((data->standby_idle & 0xffff) << 16); - data->odt_pd_arg1 = (data->pd_idle & 0xfff) | - ((data->srpd_lite_idle & 0xfff) << 16); + data->odt_pd_arg0 = + FIELD_PREP(RK3399_SET_ODT_PD_0_SR_IDLE, data->sr_idle) | + FIELD_PREP(RK3399_SET_ODT_PD_0_SR_MC_GATE_IDLE, + data->sr_mc_gate_idle) | + FIELD_PREP(RK3399_SET_ODT_PD_0_STANDBY_IDLE, + data->standby_idle); + data->odt_pd_arg1 = + FIELD_PREP(RK3399_SET_ODT_PD_1_PD_IDLE, data->pd_idle) | + FIELD_PREP(RK3399_SET_ODT_PD_1_SRPD_LITE_IDLE, + data->srpd_lite_idle); /* * We add a devfreq driver to our parent since it has a device tree node From patchwork Fri Jan 7 23:53:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brian Norris X-Patchwork-Id: 12707144 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C27ACC433F5 for ; Fri, 7 Jan 2022 23:57:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=E8epCqYNbVIMxDMVOMxwTljNHk51WieU6SLTV5kyFrs=; b=cBr+BMi6C0+MsU NeiPDxZfO1evnDpqZj8QEr/M1Zf7jhbHRhhd4+xkorBkX4QCtVpONtbCZ7Watq6aBMixRFZzA6yb1 sjQw7/8Va6RECnZmNa53v2TMZ+MhiQmGVynmWOMpI8QgvHjfIfmZMlHVMkIyoBHh6snQrtnkv8fz2 4Gz6/CeU4xQVrMutpVKSKVdL2xTIqMb4c5YAx2CrikafIPO5geKYNROqu5npUdRAqEEn0jsFF/vQL 5hTfevN349452DwKEZ+n44eodcq703AQYIqNHl3yR+ax3RXg3OeR2YcdCGl/gMWCSFx0T3aGVQF5K gFl7/0yriguLi/eK/R6w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n5z6e-005alp-5O; Fri, 07 Jan 2022 23:57:12 +0000 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1n5z3L-005Ysd-9y for linux-rockchip@lists.infradead.org; Fri, 07 Jan 2022 23:53:50 +0000 Received: by mail-pj1-x1031.google.com with SMTP id r16-20020a17090a0ad000b001b276aa3aabso13873987pje.0 for ; Fri, 07 Jan 2022 15:53:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6Xh2WAcRayquz/Kdsf8CPJU6vn+1pkaPERRV3q8+MOc=; b=YaZZufWqRGJ5Z3Lk4+FjRkBmyUgUwYG1YMsrEXuTJ6lo4dsTRis5izX/in5bs5SqEx S0FenPEqwK6lPtmwzuvWbh/+C1A5YqJISRYUk2+ioYdk29aKUFO9lH/a/lRPHoEEXdW2 LbkTOQgA4lnX5zQidjLaImjWqBfT6MfKFXtwE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6Xh2WAcRayquz/Kdsf8CPJU6vn+1pkaPERRV3q8+MOc=; b=UzMvNw+MpiU22UedhG/xr6ZtJniOr4q/ngbbSMgcV4VO1PncE3GCyojxFDUscaKcpT AGyuIvpoXRDCTYyPm3bnO3EyPveljQORDZtovn34ULM4TK4X8VZ13xFurs8fTEAjHS9A +Z5bGkhBn4gMXGl2RcaIljH6am5+PqR4vXTUbKBTg8YWonIUixeFxb/TAiYPV8KBPQ1J IdxzYMAVx/j1AJT9JPma1X4hMcEienbmx82W3VXrbPmIADsoCj9PSLyGpZiHXWJqoA12 ilenZFqkx6hO5jCcFl5bHLa6crhP3pRoIVjtoY45BX/1rsrvaW3Y4aAdLxPLgrit0atM iGCA== X-Gm-Message-State: AOAM530T7R2brinZmM/KNh23dr0V3z8aDrDH32g9GoHezIj5sMnAR/v6 XBAl8hnoLbp1d06IbepawtC1pg== X-Google-Smtp-Source: ABdhPJzLeYyNBTb3Y2nHcruEQoGGGyC4SOeMaL3pTo+pMcWUBs9W/dgNZ2RbjFIPKEP1nG7WAeePfw== X-Received: by 2002:a17:902:8346:b0:149:d1c7:fdc0 with SMTP id z6-20020a170902834600b00149d1c7fdc0mr14458886pln.166.1641599626571; Fri, 07 Jan 2022 15:53:46 -0800 (PST) Received: from localhost ([2620:15c:202:201:db:1c60:693f:c24e]) by smtp.gmail.com with UTF8SMTPSA id e21sm58740pff.24.2022.01.07.15.53.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 07 Jan 2022 15:53:46 -0800 (PST) From: Brian Norris To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring Cc: Heiko Stuebner , linux-arm-kernel@lists.infradead.org, Lin Huang , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-pm@vger.kernel.org, Derek Basehore , linux-kernel@vger.kernel.org, Brian Norris Subject: [PATCH 08/10] PM / devfreq: rk3399_dmc: Support new disable-freq properties Date: Fri, 7 Jan 2022 15:53:18 -0800 Message-Id: <20220107155215.8.I08d654522b8a1ae92ecb8d2e2a74511f778f61e5@changeid> X-Mailer: git-send-email 2.34.1.575.g55b058a8bb-goog In-Reply-To: <20220107235320.965497-1-briannorris@chromium.org> References: <20220107235320.965497-1-briannorris@chromium.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220107_155347_383779_72417879 X-CRM114-Status: GOOD ( 14.46 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Implement the newly-defined properties to allow disabling certain power-saving-at-idle features at higher frequencies. This is a rewritten version of work by Lin Huang . Signed-off-by: Brian Norris --- drivers/devfreq/rk3399_dmc.c | 51 +++++++++++++++++++++++++++++++++--- 1 file changed, 47 insertions(+), 4 deletions(-) diff --git a/drivers/devfreq/rk3399_dmc.c b/drivers/devfreq/rk3399_dmc.c index c4efbc15cbb1..58a4970918be 100644 --- a/drivers/devfreq/rk3399_dmc.c +++ b/drivers/devfreq/rk3399_dmc.c @@ -55,6 +55,12 @@ struct rk3399_dmcfreq { unsigned int ddr3_odt_dis_freq; unsigned int lpddr3_odt_dis_freq; unsigned int lpddr4_odt_dis_freq; + + unsigned int pd_idle_dis_freq; + unsigned int sr_idle_dis_freq; + unsigned int sr_mc_gate_idle_dis_freq; + unsigned int srpd_lite_idle_dis_freq; + unsigned int standby_idle_dis_freq; }; static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq, @@ -81,8 +87,25 @@ static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq, mutex_lock(&dmcfreq->lock); if (dmcfreq->regmap_pmu) { + unsigned int odt_pd_arg0 = dmcfreq->odt_pd_arg0; + unsigned int odt_pd_arg1 = dmcfreq->odt_pd_arg1; unsigned int odt_pd_arg2 = 0; + if (target_rate >= dmcfreq->sr_idle_dis_freq) + odt_pd_arg0 &= ~RK3399_SET_ODT_PD_0_SR_IDLE; + + if (target_rate >= dmcfreq->sr_mc_gate_idle_dis_freq) + odt_pd_arg0 &= ~RK3399_SET_ODT_PD_0_SR_MC_GATE_IDLE; + + if (target_rate >= dmcfreq->standby_idle_dis_freq) + odt_pd_arg0 &= ~RK3399_SET_ODT_PD_0_STANDBY_IDLE; + + if (target_rate >= dmcfreq->pd_idle_dis_freq) + odt_pd_arg1 &= ~RK3399_SET_ODT_PD_1_PD_IDLE; + + if (target_rate >= dmcfreq->srpd_lite_idle_dis_freq) + odt_pd_arg1 &= ~RK3399_SET_ODT_PD_1_SRPD_LITE_IDLE; + if (target_rate >= dmcfreq->odt_dis_freq) odt_pd_arg2 |= RK3399_SET_ODT_PD_2_ODT_ENABLE; @@ -91,10 +114,9 @@ static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq, * (power-down) timings and to enable or disable the * ODT (on-die termination) resistors. */ - arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, dmcfreq->odt_pd_arg0, - dmcfreq->odt_pd_arg1, - ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD, - odt_pd_arg2, 0, 0, 0, &res); + arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, odt_pd_arg0, odt_pd_arg1, + ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD, odt_pd_arg2, + 0, 0, 0, &res); } /* @@ -230,6 +252,16 @@ static int rk3399_dmcfreq_of_props(struct rk3399_dmcfreq *data, { int ret = 0; + /* + * These are all optional, and serve as minimum bounds. Give them large + * (i.e., never "disabled") values if the DT doesn't specify one. + */ + data->pd_idle_dis_freq = + data->sr_idle_dis_freq = + data->sr_mc_gate_idle_dis_freq = + data->srpd_lite_idle_dis_freq = + data->standby_idle_dis_freq = UINT_MAX; + ret |= of_property_read_u32(np, "rockchip,pd_idle", &data->pd_idle); ret |= of_property_read_u32(np, "rockchip,sr_idle", @@ -247,6 +279,17 @@ static int rk3399_dmcfreq_of_props(struct rk3399_dmcfreq *data, ret |= of_property_read_u32(np, "rockchip,lpddr4_odt_dis_freq", &data->lpddr4_odt_dis_freq); + ret |= of_property_read_u32(np, "rockchip,pd_idle_dis_freq", + &data->pd_idle_dis_freq); + ret |= of_property_read_u32(np, "rockchip,sr_idle_dis_freq", + &data->sr_idle_dis_freq); + ret |= of_property_read_u32(np, "rockchip,sr_mc_gate_idle_dis_freq", + &data->sr_mc_gate_idle_dis_freq); + ret |= of_property_read_u32(np, "rockchip,srpd_lite_idle_dis_freq", + &data->srpd_lite_idle_dis_freq); + ret |= of_property_read_u32(np, "rockchip,standby_idle_dis_freq", + &data->standby_idle_dis_freq); + return ret; } From patchwork Fri Jan 7 23:53:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Brian Norris X-Patchwork-Id: 12707145 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9D991C433F5 for ; Fri, 7 Jan 2022 23:57:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=OInNCXVwo5Q3FKX0sVSYTycoEsFCtNermGhxZJZx4S0=; b=rPLZGAC88m5Qru G7C229T/eRSp667PDsBmNovCvePQff6V43GFnB9ot79EfXFion2qI0AutNHUw0IsNIeq7dK8vN0q6 LG8z57tJegy75Sl4Um+lczQ/30TURJMafx9MgrFr0UuIaMNFaeVVSaKIR2TMAyUlkJM+h36mFj/um SfEXMtN37RYem/4C4kKUKBjU/zmLoyQpNxU/VFucmFGe7mo9jF35nQNdPhv3zDPQbSID0zgTwrHXj vWR9OEGSbG8JFu4ZBhGk7JE02zoKbINNRVfZqA6ugchthkfspC2mKb9ZsRek6nuKxDbGkwNsjJxVr ARVeKwmjynLCdtmQeaEg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n5z6g-005anO-Up; Fri, 07 Jan 2022 23:57:15 +0000 Received: from mail-pg1-x536.google.com ([2607:f8b0:4864:20::536]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1n5z3N-005Yu8-PB for linux-rockchip@lists.infradead.org; Fri, 07 Jan 2022 23:53:51 +0000 Received: by mail-pg1-x536.google.com with SMTP id t32so7018816pgm.7 for ; Fri, 07 Jan 2022 15:53:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bLiXD9EPxhuhl4swC8hQ6wdNP1ClmDuHZfS+mTSLPMY=; b=BYk2607hHPmSvHDebgSv5EvoUO2Eu+i/iAiOXw2Ta1ucl/Xw1m3CkSEWSoxLGk+krW 8TtKDL2dq86sfn3/TjOaQjddauSgNqwTr6imn4sJv7/DFenryx+A4mrAadJMQkIItgqo NeS17kOoVGXrYbz/o9aQI9i05ftBJHeTTORPw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bLiXD9EPxhuhl4swC8hQ6wdNP1ClmDuHZfS+mTSLPMY=; b=VlaT7+PJD6cYe2TPDzfPVpmph4Bt651J2RqvGOnf8YGIFv8IJDZXpPycdjxdFwH9oD TanbDPq6aMMe3eG4GLjy0L5U6GLk7OEvpUGdHqW1Gjs04zvuWk+Loc9OP9+gc0DVWqaU CnebUQDIzOfm4DQQLe//wtOS+cTyFXqV8lv++b8gScuC6AwztB9TWfNI2TlQJYfGnG6x L2SINrJ9SuGUAXr+6uZdOjZUremHwvpibfD0rMHer/cB/KKyDdq2wdVnQUXWz5MaXjxE P9CZFxwsO2CFu+9PslSfiyWFJvBmVKNADIEMzMW88u++abJ8NRSmqnwy6VZ8Z3BAzPGj 4edA== X-Gm-Message-State: AOAM532hStkZGdzPVF1XYe0QL/4bgwpWWfZSXwBM3H5ShVstR11CWJb6 zt87FNbAVtA99K40TXpFVYzJsQ== X-Google-Smtp-Source: ABdhPJxec9Iz4K7SGQBxWwH4Aa43xT+erYjwZOOHGJsTnXVxoFwz2OkPS74l+sChFO3DcJQ2WklFNQ== X-Received: by 2002:a05:6a00:26c5:b0:4bd:4ad6:9c71 with SMTP id p5-20020a056a0026c500b004bd4ad69c71mr482801pfw.45.1641599628943; Fri, 07 Jan 2022 15:53:48 -0800 (PST) Received: from localhost ([2620:15c:202:201:db:1c60:693f:c24e]) by smtp.gmail.com with UTF8SMTPSA id y29sm56068pfa.54.2022.01.07.15.53.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 07 Jan 2022 15:53:48 -0800 (PST) From: Brian Norris To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring Cc: Heiko Stuebner , linux-arm-kernel@lists.infradead.org, Lin Huang , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-pm@vger.kernel.org, Derek Basehore , linux-kernel@vger.kernel.org, Enric Balletbo i Serra , =?utf-8?q?Ga=C3=ABl_?= =?utf-8?q?PORTAY?= , Daniel Lezcano , Brian Norris Subject: [PATCH 09/10] arm64: dts: rk3399: Add dfi and dmc nodes Date: Fri, 7 Jan 2022 15:53:19 -0800 Message-Id: <20220107155215.9.Ie97993621975c5463d7928a8646f3737c9f2921d@changeid> X-Mailer: git-send-email 2.34.1.575.g55b058a8bb-goog In-Reply-To: <20220107235320.965497-1-briannorris@chromium.org> References: <20220107235320.965497-1-briannorris@chromium.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220107_155349_910546_85864A31 X-CRM114-Status: GOOD ( 10.58 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org From: Lin Huang These are required to support DDR DVFS on RK3399 platforms. Signed-off-by: Lin Huang Signed-off-by: Enric Balletbo i Serra Signed-off-by: Gaël PORTAY Signed-off-by: Daniel Lezcano Signed-off-by: Brian Norris --- This is based on a v5 posting from various authors: https://lore.kernel.org/lkml/20210308233858.24741-3-daniel.lezcano@linaro.org/ Much of that series was already merged, so I start over with the numbering. Change since Daniel's posting: reordered by unit address, per existing style arch/arm64/boot/dts/rockchip/rk3399.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index d3cdf6f42a30..86e2d87e008a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1295,6 +1295,25 @@ pwm3: pwm@ff420030 { status = "disabled"; }; + dfi: dfi@ff630000 { + reg = <0x00 0xff630000 0x00 0x4000>; + compatible = "rockchip,rk3399-dfi"; + rockchip,pmu = <&pmugrf>; + interrupts = ; + clocks = <&cru PCLK_DDR_MON>; + clock-names = "pclk_ddr_mon"; + status = "disabled"; + }; + + dmc: dmc { + compatible = "rockchip,rk3399-dmc"; + rockchip,pmu = <&pmugrf>; + devfreq-events = <&dfi>; + clocks = <&cru SCLK_DDRC>; + clock-names = "dmc_clk"; + status = "disabled"; + }; + vpu: video-codec@ff650000 { compatible = "rockchip,rk3399-vpu"; reg = <0x0 0xff650000 0x0 0x800>; From patchwork Fri Jan 7 23:53:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Brian Norris X-Patchwork-Id: 12707146 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 25650C433EF for ; Fri, 7 Jan 2022 23:58:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=1FSRKcevFNH89KqJVfmfRw+X7Hib4sqZa1v1FtPSliU=; b=bzzTQCWQ9gvr4m 4vF5qz2CoczHlMC02FEviTafy5vdTpgOJVWmZUdIiTWqlo8XRW8Jsats0oGW2ZnK5DUftplPOsvds bmRYC6ck2MxvCXih+O5E8jEXHblpZozkRWy8/LdES6fF+RyD4rPbkZiEvc07+TKNz9NaPgqi1DZuf CAzVvD843unXQ5umfHBwGarQ1f+lvzoZqUr9Szl93dFZ7Oqzqlc0pP+z08paRy4jv3nDGEfau9vv5 YDZcjsOC0nP5dl6NEzPXtAIXqExfY2+dEOO2U9tLDeKNXuUqtZ8WeTDgXU5/xbsPhWc3SnISRTr75 sJGtpEO45Ik7eu28B1hw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n5z7N-005bCE-MK; Fri, 07 Jan 2022 23:57:57 +0000 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1n5z3P-005Yvo-VQ for linux-rockchip@lists.infradead.org; Fri, 07 Jan 2022 23:53:54 +0000 Received: by mail-pj1-x1032.google.com with SMTP id l16-20020a17090a409000b001b2e9628c9cso8217042pjg.4 for ; Fri, 07 Jan 2022 15:53:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eGzgdGw2ygRqpcUdePm+Su5tD7TZxP9sdobQbw7EuUI=; b=RUQ7R2K0ZKIUdwB5X5NmRvSqn3fS17E6ywGorO3ouAqwwj3P5S0sZwCL/ybr4XscT4 6D5y3Njh9Bz3SdNQwXelYmKZIpQQAisRv8pd85kvQyGL+8A7U5Q86we/+xH2jY4WvEAK JdAeJlcWx2Hw74F5uoUczZ6RNG4YfJ9DkTiL0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eGzgdGw2ygRqpcUdePm+Su5tD7TZxP9sdobQbw7EuUI=; b=IHKNrBOSAU/ikuZFzFucXcYRSLmVFiazwbQxuJmVxFRqqwNYEgrMrXR4zbLYQgkADe BcPsRaywbN6vCylon0PAhcZLVH6wAY0z8QCcLfYcMT0Vejc/see7KM20daZH6P7+TDt1 Ygkf5hXoU7+0Y0JQD9/JzIWVugajBHwOrj8cF8KYQ6TIZPUfOgX/2a7m3TDs/EP5C7L0 k9eBp15aTsNKkgXEiilAi57+GbvG84tdfFj34MsDuFfhLKTvgJN/wsDhJzB/LE2rCTd1 0Z2cHg21w9uNeO61qwsDzAW+9Lum9EKU98YYnjMXSDLhkESEKuwOl1LD66RRBDRgdU5S etjQ== X-Gm-Message-State: AOAM530ssLcfXwkence+qOEZsJvBwth21jpmYO3lAiCoiTadUGSb7gIv CBZPX8ejK0WxP9YCZnqWSsMGWg== X-Google-Smtp-Source: ABdhPJwL1zbXYqcwNN1NKUrnQbenm9zESq2WGHkzK0A9KpnOeaZTWfin5pN4KEKW7GQcDUdkAFVExA== X-Received: by 2002:a17:903:191:b0:148:a2f7:9d4a with SMTP id z17-20020a170903019100b00148a2f79d4amr64690380plg.105.1641599631474; Fri, 07 Jan 2022 15:53:51 -0800 (PST) Received: from localhost ([2620:15c:202:201:db:1c60:693f:c24e]) by smtp.gmail.com with UTF8SMTPSA id u18sm49681pfi.158.2022.01.07.15.53.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 07 Jan 2022 15:53:51 -0800 (PST) From: Brian Norris To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring Cc: Heiko Stuebner , linux-arm-kernel@lists.infradead.org, Lin Huang , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-pm@vger.kernel.org, Derek Basehore , linux-kernel@vger.kernel.org, Enric Balletbo i Serra , =?utf-8?q?Ga=C3=ABl_?= =?utf-8?q?PORTAY?= , Daniel Lezcano , Brian Norris Subject: [PATCH 10/10] arm64: dts: rockchip: Enable dmc and dfi nodes on gru Date: Fri, 7 Jan 2022 15:53:20 -0800 Message-Id: <20220107155215.10.I3a5c7f21ecd8221b42c2dbcd618386bce7b3e9a6@changeid> X-Mailer: git-send-email 2.34.1.575.g55b058a8bb-goog In-Reply-To: <20220107235320.965497-1-briannorris@chromium.org> References: <20220107235320.965497-1-briannorris@chromium.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220107_155352_083105_AE3A8D28 X-CRM114-Status: GOOD ( 14.11 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org From: Lin Huang Enable the DMC (Dynamic Memory Controller) and the DFI (DDR PHY Interface) nodes on gru boards so we can support DDR DVFS. Signed-off-by: Lin Huang Signed-off-by: Enric Balletbo i Serra Signed-off-by: Gaël PORTAY Signed-off-by: Daniel Lezcano Signed-off-by: Brian Norris --- This was part of a previous series, at: https://lore.kernel.org/r/20210308233858.24741-3-daniel.lezcano@linaro.org I've picked up a bunch of changes and fixes, so I've restarted the patch series numbering. Updates since the old series: * reordered alphabetically by phandle name, per style * drop a ton of deprecated/unused properties * add required center-supply for scarlet * add new *_idle_dis_freq properties * drop the lowest (200 MHz) OPP; this was never stabilized for production * bump the voltage (0.9V -> 0.925V) for the highest OPP on Chromebook models; later (tablet) models were more stable, with a fixed DDR regulator * bump odt_dis_freq to 666 MHz; early versions used 333 MHz, but stabilization efforts landed on 666 MHz for production .../dts/rockchip/rk3399-gru-chromebook.dtsi | 7 +++++ .../boot/dts/rockchip/rk3399-gru-scarlet.dtsi | 12 ++++++++ arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 28 +++++++++++++++++++ .../boot/dts/rockchip/rk3399-op1-opp.dtsi | 25 +++++++++++++++++ 4 files changed, 72 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi index 9b2c679f5eca..46292fdceecb 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi @@ -234,6 +234,13 @@ &cdn_dp { extcon = <&usbc_extcon0>, <&usbc_extcon1>; }; +&dmc { + center-supply = <&ppvar_centerlogic>; + rockchip,pd_idle_dis_freq = <800000000>; + rockchip,sr_idle_dis_freq = <800000000>; + rockchip,sr_mc_gate_idle_dis_freq = <800000000>; +}; + &edp { status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi index a9817b3d7edc..913d845eb51a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi @@ -391,6 +391,18 @@ &cru { <400000000>; }; +/* The center supply is fixed to .9V on scarlet */ +&dmc { + center-supply = <&pp900_s0>; +}; + +/* We don't need .925 V for 928 MHz on scarlet */ +&dmc_opp_table { + opp03 { + opp-microvolt = <900000>; + }; +}; + &gpio0 { gpio-line-names = /* GPIO0 A 0-7 */ "CLK_32K_AP", diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi index 45a5ae5d2027..58b8d332f924 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi @@ -373,6 +373,34 @@ &cru { <200000000>; }; +&dfi { + status = "okay"; +}; + +&dmc { + status = "okay"; + rockchip,pd_idle = <0x40>; + rockchip,sr_idle = <0x2>; + rockchip,sr_mc_gate_idle = <0x3>; + rockchip,srpd_lite_idle = <0x4>; + rockchip,standby_idle = <0x2000>; + rockchip,ddr3_odt_dis_freq = <666000000>; + rockchip,lpddr3_odt_dis_freq = <666000000>; + rockchip,lpddr4_odt_dis_freq = <666000000>; + + rockchip,pd_idle_dis_freq = <1000000000>; + rockchip,sr_idle_dis_freq = <1000000000>; + rockchip,sr_mc_gate_idle_dis_freq = <1000000000>; + rockchip,srpd_lite_idle_dis_freq = <0>; + rockchip,standby_idle_dis_freq = <928000000>; +}; + +&dmc_opp_table { + opp03 { + opp-suspend; + }; +}; + &emmc_phy { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi index 2180e0f75003..6e29e74f6fc6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi @@ -110,6 +110,27 @@ opp05 { opp-microvolt = <1075000>; }; }; + + dmc_opp_table: dmc_opp_table { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <900000>; + }; + opp01 { + opp-hz = /bits/ 64 <666000000>; + opp-microvolt = <900000>; + }; + opp02 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <900000>; + }; + opp03 { + opp-hz = /bits/ 64 <928000000>; + opp-microvolt = <925000>; + }; + }; }; &cpu_l0 { @@ -136,6 +157,10 @@ &cpu_b1 { operating-points-v2 = <&cluster1_opp>; }; +&dmc { + operating-points-v2 = <&dmc_opp_table>; +}; + &gpu { operating-points-v2 = <&gpu_opp_table>; };