From patchwork Mon Jan 10 08:39:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 12708397 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DBE85C433F5 for ; Mon, 10 Jan 2022 08:41:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241644AbiAJIlN (ORCPT ); Mon, 10 Jan 2022 03:41:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37554 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241749AbiAJIjP (ORCPT ); Mon, 10 Jan 2022 03:39:15 -0500 Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AE3AFC03400E; Mon, 10 Jan 2022 00:39:14 -0800 (PST) Received: by mail-wr1-x432.google.com with SMTP id o3so25213123wrh.10; Mon, 10 Jan 2022 00:39:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9BZOz3rBRK9T1NJYwX4wR3Rx8LIgVrV05ZwydszvJ/w=; b=SUj2/8gzHk7Re+1i01IPUqGCS3lyvGwRjRmxmuTKEf3DL3wDTs+OjGpE3Aqr+4f9gZ Z+sRbTUBpRktgTHwE5Bx7IVWzkMYp+t9yweFs0AKn+wPs3lwtexMI+Fd0WYD+Z9AqfGF e0lHVGbLqJ0NXLjGHTlbrFBVfuaEeSUIDkL6X4oi/R2h7IdE55GWDU+azfMZaKeyBkI9 7y58en4styGl1btMiA6pzFTpxjwDLdsdRjbEsF/zLesXKYO/4ePatTR0MHcnIWy6jmMq XfzpT/ZDpC209Hy961OM8q+tWoOAvkU4G0H1rU1rqaQEIdnEQx8TvyxR9Shn2MImWViw oZrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9BZOz3rBRK9T1NJYwX4wR3Rx8LIgVrV05ZwydszvJ/w=; b=K2UKyfYCYqjw+iE728m1QisTLHYhja8ae2RdidDa+JFXJdHAlPUfzibVWrRxInQ5WM 6RjwjW0Cb5dRM6Th8ohFV4mAyoC6xNyGKIqRa3tTV1jsg7/PaOCaR85448JMXR/mA9/S 9tCmcaSKf7MP4HIONG+P9HPzQ+YT4GDd2W3nyNhX3EqkX80wogEdumeUdAI1ZLJodlna E9l/dATnB1DboShliiGBESTrOvoqRzcFSyqIFmJQl98YcoIF5XyAOvniMNmBuU3PBoEY ahM2agd5+KtuFQ4Z+IIZdG2QRwLoTcJvCf7G9XqClmYAN+IFOpqueoVPzV+vQ6R8hG0+ wG6Q== X-Gm-Message-State: AOAM530p+d1l2BF3TU1d9scQ+6fGIBFsFXUm/5MtCA0qkgAEdQWzunYS gW34iJxMpc0PylvFhC4teZZTIgQmxRDE/Q== X-Google-Smtp-Source: ABdhPJwcJYgNMCVqDHqSF6f6uVq0pRv+GQUOmxr1/UfeXK6WNusqbp8tb4Bq6/kEIIOhN6x/k7c+Bw== X-Received: by 2002:a5d:670b:: with SMTP id o11mr8947962wru.493.1641803953094; Mon, 10 Jan 2022 00:39:13 -0800 (PST) Received: from localhost.localdomain (198.red-81-44-130.dynamicip.rima-tde.net. [81.44.130.198]) by smtp.gmail.com with ESMTPSA id m7sm508926wmi.13.2022.01.10.00.39.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Jan 2022 00:39:12 -0800 (PST) From: Sergio Paracuellos To: linux-clk@vger.kernel.org Cc: john@phrozen.org, linux-staging@lists.linux.dev, gregkh@linuxfoundation.org, neil@brown.name, p.zabel@pengutronix.de, linux-kernel@vger.kernel.org, sboyd@kernel.org, Rob Herring Subject: [PATCH v6 1/4] dt-bindings: reset: add dt binding header for Mediatek MT7621 resets Date: Mon, 10 Jan 2022 09:39:07 +0100 Message-Id: <20220110083910.1351020-2-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220110083910.1351020-1-sergio.paracuellos@gmail.com> References: <20220110083910.1351020-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add dt binding header for resets lines in Mediatek MT7621 SoCs. Acked-by: Rob Herring Signed-off-by: Sergio Paracuellos --- include/dt-bindings/reset/mt7621-reset.h | 37 ++++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 include/dt-bindings/reset/mt7621-reset.h diff --git a/include/dt-bindings/reset/mt7621-reset.h b/include/dt-bindings/reset/mt7621-reset.h new file mode 100644 index 000000000000..7572c6b41453 --- /dev/null +++ b/include/dt-bindings/reset/mt7621-reset.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021 Sergio Paracuellos + * Author: Sergio Paracuellos + */ + +#ifndef DT_BINDING_MT7621_RESET_H +#define DT_BINDING_MT7621_RESET_H + +#define MT7621_RST_SYS 0 +#define MT7621_RST_MCM 2 +#define MT7621_RST_HSDMA 5 +#define MT7621_RST_FE 6 +#define MT7621_RST_SPDIFTX 7 +#define MT7621_RST_TIMER 8 +#define MT7621_RST_INT 9 +#define MT7621_RST_MC 10 +#define MT7621_RST_PCM 11 +#define MT7621_RST_PIO 13 +#define MT7621_RST_GDMA 14 +#define MT7621_RST_NFI 15 +#define MT7621_RST_I2C 16 +#define MT7621_RST_I2S 17 +#define MT7621_RST_SPI 18 +#define MT7621_RST_UART1 19 +#define MT7621_RST_UART2 20 +#define MT7621_RST_UART3 21 +#define MT7621_RST_ETH 23 +#define MT7621_RST_PCIE0 24 +#define MT7621_RST_PCIE1 25 +#define MT7621_RST_PCIE2 26 +#define MT7621_RST_AUX_STCK 28 +#define MT7621_RST_CRYPTO 29 +#define MT7621_RST_SDXC 30 +#define MT7621_RST_PPE 31 + +#endif /* DT_BINDING_MT7621_RESET_H */ From patchwork Mon Jan 10 08:39:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 12708399 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F069C433FE for ; Mon, 10 Jan 2022 08:41:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241684AbiAJIlV (ORCPT ); Mon, 10 Jan 2022 03:41:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37084 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240591AbiAJIjR (ORCPT ); Mon, 10 Jan 2022 03:39:17 -0500 Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [IPv6:2a00:1450:4864:20::330]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A798FC033241; Mon, 10 Jan 2022 00:39:15 -0800 (PST) Received: by mail-wm1-x330.google.com with SMTP id p1-20020a1c7401000000b00345c2d068bdso9212153wmc.3; Mon, 10 Jan 2022 00:39:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7Y+fkGNLGqdfMAAiGU48wuA+SIBMA19TPv5MMqKzhcc=; b=MhigOSGLaWchHK24cy23CmZKOnM8CIar36SUtK2JCZhxA8+VIjZikqsO37xv/HiqeN Xt7+LZUymU6S8pjtqa+3fOJdrNA9aFx8FipBiqWSbNHx88XGRoyjpcFD/cB4FR0fL/lh xAm8cBuMDNokwnBBciJFlLakGRO+liwUXwnCIZ3FvJNHvm+P8HnUYDBPGqSxBRCOVTHf O+XNlHGdugLWchVGNcXnMzoLtfWP+7X+JQpzLceWKcKhbEPcWYVk7V22fLiz15gijh/M G/5PC7lTtPhB8X5OXsY6zHG72eZsPVQwsS+oB+zpqwL9ZdehlVynAg6eLF7/wpsuZn4X 2ZeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7Y+fkGNLGqdfMAAiGU48wuA+SIBMA19TPv5MMqKzhcc=; b=lJyyrPUQgGUpqEtnYapqjK8Fd3F/LOwDTLDbvjQrzynJ9snxfgi6AtBjAaxcS+sO9Y UiruH1Vyyiq7kXhj+GKFRg6adpPdsRMkqE7ADBtMyAuAO7r5jqQJppIVSe57JaVPvJLF oQ1U189oET0ljol0FJ56HTJEXljNiETUce9FwoL45pDEtICbLR4vxvqPWHq6QYcn0ETm l3oNfswhNo0CGDAKSWW7WIEGtYpaPQMmKVD8wxkUvbt3Bz/r+YQX3izlGXuJMBS9vo2Z YANPwAqajuHpo525zjXYwseyvzeWGA1ljO5ckYox8uTBZek40U7oKfpegKWDUxGswNZf hS7Q== X-Gm-Message-State: AOAM530fnPkLJk1xu38uewCMxU0fNGHqv/BXkHJV5mCZVsbZaM0iphoN ZumEmmZ/XAITFnWRieLw1d/T4kN8V0fuuw== X-Google-Smtp-Source: ABdhPJycHdlLGlDD8T9SXQB3qKMTovwuGLnXIUg28UmVzzNF+rLWRW8LCju1eWkY9e6tNtzc/na3sg== X-Received: by 2002:a1c:43c5:: with SMTP id q188mr11393626wma.54.1641803954064; Mon, 10 Jan 2022 00:39:14 -0800 (PST) Received: from localhost.localdomain (198.red-81-44-130.dynamicip.rima-tde.net. [81.44.130.198]) by smtp.gmail.com with ESMTPSA id m7sm508926wmi.13.2022.01.10.00.39.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Jan 2022 00:39:13 -0800 (PST) From: Sergio Paracuellos To: linux-clk@vger.kernel.org Cc: john@phrozen.org, linux-staging@lists.linux.dev, gregkh@linuxfoundation.org, neil@brown.name, p.zabel@pengutronix.de, linux-kernel@vger.kernel.org, sboyd@kernel.org, Rob Herring Subject: [PATCH v6 2/4] dt-bindings: clock: mediatek,mt7621-sysc: add '#reset-cells' property Date: Mon, 10 Jan 2022 09:39:08 +0100 Message-Id: <20220110083910.1351020-3-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220110083910.1351020-1-sergio.paracuellos@gmail.com> References: <20220110083910.1351020-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Make system controller a reset provider for all the peripherals in the MT7621 SoC adding '#reset-cells' property. Acked-by: Rob Herring Signed-off-by: Sergio Paracuellos --- .../bindings/clock/mediatek,mt7621-sysc.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml index 915f84efd763..0c0b0ae5e2ac 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml @@ -22,6 +22,11 @@ description: | The clocks are provided inside a system controller node. + This node is also a reset provider for all the peripherals. + + Reset related bits are defined in: + [2]: . + properties: compatible: items: @@ -37,6 +42,12 @@ properties: clocks. const: 1 + "#reset-cells": + description: + The first cell indicates the reset bit within the register, see + [2] for available resets. + const: 1 + ralink,memctl: $ref: /schemas/types.yaml#/definitions/phandle description: @@ -61,6 +72,7 @@ examples: compatible = "mediatek,mt7621-sysc", "syscon"; reg = <0x0 0x100>; #clock-cells = <1>; + #reset-cells = <1>; ralink,memctl = <&memc>; clock-output-names = "xtal", "cpu", "bus", "50m", "125m", "150m", From patchwork Mon Jan 10 08:39:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 12708398 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2F384C433F5 for ; Mon, 10 Jan 2022 08:41:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241667AbiAJIlT (ORCPT ); Mon, 10 Jan 2022 03:41:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37086 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241410AbiAJIjR (ORCPT ); Mon, 10 Jan 2022 03:39:17 -0500 Received: from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com [IPv6:2a00:1450:4864:20::32f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 94901C03401F; Mon, 10 Jan 2022 00:39:16 -0800 (PST) Received: by mail-wm1-x32f.google.com with SMTP id l12-20020a7bc34c000000b003467c58cbdfso8763159wmj.2; Mon, 10 Jan 2022 00:39:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Q23sxoOBDeZmyL3t+WXmzfogUG6AamJwodCzrgho128=; b=FhKA3EQNAvkAWIqP5BtX+ExrSxhYt+fO+vyyawNO78s3PMpoYIH+gFatj9zdG1P8Fh KEPSDWwemDixS7SYvg7rIHBe23jjvRqjbg7yiXBGOnbjC1RETAGD0vjFneJrje6dOl8B IFBCgY9QNXFwJoWgXA2ceYQMu0Zfmy92Qo/0XJV2KizeErncvV5kyqWLB9Y3/+0AeCBu 1Qbh1gPDGdCSpKMyRx10mZg6M0sjN5YDirhjRJjeCR4l5k2BT2Bps51+L2xC7NwUs413 TwJ6OPhUmV+g+5cjtClMRha9tOA9TdevCNNUtxUXnRgYo0+pd5dsyfeLpdLLU/Z6k8iL 7oTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Q23sxoOBDeZmyL3t+WXmzfogUG6AamJwodCzrgho128=; b=ntWXQL7s0Foru9pepkqnEP6WretOJ6XVaNeNrGa3oXVAo74CHePbLsW/o21mBmci5j jGb8HLxHsZykHyq2SxkhEixfEFBSfaap7MEWyIzoUudGnkCvgKwpskyU60cRcpgVJZbR yBkhIlWjOrP8o9X+x6twqACXeLMh7EWCzvfN+4gN8PB8y3fwnTis6xBCNJ59aPM4INQ3 98dzm52DAOcPWwyDvoYmbB63swSBNMnaNfjqukj9/SKE240snb5IOvMyV5QZP71vlZN3 tQSMt9pFoJaYyD1VCEWTStJIZ0KyvQk34XOtpMiTGnCAMBcM2b+XVn3xKdO9dn556QD3 FGZw== X-Gm-Message-State: AOAM5329S2u5GdKUSw8z9BzysCedexgCpDx/ae9XxS8Y4qORJF3j7jcq Gb7kkgnZ+B8qbhVkYZBH9BCkDs5z1zGtNw== X-Google-Smtp-Source: ABdhPJzkDTLw2D9jwLdcwiFlEHqKcRb4nZBbdB/Z/HSm3ahVmopxRibecAnEo8lBDIhDttw3aMgqcg== X-Received: by 2002:a05:600c:4fcd:: with SMTP id o13mr21043413wmq.142.1641803954938; Mon, 10 Jan 2022 00:39:14 -0800 (PST) Received: from localhost.localdomain (198.red-81-44-130.dynamicip.rima-tde.net. [81.44.130.198]) by smtp.gmail.com with ESMTPSA id m7sm508926wmi.13.2022.01.10.00.39.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Jan 2022 00:39:14 -0800 (PST) From: Sergio Paracuellos To: linux-clk@vger.kernel.org Cc: john@phrozen.org, linux-staging@lists.linux.dev, gregkh@linuxfoundation.org, neil@brown.name, p.zabel@pengutronix.de, linux-kernel@vger.kernel.org, sboyd@kernel.org Subject: [PATCH v6 3/4] clk: ralink: make system controller node a reset provider Date: Mon, 10 Jan 2022 09:39:09 +0100 Message-Id: <20220110083910.1351020-4-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220110083910.1351020-1-sergio.paracuellos@gmail.com> References: <20220110083910.1351020-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org MT7621 system controller node is already providing the clocks for the whole system but must also serve as a reset provider. Hence, add reset controller related code to the clock driver itself. To get resets properly ready for the rest of the world we need to move platform driver initialization process to 'arch_initcall'. CC: Philipp Zabel Signed-off-by: Sergio Paracuellos --- drivers/clk/ralink/clk-mt7621.c | 86 ++++++++++++++++++++++++++++++++- 1 file changed, 85 insertions(+), 1 deletion(-) diff --git a/drivers/clk/ralink/clk-mt7621.c b/drivers/clk/ralink/clk-mt7621.c index a2c045390f00..c725bf6e6e07 100644 --- a/drivers/clk/ralink/clk-mt7621.c +++ b/drivers/clk/ralink/clk-mt7621.c @@ -11,14 +11,17 @@ #include #include #include +#include #include #include +#include /* Configuration registers */ #define SYSC_REG_SYSTEM_CONFIG0 0x10 #define SYSC_REG_SYSTEM_CONFIG1 0x14 #define SYSC_REG_CLKCFG0 0x2c #define SYSC_REG_CLKCFG1 0x30 +#define SYSC_REG_RESET_CTRL 0x34 #define SYSC_REG_CUR_CLK_STS 0x44 #define MEMC_REG_CPU_PLL 0x648 @@ -398,6 +401,76 @@ static void __init mt7621_clk_init(struct device_node *node) } CLK_OF_DECLARE_DRIVER(mt7621_clk, "mediatek,mt7621-sysc", mt7621_clk_init); +struct mt7621_rst { + struct reset_controller_dev rcdev; + struct regmap *sysc; +}; + +static struct mt7621_rst *to_mt7621_rst(struct reset_controller_dev *dev) +{ + return container_of(dev, struct mt7621_rst, rcdev); +} + +static int mt7621_assert_device(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct mt7621_rst *data = to_mt7621_rst(rcdev); + struct regmap *sysc = data->sysc; + + if (id == MT7621_RST_SYS) + return -EINVAL; + + return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), BIT(id)); +} + +static int mt7621_deassert_device(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct mt7621_rst *data = to_mt7621_rst(rcdev); + struct regmap *sysc = data->sysc; + + if (id == MT7621_RST_SYS) + return -EINVAL; + + return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), 0); +} + +static int mt7621_reset_device(struct reset_controller_dev *rcdev, + unsigned long id) +{ + int ret; + + ret = mt7621_assert_device(rcdev, id); + if (ret < 0) + return ret; + + return mt7621_deassert_device(rcdev, id); +} + +static const struct reset_control_ops reset_ops = { + .reset = mt7621_reset_device, + .assert = mt7621_assert_device, + .deassert = mt7621_deassert_device +}; + +static int mt7621_reset_init(struct device *dev, struct regmap *sysc) +{ + struct mt7621_rst *rst_data; + + rst_data = devm_kzalloc(dev, sizeof(*rst_data), GFP_KERNEL); + if (!rst_data) + return -ENOMEM; + + rst_data->sysc = sysc; + rst_data->rcdev.ops = &reset_ops; + rst_data->rcdev.owner = THIS_MODULE; + rst_data->rcdev.nr_resets = 32; + rst_data->rcdev.of_reset_n_cells = 1; + rst_data->rcdev.of_node = dev_of_node(dev); + + return devm_reset_controller_register(dev, &rst_data->rcdev); +} + static int mt7621_clk_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; @@ -424,6 +497,12 @@ static int mt7621_clk_probe(struct platform_device *pdev) return ret; } + ret = mt7621_reset_init(dev, priv->sysc); + if (ret) { + dev_err(dev, "Could not init reset controller\n"); + return ret; + } + count = ARRAY_SIZE(mt7621_clks_base) + ARRAY_SIZE(mt7621_fixed_clks) + ARRAY_SIZE(mt7621_gates); clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, count), @@ -485,4 +564,9 @@ static struct platform_driver mt7621_clk_driver = { .of_match_table = mt7621_clk_of_match, }, }; -builtin_platform_driver(mt7621_clk_driver); + +static int __init mt7621_clk_reset_init(void) +{ + return platform_driver_register(&mt7621_clk_driver); +} +arch_initcall(mt7621_clk_reset_init); From patchwork Mon Jan 10 08:39:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 12708400 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37BCBC433F5 for ; Mon, 10 Jan 2022 08:41:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241699AbiAJIlX (ORCPT ); Mon, 10 Jan 2022 03:41:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37098 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241070AbiAJIjU (ORCPT ); Mon, 10 Jan 2022 03:39:20 -0500 Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [IPv6:2a00:1450:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 79019C03327E; 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[81.44.130.198]) by smtp.gmail.com with ESMTPSA id m7sm508926wmi.13.2022.01.10.00.39.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Jan 2022 00:39:15 -0800 (PST) From: Sergio Paracuellos To: linux-clk@vger.kernel.org Cc: john@phrozen.org, linux-staging@lists.linux.dev, gregkh@linuxfoundation.org, neil@brown.name, p.zabel@pengutronix.de, linux-kernel@vger.kernel.org, sboyd@kernel.org Subject: [PATCH v6 4/4] staging: mt7621-dts: align resets with binding documentation Date: Mon, 10 Jan 2022 09:39:10 +0100 Message-Id: <20220110083910.1351020-5-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220110083910.1351020-1-sergio.paracuellos@gmail.com> References: <20220110083910.1351020-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Binding documentation for compatible 'mediatek,mt7621-sysc' has been updated to be used as a reset provider. Align reset related bits and system controller node with binding documentation along the dtsi file. Signed-off-by: Sergio Paracuellos --- drivers/staging/mt7621-dts/mt7621.dtsi | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi index 644a65d1a6a1..d72673c91dc2 100644 --- a/drivers/staging/mt7621-dts/mt7621.dtsi +++ b/drivers/staging/mt7621-dts/mt7621.dtsi @@ -2,6 +2,7 @@ #include #include #include +#include / { #address-cells = <1>; @@ -67,6 +68,7 @@ sysc: syscon@0 { compatible = "mediatek,mt7621-sysc", "syscon"; reg = <0x0 0x100>; #clock-cells = <1>; + #reset-cells = <1>; ralink,memctl = <&memc>; clock-output-names = "xtal", "cpu", "bus", "50m", "125m", "150m", @@ -96,7 +98,7 @@ i2c: i2c@900 { clocks = <&sysc MT7621_CLK_I2C>; clock-names = "i2c"; - resets = <&rstctrl 16>; + resets = <&sysc MT7621_RST_I2C>; reset-names = "i2c"; #address-cells = <1>; @@ -137,7 +139,7 @@ spi0: spi@b00 { clocks = <&sysc MT7621_CLK_SPI>; clock-names = "spi"; - resets = <&rstctrl 18>; + resets = <&sysc MT7621_RST_SPI>; reset-names = "spi"; #address-cells = <1>; @@ -234,11 +236,6 @@ pinmux { }; }; - rstctrl: rstctrl { - compatible = "ralink,rt2880-reset"; - #reset-cells = <1>; - }; - sdhci: sdhci@1e130000 { status = "disabled"; @@ -317,7 +314,7 @@ ethernet: ethernet@1e100000 { #address-cells = <1>; #size-cells = <0>; - resets = <&rstctrl 6 &rstctrl 23>; + resets = <&sysc MT7621_RST_FE &sysc MT7621_RST_ETH>; reset-names = "fe", "eth"; interrupt-parent = <&gic>; @@ -362,7 +359,7 @@ switch0: switch0@0 { #size-cells = <0>; reg = <0>; mediatek,mcm; - resets = <&rstctrl 2>; + resets = <&sysc MT7621_RST_MCM>; reset-names = "mcm"; interrupt-controller; #interrupt-cells = <1>; @@ -448,7 +445,7 @@ pcie@0,0 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>; - resets = <&rstctrl 24>; + resets = <&sysc MT7621_RST_PCIE0>; clocks = <&sysc MT7621_CLK_PCIE0>; phys = <&pcie0_phy 1>; phy-names = "pcie-phy0"; @@ -463,7 +460,7 @@ pcie@1,0 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>; - resets = <&rstctrl 25>; + resets = <&sysc MT7621_RST_PCIE1>; clocks = <&sysc MT7621_CLK_PCIE1>; phys = <&pcie0_phy 1>; phy-names = "pcie-phy1"; @@ -478,7 +475,7 @@ pcie@2,0 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; - resets = <&rstctrl 26>; + resets = <&sysc MT7621_RST_PCIE2>; clocks = <&sysc MT7621_CLK_PCIE2>; phys = <&pcie2_phy 0>; phy-names = "pcie-phy2";