From patchwork Mon Jan 10 11:10:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 12708586 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 45DB2C433F5 for ; Mon, 10 Jan 2022 11:11:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244487AbiAJLKz (ORCPT ); Mon, 10 Jan 2022 06:10:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44476 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244464AbiAJLKm (ORCPT ); Mon, 10 Jan 2022 06:10:42 -0500 Received: from mail-wr1-x434.google.com (mail-wr1-x434.google.com [IPv6:2a00:1450:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1397FC061751; Mon, 10 Jan 2022 03:10:42 -0800 (PST) Received: by mail-wr1-x434.google.com with SMTP id t28so19268744wrb.4; Mon, 10 Jan 2022 03:10:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9BZOz3rBRK9T1NJYwX4wR3Rx8LIgVrV05ZwydszvJ/w=; b=IZoGetFevexdCPMr9wmIWzK3kSyE3XlPYLgqnt2+w7Vk6nP/d+SxzqhD5+Gj3WUGSi R6HS5Mc5HUbM5sh5+HLXuZo+Wqcg8C1EdMprgIaChKXWZ2RAiLJsY9u92AKzoO+QW7hL H+aN89QiLW3sjzx5v9KtkvjVK2bk3Seqgys+fXl94DcbPW5qOa38MzA8jRfy7NyzrbJc WAWmOLerHwVzkeU6sZeVN4WiJXoXljGpab0Dgt3WQy8Vci46lFGhC4bxGn49jFgH7Kwy YcMv1MQ8wEFNxPR/zq1+KJowE2ChhBAgnOGgdq3DT72LrH8xON7y0F/8Vvvns6FoWsAG ipbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9BZOz3rBRK9T1NJYwX4wR3Rx8LIgVrV05ZwydszvJ/w=; b=DQOX5HksC91hqg7jJnAVHsXqbagcTKxaeHRoNK2tBu8Y6F7Qy3NaAECELwNjr5D6e4 +jhn1+0LoIW7zQw+VqYodTY0vkyFi9wQIEDAGPDMgbumTOBb0mzmi0KWxxc2IBGxlFky vKZ5wVIZ9pT0xKaYF4LjX9uAvWxpPnvL+uLM3lX2CmHgM8ZwU1QhUEEIcui8n1H6trbj datx4m6l9xOseMbvV2ZUr0TQbtewzFH76KF1se3LQO1bY3K/0NBfd83iNU6/SQGLYVuC 6OhhkJ6TkjwiOR7YKH0WKa323k10KnSX7YRGo3VwHgf7tCijwzPyljsxtIYEWntFJxw5 oEqA== X-Gm-Message-State: AOAM531FQnvrUpIpxk0hiLgCj4EAiAzsD4Kx4nSEp34mselOscYxBEZ4 zcpLJEm3b5kmNn92UFAbmFyi7SXeVkOfRg== X-Google-Smtp-Source: ABdhPJzYiVaMPTldnZT9Y7Zg8N5WZr4CYFjcg8SxU5eVhiv8fK8T2FTxBAoQbwBjE0Qt1IBbgo8fFA== X-Received: by 2002:a5d:494f:: with SMTP id r15mr3060751wrs.388.1641813040424; Mon, 10 Jan 2022 03:10:40 -0800 (PST) Received: from localhost.localdomain (198.red-81-44-130.dynamicip.rima-tde.net. [81.44.130.198]) by smtp.gmail.com with ESMTPSA id x8sm6256733wmj.44.2022.01.10.03.10.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Jan 2022 03:10:39 -0800 (PST) From: Sergio Paracuellos To: linux-clk@vger.kernel.org Cc: john@phrozen.org, linux-staging@lists.linux.dev, gregkh@linuxfoundation.org, neil@brown.name, p.zabel@pengutronix.de, linux-kernel@vger.kernel.org, sboyd@kernel.org, Rob Herring Subject: [PATCH v7 1/4] dt-bindings: reset: add dt binding header for Mediatek MT7621 resets Date: Mon, 10 Jan 2022 12:10:33 +0100 Message-Id: <20220110111036.1380288-2-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220110111036.1380288-1-sergio.paracuellos@gmail.com> References: <20220110111036.1380288-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add dt binding header for resets lines in Mediatek MT7621 SoCs. Acked-by: Rob Herring Signed-off-by: Sergio Paracuellos --- include/dt-bindings/reset/mt7621-reset.h | 37 ++++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 include/dt-bindings/reset/mt7621-reset.h diff --git a/include/dt-bindings/reset/mt7621-reset.h b/include/dt-bindings/reset/mt7621-reset.h new file mode 100644 index 000000000000..7572c6b41453 --- /dev/null +++ b/include/dt-bindings/reset/mt7621-reset.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021 Sergio Paracuellos + * Author: Sergio Paracuellos + */ + +#ifndef DT_BINDING_MT7621_RESET_H +#define DT_BINDING_MT7621_RESET_H + +#define MT7621_RST_SYS 0 +#define MT7621_RST_MCM 2 +#define MT7621_RST_HSDMA 5 +#define MT7621_RST_FE 6 +#define MT7621_RST_SPDIFTX 7 +#define MT7621_RST_TIMER 8 +#define MT7621_RST_INT 9 +#define MT7621_RST_MC 10 +#define MT7621_RST_PCM 11 +#define MT7621_RST_PIO 13 +#define MT7621_RST_GDMA 14 +#define MT7621_RST_NFI 15 +#define MT7621_RST_I2C 16 +#define MT7621_RST_I2S 17 +#define MT7621_RST_SPI 18 +#define MT7621_RST_UART1 19 +#define MT7621_RST_UART2 20 +#define MT7621_RST_UART3 21 +#define MT7621_RST_ETH 23 +#define MT7621_RST_PCIE0 24 +#define MT7621_RST_PCIE1 25 +#define MT7621_RST_PCIE2 26 +#define MT7621_RST_AUX_STCK 28 +#define MT7621_RST_CRYPTO 29 +#define MT7621_RST_SDXC 30 +#define MT7621_RST_PPE 31 + +#endif /* DT_BINDING_MT7621_RESET_H */ From patchwork Mon Jan 10 11:10:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 12708587 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E84C8C433EF for ; Mon, 10 Jan 2022 11:11:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244501AbiAJLLC (ORCPT ); Mon, 10 Jan 2022 06:11:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44482 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244468AbiAJLKn (ORCPT ); Mon, 10 Jan 2022 06:10:43 -0500 Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 145FFC061757; Mon, 10 Jan 2022 03:10:43 -0800 (PST) Received: by mail-wr1-x42e.google.com with SMTP id s1so26063006wra.6; Mon, 10 Jan 2022 03:10:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7Y+fkGNLGqdfMAAiGU48wuA+SIBMA19TPv5MMqKzhcc=; b=WEPjMZtOAXr7fZIRboXRNF6OMOzS5/39hE9F4zXCYn2EdfnL786zpdkn28+k8Fidky RwnQeCtuTO8AauTUqcvS0suoNpCm/R5Gy57MpjQd7W9nzIMyUS4Xzug1zthyBgH9LRo4 svZqq2ZJtU2z9RTKt9ibxBu7W6GbdzGjpGu/YREmAIIjJOZ8ghee7LsjVlmYHk1BzV5O E0B95Zjybm1NmMJK4J4xfholJEsZ5K9iotEbv1T3UCmSk6EYIMFsejR2wSO8POCIh/ZM sEa+79OjjjSCtk5n+fMdnSKEECJfyjkbeypV2SSEE0e14J1/42e38OEAEcCfEWR4fBTi rryQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7Y+fkGNLGqdfMAAiGU48wuA+SIBMA19TPv5MMqKzhcc=; b=RqjkY9bsxNzN42NX0PuRoxDahm4XocuCQqu5Vn7qRYED+RSrZQLOWlhQU4lLKYtiN9 fUmp3YzDH3VRZZe71K2BJeT7dXuIp9zklzbWX934lh85qRz9jO5J58J+CTUs1bbv8juu VwkH4Sl9nV1Kp/ZBD27VpOPDf+bRixIwzDEpxuTMBzQ6WFqEn6m+QkywlcQKQJqIfXDC jcp0rJo6rJjQRezDToCNKLNQ0DqklST3FBzmLBSPu8L3nB397VsgTqs7qquUDq93h/kl Stt6n8a0jLQ/KEA3B72fU15WQAhGBOar7wCC5qy5HG6GbhK+tzK4VZHTR22e0ZW16ics md9w== X-Gm-Message-State: AOAM533KdSpq3XP3Fbj8i8gxGAWQSK3jcf/DNvo9XoA6/Bv5uDCI14ak nKbioFlnHP48IdlPTFIAMdq5SfH0yYwgsw== X-Google-Smtp-Source: ABdhPJwW9kIN/9Mh/TG8AKFuyWScF5czudxJwo1Pcxa3oPDf+2UX/F48pWPW1R/oPWWcYS1b30TCLQ== X-Received: by 2002:adf:a443:: with SMTP id e3mr3841195wra.183.1641813041463; Mon, 10 Jan 2022 03:10:41 -0800 (PST) Received: from localhost.localdomain (198.red-81-44-130.dynamicip.rima-tde.net. [81.44.130.198]) by smtp.gmail.com with ESMTPSA id x8sm6256733wmj.44.2022.01.10.03.10.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Jan 2022 03:10:41 -0800 (PST) From: Sergio Paracuellos To: linux-clk@vger.kernel.org Cc: john@phrozen.org, linux-staging@lists.linux.dev, gregkh@linuxfoundation.org, neil@brown.name, p.zabel@pengutronix.de, linux-kernel@vger.kernel.org, sboyd@kernel.org, Rob Herring Subject: [PATCH v7 2/4] dt-bindings: clock: mediatek,mt7621-sysc: add '#reset-cells' property Date: Mon, 10 Jan 2022 12:10:34 +0100 Message-Id: <20220110111036.1380288-3-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220110111036.1380288-1-sergio.paracuellos@gmail.com> References: <20220110111036.1380288-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Make system controller a reset provider for all the peripherals in the MT7621 SoC adding '#reset-cells' property. Acked-by: Rob Herring Signed-off-by: Sergio Paracuellos --- .../bindings/clock/mediatek,mt7621-sysc.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml index 915f84efd763..0c0b0ae5e2ac 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml @@ -22,6 +22,11 @@ description: | The clocks are provided inside a system controller node. + This node is also a reset provider for all the peripherals. + + Reset related bits are defined in: + [2]: . + properties: compatible: items: @@ -37,6 +42,12 @@ properties: clocks. const: 1 + "#reset-cells": + description: + The first cell indicates the reset bit within the register, see + [2] for available resets. + const: 1 + ralink,memctl: $ref: /schemas/types.yaml#/definitions/phandle description: @@ -61,6 +72,7 @@ examples: compatible = "mediatek,mt7621-sysc", "syscon"; reg = <0x0 0x100>; #clock-cells = <1>; + #reset-cells = <1>; ralink,memctl = <&memc>; clock-output-names = "xtal", "cpu", "bus", "50m", "125m", "150m", From patchwork Mon Jan 10 11:10:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 12708588 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87B34C433F5 for ; Mon, 10 Jan 2022 11:11:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244511AbiAJLLF (ORCPT ); Mon, 10 Jan 2022 06:11:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44386 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244449AbiAJLKo (ORCPT ); Mon, 10 Jan 2022 06:10:44 -0500 Received: from mail-wr1-x433.google.com (mail-wr1-x433.google.com [IPv6:2a00:1450:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 12411C06173F; Mon, 10 Jan 2022 03:10:44 -0800 (PST) Received: by mail-wr1-x433.google.com with SMTP id x4so851453wru.7; Mon, 10 Jan 2022 03:10:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/ICLpvIKc6Y/daWQpRiyo0jffnPkaJB8CpiTYNoD1sk=; b=hmaVuoel0i48fMrYMjoukOnx0rmHDSsZr3ZfN8NpjTpceUFxKS1f6uO/570VySWYGp n7OEQmZKkYIVbKWQmbs4gSBf5d1SVGxlpHj6m2gphbvGCLnu9+Z4lTo5bSrKtxd8Nxhe ygploc+4djnPTcifUfo8oSEoQMhSEE6OH562BF4fBUjjJyfic1lGbKZPUDEHB2XVXxqp wmPxlA37ZpWiIHX7rxQtTVSm/ie6m4mYWXkA9nmJcsuOr7BwfwVEKyjWk5+JFluGLJe7 7tLD4Ki+sP9SFDjIX9xVviKCwV54aAGrFKyaIYd8zBdFd92nM7Bm8BdiQ6T/zpUOGI2Y YsHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/ICLpvIKc6Y/daWQpRiyo0jffnPkaJB8CpiTYNoD1sk=; b=M9rRT0SBomYdhxVd6PiP5dnVr7n1ZQY/dUl88Q+jwPQjf2CRMNKFF74tABqCYdZsOv WHWMa6dDObW/7qB4S8EjgYCXaqbM3D0i1NpJojqOR5GxKaVmyLTURUFVqw/g6+XDSA6p qZYkAqa0IAV3Q0aF2vZr8XXnRYa6dsWk89EK+GaLk1VHaLRU7C+PvObnHLOf/GAho6Hq JnIyhLhsy5MdYTYpD6PBq22J3RwY5q140ndhzz1/umDE8X4twGhSbWdSEOmHhZ4O3OAH vHBZJtnVY4gFCWXOpCs1RDpyLH4qXxgD0YB5YV80g7eDBNKuoMdh7g4ARI5wPpVP10rt RHoQ== X-Gm-Message-State: AOAM531EtCBHWRdKVtdviBT76+6DVIb12PogBtreRAhyKlb8d/SRZKmr jKdynqan7QcGImxAXwU/DFYZFks8XsB4/Q== X-Google-Smtp-Source: ABdhPJy+XL48SiTYf3Hj0SWhysnGZ5qzWV1JknCWr7TscmkiSjwTRq8/F01apZqfJOFoLqBYWbsv8w== X-Received: by 2002:a05:6000:1acd:: with SMTP id i13mr64121032wry.406.1641813042437; Mon, 10 Jan 2022 03:10:42 -0800 (PST) Received: from localhost.localdomain (198.red-81-44-130.dynamicip.rima-tde.net. [81.44.130.198]) by smtp.gmail.com with ESMTPSA id x8sm6256733wmj.44.2022.01.10.03.10.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Jan 2022 03:10:42 -0800 (PST) From: Sergio Paracuellos To: linux-clk@vger.kernel.org Cc: john@phrozen.org, linux-staging@lists.linux.dev, gregkh@linuxfoundation.org, neil@brown.name, p.zabel@pengutronix.de, linux-kernel@vger.kernel.org, sboyd@kernel.org Subject: [PATCH v7 3/4] clk: ralink: make system controller node a reset provider Date: Mon, 10 Jan 2022 12:10:35 +0100 Message-Id: <20220110111036.1380288-4-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220110111036.1380288-1-sergio.paracuellos@gmail.com> References: <20220110111036.1380288-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org MT7621 system controller node is already providing the clocks for the whole system but must also serve as a reset provider. Hence, add reset controller related code to the clock driver itself. To get resets properly ready for the rest of the world we need to move platform driver initialization process to 'arch_initcall'. CC: Philipp Zabel Signed-off-by: Sergio Paracuellos --- drivers/clk/ralink/clk-mt7621.c | 92 ++++++++++++++++++++++++++++++++- 1 file changed, 91 insertions(+), 1 deletion(-) diff --git a/drivers/clk/ralink/clk-mt7621.c b/drivers/clk/ralink/clk-mt7621.c index a2c045390f00..7ed121574bad 100644 --- a/drivers/clk/ralink/clk-mt7621.c +++ b/drivers/clk/ralink/clk-mt7621.c @@ -11,14 +11,17 @@ #include #include #include +#include #include #include +#include /* Configuration registers */ #define SYSC_REG_SYSTEM_CONFIG0 0x10 #define SYSC_REG_SYSTEM_CONFIG1 0x14 #define SYSC_REG_CLKCFG0 0x2c #define SYSC_REG_CLKCFG1 0x30 +#define SYSC_REG_RESET_CTRL 0x34 #define SYSC_REG_CUR_CLK_STS 0x44 #define MEMC_REG_CPU_PLL 0x648 @@ -398,6 +401,82 @@ static void __init mt7621_clk_init(struct device_node *node) } CLK_OF_DECLARE_DRIVER(mt7621_clk, "mediatek,mt7621-sysc", mt7621_clk_init); +struct mt7621_rst { + struct reset_controller_dev rcdev; + struct regmap *sysc; +}; + +static struct mt7621_rst *to_mt7621_rst(struct reset_controller_dev *dev) +{ + return container_of(dev, struct mt7621_rst, rcdev); +} + +static int mt7621_assert_device(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct mt7621_rst *data = to_mt7621_rst(rcdev); + struct regmap *sysc = data->sysc; + + return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), BIT(id)); +} + +static int mt7621_deassert_device(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct mt7621_rst *data = to_mt7621_rst(rcdev); + struct regmap *sysc = data->sysc; + + return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), 0); +} + +static int mt7621_reset_device(struct reset_controller_dev *rcdev, + unsigned long id) +{ + int ret; + + ret = mt7621_assert_device(rcdev, id); + if (ret < 0) + return ret; + + return mt7621_deassert_device(rcdev, id); +} + +static int mt7621_rst_xlate(struct reset_controller_dev *rcdev, + const struct of_phandle_args *reset_spec) +{ + unsigned long id = reset_spec->args[0]; + + if (id == MT7621_RST_SYS) + return -EINVAL; + + return id; +} + +static const struct reset_control_ops reset_ops = { + .reset = mt7621_reset_device, + .assert = mt7621_assert_device, + .deassert = mt7621_deassert_device +}; + +static int mt7621_reset_init(struct device *dev, struct regmap *sysc) +{ + struct mt7621_rst *rst_data; + + rst_data = devm_kzalloc(dev, sizeof(*rst_data), GFP_KERNEL); + if (!rst_data) + return -ENOMEM; + + rst_data->sysc = sysc; + rst_data->rcdev.ops = &reset_ops; + rst_data->rcdev.owner = THIS_MODULE; + rst_data->rcdev.nr_resets = 32; + rst_data->rcdev.of_reset_n_cells = 1; + rst_data->rcdev.of_xlate = mt7621_rst_xlate; + rst_data->rcdev.of_node = dev_of_node(dev); + + return devm_reset_controller_register(dev, &rst_data->rcdev); +} + static int mt7621_clk_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; @@ -424,6 +503,12 @@ static int mt7621_clk_probe(struct platform_device *pdev) return ret; } + ret = mt7621_reset_init(dev, priv->sysc); + if (ret) { + dev_err(dev, "Could not init reset controller\n"); + return ret; + } + count = ARRAY_SIZE(mt7621_clks_base) + ARRAY_SIZE(mt7621_fixed_clks) + ARRAY_SIZE(mt7621_gates); clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, count), @@ -485,4 +570,9 @@ static struct platform_driver mt7621_clk_driver = { .of_match_table = mt7621_clk_of_match, }, }; -builtin_platform_driver(mt7621_clk_driver); + +static int __init mt7621_clk_reset_init(void) +{ + return platform_driver_register(&mt7621_clk_driver); +} +arch_initcall(mt7621_clk_reset_init); From patchwork Mon Jan 10 11:10:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 12708589 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0D64C433EF for ; Mon, 10 Jan 2022 11:11:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244464AbiAJLLG (ORCPT ); Mon, 10 Jan 2022 06:11:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44490 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244448AbiAJLKp (ORCPT ); Mon, 10 Jan 2022 06:10:45 -0500 Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 08A75C061759; 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[81.44.130.198]) by smtp.gmail.com with ESMTPSA id x8sm6256733wmj.44.2022.01.10.03.10.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Jan 2022 03:10:42 -0800 (PST) From: Sergio Paracuellos To: linux-clk@vger.kernel.org Cc: john@phrozen.org, linux-staging@lists.linux.dev, gregkh@linuxfoundation.org, neil@brown.name, p.zabel@pengutronix.de, linux-kernel@vger.kernel.org, sboyd@kernel.org Subject: [PATCH v7 4/4] staging: mt7621-dts: align resets with binding documentation Date: Mon, 10 Jan 2022 12:10:36 +0100 Message-Id: <20220110111036.1380288-5-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220110111036.1380288-1-sergio.paracuellos@gmail.com> References: <20220110111036.1380288-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Binding documentation for compatible 'mediatek,mt7621-sysc' has been updated to be used as a reset provider. Align reset related bits and system controller node with binding documentation along the dtsi file. Signed-off-by: Sergio Paracuellos --- drivers/staging/mt7621-dts/mt7621.dtsi | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi index 644a65d1a6a1..d72673c91dc2 100644 --- a/drivers/staging/mt7621-dts/mt7621.dtsi +++ b/drivers/staging/mt7621-dts/mt7621.dtsi @@ -2,6 +2,7 @@ #include #include #include +#include / { #address-cells = <1>; @@ -67,6 +68,7 @@ sysc: syscon@0 { compatible = "mediatek,mt7621-sysc", "syscon"; reg = <0x0 0x100>; #clock-cells = <1>; + #reset-cells = <1>; ralink,memctl = <&memc>; clock-output-names = "xtal", "cpu", "bus", "50m", "125m", "150m", @@ -96,7 +98,7 @@ i2c: i2c@900 { clocks = <&sysc MT7621_CLK_I2C>; clock-names = "i2c"; - resets = <&rstctrl 16>; + resets = <&sysc MT7621_RST_I2C>; reset-names = "i2c"; #address-cells = <1>; @@ -137,7 +139,7 @@ spi0: spi@b00 { clocks = <&sysc MT7621_CLK_SPI>; clock-names = "spi"; - resets = <&rstctrl 18>; + resets = <&sysc MT7621_RST_SPI>; reset-names = "spi"; #address-cells = <1>; @@ -234,11 +236,6 @@ pinmux { }; }; - rstctrl: rstctrl { - compatible = "ralink,rt2880-reset"; - #reset-cells = <1>; - }; - sdhci: sdhci@1e130000 { status = "disabled"; @@ -317,7 +314,7 @@ ethernet: ethernet@1e100000 { #address-cells = <1>; #size-cells = <0>; - resets = <&rstctrl 6 &rstctrl 23>; + resets = <&sysc MT7621_RST_FE &sysc MT7621_RST_ETH>; reset-names = "fe", "eth"; interrupt-parent = <&gic>; @@ -362,7 +359,7 @@ switch0: switch0@0 { #size-cells = <0>; reg = <0>; mediatek,mcm; - resets = <&rstctrl 2>; + resets = <&sysc MT7621_RST_MCM>; reset-names = "mcm"; interrupt-controller; #interrupt-cells = <1>; @@ -448,7 +445,7 @@ pcie@0,0 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>; - resets = <&rstctrl 24>; + resets = <&sysc MT7621_RST_PCIE0>; clocks = <&sysc MT7621_CLK_PCIE0>; phys = <&pcie0_phy 1>; phy-names = "pcie-phy0"; @@ -463,7 +460,7 @@ pcie@1,0 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>; - resets = <&rstctrl 25>; + resets = <&sysc MT7621_RST_PCIE1>; clocks = <&sysc MT7621_CLK_PCIE1>; phys = <&pcie0_phy 1>; phy-names = "pcie-phy1"; @@ -478,7 +475,7 @@ pcie@2,0 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; - resets = <&rstctrl 26>; + resets = <&sysc MT7621_RST_PCIE2>; clocks = <&sysc MT7621_CLK_PCIE2>; phys = <&pcie2_phy 0>; phy-names = "pcie-phy2";