From patchwork Mon Jan 10 11:49:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 12708599 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 41D60C43217 for ; Mon, 10 Jan 2022 11:50:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245070AbiAJLud (ORCPT ); Mon, 10 Jan 2022 06:50:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53556 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245086AbiAJLtf (ORCPT ); Mon, 10 Jan 2022 06:49:35 -0500 Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CA656C061759; Mon, 10 Jan 2022 03:49:34 -0800 (PST) Received: by mail-wr1-x42f.google.com with SMTP id r9so24475794wrg.0; Mon, 10 Jan 2022 03:49:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9BZOz3rBRK9T1NJYwX4wR3Rx8LIgVrV05ZwydszvJ/w=; b=lr5Z+SCtLVTeLyQ0yAPGeriul3M/sb48r09iMN2fpfsN9I4KSJrxq8ZAVNGhny/guE NbGRpskBFwrAnY7k/Z6t+abNFO+UDUJls9DtSpJ+48fnAI/p8X4ZEZ+bD6i6ULFhFaH2 z8SX21ZoICYKFa+nh8y3GmgnLh4DmnXUQjIBIh8rdRcO8DUGAU8rE/d8x1MWO9JQb0+9 YsTgnVAH09ap7BgXNtGOSHPiBGvIUOH+UP0Ee8IjxJamjNFv3DnSf0+/bgyb1FsCwYDp gYCoPXqgORScffFlDqdTnyZuuDxebRagdAVBTxykxozU4sILYUOTcFV24IxC2OVHQISU iu8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9BZOz3rBRK9T1NJYwX4wR3Rx8LIgVrV05ZwydszvJ/w=; b=26bklaCURiB+M5d5FsGQIL0ovTDVdyCCyuZBvAbhfI5XEILuhwzEh7nbAbDWStoZSQ bV6y5NthBsFg/Lvh2LQI/AC/cLA4BNgJCUxnUgF2sixsMG30uG1YBvj3S4ckG8dFtWiR G5pCtd/DfEml++BZpwCbxyLtLrPvRPGud7rFwLz7/LNGvnHj8IgaPIIrbBxWL+9wQzS2 inWujjdSAFdmQB/q6LH359LTYHR7nj9KQu90/Tmo7jozqp+Uyx3UU44ktIoyUpN2fA5c EU+KgxZ7MNxrCc0qToca2gmXlz33hZScpekWi47xx8pMVZpz7Z6e8fGCGnD9NR4e1hOk kVhg== X-Gm-Message-State: AOAM532txeyFTyUKEeoKE+ImPsmXi6t0bcWKEoyC0LqG4U3XvHNM3iIh 1VMI7386rVWKAcJFXx3SsZMBUbjk17tPpA== X-Google-Smtp-Source: ABdhPJzYRkhfIUUAVvWoSVT58H+K9Hf2lyW+S7Dp7ffh/c+SDBL/4d6PNn9tY0/XBsBBAJnJJED7Vg== X-Received: by 2002:adf:e8d2:: with SMTP id k18mr65592698wrn.187.1641815373164; Mon, 10 Jan 2022 03:49:33 -0800 (PST) Received: from localhost.localdomain (198.red-81-44-130.dynamicip.rima-tde.net. [81.44.130.198]) by smtp.gmail.com with ESMTPSA id 9sm8090252wrz.90.2022.01.10.03.49.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Jan 2022 03:49:32 -0800 (PST) From: Sergio Paracuellos To: linux-clk@vger.kernel.org Cc: john@phrozen.org, linux-staging@lists.linux.dev, gregkh@linuxfoundation.org, neil@brown.name, p.zabel@pengutronix.de, linux-kernel@vger.kernel.org, sboyd@kernel.org, Rob Herring Subject: [PATCH v8 1/4] dt-bindings: reset: add dt binding header for Mediatek MT7621 resets Date: Mon, 10 Jan 2022 12:49:27 +0100 Message-Id: <20220110114930.1406665-2-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220110114930.1406665-1-sergio.paracuellos@gmail.com> References: <20220110114930.1406665-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add dt binding header for resets lines in Mediatek MT7621 SoCs. Acked-by: Rob Herring Signed-off-by: Sergio Paracuellos --- include/dt-bindings/reset/mt7621-reset.h | 37 ++++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 include/dt-bindings/reset/mt7621-reset.h diff --git a/include/dt-bindings/reset/mt7621-reset.h b/include/dt-bindings/reset/mt7621-reset.h new file mode 100644 index 000000000000..7572c6b41453 --- /dev/null +++ b/include/dt-bindings/reset/mt7621-reset.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021 Sergio Paracuellos + * Author: Sergio Paracuellos + */ + +#ifndef DT_BINDING_MT7621_RESET_H +#define DT_BINDING_MT7621_RESET_H + +#define MT7621_RST_SYS 0 +#define MT7621_RST_MCM 2 +#define MT7621_RST_HSDMA 5 +#define MT7621_RST_FE 6 +#define MT7621_RST_SPDIFTX 7 +#define MT7621_RST_TIMER 8 +#define MT7621_RST_INT 9 +#define MT7621_RST_MC 10 +#define MT7621_RST_PCM 11 +#define MT7621_RST_PIO 13 +#define MT7621_RST_GDMA 14 +#define MT7621_RST_NFI 15 +#define MT7621_RST_I2C 16 +#define MT7621_RST_I2S 17 +#define MT7621_RST_SPI 18 +#define MT7621_RST_UART1 19 +#define MT7621_RST_UART2 20 +#define MT7621_RST_UART3 21 +#define MT7621_RST_ETH 23 +#define MT7621_RST_PCIE0 24 +#define MT7621_RST_PCIE1 25 +#define MT7621_RST_PCIE2 26 +#define MT7621_RST_AUX_STCK 28 +#define MT7621_RST_CRYPTO 29 +#define MT7621_RST_SDXC 30 +#define MT7621_RST_PPE 31 + +#endif /* DT_BINDING_MT7621_RESET_H */ From patchwork Mon Jan 10 11:49:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 12708601 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C1CFC4332F for ; Mon, 10 Jan 2022 11:50:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245134AbiAJLuh (ORCPT ); Mon, 10 Jan 2022 06:50:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53564 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245088AbiAJLtg (ORCPT ); Mon, 10 Jan 2022 06:49:36 -0500 Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C5662C06175A; Mon, 10 Jan 2022 03:49:35 -0800 (PST) Received: by mail-wr1-x436.google.com with SMTP id k30so8659427wrd.9; Mon, 10 Jan 2022 03:49:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7Y+fkGNLGqdfMAAiGU48wuA+SIBMA19TPv5MMqKzhcc=; b=lVXip1dWvHl5uaJX4J+UpjVH/1Gtu4QhKzJ/mCA/2T5/C0W0OILrKY8FDo7hupDADK C2hcH3i3EQ3d9O5s0Ijs1UivEHbEevw7J/Avmq4qHeI7TDblkFWY+vPPZLem+oK5VwoZ eMCKpcDn0khEF24WtIBlGubYN2LmANMlqXM8AhiJoVM/HuAQj3alqMg+itaca6H2r624 3elRU5AELfurEpaHRftnwzO5ppJ3bvx6eVmWIOvuSqyqd/eqRN6eABAuw8m3Xi+pK1nk Fzqqlh15ZWObe/iHkyNmFCJdktmF65AvABcRHm6vwGgJDlX/Ql6vXrB2kU5DkxTzRaPQ cI9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7Y+fkGNLGqdfMAAiGU48wuA+SIBMA19TPv5MMqKzhcc=; b=3WJEXMmWBUwSLhSBOtGsyZkRC9UzLHJiCnq5bu092qD7/kgghqM8ittWj98A2VMrmP pvs3FDVEKBdHxMJckNrUUXD5ignbmNucAUV8ow1XLPiHA7KIw/lFBj51zCCNXnWBKB6/ NrALAZm+klQeGKdxhTmPIit85vst3iHq9BtOdt2ESp3zhygEBqhnwRbOJf8njEjB6pwV iDuN/ND2w0hqVrUCcR5MR/gttZcreJhvuHF0zW4lpk/Sg9ysh+aVl7VCr+itvRsR+Y3a cHTDKp864u4BD4wRLA6S1ZjG5a0I6WJgm+GD0lwSoO/BFmfoH8nY4RO1/UfuT4OpPoOq Ng8w== X-Gm-Message-State: AOAM533oghEDMdfrihwi2F36ZXWhEcEhHg1QZQSP8OYalDPzvyDf1OQ0 A1yI8vBA4lAhmjlxvyVWR6VMRLm666c/gQ== X-Google-Smtp-Source: ABdhPJx0e3sLyqHMqz2xYe//mTRSM6DeViz0IEmgQaHzYtHdudmaf7dxI3j+8ZHcGdpoSWUAXt62GA== X-Received: by 2002:adf:e3c9:: with SMTP id k9mr1398036wrm.193.1641815374165; Mon, 10 Jan 2022 03:49:34 -0800 (PST) Received: from localhost.localdomain (198.red-81-44-130.dynamicip.rima-tde.net. [81.44.130.198]) by smtp.gmail.com with ESMTPSA id 9sm8090252wrz.90.2022.01.10.03.49.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Jan 2022 03:49:33 -0800 (PST) From: Sergio Paracuellos To: linux-clk@vger.kernel.org Cc: john@phrozen.org, linux-staging@lists.linux.dev, gregkh@linuxfoundation.org, neil@brown.name, p.zabel@pengutronix.de, linux-kernel@vger.kernel.org, sboyd@kernel.org, Rob Herring Subject: [PATCH v8 2/4] dt-bindings: clock: mediatek,mt7621-sysc: add '#reset-cells' property Date: Mon, 10 Jan 2022 12:49:28 +0100 Message-Id: <20220110114930.1406665-3-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220110114930.1406665-1-sergio.paracuellos@gmail.com> References: <20220110114930.1406665-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Make system controller a reset provider for all the peripherals in the MT7621 SoC adding '#reset-cells' property. Acked-by: Rob Herring Signed-off-by: Sergio Paracuellos --- .../bindings/clock/mediatek,mt7621-sysc.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml index 915f84efd763..0c0b0ae5e2ac 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml @@ -22,6 +22,11 @@ description: | The clocks are provided inside a system controller node. + This node is also a reset provider for all the peripherals. + + Reset related bits are defined in: + [2]: . + properties: compatible: items: @@ -37,6 +42,12 @@ properties: clocks. const: 1 + "#reset-cells": + description: + The first cell indicates the reset bit within the register, see + [2] for available resets. + const: 1 + ralink,memctl: $ref: /schemas/types.yaml#/definitions/phandle description: @@ -61,6 +72,7 @@ examples: compatible = "mediatek,mt7621-sysc", "syscon"; reg = <0x0 0x100>; #clock-cells = <1>; + #reset-cells = <1>; ralink,memctl = <&memc>; clock-output-names = "xtal", "cpu", "bus", "50m", "125m", "150m", From patchwork Mon Jan 10 11:49:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 12708602 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0AA2C4167B for ; Mon, 10 Jan 2022 11:50:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245175AbiAJLul (ORCPT ); Mon, 10 Jan 2022 06:50:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53568 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245093AbiAJLth (ORCPT ); Mon, 10 Jan 2022 06:49:37 -0500 Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 721EAC06175B; Mon, 10 Jan 2022 03:49:37 -0800 (PST) Received: by mail-wr1-x436.google.com with SMTP id x4so1061063wru.7; Mon, 10 Jan 2022 03:49:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6RA5/HJJmVlMA5txu/YniwjTRZxIND85s5ggXhBk9yU=; b=hab8/uh0IJZLbdjLdpPTpa7bZzxs6tSzo/t4MddfVwKGrmNwr27pBzkn6oVpkCl1Ae RzWRcGGoDIMi2yvJVkjG0a/zT4bdwPB5CbDJ2UsEMeXM0i8Vayj4oqsbsFHd/aa2o1tJ hADFsem9NxuMBriyOO7ZUZZXfXj0W7MM+8QIciIkK+Y0tFuCjzmDDfWaiz1t6Vlf/Yj7 TBrIyez/Ap6GTDYkVckwWEJ7qIxOsyo0DI/hayg2lpmRVjo3aJFuHDIbCBwIoSijQcvZ CIKKp+3hwR7KgJ5KK1IwpgfobgrJHLR+eWA/f/D0/Nl7GeWwgmc8BkeDhpNZI/dWvJnA aaZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6RA5/HJJmVlMA5txu/YniwjTRZxIND85s5ggXhBk9yU=; b=aher3cxutKIEVQFAHjeCrTu65irSGhOTdpnZaPR7zUb3vLvZaNmKnb8uGr01NVOW7d kDyOgHe9YVd4lzNI7TbtTEcdlx4m75jTBaRHYfwO1SyIQMYJGaZj9jViyeBmEuEBvVCh eJ4fKL1CXxeK90/dCgH5e88za4gH6zDfLyB4QKQI+aylHhjSOkaZQ0Qa+w8nW+udJKrj 02Z8lB5g2UsqItFQtE2aoU+gbGUOmpTo9+ExUDWCpjriSq8EApy9/zPkqYNyVGUTBcK0 tSPNvuoQAr9SBWiBgZqFvXgGRRRZF2pGufFLQeaYuagPtCOYeTBRWwza7ZflKOh/wxoW lBZQ== X-Gm-Message-State: AOAM532/RiTVmUqOg1ReOJ831cg8tYRJHvmRhsCeJCYvxar2shbuARDP dfsVi/sSQmnp+xu6bYWnJmVRVmK9h47Tdw== X-Google-Smtp-Source: ABdhPJw1/pLJqo/haicWXi1EcmsfpsK9GX+kjxiMkCdLXaTAg9GL8dmaFWRwHoNhpuQDCAbyKhp76w== X-Received: by 2002:adf:ebc5:: with SMTP id v5mr64843552wrn.194.1641815375091; Mon, 10 Jan 2022 03:49:35 -0800 (PST) Received: from localhost.localdomain (198.red-81-44-130.dynamicip.rima-tde.net. [81.44.130.198]) by smtp.gmail.com with ESMTPSA id 9sm8090252wrz.90.2022.01.10.03.49.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Jan 2022 03:49:34 -0800 (PST) From: Sergio Paracuellos To: linux-clk@vger.kernel.org Cc: john@phrozen.org, linux-staging@lists.linux.dev, gregkh@linuxfoundation.org, neil@brown.name, p.zabel@pengutronix.de, linux-kernel@vger.kernel.org, sboyd@kernel.org Subject: [PATCH v8 3/4] clk: ralink: make system controller node a reset provider Date: Mon, 10 Jan 2022 12:49:29 +0100 Message-Id: <20220110114930.1406665-4-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220110114930.1406665-1-sergio.paracuellos@gmail.com> References: <20220110114930.1406665-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org MT7621 system controller node is already providing the clocks for the whole system but must also serve as a reset provider. Hence, add reset controller related code to the clock driver itself. To get resets properly ready for the rest of the world we need to move platform driver initialization process to 'arch_initcall'. CC: Philipp Zabel Signed-off-by: Sergio Paracuellos Reviewed-by: Philipp Zabel --- drivers/clk/ralink/clk-mt7621.c | 92 ++++++++++++++++++++++++++++++++- 1 file changed, 91 insertions(+), 1 deletion(-) diff --git a/drivers/clk/ralink/clk-mt7621.c b/drivers/clk/ralink/clk-mt7621.c index a2c045390f00..99256659dd96 100644 --- a/drivers/clk/ralink/clk-mt7621.c +++ b/drivers/clk/ralink/clk-mt7621.c @@ -11,14 +11,17 @@ #include #include #include +#include #include #include +#include /* Configuration registers */ #define SYSC_REG_SYSTEM_CONFIG0 0x10 #define SYSC_REG_SYSTEM_CONFIG1 0x14 #define SYSC_REG_CLKCFG0 0x2c #define SYSC_REG_CLKCFG1 0x30 +#define SYSC_REG_RESET_CTRL 0x34 #define SYSC_REG_CUR_CLK_STS 0x44 #define MEMC_REG_CPU_PLL 0x648 @@ -398,6 +401,82 @@ static void __init mt7621_clk_init(struct device_node *node) } CLK_OF_DECLARE_DRIVER(mt7621_clk, "mediatek,mt7621-sysc", mt7621_clk_init); +struct mt7621_rst { + struct reset_controller_dev rcdev; + struct regmap *sysc; +}; + +static struct mt7621_rst *to_mt7621_rst(struct reset_controller_dev *dev) +{ + return container_of(dev, struct mt7621_rst, rcdev); +} + +static int mt7621_assert_device(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct mt7621_rst *data = to_mt7621_rst(rcdev); + struct regmap *sysc = data->sysc; + + return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), BIT(id)); +} + +static int mt7621_deassert_device(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct mt7621_rst *data = to_mt7621_rst(rcdev); + struct regmap *sysc = data->sysc; + + return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), 0); +} + +static int mt7621_reset_device(struct reset_controller_dev *rcdev, + unsigned long id) +{ + int ret; + + ret = mt7621_assert_device(rcdev, id); + if (ret < 0) + return ret; + + return mt7621_deassert_device(rcdev, id); +} + +static int mt7621_rst_xlate(struct reset_controller_dev *rcdev, + const struct of_phandle_args *reset_spec) +{ + unsigned long id = reset_spec->args[0]; + + if (id == MT7621_RST_SYS || id >= rcdev->nr_resets) + return -EINVAL; + + return id; +} + +static const struct reset_control_ops reset_ops = { + .reset = mt7621_reset_device, + .assert = mt7621_assert_device, + .deassert = mt7621_deassert_device +}; + +static int mt7621_reset_init(struct device *dev, struct regmap *sysc) +{ + struct mt7621_rst *rst_data; + + rst_data = devm_kzalloc(dev, sizeof(*rst_data), GFP_KERNEL); + if (!rst_data) + return -ENOMEM; + + rst_data->sysc = sysc; + rst_data->rcdev.ops = &reset_ops; + rst_data->rcdev.owner = THIS_MODULE; + rst_data->rcdev.nr_resets = 32; + rst_data->rcdev.of_reset_n_cells = 1; + rst_data->rcdev.of_xlate = mt7621_rst_xlate; + rst_data->rcdev.of_node = dev_of_node(dev); + + return devm_reset_controller_register(dev, &rst_data->rcdev); +} + static int mt7621_clk_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; @@ -424,6 +503,12 @@ static int mt7621_clk_probe(struct platform_device *pdev) return ret; } + ret = mt7621_reset_init(dev, priv->sysc); + if (ret) { + dev_err(dev, "Could not init reset controller\n"); + return ret; + } + count = ARRAY_SIZE(mt7621_clks_base) + ARRAY_SIZE(mt7621_fixed_clks) + ARRAY_SIZE(mt7621_gates); clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, count), @@ -485,4 +570,9 @@ static struct platform_driver mt7621_clk_driver = { .of_match_table = mt7621_clk_of_match, }, }; -builtin_platform_driver(mt7621_clk_driver); + +static int __init mt7621_clk_reset_init(void) +{ + return platform_driver_register(&mt7621_clk_driver); +} +arch_initcall(mt7621_clk_reset_init); From patchwork Mon Jan 10 11:49:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 12708603 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC65CC433F5 for ; Mon, 10 Jan 2022 11:50:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245069AbiAJLum (ORCPT ); Mon, 10 Jan 2022 06:50:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53570 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245094AbiAJLti (ORCPT ); Mon, 10 Jan 2022 06:49:38 -0500 Received: from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com [IPv6:2a00:1450:4864:20::32f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 997E7C06175C; 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[81.44.130.198]) by smtp.gmail.com with ESMTPSA id 9sm8090252wrz.90.2022.01.10.03.49.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Jan 2022 03:49:35 -0800 (PST) From: Sergio Paracuellos To: linux-clk@vger.kernel.org Cc: john@phrozen.org, linux-staging@lists.linux.dev, gregkh@linuxfoundation.org, neil@brown.name, p.zabel@pengutronix.de, linux-kernel@vger.kernel.org, sboyd@kernel.org Subject: [PATCH v8 4/4] staging: mt7621-dts: align resets with binding documentation Date: Mon, 10 Jan 2022 12:49:30 +0100 Message-Id: <20220110114930.1406665-5-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220110114930.1406665-1-sergio.paracuellos@gmail.com> References: <20220110114930.1406665-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Binding documentation for compatible 'mediatek,mt7621-sysc' has been updated to be used as a reset provider. Align reset related bits and system controller node with binding documentation along the dtsi file. Signed-off-by: Sergio Paracuellos Reviewed-by: Philipp Zabel Acked-by: Greg Kroah-Hartman --- drivers/staging/mt7621-dts/mt7621.dtsi | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi index 644a65d1a6a1..d72673c91dc2 100644 --- a/drivers/staging/mt7621-dts/mt7621.dtsi +++ b/drivers/staging/mt7621-dts/mt7621.dtsi @@ -2,6 +2,7 @@ #include #include #include +#include / { #address-cells = <1>; @@ -67,6 +68,7 @@ sysc: syscon@0 { compatible = "mediatek,mt7621-sysc", "syscon"; reg = <0x0 0x100>; #clock-cells = <1>; + #reset-cells = <1>; ralink,memctl = <&memc>; clock-output-names = "xtal", "cpu", "bus", "50m", "125m", "150m", @@ -96,7 +98,7 @@ i2c: i2c@900 { clocks = <&sysc MT7621_CLK_I2C>; clock-names = "i2c"; - resets = <&rstctrl 16>; + resets = <&sysc MT7621_RST_I2C>; reset-names = "i2c"; #address-cells = <1>; @@ -137,7 +139,7 @@ spi0: spi@b00 { clocks = <&sysc MT7621_CLK_SPI>; clock-names = "spi"; - resets = <&rstctrl 18>; + resets = <&sysc MT7621_RST_SPI>; reset-names = "spi"; #address-cells = <1>; @@ -234,11 +236,6 @@ pinmux { }; }; - rstctrl: rstctrl { - compatible = "ralink,rt2880-reset"; - #reset-cells = <1>; - }; - sdhci: sdhci@1e130000 { status = "disabled"; @@ -317,7 +314,7 @@ ethernet: ethernet@1e100000 { #address-cells = <1>; #size-cells = <0>; - resets = <&rstctrl 6 &rstctrl 23>; + resets = <&sysc MT7621_RST_FE &sysc MT7621_RST_ETH>; reset-names = "fe", "eth"; interrupt-parent = <&gic>; @@ -362,7 +359,7 @@ switch0: switch0@0 { #size-cells = <0>; reg = <0>; mediatek,mcm; - resets = <&rstctrl 2>; + resets = <&sysc MT7621_RST_MCM>; reset-names = "mcm"; interrupt-controller; #interrupt-cells = <1>; @@ -448,7 +445,7 @@ pcie@0,0 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>; - resets = <&rstctrl 24>; + resets = <&sysc MT7621_RST_PCIE0>; clocks = <&sysc MT7621_CLK_PCIE0>; phys = <&pcie0_phy 1>; phy-names = "pcie-phy0"; @@ -463,7 +460,7 @@ pcie@1,0 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>; - resets = <&rstctrl 25>; + resets = <&sysc MT7621_RST_PCIE1>; clocks = <&sysc MT7621_CLK_PCIE1>; phys = <&pcie0_phy 1>; phy-names = "pcie-phy1"; @@ -478,7 +475,7 @@ pcie@2,0 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; - resets = <&rstctrl 26>; + resets = <&sysc MT7621_RST_PCIE2>; clocks = <&sysc MT7621_CLK_PCIE2>; phys = <&pcie2_phy 0>; phy-names = "pcie-phy2";