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Mon, 10 Jan 2022 09:51:05 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 6044A1FFB8; Mon, 10 Jan 2022 17:51:04 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [RFC PATCH 1/6] hw/arm: arm initial boilerplate for RP2040 SoC Date: Mon, 10 Jan 2022 17:50:59 +0000 Message-Id: <20220110175104.2908956-2-alex.bennee@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220110175104.2908956-1-alex.bennee@linaro.org> References: <20220110175104.2908956-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::52e (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::52e; envelope-from=alex.bennee@linaro.org; helo=mail-ed1-x52e.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé --- configs/devices/arm-softmmu/default.mak | 1 + include/hw/arm/rp2040.h | 32 ++++++++++ hw/arm/rp2040.c | 79 +++++++++++++++++++++++++ hw/arm/Kconfig | 3 + hw/arm/meson.build | 1 + 5 files changed, 116 insertions(+) create mode 100644 include/hw/arm/rp2040.h create mode 100644 hw/arm/rp2040.c diff --git a/configs/devices/arm-softmmu/default.mak b/configs/devices/arm-softmmu/default.mak index 6985a25377..dce1c39aad 100644 --- a/configs/devices/arm-softmmu/default.mak +++ b/configs/devices/arm-softmmu/default.mak @@ -32,6 +32,7 @@ CONFIG_NETDUINO2=y CONFIG_NETDUINOPLUS2=y CONFIG_MPS2=y CONFIG_RASPI=y +CONFIG_RP2040=y CONFIG_DIGIC=y CONFIG_SABRELITE=y CONFIG_EMCRAFT_SF2=y diff --git a/include/hw/arm/rp2040.h b/include/hw/arm/rp2040.h new file mode 100644 index 0000000000..6bf4a4e57e --- /dev/null +++ b/include/hw/arm/rp2040.h @@ -0,0 +1,32 @@ +/* + * RP2040 SoC Emulation + * + * Copyright (c) 2021 Linaro Ltd + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef _RP2040_H_ +#define _RP2040_H_ + +#include "target/arm/cpu.h" +#include "hw/arm/armv7m.h" +#include "qom/object.h" + +#define TYPE_RP2040 "rp2040" +OBJECT_DECLARE_TYPE(RP2040State, RP2040Class, RP2040) + +#define RP2040_NCPUS 2 + +struct RP2040State { + /*< private >*/ + DeviceState parent_obj; + /*< public >*/ + + ARMv7MState armv7m[RP2040_NCPUS]; + + MemoryRegion container; +}; + + +#endif /* _RP2040_H_ */ diff --git a/hw/arm/rp2040.c b/hw/arm/rp2040.c new file mode 100644 index 0000000000..2feedc0da8 --- /dev/null +++ b/hw/arm/rp2040.c @@ -0,0 +1,79 @@ +/* + * RP2040 SoC Emulation + * + * Copyright (c) 2021 Linaro Ltd + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu/module.h" +#include "hw/arm/armv7m.h" +#include "hw/arm/rp2040.h" +#include "hw/sysbus.h" +#include "hw/qdev-properties.h" + +typedef struct RP2040Class { + /*< private >*/ + DeviceClass parent_class; + /*< public >*/ + const char *name; + const char *cpu_type; +} RP2040Class; + +#define RP2040_CLASS(klass) \ + OBJECT_CLASS_CHECK(RP2040Class, (klass), TYPE_RP2040) +#define RP2040_GET_CLASS(obj) \ + OBJECT_GET_CLASS(RP2040Class, (obj), TYPE_RP2040) + +static void rp2040_init(Object *obj) +{ + RP2040State *s = RP2040(obj); + int n; + + for (n = 0; n < RP2040_NCPUS; n++) { + g_autofree char *name = g_strdup_printf("cpu[%d]", n); + object_initialize_child(obj, name, &s->armv7m[n], TYPE_ARMV7M); + qdev_prop_set_string(DEVICE(&s->armv7m[n]), "cpu-type", + ARM_CPU_TYPE_NAME("cortex-m0")); + } +} + +static void rp2040_realize(DeviceState *dev, Error **errp) +{ + RP2040State *s = RP2040(dev); + Object *obj = OBJECT(dev); + int n; + + for (n = 0; n < RP2040_NCPUS; n++) { + Object *cpuobj = OBJECT(&s->armv7m[n]); + if (!sysbus_realize(SYS_BUS_DEVICE(cpuobj), errp)) { + return; + } + } +} + +static void rp2040_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + RP2040Class *bc = RP2040_CLASS(oc); + + bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-m0"); + dc->realize = rp2040_realize; + /* any props? */ +}; + +static const TypeInfo rp2040_types[] = { + { + .name = TYPE_RP2040, + /* .parent = TYPE_SYS_BUS_DEVICE, */ + .parent = TYPE_DEVICE, + .instance_size = sizeof(RP2040State), + .instance_init = rp2040_init, + .class_size = sizeof(RP2040Class), + .class_init = rp2040_class_init, + } +}; + +DEFINE_TYPES(rp2040_types) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index e652590943..1c5150c180 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -203,6 +203,9 @@ config REALVIEW select DS1338 # I2C RTC+NVRAM select USB_OHCI +config RP2040 + bool + config SBSA_REF bool imply PCI_DEVICES diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 721a8eb8be..9f1b040c57 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -40,6 +40,7 @@ arm_ss.add(when: 'CONFIG_STRONGARM', if_true: files('strongarm.c')) arm_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10.c', 'cubieboard.c')) arm_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', 'orangepi.c')) arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_peripherals.c', 'bcm2836.c', 'raspi.c')) +arm_ss.add(when: 'CONFIG_RP2040', if_true: files('rp2040.c')) arm_ss.add(when: 'CONFIG_STM32F100_SOC', if_true: files('stm32f100_soc.c')) arm_ss.add(when: 'CONFIG_STM32F205_SOC', if_true: files('stm32f205_soc.c')) arm_ss.add(when: 'CONFIG_STM32F405_SOC', if_true: files('stm32f405_soc.c')) From patchwork Mon Jan 10 17:51:00 2022 Content-Type: text/plain; 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Mon, 10 Jan 2022 09:51:08 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id a1sm3828963edu.17.2022.01.10.09.51.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Jan 2022 09:51:06 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 7DE8B1FFBA; Mon, 10 Jan 2022 17:51:04 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [RFC PATCH 2/6] hw/arm: add boilerplate for machines based on the RP2040 Date: Mon, 10 Jan 2022 17:51:00 +0000 Message-Id: <20220110175104.2908956-3-alex.bennee@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220110175104.2908956-1-alex.bennee@linaro.org> References: <20220110175104.2908956-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::52b (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::52b; envelope-from=alex.bennee@linaro.org; helo=mail-ed1-x52b.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Currently we are only targeting the official RaspberryPi Pico although I suspect most RP2040 based boards will look broadly the same. Signed-off-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé --- configs/devices/arm-softmmu/default.mak | 1 + hw/arm/raspi_pico.c | 77 +++++++++++++++++++++++++ hw/arm/Kconfig | 3 + hw/arm/meson.build | 1 + 4 files changed, 82 insertions(+) create mode 100644 hw/arm/raspi_pico.c diff --git a/configs/devices/arm-softmmu/default.mak b/configs/devices/arm-softmmu/default.mak index dce1c39aad..7322213127 100644 --- a/configs/devices/arm-softmmu/default.mak +++ b/configs/devices/arm-softmmu/default.mak @@ -32,6 +32,7 @@ CONFIG_NETDUINO2=y CONFIG_NETDUINOPLUS2=y CONFIG_MPS2=y CONFIG_RASPI=y +CONFIG_RASPI_PICO=y CONFIG_RP2040=y CONFIG_DIGIC=y CONFIG_SABRELITE=y diff --git a/hw/arm/raspi_pico.c b/hw/arm/raspi_pico.c new file mode 100644 index 0000000000..9826f4d608 --- /dev/null +++ b/hw/arm/raspi_pico.c @@ -0,0 +1,77 @@ +/* + * Raspberry Pi Pico emulation + * + * Copyright (c) 2021 Linaro Ltd + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "qemu/cutils.h" +#include "qapi/error.h" +#include "hw/arm/rp2040.h" +#include "qemu/error-report.h" +#include "hw/boards.h" +#include "hw/loader.h" +#include "hw/arm/boot.h" +#include "qom/object.h" + +struct PiPicoMachineState { + /*< private >*/ + MachineState parent_obj; + /*< public >*/ + RP2040State soc; +}; +typedef struct PiPicoMachineState PiPicoMachineState; + +struct PiPicoMachineClass { + /*< private >*/ + MachineClass parent_obj; + /*< public >*/ +}; + +typedef struct PiPicoMachineClass PiPicoMachineClass; + +#define TYPE_PIPICO_MACHINE MACHINE_TYPE_NAME("raspi-pico") +DECLARE_OBJ_CHECKERS(PiPicoMachineState, PiPicoMachineClass, + PIPICO_MACHINE, TYPE_PIPICO_MACHINE) + + +static void pipico_machine_init(MachineState *machine) +{ + PiPicoMachineState *s = PIPICO_MACHINE(machine); + + /* Setup the SOC */ + object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RP2040); + sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal); +} + +static void pipico_machine_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + + mc->desc = g_strdup_printf("Raspberry Pi Pico"); + mc->init = pipico_machine_init; + mc->block_default_type = IF_PFLASH; + mc->no_parallel = 1; + mc->no_floppy = 1; + mc->no_cdrom = 1; + mc->no_sdcard = 1; + mc->min_cpus = 2; + mc->default_cpus = 2; + mc->max_cpus = 2; +}; + + +static const TypeInfo pipico_machine_types[] = { + { + .name = TYPE_PIPICO_MACHINE, + .parent = TYPE_MACHINE, + .instance_size = sizeof(PiPicoMachineState), + .class_size = sizeof(PiPicoMachineClass), + .class_init = pipico_machine_class_init, + } +}; + +DEFINE_TYPES(pipico_machine_types) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 1c5150c180..288a03f428 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -336,6 +336,9 @@ config RASPI select SDHCI select USB_DWC2 +config RASPI_PICO + bool + config STM32F100_SOC bool select ARM_V7M diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 9f1b040c57..4913cd1a50 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -41,6 +41,7 @@ arm_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10.c', 'cubi arm_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', 'orangepi.c')) arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_peripherals.c', 'bcm2836.c', 'raspi.c')) arm_ss.add(when: 'CONFIG_RP2040', if_true: files('rp2040.c')) +arm_ss.add(when: 'CONFIG_RASPI_PICO', if_true: files('raspi_pico.c')) arm_ss.add(when: 'CONFIG_STM32F100_SOC', if_true: files('stm32f100_soc.c')) arm_ss.add(when: 'CONFIG_STM32F205_SOC', if_true: files('stm32f205_soc.c')) arm_ss.add(when: 'CONFIG_STM32F405_SOC', if_true: files('stm32f405_soc.c')) From patchwork Mon Jan 10 17:51:01 2022 Content-Type: text/plain; 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Mon, 10 Jan 2022 09:51:09 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id b4sm2679617ejl.129.2022.01.10.09.51.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Jan 2022 09:51:07 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 9A5FB1FFBB; Mon, 10 Jan 2022 17:51:04 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [RFC PATCH 3/6] hw/arm: wire-up memory from the Pico board and the SoC Date: Mon, 10 Jan 2022 17:51:01 +0000 Message-Id: <20220110175104.2908956-4-alex.bennee@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220110175104.2908956-1-alex.bennee@linaro.org> References: <20220110175104.2908956-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::532 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::532; envelope-from=alex.bennee@linaro.org; helo=mail-ed1-x532.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" All the memory aside from the external flash is a feature of the SoC itself. However the flash is part of the board and different RP2040 boards can choose to wire up different amounts of it. For now add unimplemented devices for all the rp2040 peripheral blocks. Before we can boot more of the ROM we will need to model at least the SIO and CLOCKS blocks. For now CPU#1 starts disabled as it needs a working CPUID register so it can identify itself before sleeping. Signed-off-by: Alex Bennée --- include/hw/arm/rp2040.h | 9 +++- hw/arm/raspi_pico.c | 20 +++++++ hw/arm/rp2040.c | 113 ++++++++++++++++++++++++++++++++++++++-- 3 files changed, 137 insertions(+), 5 deletions(-) diff --git a/include/hw/arm/rp2040.h b/include/hw/arm/rp2040.h index 6bf4a4e57e..760cef98fc 100644 --- a/include/hw/arm/rp2040.h +++ b/include/hw/arm/rp2040.h @@ -25,7 +25,14 @@ struct RP2040State { ARMv7MState armv7m[RP2040_NCPUS]; - MemoryRegion container; + /* RP2040 regions */ + MemoryRegion *memory; /* from board */ + MemoryRegion memory_alias[RP2040_NCPUS - 1]; + + MemoryRegion rom; /* internal mask rom */ + MemoryRegion sram03; /* shared SRAM0-3 banks */ + MemoryRegion sram4; /* non-stripped SRAM4 */ + MemoryRegion sram5; /* non-stripped SRAM5 */ }; diff --git a/hw/arm/raspi_pico.c b/hw/arm/raspi_pico.c index 9826f4d608..76839e93bf 100644 --- a/hw/arm/raspi_pico.c +++ b/hw/arm/raspi_pico.c @@ -22,6 +22,7 @@ struct PiPicoMachineState { MachineState parent_obj; /*< public >*/ RP2040State soc; + MemoryRegion flash; }; typedef struct PiPicoMachineState PiPicoMachineState; @@ -37,14 +38,33 @@ typedef struct PiPicoMachineClass PiPicoMachineClass; DECLARE_OBJ_CHECKERS(PiPicoMachineState, PiPicoMachineClass, PIPICO_MACHINE, TYPE_PIPICO_MACHINE) +#define RP2040_XIP_BASE 0x10000000 static void pipico_machine_init(MachineState *machine) { PiPicoMachineState *s = PIPICO_MACHINE(machine); + MemoryRegion *sysmem = get_system_memory(); + Error **errp = &error_fatal; /* Setup the SOC */ object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RP2040); + object_property_set_link(OBJECT(&s->soc), "memory", OBJECT(sysmem), errp); + + /* + * The flash device it external to the SoC and mounted on the + * PiPico board itself. We will "load" the actual contents with + * armv7_load_kernel later although we still rely on the SoC's + * mask ROM to get to it. + */ + const uint32_t flash_size = 256 * KiB; + memory_region_init_rom(&s->flash, NULL, "pico.flash0", flash_size, errp); + memory_region_add_subregion(sysmem, RP2040_XIP_BASE, &s->flash); + + sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal); + + /* This assumes the "kernel" is positioned in the XIP Flash block */ + armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, RP2040_XIP_BASE); } static void pipico_machine_class_init(ObjectClass *oc, void *data) diff --git a/hw/arm/rp2040.c b/hw/arm/rp2040.c index 2feedc0da8..c6cc9b7165 100644 --- a/hw/arm/rp2040.c +++ b/hw/arm/rp2040.c @@ -7,10 +7,11 @@ */ #include "qemu/osdep.h" +#include "qemu/units.h" #include "qapi/error.h" -#include "qemu/module.h" #include "hw/arm/armv7m.h" #include "hw/arm/rp2040.h" +#include "hw/misc/unimp.h" #include "hw/sysbus.h" #include "hw/qdev-properties.h" @@ -27,6 +28,11 @@ typedef struct RP2040Class { #define RP2040_GET_CLASS(obj) \ OBJECT_GET_CLASS(RP2040Class, (obj), TYPE_RP2040) +/* See Table 2.2.2 in the RP2040 Datasheet */ +#define RP2040_SRAM_BASE 0x20000000 +#define RP2040_SRAM4_BASE 0x20040000 +#define RP2040_SRAM5_BASE 0x20041000 + static void rp2040_init(Object *obj) { RP2040State *s = RP2040(obj); @@ -37,6 +43,16 @@ static void rp2040_init(Object *obj) object_initialize_child(obj, name, &s->armv7m[n], TYPE_ARMV7M); qdev_prop_set_string(DEVICE(&s->armv7m[n]), "cpu-type", ARM_CPU_TYPE_NAME("cortex-m0")); + /* + * Confusingly ARMv7M creates it's own per-core container so + * we need to alias additional regions to avoid trying to give + * a region two parents. + */ + if (n > 0) { + memory_region_init_alias(&s->memory_alias[n - 1], obj, + "system-memory.alias", s->memory, + 0, -1); + } } } @@ -46,14 +62,104 @@ static void rp2040_realize(DeviceState *dev, Error **errp) Object *obj = OBJECT(dev); int n; + if (!s->memory) { + error_setg(errp, "%s: memory property was not set", __func__); + return; + } + + /* initialize internal 16 KB internal ROM */ + memory_region_init_rom(&s->rom, obj, "rp2040.rom0", 16 * KiB, errp); + memory_region_add_subregion(s->memory, 0, &s->rom); + + /* SRAM (Main 256k bank + two 4k banks)*/ + memory_region_init_ram(&s->sram03, obj, "rp2040.sram03", 256 * KiB, errp); + memory_region_add_subregion(s->memory, RP2040_SRAM_BASE, &s->sram03); + + memory_region_init_ram(&s->sram4, obj, "rp2040.sram4", 4 * KiB, errp); + memory_region_add_subregion(s->memory, RP2040_SRAM4_BASE, &s->sram4); + + memory_region_init_ram(&s->sram5, obj, "rp2040.sram5", 4 * KiB, errp); + memory_region_add_subregion(s->memory, RP2040_SRAM5_BASE, &s->sram5); + + /* Map all the devices - see table 2.2.2 from the datasheet */ + + /* APB Peripherals */ + create_unimplemented_device("rp2040.sysinfo", 0x40000000, 0x4000); + create_unimplemented_device("rp2040.syscfg", 0x40004000, 0x4000); + create_unimplemented_device("rp2040.clocks", 0x40008000, 0x4000); + create_unimplemented_device("rp2040.resets", 0x4000c000, 0x4000); + create_unimplemented_device("rp2040.psm", 0x40010000, 0x4000); + create_unimplemented_device("rp2040.iobnk0", 0x40014000, 0x4000); + create_unimplemented_device("rp2040.ioqspi", 0x40018000, 0x4000); + create_unimplemented_device("rp2040.padsbnk0", 0x4001c000, 0x4000); + create_unimplemented_device("rp2040.padsqspi", 0x40020000, 0x4000); + create_unimplemented_device("rp2040.xosc", 0x40024000, 0x4000); + + create_unimplemented_device("rp2040.pllsys", 0x40028000, 0x4000); + create_unimplemented_device("rp2040.pllusb", 0x4002c000, 0x4000); + create_unimplemented_device("rp2040.busctrl", 0x40030000, 0x4000); + create_unimplemented_device("rp2040.uart0", 0x40034000, 0x4000); + create_unimplemented_device("rp2040.uart1", 0x40038000, 0x4000); + create_unimplemented_device("rp2040.spi0", 0x4003c000, 0x4000); + create_unimplemented_device("rp2040.spi1", 0x40040000, 0x4000); + create_unimplemented_device("rp2040.i2c0", 0x40044000, 0x4000); + create_unimplemented_device("rp2040.i2c1", 0x40048000, 0x4000); + create_unimplemented_device("rp2040.adc", 0x4004c000, 0x4000); + create_unimplemented_device("rp2040.pwm", 0x40050000, 0x4000); + create_unimplemented_device("rp2040.timer", 0x40054000, 0x4000); + create_unimplemented_device("rp2040.watchdog", 0x40058000, 0x4000); + create_unimplemented_device("rp2040.rtc", 0x4005c000, 0x4000); + create_unimplemented_device("rp2040.rosc", 0x40060000, 0x4000); + create_unimplemented_device("rp2040.vreg&reset", 0x40064000, 0x4000); + create_unimplemented_device("rp2040.tbman", 0x4006c000, 0x4000); + + /* AHB-Lite Peripherals */ + create_unimplemented_device("rp2040.dmabase", 0x50000000, 0x1000); + + /* USB */ + create_unimplemented_device("rp2040.usbram", 0x50100000, 0x10000); + create_unimplemented_device("rp2040.usbregs", 0x50110000, 0x10000); + + /* Remaining AHB-Lite peripherals */ + create_unimplemented_device("rp2040.pi00", 0x50200000, 0x10000); + create_unimplemented_device("rp2040.pi01", 0x50300000, 0x10000); + + /* IOPORT Peripherals */ + create_unimplemented_device("rp2040.sio", 0xd0000000, 0x10000000); + + /* + * Cortex-M0+ internal peripherals (PPB_BASE) are handled by + * the v7m model and live at 0xe0000000. + */ + + /* TODO: deal with stripped aliases */ + for (n = 0; n < RP2040_NCPUS; n++) { Object *cpuobj = OBJECT(&s->armv7m[n]); + MemoryRegion *mr = n == 0 ? s->memory : &s->memory_alias[n - 1]; + object_property_set_link(cpuobj, "memory", OBJECT(mr), errp); + + /* + * FIXME: temp hack - until more of the logic is emulated we + * can't let the second CPU run off into the wild. + */ + if (n > 0) { + object_property_set_bool(cpuobj, "start-powered-off", + true, &error_fatal); + } + if (!sysbus_realize(SYS_BUS_DEVICE(cpuobj), errp)) { return; } } } +static Property rp2040_soc_properties[] = { + DEFINE_PROP_LINK("memory", RP2040State, memory, TYPE_MEMORY_REGION, + MemoryRegion *), + DEFINE_PROP_END_OF_LIST(), +}; + static void rp2040_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); @@ -61,14 +167,13 @@ static void rp2040_class_init(ObjectClass *oc, void *data) bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-m0"); dc->realize = rp2040_realize; - /* any props? */ + device_class_set_props(dc, rp2040_soc_properties); }; static const TypeInfo rp2040_types[] = { { .name = TYPE_RP2040, - /* .parent = TYPE_SYS_BUS_DEVICE, */ - .parent = TYPE_DEVICE, + .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(RP2040State), .instance_init = rp2040_init, .class_size = sizeof(RP2040Class), From patchwork Mon Jan 10 17:51:02 2022 Content-Type: text/plain; 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Mon, 10 Jan 2022 09:51:10 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id k21sm3826268edo.87.2022.01.10.09.51.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Jan 2022 09:51:08 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id A517C1FFBC; Mon, 10 Jan 2022 17:51:04 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [RFC PATCH 4/6] pc-bios: add pipico mask rom (!upstream) Date: Mon, 10 Jan 2022 17:51:02 +0000 Message-Id: <20220110175104.2908956-5-alex.bennee@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220110175104.2908956-1-alex.bennee@linaro.org> References: <20220110175104.2908956-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::530 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::530; envelope-from=alex.bennee@linaro.org; helo=mail-ed1-x530.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, LOTS_OF_MONEY=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The boot code for the RP2040 is fully open source and can be found at: https://github.com/raspberrypi/pico-bootrom it contains not only the initial boot code but a full USB stack (for programming) and a number of library functions that the user code might use. We really should be able to build this ourselves but until I figure out how to integrate the build this will do. This image was extracted from a B1 pipico by a friendly hardware hacker. Signed-off-by: Alex Bennée --- pc-bios/pipico.rom | Bin 0 -> 16384 bytes 1 file changed, 0 insertions(+), 0 deletions(-) create mode 100644 pc-bios/pipico.rom GIT binary patch literal 16384 zcma)jd0bT2+3<7j?86KUpkWrkJ2Rlbhz{TuaJe%V2WAF0)YP>d7R}%iM{&Uw!~o*#*P z>w$j7!1Lu`B>`6;;&~RoI(YgWD%-sz|7lGoKn|bF7CH-^Y-Lq_sCvzoEj!tTb?lNY zRkd{w+|O2Qt%Zd}mzm0<5vHPOf^13Ak7V-}Um3r6ia35A?;6if$sNDc-I`sx7r5 zc!_uxFPq?*TQRA0@sdfUb5G9#s4pi$$Q>t2(dVSi-pzh((Cj8cLf~*@(}K|ar2jtS zR*B0w&L|fRb7lng+*0p9QpWUuc85K0-FQGf)D>96oqr(RSyolCW`W##Z`BJMtsA}S zq0WRCft8{+C6aR+$Np0KT|kO{A%(HO6ul~u7p3U`O6?xN9^tap5%xU0k;BoBZG@ap zg-{t8Kb`+w8N59hNuJUEAhbcNn}a;)X9jL}{+B1@fif2A8~|%D6-)#e!89RfG`*IO zdxqZ&Fzv>)7t>!bUB(o_^d+YAxd7WRUBN{6_;Y+O$OA~gx_W&72H&q?dJfYsG3`cT z*o)~Prk`S(H4UI@62MYSZIb~^ILP`bqv=W^!i8<_$5fAL8>S1`{tuYm!qkSTUgvEBHNnln!Js=3`7&N#_i&W962 zW%<5E>O~w6v<;^=@_QkbGjL(GjL-2IiGfSyEE*#ZZ-&aUn~6>*?$*jhqEU#(Rc2?X zY}qP9{Qo`pe?Qi!HF9y;DlO)Wt7uZ<*Mw#wPZIVMg|M5b1Wl5mU>VjONE~e!PBgBP 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Message-Id: <20220110175104.2908956-6-alex.bennee@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220110175104.2908956-1-alex.bennee@linaro.org> References: <20220110175104.2908956-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::535 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::535; envelope-from=alex.bennee@linaro.org; helo=mail-ed1-x535.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The mask ROM contains the initial boot code to start the RP2040. It also contains some common sub-routines as well as the flash programming code for drag and drop programming. As a result we need to ensure the full version is available to any user supplied programs we might want to run. Signed-off-by: Alex Bennée --- hw/arm/rp2040.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/hw/arm/rp2040.c b/hw/arm/rp2040.c index c6cc9b7165..9a5bc20159 100644 --- a/hw/arm/rp2040.c +++ b/hw/arm/rp2040.c @@ -8,10 +8,12 @@ #include "qemu/osdep.h" #include "qemu/units.h" +#include "qemu/datadir.h" #include "qapi/error.h" #include "hw/arm/armv7m.h" #include "hw/arm/rp2040.h" #include "hw/misc/unimp.h" +#include "hw/loader.h" #include "hw/sysbus.h" #include "hw/qdev-properties.h" @@ -33,6 +35,8 @@ typedef struct RP2040Class { #define RP2040_SRAM4_BASE 0x20040000 #define RP2040_SRAM5_BASE 0x20041000 +#define RP2040_MASK_ROM "pipico.rom" + static void rp2040_init(Object *obj) { RP2040State *s = RP2040(obj); @@ -61,6 +65,8 @@ static void rp2040_realize(DeviceState *dev, Error **errp) RP2040State *s = RP2040(dev); Object *obj = OBJECT(dev); int n; + g_autofree char *mask_rom = qemu_find_file(QEMU_FILE_TYPE_BIOS, + RP2040_MASK_ROM); if (!s->memory) { error_setg(errp, "%s: memory property was not set", __func__); @@ -68,9 +74,20 @@ static void rp2040_realize(DeviceState *dev, Error **errp) } /* initialize internal 16 KB internal ROM */ - memory_region_init_rom(&s->rom, obj, "rp2040.rom0", 16 * KiB, errp); + memory_region_init_rom(&s->rom, obj, "rp2040.rom", 16 * KiB, errp); memory_region_add_subregion(s->memory, 0, &s->rom); + if (!mask_rom) { + error_setg(errp, "%s: unable to find mask_rom %s", + __func__, RP2040_MASK_ROM); + return; + } + n = load_image_targphys(mask_rom, 0x0, 16 * KiB); + if (n <= 0) { + error_setg(errp, "%s: failed to load mask rom image: %s", + __func__, RP2040_MASK_ROM); + } + /* SRAM (Main 256k bank + two 4k banks)*/ memory_region_init_ram(&s->sram03, obj, "rp2040.sram03", 256 * KiB, errp); memory_region_add_subregion(s->memory, RP2040_SRAM_BASE, &s->sram03); From patchwork Mon Jan 10 17:51:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 12709006 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C058AC433F5 for ; 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Mon, 10 Jan 2022 09:51:11 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id 21sm2655615ejz.24.2022.01.10.09.51.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Jan 2022 09:51:08 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id C80101FFBE; Mon, 10 Jan 2022 17:51:04 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [RFC PATCH 6/6] docs/devel: add some clarifying text for aliases Date: Mon, 10 Jan 2022 17:51:04 +0000 Message-Id: <20220110175104.2908956-7-alex.bennee@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220110175104.2908956-1-alex.bennee@linaro.org> References: <20220110175104.2908956-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::52c (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::52c; envelope-from=alex.bennee@linaro.org; helo=mail-ed1-x52c.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" We do mention the limitation of single parenthood for memory_region_add_subregion but lets also make it clear how aliases help solve that conundrum. Signed-off-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé --- docs/devel/memory.rst | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/docs/devel/memory.rst b/docs/devel/memory.rst index 5dc8a12682..69c5e3f914 100644 --- a/docs/devel/memory.rst +++ b/docs/devel/memory.rst @@ -67,11 +67,15 @@ MemoryRegion): You initialize a pure container with memory_region_init(). -- alias: a subsection of another region. Aliases allow a region to be - split apart into discontiguous regions. Examples of uses are memory banks - used when the guest address space is smaller than the amount of RAM - addressed, or a memory controller that splits main memory to expose a "PCI - hole". Aliases may point to any type of region, including other aliases, +- alias: a subsection of another region. Aliases allow a region to be + split apart into discontiguous regions. Examples of uses are memory + banks used when the guest address space is smaller than the amount + of RAM addressed, or a memory controller that splits main memory to + expose a "PCI hole". You can also create aliases to avoid trying to + add the original region to multiple parents via + `memory_region_add_subregion`. + + Aliases may point to any type of region, including other aliases, but an alias may not point back to itself, directly or indirectly. You initialize these with memory_region_init_alias().