From patchwork Wed Jan 12 09:42:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Stefan Roese X-Patchwork-Id: 12711079 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 63D17C433EF for ; Wed, 12 Jan 2022 09:43:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349438AbiALJnB (ORCPT ); Wed, 12 Jan 2022 04:43:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38332 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237055AbiALJm7 (ORCPT ); Wed, 12 Jan 2022 04:42:59 -0500 Received: from mout-u-204.mailbox.org (mout-u-204.mailbox.org [IPv6:2001:67c:2050:1::465:204]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ACA6AC061748 for ; Wed, 12 Jan 2022 01:42:59 -0800 (PST) Received: from smtp202.mailbox.org (unknown [91.198.250.118]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-u-204.mailbox.org (Postfix) with ESMTPS id 4JYjKX3BgjzQkBc; Wed, 12 Jan 2022 10:42:56 +0100 (CET) X-Virus-Scanned: amavisd-new at heinlein-support.de From: Stefan Roese To: linux-pci@vger.kernel.org Cc: Bharat Kumar Gogada , Bjorn Helgaas , =?utf-8?q?Pali_Roh=C3=A1r?= , Michal Simek Subject: [RESEND PATCH v2 1/4] PCI: Add setup_platform_service_irq hook to struct pci_host_bridge Date: Wed, 12 Jan 2022 10:42:48 +0100 Message-Id: <20220112094251.1271531-1-sr@denx.de> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Bharat Kumar Gogada As per section 6.2.4.1.2, 6.2.6 in PCIe r4.0 error interrupts can be delivered with platform specific interrupt lines. Add setup_platform_service_irq hook to struct pci_host_bridge. Some platforms have dedicated interrupt line from root complex to interrupt controller for PCIe services like AER. This hook is to register platform IRQ's to PCIe port services. Signed-off-by: Bharat Kumar Gogada Signed-off-by: Stefan Roese Tested-by: Stefan Roese Cc: Bjorn Helgaas Cc: Pali Rohár Cc: Michal Simek --- include/linux/pci.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/linux/pci.h b/include/linux/pci.h index 18a75c8e615c..291eadade811 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -554,6 +554,8 @@ struct pci_host_bridge { u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */ int (*map_irq)(const struct pci_dev *, u8, u8); void (*release_fn)(struct pci_host_bridge *); + void (*setup_platform_service_irq)(struct pci_host_bridge *, int *, + int); void *release_data; unsigned int ignore_reset_delay:1; /* For entire hierarchy */ unsigned int no_ext_tags:1; /* No Extended Tags */ From patchwork Wed Jan 12 09:42:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Stefan Roese X-Patchwork-Id: 12711078 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74576C433FE for ; Wed, 12 Jan 2022 09:43:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237055AbiALJnB (ORCPT ); Wed, 12 Jan 2022 04:43:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38328 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238775AbiALJm7 (ORCPT ); Wed, 12 Jan 2022 04:42:59 -0500 Received: from mout-u-204.mailbox.org (mout-u-204.mailbox.org [IPv6:2001:67c:2050:1::465:204]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9E88EC06173F for ; Wed, 12 Jan 2022 01:42:59 -0800 (PST) Received: from smtp202.mailbox.org (unknown [91.198.250.118]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-u-204.mailbox.org (Postfix) with ESMTPS id 4JYjKY0SpMzQlGd; Wed, 12 Jan 2022 10:42:57 +0100 (CET) X-Virus-Scanned: amavisd-new at heinlein-support.de From: Stefan Roese To: linux-pci@vger.kernel.org Cc: Bharat Kumar Gogada , Bjorn Helgaas , =?utf-8?q?Pali_Roh=C3=A1r?= , Michal Simek Subject: [RESEND PATCH v2 2/4] PCI: Add pci_check_platform_service_irqs Date: Wed, 12 Jan 2022 10:42:49 +0100 Message-Id: <20220112094251.1271531-2-sr@denx.de> In-Reply-To: <20220112094251.1271531-1-sr@denx.de> References: <20220112094251.1271531-1-sr@denx.de> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Bharat Kumar Gogada Adding method pci_check_platform_service_irqs to check if platform has registered method to proivde dedicated IRQ lines for PCIe services like AER. Signed-off-by: Bharat Kumar Gogada Signed-off-by: Stefan Roese Tested-by: Stefan Roese Cc: Bjorn Helgaas Cc: Pali Rohár Cc: Michal Simek --- include/linux/pci.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/include/linux/pci.h b/include/linux/pci.h index 291eadade811..d6812d596ecc 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -2420,6 +2420,24 @@ static inline bool pci_ari_enabled(struct pci_bus *bus) return bus->self && bus->self->ari_enabled; } +/** + * pci_check_platform_service_irqs - check platform service irq's + * @pdev: PCI Express device to check + * @irqs: Array of irqs to populate + * @mask: Bitmask of capabilities + */ +static inline void pci_check_platform_service_irqs(struct pci_dev *dev, + int *irqs, int mask) +{ + struct pci_host_bridge *bridge; + + if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) { + bridge = pci_find_host_bridge(dev->bus); + if (bridge && bridge->setup_platform_service_irq) + bridge->setup_platform_service_irq(bridge, irqs, mask); + } +} + /** * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain * @pdev: PCI device to check From patchwork Wed Jan 12 09:42:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Stefan Roese X-Patchwork-Id: 12711080 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A8CA1C433F5 for ; Wed, 12 Jan 2022 09:43:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238775AbiALJnC (ORCPT ); Wed, 12 Jan 2022 04:43:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38330 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346463AbiALJm7 (ORCPT ); Wed, 12 Jan 2022 04:42:59 -0500 Received: from mout-u-107.mailbox.org (mout-u-107.mailbox.org [IPv6:2001:67c:2050:1::465:107]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ACAD6C061751 for ; Wed, 12 Jan 2022 01:42:59 -0800 (PST) Received: from smtp202.mailbox.org (smtp202.mailbox.org [IPv6:2001:67c:2050:105:465:1:4:0]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-u-107.mailbox.org (Postfix) with ESMTPS id 4JYjKY4ym1zQl5l; Wed, 12 Jan 2022 10:42:57 +0100 (CET) X-Virus-Scanned: amavisd-new at heinlein-support.de From: Stefan Roese To: linux-pci@vger.kernel.org Cc: Bharat Kumar Gogada , Bjorn Helgaas , =?utf-8?q?Pali_Roh=C3=A1r?= , Michal Simek Subject: [RESEND PATCH v2 3/4] PCI/portdrv: Check platform supported service IRQ's Date: Wed, 12 Jan 2022 10:42:50 +0100 Message-Id: <20220112094251.1271531-3-sr@denx.de> In-Reply-To: <20220112094251.1271531-1-sr@denx.de> References: <20220112094251.1271531-1-sr@denx.de> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Bharat Kumar Gogada Platforms may have dedicated IRQ lines for PCIe services like AER/PME etc., check for such IRQ lines. Check if platform has any dedicated IRQ lines for PCIe services. Signed-off-by: Bharat Kumar Gogada Signed-off-by: Stefan Roese Tested-by: Stefan Roese Cc: Bjorn Helgaas Cc: Pali Rohár Cc: Michal Simek --- drivers/pci/pcie/portdrv_core.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c index bda630889f95..70dd45671ed8 100644 --- a/drivers/pci/pcie/portdrv_core.c +++ b/drivers/pci/pcie/portdrv_core.c @@ -358,6 +358,14 @@ int pcie_port_device_register(struct pci_dev *dev) } } + /* + * Some platforms have dedicated interrupt line from root complex to + * interrupt controller for PCIe services like AER/PME etc., check + * if platform registered with any such IRQ. + */ + if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) + pci_check_platform_service_irqs(dev, irqs, capabilities); + /* Allocate child services if any */ status = -ENODEV; nr_service = 0; From patchwork Wed Jan 12 09:42:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Stefan Roese X-Patchwork-Id: 12711081 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CAA83C4332F for ; Wed, 12 Jan 2022 09:43:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346463AbiALJnC (ORCPT ); Wed, 12 Jan 2022 04:43:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38334 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346466AbiALJnA (ORCPT ); Wed, 12 Jan 2022 04:43:00 -0500 Received: from mout-u-107.mailbox.org (mout-u-107.mailbox.org [IPv6:2001:67c:2050:1::465:107]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 40029C061756 for ; Wed, 12 Jan 2022 01:43:00 -0800 (PST) Received: from smtp202.mailbox.org (unknown [91.198.250.118]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-u-107.mailbox.org (Postfix) with ESMTPS id 4JYjKZ3dCTzQl7q; Wed, 12 Jan 2022 10:42:58 +0100 (CET) X-Virus-Scanned: amavisd-new at heinlein-support.de From: Stefan Roese To: linux-pci@vger.kernel.org Cc: Bharat Kumar Gogada , Bjorn Helgaas , =?utf-8?q?Pali_Roh=C3=A1r?= , Michal Simek Subject: [RESEND PATCH v2 4/4] PCI: xilinx-nwl: Add method to setup_platform_service_irq hook Date: Wed, 12 Jan 2022 10:42:51 +0100 Message-Id: <20220112094251.1271531-4-sr@denx.de> In-Reply-To: <20220112094251.1271531-1-sr@denx.de> References: <20220112094251.1271531-1-sr@denx.de> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Bharat Kumar Gogada Add nwl_setup_service_irqs hook to setup_platform_service_irq to register platform provided IRQ number to kernel AER service. Signed-off-by: Bharat Kumar Gogada Signed-off-by: Stefan Roese Tested-by: Stefan Roese Cc: Bjorn Helgaas Cc: Pali Rohár Cc: Michal Simek --- drivers/pci/controller/pcie-xilinx-nwl.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c index 414b679175b3..4969f35db7e5 100644 --- a/drivers/pci/controller/pcie-xilinx-nwl.c +++ b/drivers/pci/controller/pcie-xilinx-nwl.c @@ -24,6 +24,7 @@ #include #include "../pci.h" +#include "../pcie/portdrv.h" /* Bridge core config registers */ #define BRCFG_PCIE_RX0 0x00000000 @@ -806,6 +807,16 @@ static int nwl_pcie_parse_dt(struct nwl_pcie *pcie, return 0; } +static void nwl_setup_service_irqs(struct pci_host_bridge *bridge, int *irqs, + int plat_mask) +{ + struct nwl_pcie *pcie; + + pcie = pci_host_bridge_priv(bridge); + if (plat_mask & PCIE_PORT_SERVICE_AER) + irqs[PCIE_PORT_SERVICE_AER_SHIFT] = pcie->irq_misc; +} + static const struct of_device_id nwl_pcie_of_match[] = { { .compatible = "xlnx,nwl-pcie-2.11", }, {} @@ -857,6 +868,7 @@ static int nwl_pcie_probe(struct platform_device *pdev) bridge->sysdata = pcie; bridge->ops = &nwl_pcie_ops; + bridge->setup_platform_service_irq = nwl_setup_service_irqs; if (IS_ENABLED(CONFIG_PCI_MSI)) { err = nwl_pcie_enable_msi(pcie);