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Signed-off-by: Robert Hancock --- .../devicetree/bindings/net/macb.txt | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/Documentation/devicetree/bindings/net/macb.txt b/Documentation/devicetree/bindings/net/macb.txt index a1b06fd1962e..e526952145b8 100644 --- a/Documentation/devicetree/bindings/net/macb.txt +++ b/Documentation/devicetree/bindings/net/macb.txt @@ -29,6 +29,12 @@ Required properties: Optional elements: 'rx_clk' applies to cdns,zynqmp-gem Optional elements: 'tsu_clk' - clocks: Phandles to input clocks. +- phy_names, phys: Required with ZynqMP SoC when in SGMII mode. + phy_names should be "sgmii-phy" and phys should + reference PS-GTR generic PHY device for this controller + instance. See ZynqMP example below. +- resets, reset-names: Recommended with ZynqMP, specify reset control for this + controller instance with zynqmp-reset driver. Optional properties: - mdio: node containing PHY children. If this node is not present, then PHYs @@ -58,3 +64,30 @@ Examples: reset-gpios = <&pioE 6 1>; }; }; + + gem1: ethernet@ff0c0000 { + compatible = "cdns,zynqmp-gem", "cdns,gem"; + interrupt-parent = <&gic>; + interrupts = <0 59 4>, <0 59 4>; + reg = <0x0 0xff0c0000 0x0 0x1000>; + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, + <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>, + <&zynqmp_clk GEM_TSU>; + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; + #address-cells = <1>; + #size-cells = <0>; + #stream-id-cells = <1>; + iommus = <&smmu 0x875>; + power-domains = <&zynqmp_firmware PD_ETH_1>; + resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>; + reset-names = "gem1_rst"; + status = "okay"; + phy-mode = "sgmii"; + phy-names = "sgmii-phy"; + phys = <&psgtr 1 PHY_TYPE_SGMII 1 1>; + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; From patchwork Wed Jan 12 18:11:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Hancock X-Patchwork-Id: 12711835 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 029BEC433FE for ; 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The GEM core appears to need a hardware-level reset in order to work properly in SGMII mode in cases where the GT reference clock was not present at initial power-on. This can be done using a reset mapped to the zynqmp-reset driver in the device tree. Also, when in SGMII mode, the GEM driver needs to ensure the PHY is initialized and powered on when it is initializing. Signed-off-by: Robert Hancock --- drivers/net/ethernet/cadence/macb_main.c | 47 +++++++++++++++++++++++- 1 file changed, 46 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c index a363da928e8b..65b0360c487a 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -34,7 +34,9 @@ #include #include #include +#include #include +#include #include "macb.h" /* This structure is only used for MACB on SiFive FU540 devices */ @@ -4455,6 +4457,49 @@ static int fu540_c000_init(struct platform_device *pdev) return macb_init(pdev); } +static int zynqmp_init(struct platform_device *pdev) +{ + struct net_device *dev = platform_get_drvdata(pdev); + struct macb *bp = netdev_priv(dev); + int ret; + + /* Fully reset GEM controller at hardware level using zynqmp-reset driver, + * if mapped in device tree. + */ + ret = device_reset(&pdev->dev); + if (ret) { + dev_err_probe(&pdev->dev, ret, "failed to reset controller"); + return ret; + } + + if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) { + /* Ensure PS-GTR PHY device used in SGMII mode is ready */ + struct phy *sgmii_phy = devm_phy_get(&pdev->dev, "sgmii-phy"); + + if (IS_ERR(sgmii_phy)) { + ret = PTR_ERR(sgmii_phy); + dev_err_probe(&pdev->dev, ret, + "failed to get PS-GTR PHY\n"); + return ret; + } + + ret = phy_init(sgmii_phy); + if (ret) { + dev_err(&pdev->dev, "failed to init PS-GTR PHY: %d\n", + ret); + return ret; + } + + ret = phy_power_on(sgmii_phy); + if (ret) { + dev_err(&pdev->dev, "failed to power on PS-GTR PHY: %d\n", + ret); + return ret; + } + } + return macb_init(pdev); +} + static const struct macb_usrio_config sama7g5_usrio = { .mii = 0, .rmii = 1, @@ -4550,7 +4595,7 @@ static const struct macb_config zynqmp_config = { MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH, .dma_burst_length = 16, .clk_init = macb_clk_init, - .init = macb_init, + .init = zynqmp_init, .jumbo_max_len = 10240, .usrio = &macb_default_usrio, }; From patchwork Wed Jan 12 18:11:13 2022 Content-Type: text/plain; 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Wed, 12 Jan 2022 18:12:59 +0000 From: Robert Hancock To: netdev@vger.kernel.org Cc: davem@davemloft.net, kuba@kernel.org, robh+dt@kernel.org, michal.simek@xilinx.com, nicolas.ferre@microchip.com, claudiu.beznea@microchip.com, devicetree@vger.kernel.org, Robert Hancock Subject: [PATCH net-next 3/3] arm64: dts: zynqmp: Added GEM reset definitions Date: Wed, 12 Jan 2022 12:11:13 -0600 Message-Id: <20220112181113.875567-4-robert.hancock@calian.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220112181113.875567-1-robert.hancock@calian.com> References: <20220112181113.875567-1-robert.hancock@calian.com> X-ClientProxiedBy: CO2PR05CA0092.namprd05.prod.outlook.com (2603:10b6:104:1::18) To YT3PR01MB6274.CANPRD01.PROD.OUTLOOK.COM (2603:10b6:b01:6a::19) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 07acaa93-148a-4a86-e2f4-08d9d5f72a34 X-MS-TrafficTypeDiagnostic: YT1PR01MB3516:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3044; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Add reset definitions to the ZynqMP platform device tree to allow this to be used. Signed-off-by: Robert Hancock --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 74e66443e4ce..9bec3ba20c69 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -512,6 +512,8 @@ gem0: ethernet@ff0b0000 { #stream-id-cells = <1>; iommus = <&smmu 0x874>; power-domains = <&zynqmp_firmware PD_ETH_0>; + resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>; + reset-names = "gem0_rst"; }; gem1: ethernet@ff0c0000 { @@ -526,6 +528,8 @@ gem1: ethernet@ff0c0000 { #stream-id-cells = <1>; iommus = <&smmu 0x875>; power-domains = <&zynqmp_firmware PD_ETH_1>; + resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>; + reset-names = "gem1_rst"; }; gem2: ethernet@ff0d0000 { @@ -540,6 +544,8 @@ gem2: ethernet@ff0d0000 { #stream-id-cells = <1>; iommus = <&smmu 0x876>; power-domains = <&zynqmp_firmware PD_ETH_2>; + resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>; + reset-names = "gem2_rst"; }; gem3: ethernet@ff0e0000 { @@ -554,6 +560,8 @@ gem3: ethernet@ff0e0000 { #stream-id-cells = <1>; iommus = <&smmu 0x877>; power-domains = <&zynqmp_firmware PD_ETH_3>; + resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>; + reset-names = "gem3_rst"; }; gpio: gpio@ff0a0000 {