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Thu, 13 Jan 2022 21:23:10 +0900 (KST) Received: from Jaguar.sa.corp.samsungelectronics.net (unknown [107.108.73.139]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20220113122308epsmtip275852b5cc5a98348cc2be60758ec3744~J0-UJEQlZ1245412454epsmtip2U; Thu, 13 Jan 2022 12:23:08 +0000 (GMT) From: Alim Akhtar To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org List-Id: Cc: soc@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, olof@lixom.net, linus.walleij@linaro.org, catalin.marinas@arm.com, robh+dt@kernel.org, krzysztof.kozlowski@canonical.com, s.nawrocki@samsung.com, linux-samsung-soc@vger.kernel.org, pankaj.dubey@samsung.com, Alim Akhtar , linux-fsd@tesla.com Subject: [PATCH 01/23] dt-bindings: clock: Document FSD CMU bindings Date: Thu, 13 Jan 2022 17:41:21 +0530 Message-Id: <20220113121143.22280-2-alim.akhtar@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220113121143.22280-1-alim.akhtar@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFuphk+LIzCtJLcpLzFFi42LZdlhTXXe95INEg7ZmVosH87axWbxf1sNo Mf/IOVaLjW9/MFlM+bOcyWLT42usFh977rFaPHwVbnF51xw2ixnn9zFZnLr+mc1i0dYv7Bat e4+wWxx+085q8fj6HzYHfo8189Ywesxq6GXz2LSqk83jzrU9bB6bl9R7XDnRxOrRt2UVo8e/ prnsHp83yQVwRmXbZKQmpqQWKaTmJeenZOal2yp5B8c7x5uaGRjqGlpamCsp5CXmptoqufgE 6Lpl5gA9oKRQlphTChQKSCwuVtK3synKLy1JVcjILy6xVUotSMkpMCnQK07MLS7NS9fLSy2x MjQwMDIFKkzIzlgxT6HgnGHFwbM72RoYJyp2MXJySAiYSHycc5qpi5GLQ0hgN6PEtu5mVgjn E6PE5LVPWSCcb4wS65qPsMK0nFjUxAyR2MsosezGT0YIp4VJYknPZiaQKjYBbYm707eA2SIC bhI3GjvAljAL3GOS+HG4gRkkISzgItF/fQo7iM0ioCrxe+8csBW8AjYSC8/cZYdYJy+xesMB oHoODk4BW4m7q/JA5kgIzOWQmPV/CVSNi8SXU3dYIGxhiVfHt0DFpSQ+v9vLBtIrIZAt0bPL GCJcI7F03jGocnuJA1fmsICUMAtoSqzfpQ8SZhbgk+j9/YQJopNXoqNNCKJaVaL53VWoTmmJ id3d0DDxkFh6djE7JBgmMErMnjyBdQKj7CyEqQsYGVcxSqYWFOempxabFhjmpZbD4yk5P3cT IzhZannuYLz74IPeIUYmDsZDjBIczEoivP1F9xOFeFMSK6tSi/Lji0pzUosPMZoCQ2wis5Ro cj4wXeeVxBuaWBqYmJmZmVgamxkqifOeTt+QKCSQnliSmp2aWpBaBNPHxMEp1cA0xb1lij77 vpP5tuFd2a6XwoVdTh+alntnh8y840Uzk553euve++2XfSMxh/Xrl+bwf86q3zw7Vqh9kF0r pmi5JaB1jV6A4+NbtwsWLWZkmftuTu7UA6ZL522SeVzdHhJZ+G6zz6sLWeI5jmFrrqbvvpD3 zenwZeuIq+9iX6+dvLx827oX7UdvcPy6yG8lcdLo8NF96/r+hjX1zM58W2gn09ev7T7zsEyb tP2UtDpfE5/P+0q3Ve+oVPT+8f1MUvzS7n8vfX/YKL82jGbVPqlzZWGulzeLtrCnH+Pa+Zq8 h3Q+Nd7V8Nj9dqPXckOxvw86Lbb1342OEfiRcebYlaCDnzY3Oy3UuKUZ1yDHtXCbEktxRqKh FnNRcSIAMjlZ7x8EAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrALMWRmVeSWpSXmKPExsWy7bCSvO46yQeJBn1tqhYP5m1js3i/rIfR Yv6Rc6wWG9/+YLKY8mc5k8Wmx9dYLT723GO1ePgq3OLyrjlsFjPO72OyOHX9M5vFoq1f2C1a 9x5htzj8pp3V4vH1P2wO/B5r5q1h9JjV0MvmsWlVJ5vHnWt72Dw2L6n3uHKiidWjb8sqRo9/ TXPZPT5vkgvgjOKySUnNySxLLdK3S+DKWDFPoeCcYcXBszvZGhgnKnYxcnJICJhInFjUxNzF yMUhJLCbUeLR2essEAlpiesbJ7BD2MISK/89Z4coamKSmHj8NhtIgk1AW+Lu9C1MILaIgIdE 2797YJOYBd4wSfy/PwdskrCAi0T/9Slgk1gEVCV+753DCmLzCthILDxzF2qDvMTqDQeAmjk4 OAVsJe6uygMJCwGVnHu1nm0CI98CRoZVjJKpBcW56bnFhgWGeanlesWJucWleel6yfm5mxjB ga6luYNx+6oPeocYmTgYDzFKcDArifD2F91PFOJNSaysSi3Kjy8qzUktPsQozcGiJM57oetk vJBAemJJanZqakFqEUyWiYNTqoHJ4OaL1rsLvF58NNMokfW+tXfyA56k1/Hf+MXOppqkzc+Z 7/7T057zcrXSLK24Ak3TzEO+72VL23QKlvFvNi7Z+kchqVzLdMulj/mX35xOmh5k2d8427BV wPKe1/cfDI55s/+H3NgT1/5qU4ZEQPM+Ht6Z/G35+VHsDJc/l99YNTXt7pPf28ruZVWyL7/h +ZH1+pX7fE+kbx+6WX3iS/zH4iyWR4L83RF7mW9e2Js+bU3cxnNxWYkaLZvX2CpZCv/S8wt9 +KD5Vfc7p4hL/U4flt47UJtmYVWyxflo8hm22mT1Zw0vJ9jqTv5wMIf1y5Wcl1oef/TiLh97 /fEi/2drl0euz/x2z7+25XKAV9kMJZbijERDLeai4kQAAMHgjOMCAAA= X-CMS-MailID: 20220113122311epcas5p4b7c253b49dce3bd3580407fcf312e70e X-Msg-Generator: CA CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220113122311epcas5p4b7c253b49dce3bd3580407fcf312e70e References: <20220113121143.22280-1-alim.akhtar@samsung.com> Add dt-schema documentation for Tesla FSD SoC clock controller. Cc: linux-fsd@tesla.com Signed-off-by: Alim Akhtar --- .../bindings/clock/tesla,fsd-clock.yaml | 212 ++++++++++++++++++ 1 file changed, 212 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/tesla,fsd-clock.yaml diff --git a/Documentation/devicetree/bindings/clock/tesla,fsd-clock.yaml b/Documentation/devicetree/bindings/clock/tesla,fsd-clock.yaml new file mode 100644 index 000000000000..58f341e5004d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/tesla,fsd-clock.yaml @@ -0,0 +1,212 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/tesla,fsd-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Tesla FSD (Full Self-Driving) SoC clock controller + +maintainers: + - Alim Akhtar + - linux-fsd@tesla.com + +description: | + FSD clock controller consist of several clock management unit + (CMU), which generates clocks for various inteernal SoC blocks. + The root clock comes from external OSC clock (24 MHz). + + All available clocks are defined as preprocessor macros in + 'dt-bindings/clock/fsd-clk.h' header. + +properties: + compatible: + enum: + - tesla,fsd-clock-cmu + - tesla,fsd-clock-imem + - tesla,fsd-clock-peric + - tesla,fsd-clock-fsys0 + - tesla,fsd-clock-fsys1 + - tesla,fsd-clock-mfc + - tesla,fsd-clock-cam_csi + + clocks: + minItems: 1 + maxItems: 6 + + clock-names: + minItems: 1 + maxItems: 6 + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +allOf: + - if: + properties: + compatible: + contains: + const: tesla,fsd-clock-cmu + + then: + properties: + clocks: + items: + - description: External reference clock (24 MHz) + + clock-names: + items: + - const: fin_pll + + - if: + properties: + compatible: + contains: + const: tesla,fsd-clock-imem + + then: + properties: + clocks: + items: + - description: External reference clock (24 MHz) + - description: IMEM TCU clock (from CMU_CMU) + - description: IMEM bus clock (from CMU_CMU) + - description: IMEM DMA clock (from CMU_CMU) + + clock-names: + items: + - const: fin_pll + - const: dout_cmu_imem_tcuclk + - const: dout_cmu_imem_aclk + - const: dout_cmu_imem_dmaclk + + - if: + properties: + compatible: + contains: + const: tesla,fsd-clock-peric + + then: + properties: + clocks: + items: + - description: External reference clock (24 MHz) + - description: Shared0 PLL div4 clock (from CMU_CMU) + - description: PERIC shared1 div36 clock (from CMU_CMU) + - description: PERIC shared0 div3 TBU clock (from CMU_CMU) + - description: PERIC shared0 div20 clock (from CMU_CMU) + - description: PERIC shared1 div4 DMAclock (from CMU_CMU) + + clock-names: + items: + - const: fin_pll + - const: dout_cmu_pll_shared0_div4 + - const: dout_cmu_peric_shared1div36 + - const: dout_cmu_peric_shared0div3_tbuclk + - const: dout_cmu_peric_shared0div20 + - const: dout_cmu_peric_shared1div4_dmaclk + + - if: + properties: + compatible: + contains: + const: tesla,fsd-clock-fsys0 + + then: + properties: + clocks: + items: + - description: External reference clock (24 MHz) + - description: Shared0 PLL div6 clock (from CMU_CMU) + - description: FSYS0 shared1 div4 clock (from CMU_CMU) + - description: FSYS0 shared0 div4 clock (from CMU_CMU) + + clock-names: + items: + - const: fin_pll + - const: dout_cmu_pll_shared0_div6 + - const: dout_cmu_fsys0_shared1div4 + - const: dout_cmu_fsys0_shared0div4 + + - if: + properties: + compatible: + contains: + const: tesla,fsd-clock-fsys1 + + then: + properties: + clocks: + items: + - description: External reference clock (24 MHz) + - description: FSYS1 shared0 div8 clock (from CMU_CMU) + - description: FSYS1 shared0 div4 clock (from CMU_CMU) + + clock-names: + items: + - const: fin_pll + - const: dout_cmu_fsys1_shared0div8 + - const: dout_cmu_fsys1_shared0div4 + + - if: + properties: + compatible: + contains: + const: tesla,fsd-clock-mfc + + then: + properties: + clocks: + items: + - description: External reference clock (24 MHz) + + clock-names: + items: + - const: fin_pll + + - if: + properties: + compatible: + contains: + const: tesla,fsd-clock-cam_csi + + then: + properties: + clocks: + items: + - description: External reference clock (24 MHz) + + clock-names: + items: + - const: fin_pll + +required: + - compatible + - "#clock-cells" + - clocks + - clock-names + - reg + +additionalProperties: false + +examples: + # Clock controller node for CMU_FSYS1 + - | + #include + + clock_fsys1: clock-controller@16810000 { + compatible = "tesla,fsd-clock-fsys1"; + reg = <0x0 0x16810000 0x0 0x3000>; + #clock-cells = <1>; + + clocks = <&fin_pll>, + <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV8>, + <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV4>; + clock-names = "fin_pll", + "dout_cmu_fsys1_shared0div8", + "dout_cmu_fsys1_shared0div4"; + }; + +... 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Thu, 13 Jan 2022 21:23:16 +0900 (KST) Received: from Jaguar.sa.corp.samsungelectronics.net (unknown [107.108.73.139]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20220113122314epsmtip23e1b8747bd33638d73f8c8d98404bb32~J0-aEJDBH1245812458epsmtip2g; Thu, 13 Jan 2022 12:23:14 +0000 (GMT) From: Alim Akhtar To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org List-Id: Cc: soc@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, olof@lixom.net, linus.walleij@linaro.org, catalin.marinas@arm.com, robh+dt@kernel.org, krzysztof.kozlowski@canonical.com, s.nawrocki@samsung.com, linux-samsung-soc@vger.kernel.org, pankaj.dubey@samsung.com, Alim Akhtar , linux-fsd@tesla.com Subject: [PATCH 02/23] dt-bindings: clock: Add bindings definitions for FSD CMU blocks Date: Thu, 13 Jan 2022 17:41:22 +0530 Message-Id: <20220113121143.22280-3-alim.akhtar@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220113121143.22280-1-alim.akhtar@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupik+LIzCtJLcpLzFFi42LZdlhTQ3er5INEg/+HlSwezNvGZvF+WQ+j xfwj51gtNr79wWQx5c9yJotNj6+xWnzsucdq8fBVuMXlXXPYLGac38dkcer6ZzaLRVu/sFu0 7j3CbnH4TTurxePrf9gc+D3WzFvD6DGroZfNY9OqTjaPO9f2sHlsXlLvceVEE6tH35ZVjB7/ muaye3zeJBfAGZVtk5GamJJapJCal5yfkpmXbqvkHRzvHG9qZmCoa2hpYa6kkJeYm2qr5OIT oOuWmQP0gJJCWWJOKVAoILG4WEnfzqYov7QkVSEjv7jEVim1ICWnwKRArzgxt7g0L10vL7XE ytDAwMgUqDAhO2PLlktsBa/1K65uWsTUwHhJvYuRk0NCwERiwZMlzF2MXBxCArsZJW51vGKH cD4xSvxfvoMFpEpI4DOjxLteTpiOMxOeQXXsYpR49WAyK0RRC5NE6zpHEJtNQFvi7vQtTCC2 iICbxI3GDiaQBmaBe0wSPw43MIMkhAUiJBadXcsOYrMIqErc3vMCLM4rYCOx8epNZoht8hKr NxwAsjk4OAVsJe6uygOZIyEwl0Ni16teRogaF4nzl+4zQdjCEq+Ob2GHsKUkXva3sYP0Sghk S/TsMoYI10gsnXeMBcK2lzhwZQ4LSAmzgKbE+l36IGFmAT6J3t9PmCA6eSU62oQgqlUlmt9d heqUlpjY3c0KYXtIvJv9BxoKExgllk50m8AoOwth6AJGxlWMkqkFxbnpqcWmBcZ5qeXwWErO z93ECE6UWt47GB89+KB3iJGJg/EQowQHs5IIb3/R/UQh3pTEyqrUovz4otKc1OJDjKbAAJvI LCWanA9M1Xkl8YYmlgYmZmZmJpbGZoZK4ryn0jckCgmkJ5akZqemFqQWwfQxcXBKNTAVVL9w 443rKwtd/I9LwC9jBz9T/+zv3nJiFzdrHO/guC654W3+yl8HM9tXrHBmnLDVTMw+0VEuZudt 5tRG1e/5yaEy6fYGHMGrrjjcU1K57PzMc2rh1gXBm/fcEUmuFjGYds7HqX92Qkmg2tGV+VHh hq9Ot0/ZP/v1hHlBR09x8SlszfK5eG/JRBXdrbt/HsniUnl+5yyL+vxVyWtP3VvVZvREdIOB a4dRgKM6V/nZGTpmay9NSZ345/X6ADe+KnXej35ZTyZ8tbhseb74HYOuoca19j+HsqqeXN9q mbNVju+M6tL1Kztnz/cV8H97NO1Y5WOFT4pTnpXoPenO3GC5SUjk8879Zu66Ta27d7srsRRn JBpqMRcVJwIAsYYXfx0EAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrALMWRmVeSWpSXmKPExsWy7bCSvO4WyQeJBvc6DCwezNvGZvF+WQ+j xfwj51gtNr79wWQx5c9yJotNj6+xWnzsucdq8fBVuMXlXXPYLGac38dkcer6ZzaLRVu/sFu0 7j3CbnH4TTurxePrf9gc+D3WzFvD6DGroZfNY9OqTjaPO9f2sHlsXlLvceVEE6tH35ZVjB7/ muaye3zeJBfAGcVlk5Kak1mWWqRvl8CVsWXLJbaC1/oVVzctYmpgvKTexcjJISFgInFmwjPm LkYuDiGBHYwSj083MEEkpCWub5zADmELS6z895wdoqiJSeL/w16wIjYBbYm707eA2SICHhJt /+6BTWIWeANUdH8OSxcjB4ewQJjE/UZ5kBoWAVWJ23teMIPYvAI2Ehuv3mSGWCAvsXrDAWaQ ck4BW4m7q/JAwkJAJederWebwMi3gJFhFaNkakFxbnpusWGBUV5quV5xYm5xaV66XnJ+7iZG cKBrae1g3LPqg94hRiYOxkOMEhzMSiK8/UX3E4V4UxIrq1KL8uOLSnNSiw8xSnOwKInzXug6 GS8kkJ5YkpqdmlqQWgSTZeLglGpg4mSqeLmY5fKlJQ0TZFybqq7GbswSLz/f9exz9c+HmTeb Hl31+BD7qyivNdyJybR3c3LR55qF60wXNv40rJucv9tBc82Rl2/tlhbvsXeTPj+xY+uqbR9m GCharntiFTvH9/v/k3aTDz70qrQuN69jK5djU3u/eVpkYPZ2259fuTbeNFGR5k9P5dY2mG1t n5T9Lyjh+58+lg/pXTOLXjwq+XYlZevmzPZoIakLzxaUMVje9XK1K7p6daL31uOrWIP52yTn N93aJ6552/D1DW9twZfVua9U1O6Kaf/11itMY2c0M+v6WvgrreqTnbJV/ialJ2GPmENmcZfP zvjr8sZ5t3JVb5V08ldZl6qqj7ZKLMUZiYZazEXFiQCBsnzi4wIAAA== X-CMS-MailID: 20220113122317epcas5p11937078e2701b319a13b29e044224ec0 X-Msg-Generator: CA CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220113122317epcas5p11937078e2701b319a13b29e044224ec0 References: <20220113121143.22280-1-alim.akhtar@samsung.com> Clock controller driver of FSD platform is designed to have separate instances for each particular CMU. So clock IDs in this bindings header also start from 1 for each CMU block. Cc: linux-fsd@tesla.com Signed-off-by: Pankaj Dubey Signed-off-by: Alim Akhtar --- include/dt-bindings/clock/fsd-clk.h | 146 ++++++++++++++++++++++++++++ 1 file changed, 146 insertions(+) create mode 100644 include/dt-bindings/clock/fsd-clk.h +#define CAM_CSI2_3_IPCLKPORT_I_ACLK 12 +#define CAM_CSI_NR_CLK 13 +#endif /* _DT_BINDINGS_CLOCK_FSD_H */ diff --git a/include/dt-bindings/clock/fsd-clk.h b/include/dt-bindings/clock/fsd-clk.h new file mode 100644 index 000000000000..9b97417ea6a1 --- /dev/null +++ b/include/dt-bindings/clock/fsd-clk.h @@ -0,0 +1,146 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017 - 2022: Samsung Electronics Co., Ltd. + * https://www.samsung.com + * Copyright (c) 2017-2022 Tesla, Inc. + * https://www.tesla.com + * + * The constants defined in this header are being used in dts + * and fsd platform driver. + */ + +#ifndef _DT_BINDINGS_CLOCK_FSD_H +#define _DT_BINDINGS_CLOCK_FSD_H + +/* CMU */ +#define DOUT_CMU_PLL_SHARED0_DIV4 1 +#define DOUT_CMU_PERIC_SHARED1DIV36 2 +#define DOUT_CMU_PERIC_SHARED0DIV3_TBUCLK 3 +#define DOUT_CMU_PERIC_SHARED0DIV20 4 +#define DOUT_CMU_PERIC_SHARED1DIV4_DMACLK 5 +#define DOUT_CMU_PLL_SHARED0_DIV6 6 +#define DOUT_CMU_FSYS0_SHARED1DIV4 7 +#define DOUT_CMU_FSYS0_SHARED0DIV4 8 +#define DOUT_CMU_FSYS1_SHARED0DIV8 9 +#define DOUT_CMU_FSYS1_SHARED0DIV4 10 +#define CMU_CPUCL_SWITCH_GATE 11 +#define DOUT_CMU_IMEM_TCUCLK 12 +#define DOUT_CMU_IMEM_ACLK 13 +#define DOUT_CMU_IMEM_DMACLK 14 +#define GAT_CMU_FSYS0_SHARED0DIV4 15 +#define CMU_NR_CLK 16 + +/* PERIC */ +#define PERIC_SCLK_UART0 1 +#define PERIC_PCLK_UART0 2 +#define PERIC_SCLK_UART1 3 +#define PERIC_PCLK_UART1 4 +#define PERIC_DMA0_IPCLKPORT_ACLK 5 +#define PERIC_DMA1_IPCLKPORT_ACLK 6 +#define PERIC_PWM0_IPCLKPORT_I_PCLK_S0 7 +#define PERIC_PWM1_IPCLKPORT_I_PCLK_S0 8 +#define PERIC_PCLK_SPI0 9 +#define PERIC_SCLK_SPI0 10 +#define PERIC_PCLK_SPI1 11 +#define PERIC_SCLK_SPI1 12 +#define PERIC_PCLK_SPI2 13 +#define PERIC_SCLK_SPI2 14 +#define PERIC_PCLK_TDM0 15 +#define PERIC_PCLK_HSI2C0 16 +#define PERIC_PCLK_HSI2C1 17 +#define PERIC_PCLK_HSI2C2 18 +#define PERIC_PCLK_HSI2C3 19 +#define PERIC_PCLK_HSI2C4 20 +#define PERIC_PCLK_HSI2C5 21 +#define PERIC_PCLK_HSI2C6 22 +#define PERIC_PCLK_HSI2C7 23 +#define PERIC_MCAN0_IPCLKPORT_CCLK 24 +#define PERIC_MCAN0_IPCLKPORT_PCLK 25 +#define PERIC_MCAN1_IPCLKPORT_CCLK 26 +#define PERIC_MCAN1_IPCLKPORT_PCLK 27 +#define PERIC_MCAN2_IPCLKPORT_CCLK 28 +#define PERIC_MCAN2_IPCLKPORT_PCLK 29 +#define PERIC_MCAN3_IPCLKPORT_CCLK 30 +#define PERIC_MCAN3_IPCLKPORT_PCLK 31 +#define PERIC_PCLK_ADCIF 32 +#define PERIC_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I 33 +#define PERIC_EQOS_TOP_IPCLKPORT_ACLK_I 34 +#define PERIC_EQOS_TOP_IPCLKPORT_HCLK_I 35 +#define PERIC_EQOS_TOP_IPCLKPORT_RGMII_CLK_I 36 +#define PERIC_EQOS_TOP_IPCLKPORT_CLK_RX_I 37 +#define PERIC_BUS_D_PERIC_IPCLKPORT_EQOSCLK 38 +#define PERIC_BUS_P_PERIC_IPCLKPORT_EQOSCLK 39 +#define PERIC_HCLK_TDM0 40 +#define PERIC_PCLK_TDM1 41 +#define PERIC_HCLK_TDM1 42 +#define PERIC_EQOS_PHYRXCLK_MUX 43 +#define PERIC_EQOS_PHYRXCLK 44 +#define PERIC_DOUT_RGMII_CLK 45 +#define PERIC_NR_CLK 46 + +/* FSYS0 */ +#define UFS0_MPHY_REFCLK_IXTAL24 1 +#define UFS0_MPHY_REFCLK_IXTAL26 2 +#define UFS1_MPHY_REFCLK_IXTAL24 3 +#define UFS1_MPHY_REFCLK_IXTAL26 4 +#define UFS0_TOP0_HCLK_BUS 5 +#define UFS0_TOP0_ACLK 6 +#define UFS0_TOP0_CLK_UNIPRO 7 +#define UFS0_TOP0_FMP_CLK 8 +#define UFS1_TOP1_HCLK_BUS 9 +#define UFS1_TOP1_ACLK 10 +#define UFS1_TOP1_CLK_UNIPRO 11 +#define UFS1_TOP1_FMP_CLK 12 +#define PCIE_SUBCTRL_INST0_DBI_ACLK_SOC 13 +#define PCIE_SUBCTRL_INST0_AUX_CLK_SOC 14 +#define PCIE_SUBCTRL_INST0_MSTR_ACLK_SOC 15 +#define PCIE_SUBCTRL_INST0_SLV_ACLK_SOC 16 +#define FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I 17 +#define FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I 18 +#define FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I 19 +#define FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I 20 +#define FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I 21 +#define FSYS0_DOUT_FSYS0_PERIBUS_GRP 22 +#define FSYS0_NR_CLK 23 + +/* FSYS1 */ +#define PCIE_LINK0_IPCLKPORT_DBI_ACLK 1 +#define PCIE_LINK0_IPCLKPORT_AUX_ACLK 2 +#define PCIE_LINK0_IPCLKPORT_MSTR_ACLK 3 +#define PCIE_LINK0_IPCLKPORT_SLV_ACLK 4 +#define PCIE_LINK1_IPCLKPORT_DBI_ACLK 5 +#define PCIE_LINK1_IPCLKPORT_AUX_ACLK 6 +#define PCIE_LINK1_IPCLKPORT_MSTR_ACLK 7 +#define PCIE_LINK1_IPCLKPORT_SLV_ACLK 8 +#define FSYS1_NR_CLK 9 + +/* IMEM */ +#define IMEM_DMA0_IPCLKPORT_ACLK 1 +#define IMEM_DMA1_IPCLKPORT_ACLK 2 +#define IMEM_WDT0_IPCLKPORT_PCLK 3 +#define IMEM_WDT1_IPCLKPORT_PCLK 4 +#define IMEM_WDT2_IPCLKPORT_PCLK 5 +#define IMEM_MCT_PCLK 6 +#define IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS 7 +#define IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS 8 +#define IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS 9 +#define IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS 10 +#define IMEM_TMU_GT_IPCLKPORT_I_CLK_TS 11 +#define IMEM_NR_CLK 12 + +/* MFC */ +#define MFC_MFC_IPCLKPORT_ACLK 1 +#define MFC_NR_CLK 2 + +/* CAM_CSI */ +#define CAM_CSI0_0_IPCLKPORT_I_ACLK 1 +#define CAM_CSI0_1_IPCLKPORT_I_ACLK 2 +#define CAM_CSI0_2_IPCLKPORT_I_ACLK 3 +#define CAM_CSI0_3_IPCLKPORT_I_ACLK 4 +#define CAM_CSI1_0_IPCLKPORT_I_ACLK 5 +#define CAM_CSI1_1_IPCLKPORT_I_ACLK 6 +#define CAM_CSI1_2_IPCLKPORT_I_ACLK 7 +#define CAM_CSI1_3_IPCLKPORT_I_ACLK 8 +#define CAM_CSI2_0_IPCLKPORT_I_ACLK 9 +#define CAM_CSI2_1_IPCLKPORT_I_ACLK 10 +#define CAM_CSI2_2_IPCLKPORT_I_ACLK 11 From patchwork Thu Jan 13 12:11:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alim Akhtar X-Patchwork-Id: 12712655 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 38632C433FE for ; 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2022 12:23:21 +0000 (GMT) From: Alim Akhtar To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org List-Id: Cc: soc@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, olof@lixom.net, linus.walleij@linaro.org, catalin.marinas@arm.com, robh+dt@kernel.org, krzysztof.kozlowski@canonical.com, s.nawrocki@samsung.com, linux-samsung-soc@vger.kernel.org, pankaj.dubey@samsung.com, Alim Akhtar , linux-fsd@tesla.com, Jayati Sahu , Ajay Kumar Subject: [PATCH 03/23] clk: samsung: fsd: Add initial clock support Date: Thu, 13 Jan 2022 17:41:23 +0530 Message-Id: <20220113121143.22280-4-alim.akhtar@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220113121143.22280-1-alim.akhtar@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprOJsWRmVeSWpSXmKPExsWy7bCmhu5eyQeJBuf+ilgceH+QxeLBvG1s Fu+X9TBazD9yjtXiyKklTBYb3/5gspjyZzmTxabH11gtPvbcY7V4+Crc4vKuOWwWM87vY7I4 df0zm8WirV/YLVr3HmG3OPymndXi8fU/bA6CHmvmrWH0mNXQy+axaVUnm8eda3vYPDYvqfe4 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XeOdZXrjbq3oK8aNBUK/znZ1+K2etszcRm+p8JmrS6XmBAk+i5pUWVlpv8RG22yt4r0FJxIe moa/rWv5MG0ee4mhw4e7Vz49+H15hceDHWkFjsqrRWdMaJjnw7s0ySbtuVOE8c8Epvs8F1q3 3u2faeK70/PbCXclQ5bNu/5wvg5h3LEm1epQf1SuifaeSTzPIh8tYVUr8lSvsKjezaJgE3fM NyLmS8+7Jq1Vf+pTpEJXylwNrRU+uTKkQdb3b8e7zOObG6Yb5imxFGckGmoxFxUnAgCv8H8H 7gIAAA== X-CMS-MailID: 20220113122324epcas5p105c53b448b5801813a02a88c6107a2f3 X-Msg-Generator: CA CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220113122324epcas5p105c53b448b5801813a02a88c6107a2f3 References: <20220113121143.22280-1-alim.akhtar@samsung.com> Add initial clock support for FSD (Full Self-Driving) SoC which is required to bring-up platforms based on this SoC. Cc: linux-fsd@tesla.com Signed-off-by: Jayati Sahu Signed-off-by: Ajay Kumar Signed-off-by: Pankaj Dubey Signed-off-by: Alim Akhtar --- drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-fsd.c | 308 ++++++++++++++++++++++++++++++++++ drivers/clk/samsung/clk-pll.c | 1 + drivers/clk/samsung/clk-pll.h | 1 + 4 files changed, 311 insertions(+) create mode 100644 drivers/clk/samsung/clk-fsd.c diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index c46cf11e4d0b..d66b2ede004c 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_EXYNOS_AUDSS_CLK_CON) += clk-exynos-audss.o obj-$(CONFIG_EXYNOS_CLKOUT) += clk-exynos-clkout.o obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos850.o +obj-$(CONFIG_ARCH_TESLA_FSD) += clk-fsd.o obj-$(CONFIG_S3C2410_COMMON_CLK)+= clk-s3c2410.o obj-$(CONFIG_S3C2410_COMMON_DCLK)+= clk-s3c2410-dclk.o obj-$(CONFIG_S3C2412_COMMON_CLK)+= clk-s3c2412.o diff --git a/drivers/clk/samsung/clk-fsd.c b/drivers/clk/samsung/clk-fsd.c new file mode 100644 index 000000000000..e47523106d9e --- /dev/null +++ b/drivers/clk/samsung/clk-fsd.c @@ -0,0 +1,308 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Common Clock Framework support for FSD SoC. + * + * Copyright (c) 2017-2022 Samsung Electronics Co., Ltd. + * https://www.samsung.com + * Copyright (c) 2017-2022 Tesla, Inc. + * https://www.tesla.com + * + */ + +#include +#include + +#include "clk.h" +#include + +/* Register Offset definitions for CMU_CMU (0x11c10000) */ +#define PLL_LOCKTIME_PLL_SHARED0 0x0 +#define PLL_LOCKTIME_PLL_SHARED1 0x4 +#define PLL_LOCKTIME_PLL_SHARED2 0x8 +#define PLL_LOCKTIME_PLL_SHARED3 0xc +#define PLL_CON0_PLL_SHARED0 0x100 +#define PLL_CON0_PLL_SHARED1 0x120 +#define PLL_CON0_PLL_SHARED2 0x140 +#define PLL_CON0_PLL_SHARED3 0x160 +#define MUX_CMU_CIS0_CLKMUX 0x1000 +#define MUX_CMU_CIS1_CLKMUX 0x1004 +#define MUX_CMU_CIS2_CLKMUX 0x1008 +#define MUX_CMU_CPUCL_SWITCHMUX 0x100c +#define MUX_CMU_FSYS1_ACLK_MUX 0x1014 +#define MUX_PLL_SHARED0_MUX 0x1020 +#define MUX_PLL_SHARED1_MUX 0x1024 +#define DIV_CMU_CIS0_CLK 0x1800 +#define DIV_CMU_CIS1_CLK 0x1804 +#define DIV_CMU_CIS2_CLK 0x1808 +#define DIV_CMU_CMU_ACLK 0x180c +#define DIV_CMU_CPUCL_SWITCH 0x1810 +#define DIV_CMU_FSYS0_SHARED0DIV4 0x181c +#define DIV_CMU_FSYS0_SHARED1DIV3 0x1820 +#define DIV_CMU_FSYS0_SHARED1DIV4 0x1824 +#define DIV_CMU_FSYS1_SHARED0DIV4 0x1828 +#define DIV_CMU_FSYS1_SHARED0DIV8 0x182c +#define DIV_CMU_IMEM_ACLK 0x1834 +#define DIV_CMU_IMEM_DMACLK 0x1838 +#define DIV_CMU_IMEM_TCUCLK 0x183c +#define DIV_CMU_PERIC_SHARED0DIV20 0x1844 +#define DIV_CMU_PERIC_SHARED0DIV3_TBUCLK 0x1848 +#define DIV_CMU_PERIC_SHARED1DIV36 0x184c +#define DIV_CMU_PERIC_SHARED1DIV4_DMACLK 0x1850 +#define DIV_PLL_SHARED0_DIV2 0x1858 +#define DIV_PLL_SHARED0_DIV3 0x185c +#define DIV_PLL_SHARED0_DIV4 0x1860 +#define DIV_PLL_SHARED0_DIV6 0x1864 +#define DIV_PLL_SHARED1_DIV3 0x1868 +#define DIV_PLL_SHARED1_DIV36 0x186c +#define DIV_PLL_SHARED1_DIV4 0x1870 +#define DIV_PLL_SHARED1_DIV9 0x1874 +#define GAT_CMU_CIS0_CLKGATE 0x2000 +#define GAT_CMU_CIS1_CLKGATE 0x2004 +#define GAT_CMU_CIS2_CLKGATE 0x2008 +#define GAT_CMU_CPUCL_SWITCH_GATE 0x200c +#define GAT_CMU_FSYS0_SHARED0DIV4_GATE 0x2018 +#define GAT_CMU_FSYS0_SHARED1DIV4_CLK 0x201c +#define GAT_CMU_FSYS0_SHARED1DIV4_GATE 0x2020 +#define GAT_CMU_FSYS1_SHARED0DIV4_GATE 0x2024 +#define GAT_CMU_FSYS1_SHARED1DIV4_GATE 0x2028 +#define GAT_CMU_IMEM_ACLK_GATE 0x2030 +#define GAT_CMU_IMEM_DMACLK_GATE 0x2034 +#define GAT_CMU_IMEM_TCUCLK_GATE 0x2038 +#define GAT_CMU_PERIC_SHARED0DIVE3_TBUCLK_GATE 0x2040 +#define GAT_CMU_PERIC_SHARED0DIVE4_GATE 0x2044 +#define GAT_CMU_PERIC_SHARED1DIV4_DMACLK_GATE 0x2048 +#define GAT_CMU_PERIC_SHARED1DIVE4_GATE 0x204c +#define GAT_CMU_CMU_CMU_IPCLKPORT_PCLK 0x2054 +#define GAT_CMU_AXI2APB_CMU_IPCLKPORT_ACLK 0x2058 +#define GAT_CMU_NS_BRDG_CMU_IPCLKPORT_CLK__PSOC_CMU__CLK_CMU 0x205c +#define GAT_CMU_SYSREG_CMU_IPCLKPORT_PCLK 0x2060 + +static const unsigned long cmu_clk_regs[] __initconst = { + PLL_LOCKTIME_PLL_SHARED0, + PLL_LOCKTIME_PLL_SHARED1, + PLL_LOCKTIME_PLL_SHARED2, + PLL_LOCKTIME_PLL_SHARED3, + PLL_CON0_PLL_SHARED0, + PLL_CON0_PLL_SHARED1, + PLL_CON0_PLL_SHARED2, + PLL_CON0_PLL_SHARED3, + MUX_CMU_CIS0_CLKMUX, + MUX_CMU_CIS1_CLKMUX, + MUX_CMU_CIS2_CLKMUX, + MUX_CMU_CPUCL_SWITCHMUX, + MUX_CMU_FSYS1_ACLK_MUX, + MUX_PLL_SHARED0_MUX, + MUX_PLL_SHARED1_MUX, + DIV_CMU_CIS0_CLK, + DIV_CMU_CIS1_CLK, + DIV_CMU_CIS2_CLK, + DIV_CMU_CMU_ACLK, + DIV_CMU_CPUCL_SWITCH, + DIV_CMU_FSYS0_SHARED0DIV4, + DIV_CMU_FSYS0_SHARED1DIV3, + DIV_CMU_FSYS0_SHARED1DIV4, + DIV_CMU_FSYS1_SHARED0DIV4, + DIV_CMU_FSYS1_SHARED0DIV8, + DIV_CMU_IMEM_ACLK, + DIV_CMU_IMEM_DMACLK, + DIV_CMU_IMEM_TCUCLK, + DIV_CMU_PERIC_SHARED0DIV20, + DIV_CMU_PERIC_SHARED0DIV3_TBUCLK, + DIV_CMU_PERIC_SHARED1DIV36, + DIV_CMU_PERIC_SHARED1DIV4_DMACLK, + DIV_PLL_SHARED0_DIV2, + DIV_PLL_SHARED0_DIV3, + DIV_PLL_SHARED0_DIV4, + DIV_PLL_SHARED0_DIV6, + DIV_PLL_SHARED1_DIV3, + DIV_PLL_SHARED1_DIV36, + DIV_PLL_SHARED1_DIV4, + DIV_PLL_SHARED1_DIV9, + GAT_CMU_CIS0_CLKGATE, + GAT_CMU_CIS1_CLKGATE, + GAT_CMU_CIS2_CLKGATE, + GAT_CMU_CPUCL_SWITCH_GATE, + GAT_CMU_FSYS0_SHARED0DIV4_GATE, + GAT_CMU_FSYS0_SHARED1DIV4_CLK, + GAT_CMU_FSYS0_SHARED1DIV4_GATE, + GAT_CMU_FSYS1_SHARED0DIV4_GATE, + GAT_CMU_FSYS1_SHARED1DIV4_GATE, + GAT_CMU_IMEM_ACLK_GATE, + GAT_CMU_IMEM_DMACLK_GATE, + GAT_CMU_IMEM_TCUCLK_GATE, + GAT_CMU_PERIC_SHARED0DIVE3_TBUCLK_GATE, + GAT_CMU_PERIC_SHARED0DIVE4_GATE, + GAT_CMU_PERIC_SHARED1DIV4_DMACLK_GATE, + GAT_CMU_PERIC_SHARED1DIVE4_GATE, + GAT_CMU_CMU_CMU_IPCLKPORT_PCLK, + GAT_CMU_AXI2APB_CMU_IPCLKPORT_ACLK, + GAT_CMU_NS_BRDG_CMU_IPCLKPORT_CLK__PSOC_CMU__CLK_CMU, + GAT_CMU_SYSREG_CMU_IPCLKPORT_PCLK, +}; + +static const struct samsung_pll_rate_table pll_shared0_rate_table[] __initconst = { + PLL_35XX_RATE(24 * MHZ, 2000000000, 250, 3, 0), +}; + +static const struct samsung_pll_rate_table pll_shared1_rate_table[] __initconst = { + PLL_35XX_RATE(24 * MHZ, 2400000000, 200, 2, 0), +}; + +static const struct samsung_pll_rate_table pll_shared2_rate_table[] __initconst = { + PLL_35XX_RATE(24 * MHZ, 2400000000, 200, 2, 0), +}; + +static const struct samsung_pll_rate_table pll_shared3_rate_table[] __initconst = { + PLL_35XX_RATE(24 * MHZ, 1800000000, 150, 2, 0), +}; + +static const struct samsung_pll_clock cmu_pll_clks[] __initconst = { + PLL(pll_142xx, 0, "fout_pll_shared0", "fin_pll", PLL_LOCKTIME_PLL_SHARED0, + PLL_CON0_PLL_SHARED0, pll_shared0_rate_table), + PLL(pll_142xx, 0, "fout_pll_shared1", "fin_pll", PLL_LOCKTIME_PLL_SHARED1, + PLL_CON0_PLL_SHARED1, pll_shared1_rate_table), + PLL(pll_142xx, 0, "fout_pll_shared2", "fin_pll", PLL_LOCKTIME_PLL_SHARED2, + PLL_CON0_PLL_SHARED2, pll_shared2_rate_table), + PLL(pll_142xx, 0, "fout_pll_shared3", "fin_pll", PLL_LOCKTIME_PLL_SHARED3, + PLL_CON0_PLL_SHARED3, pll_shared3_rate_table), +}; + +/* List of parent clocks for Muxes in CMU_CMU */ +PNAME(mout_cmu_shared0_pll_p) = { "fin_pll", "fout_pll_shared0" }; +PNAME(mout_cmu_shared1_pll_p) = { "fin_pll", "fout_pll_shared1" }; +PNAME(mout_cmu_shared2_pll_p) = { "fin_pll", "fout_pll_shared2" }; +PNAME(mout_cmu_shared3_pll_p) = { "fin_pll", "fout_pll_shared3" }; +PNAME(mout_cmu_cis0_clkmux_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" }; +PNAME(mout_cmu_cis1_clkmux_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" }; +PNAME(mout_cmu_cis2_clkmux_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" }; +PNAME(mout_cmu_cpucl_switchmux_p) = { "mout_cmu_pll_shared2", "mout_cmu_pll_shared0_mux" }; +PNAME(mout_cmu_fsys1_aclk_mux_p) = { "dout_cmu_pll_shared0_div4", "fin_pll" }; +PNAME(mout_cmu_pll_shared0_mux_p) = { "fin_pll", "mout_cmu_pll_shared0" }; +PNAME(mout_cmu_pll_shared1_mux_p) = { "fin_pll", "mout_cmu_pll_shared1" }; + +static const struct samsung_mux_clock cmu_mux_clks[] __initconst = { + MUX(0, "mout_cmu_pll_shared0", mout_cmu_shared0_pll_p, PLL_CON0_PLL_SHARED0, 4, 1), + MUX(0, "mout_cmu_pll_shared1", mout_cmu_shared1_pll_p, PLL_CON0_PLL_SHARED1, 4, 1), + MUX(0, "mout_cmu_pll_shared2", mout_cmu_shared2_pll_p, PLL_CON0_PLL_SHARED2, 4, 1), + MUX(0, "mout_cmu_pll_shared3", mout_cmu_shared3_pll_p, PLL_CON0_PLL_SHARED3, 4, 1), + MUX(0, "mout_cmu_cis0_clkmux", mout_cmu_cis0_clkmux_p, MUX_CMU_CIS0_CLKMUX, 0, 1), + MUX(0, "mout_cmu_cis1_clkmux", mout_cmu_cis1_clkmux_p, MUX_CMU_CIS1_CLKMUX, 0, 1), + MUX(0, "mout_cmu_cis2_clkmux", mout_cmu_cis2_clkmux_p, MUX_CMU_CIS2_CLKMUX, 0, 1), + MUX(0, "mout_cmu_cpucl_switchmux", mout_cmu_cpucl_switchmux_p, + MUX_CMU_CPUCL_SWITCHMUX, 0, 1), + MUX(0, "mout_cmu_fsys1_aclk_mux", mout_cmu_fsys1_aclk_mux_p, MUX_CMU_FSYS1_ACLK_MUX, 0, 1), + MUX(0, "mout_cmu_pll_shared0_mux", mout_cmu_pll_shared0_mux_p, MUX_PLL_SHARED0_MUX, 0, 1), + MUX(0, "mout_cmu_pll_shared1_mux", mout_cmu_pll_shared1_mux_p, MUX_PLL_SHARED1_MUX, 0, 1), +}; + +static const struct samsung_div_clock cmu_div_clks[] __initconst = { + DIV(0, "dout_cmu_cis0_clk", "cmu_cis0_clkgate", DIV_CMU_CIS0_CLK, 0, 4), + DIV(0, "dout_cmu_cis1_clk", "cmu_cis1_clkgate", DIV_CMU_CIS1_CLK, 0, 4), + DIV(0, "dout_cmu_cis2_clk", "cmu_cis2_clkgate", DIV_CMU_CIS2_CLK, 0, 4), + DIV(0, "dout_cmu_cmu_aclk", "dout_cmu_pll_shared1_div9", DIV_CMU_CMU_ACLK, 0, 4), + DIV(0, "dout_cmu_cpucl_switch", "cmu_cpucl_switch_gate", DIV_CMU_CPUCL_SWITCH, 0, 4), + DIV(DOUT_CMU_FSYS0_SHARED0DIV4, "dout_cmu_fsys0_shared0div4", "cmu_fsys0_shared0div4_gate", + DIV_CMU_FSYS0_SHARED0DIV4, 0, 4), + DIV(0, "dout_cmu_fsys0_shared1div3", "cmu_fsys0_shared1div4_clk", + DIV_CMU_FSYS0_SHARED1DIV3, 0, 4), + DIV(DOUT_CMU_FSYS0_SHARED1DIV4, "dout_cmu_fsys0_shared1div4", "cmu_fsys0_shared1div4_gate", + DIV_CMU_FSYS0_SHARED1DIV4, 0, 4), + DIV(DOUT_CMU_FSYS1_SHARED0DIV4, "dout_cmu_fsys1_shared0div4", "cmu_fsys1_shared0div4_gate", + DIV_CMU_FSYS1_SHARED0DIV4, 0, 4), + DIV(DOUT_CMU_FSYS1_SHARED0DIV8, "dout_cmu_fsys1_shared0div8", "cmu_fsys1_shared1div4_gate", + DIV_CMU_FSYS1_SHARED0DIV8, 0, 4), + DIV(DOUT_CMU_IMEM_ACLK, "dout_cmu_imem_aclk", "cmu_imem_aclk_gate", + DIV_CMU_IMEM_ACLK, 0, 4), + DIV(DOUT_CMU_IMEM_DMACLK, "dout_cmu_imem_dmaclk", "cmu_imem_dmaclk_gate", + DIV_CMU_IMEM_DMACLK, 0, 4), + DIV(DOUT_CMU_IMEM_TCUCLK, "dout_cmu_imem_tcuclk", "cmu_imem_tcuclk_gate", + DIV_CMU_IMEM_TCUCLK, 0, 4), + DIV(DOUT_CMU_PERIC_SHARED0DIV20, "dout_cmu_peric_shared0div20", + "cmu_peric_shared0dive4_gate", DIV_CMU_PERIC_SHARED0DIV20, 0, 4), + DIV(DOUT_CMU_PERIC_SHARED0DIV3_TBUCLK, "dout_cmu_peric_shared0div3_tbuclk", + "cmu_peric_shared0dive3_tbuclk_gate", DIV_CMU_PERIC_SHARED0DIV3_TBUCLK, 0, 4), + DIV(DOUT_CMU_PERIC_SHARED1DIV36, "dout_cmu_peric_shared1div36", + "cmu_peric_shared1dive4_gate", DIV_CMU_PERIC_SHARED1DIV36, 0, 4), + DIV(DOUT_CMU_PERIC_SHARED1DIV4_DMACLK, "dout_cmu_peric_shared1div4_dmaclk", + "cmu_peric_shared1div4_dmaclk_gate", DIV_CMU_PERIC_SHARED1DIV4_DMACLK, 0, 4), + DIV(0, "dout_cmu_pll_shared0_div2", "mout_cmu_pll_shared0_mux", + DIV_PLL_SHARED0_DIV2, 0, 4), + DIV(0, "dout_cmu_pll_shared0_div3", "mout_cmu_pll_shared0_mux", + DIV_PLL_SHARED0_DIV3, 0, 4), + DIV(DOUT_CMU_PLL_SHARED0_DIV4, "dout_cmu_pll_shared0_div4", "dout_cmu_pll_shared0_div2", + DIV_PLL_SHARED0_DIV4, 0, 4), + DIV(DOUT_CMU_PLL_SHARED0_DIV6, "dout_cmu_pll_shared0_div6", "dout_cmu_pll_shared0_div3", + DIV_PLL_SHARED0_DIV6, 0, 4), + DIV(0, "dout_cmu_pll_shared1_div3", "mout_cmu_pll_shared1_mux", + DIV_PLL_SHARED1_DIV3, 0, 4), + DIV(0, "dout_cmu_pll_shared1_div36", "dout_cmu_pll_shared1_div9", + DIV_PLL_SHARED1_DIV36, 0, 4), + DIV(0, "dout_cmu_pll_shared1_div4", "mout_cmu_pll_shared1_mux", + DIV_PLL_SHARED1_DIV4, 0, 4), + DIV(0, "dout_cmu_pll_shared1_div9", "dout_cmu_pll_shared1_div3", + DIV_PLL_SHARED1_DIV9, 0, 4), +}; + +static const struct samsung_gate_clock cmu_gate_clks[] __initconst = { + GATE(0, "cmu_cis0_clkgate", "mout_cmu_cis0_clkmux", GAT_CMU_CIS0_CLKGATE, 21, + CLK_IGNORE_UNUSED, 0), + GATE(0, "cmu_cis1_clkgate", "mout_cmu_cis1_clkmux", GAT_CMU_CIS1_CLKGATE, 21, + CLK_IGNORE_UNUSED, 0), + GATE(0, "cmu_cis2_clkgate", "mout_cmu_cis2_clkmux", GAT_CMU_CIS2_CLKGATE, 21, + CLK_IGNORE_UNUSED, 0), + GATE(CMU_CPUCL_SWITCH_GATE, "cmu_cpucl_switch_gate", "mout_cmu_cpucl_switchmux", + GAT_CMU_CPUCL_SWITCH_GATE, 21, CLK_IGNORE_UNUSED, 0), + GATE(GAT_CMU_FSYS0_SHARED0DIV4, "cmu_fsys0_shared0div4_gate", "dout_cmu_pll_shared0_div4", + GAT_CMU_FSYS0_SHARED0DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cmu_fsys0_shared1div4_clk", "dout_cmu_pll_shared1_div3", + GAT_CMU_FSYS0_SHARED1DIV4_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cmu_fsys0_shared1div4_gate", "dout_cmu_pll_shared1_div4", + GAT_CMU_FSYS0_SHARED1DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cmu_fsys1_shared0div4_gate", "mout_cmu_fsys1_aclk_mux", + GAT_CMU_FSYS1_SHARED0DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cmu_fsys1_shared1div4_gate", "dout_cmu_fsys1_shared0div4", + GAT_CMU_FSYS1_SHARED1DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cmu_imem_aclk_gate", "dout_cmu_pll_shared1_div9", GAT_CMU_IMEM_ACLK_GATE, 21, + CLK_IGNORE_UNUSED, 0), + GATE(0, "cmu_imem_dmaclk_gate", "mout_cmu_pll_shared1_mux", GAT_CMU_IMEM_DMACLK_GATE, 21, + CLK_IGNORE_UNUSED, 0), + GATE(0, "cmu_imem_tcuclk_gate", "dout_cmu_pll_shared0_div3", GAT_CMU_IMEM_TCUCLK_GATE, 21, + CLK_IGNORE_UNUSED, 0), + GATE(0, "cmu_peric_shared0dive3_tbuclk_gate", "dout_cmu_pll_shared0_div3", + GAT_CMU_PERIC_SHARED0DIVE3_TBUCLK_GATE, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cmu_peric_shared0dive4_gate", "dout_cmu_pll_shared0_div4", + GAT_CMU_PERIC_SHARED0DIVE4_GATE, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cmu_peric_shared1div4_dmaclk_gate", "dout_cmu_pll_shared1_div4", + GAT_CMU_PERIC_SHARED1DIV4_DMACLK_GATE, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cmu_peric_shared1dive4_gate", "dout_cmu_pll_shared1_div36", + GAT_CMU_PERIC_SHARED1DIVE4_GATE, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cmu_uid_cmu_cmu_cmu_ipclkport_pclk", "dout_cmu_cmu_aclk", + GAT_CMU_CMU_CMU_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cmu_uid_axi2apb_cmu_ipclkport_aclk", "dout_cmu_cmu_aclk", + GAT_CMU_AXI2APB_CMU_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cmu_uid_ns_brdg_cmu_ipclkport_clk__psoc_cmu__clk_cmu", "dout_cmu_cmu_aclk", + GAT_CMU_NS_BRDG_CMU_IPCLKPORT_CLK__PSOC_CMU__CLK_CMU, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cmu_uid_sysreg_cmu_ipclkport_pclk", "dout_cmu_cmu_aclk", + GAT_CMU_SYSREG_CMU_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), +}; + +static const struct samsung_cmu_info cmu_cmu_info __initconst = { + .pll_clks = cmu_pll_clks, + .nr_pll_clks = ARRAY_SIZE(cmu_pll_clks), + .mux_clks = cmu_mux_clks, + .nr_mux_clks = ARRAY_SIZE(cmu_mux_clks), + .div_clks = cmu_div_clks, + .nr_div_clks = ARRAY_SIZE(cmu_div_clks), + .gate_clks = cmu_gate_clks, + .nr_gate_clks = ARRAY_SIZE(cmu_gate_clks), + .nr_clk_ids = CMU_NR_CLK, + .clk_regs = cmu_clk_regs, + .nr_clk_regs = ARRAY_SIZE(cmu_clk_regs), +}; + +static void __init fsd_clk_cmu_init(struct device_node *np) +{ + samsung_cmu_register_one(np, &cmu_cmu_info); +} + +CLK_OF_DECLARE(fsd_clk_cmu, "tesla,fsd-clock-cmu", fsd_clk_cmu_init); diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index 83d1b03647db..e321036875f0 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -1469,6 +1469,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, case pll_1450x: case pll_1451x: case pll_1452x: + case pll_142xx: pll->enable_offs = PLL35XX_ENABLE_SHIFT; pll->lock_offs = PLL35XX_LOCK_STAT_SHIFT; if (!pll->rate_table) diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index a739f2b7ae80..9ba5d7c867c5 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -38,6 +38,7 @@ enum samsung_pll_type { pll_1460x, pll_0822x, pll_0831x, + pll_142xx, }; #define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \ From patchwork Thu Jan 13 12:11:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 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04/23] clk: samsung: fsd: Add cmu_peric block clock information Date: Thu, 13 Jan 2022 17:41:24 +0530 Message-Id: <20220113121143.22280-5-alim.akhtar@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220113121143.22280-1-alim.akhtar@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrLJsWRmVeSWpSXmKPExsWy7bCmpu4hyQeJBh0/zCwOvD/IYvFg3jY2 i0Obt7JbvF/Ww2gx/8g5Vosjp5YwWWx8+4PJYsqf5UwWmx5fY7X42HOP1eLhq3CLy7vmsFnM OL+PyeLJlEesFqeuf2azWLT1C7vFrAs7WC1a9x5htzj8pp3V4vH1P2wWt9+sY3UQ9Vgzbw2j x6yGXjaPTas62TzuXNvD5rF5Sb3HlRNNrB59W1Yxevxrmsvu8XmTXABnVLZNRmpiSmqRQmpe cn5KZl66rZJ3cLxzvKmZgaGuoaWFuZJCXmJuqq2Si0+ArltmDtB7SgpliTmlQKGAxOJiJX07 m6L80pJUhYz84hJbpdSClJwCkwK94sTc4tK8dL281BIrQwMDI1OgwoTsjOWz5rMUbNrDWPH5 2Eq2BsbVyxi7GDk5JARMJG492cXexcjFISSwm1Hi5pzlrBDOJ0aJ6xs+MEM4nxklnqy+yQbT 8nByCxtEYhejRO/VH1AtLUwSd6csYQGpYhPQlrg7fQsTiC0i4CZxo7GDCaSIWeAqi8SP69+Y QRLCAoESq36eB7uERUBV4s3i92ANvAI2Et8PdDFBrJOXWL3hAFA9BwengK3E3VV5IHMkBC5w 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x6yGXjaPTas62TzuXNvD5rF5Sb3HlRNNrB59W1Yxevxrmsvu8XmTXABnFJdNSmpOZllqkb5d AlfG8lnzWQo27WGs+HxsJVsD4+pljF2MnBwSAiYSDye3sIHYQgI7GCVWd/BDxKUlrm+cwA5h C0us/PccyOYCqmliktg5YRczSIJNQFvi7vQtTCC2iICHRNu/e8wgRcwCL1kk5tyZzgqSEBbw l3g9dQYLiM0ioCrxZvF7sAZeARuJ7we6mCA2yEus3nAAqJmDg1PAVuLuqjyIg2wkzr1azzaB kW8BI8MqRsnUguLc9NxiwwKjvNRyveLE3OLSvHS95PzcTYzgSNHS2sG4Z9UHvUOMTByMhxgl OJiVRHj7i+4nCvGmJFZWpRblxxeV5qQWH2KU5mBREue90HUyXkggPbEkNTs1tSC1CCbLxMEp 1cAktNjbIOKhYZyquKDPM431goekjSX7nkUtf/OZYVmD9+THIgt+MXIuj+nfd3fJ28i0b2pW NppXFofW1G+MS02auv5AmpTU0iePzzOYfP+Tc5LnTblxf1HXv577cgErndUWcj3M+DSlbU7e 8vMG5xvu5im9mW519JYpO9ddaaMj/iFNcT4fdvkrzt/i++rk0brrORuar8xtkjVc79R44Xjg UUPTl6qqNbYaUg4//Kfl3+qrUn1Tm7PF8tjeI6HOwaKBL4vnLnz14/6swEv8SV37b92Z8U3k eXi0N6Mcx9pVz37N7YtTeOaz6Gfx783JIRcXmd79XV1leWFbxu2+0r4NfGELX6lMWVB+NGbW p2AVJZbijERDLeai4kQAlq5H8wMDAAA= X-CMS-MailID: 20220113122330epcas5p46ae5cd30950b1d9126479231dcf5da49 X-Msg-Generator: CA CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220113122330epcas5p46ae5cd30950b1d9126479231dcf5da49 References: <20220113121143.22280-1-alim.akhtar@samsung.com> This patch adds CMU_PERIC block clock information needed for various IPs functions found in this block. Cc: linux-fsd@tesla.com Signed-off-by: Aswani Reddy Signed-off-by: Niyas Ahmed S T Signed-off-by: Chandrasekar R Signed-off-by: Jayati Sahu Signed-off-by: Sriranjani P Signed-off-by: Ajay Kumar Signed-off-by: Pankaj Dubey Signed-off-by: Alim Akhtar --- drivers/clk/samsung/clk-fsd.c | 464 +++++++++++++++++++++++++++++++++- 1 file changed, 463 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-fsd.c b/drivers/clk/samsung/clk-fsd.c index e47523106d9e..6da20966ba99 100644 --- a/drivers/clk/samsung/clk-fsd.c +++ b/drivers/clk/samsung/clk-fsd.c @@ -9,12 +9,59 @@ * */ -#include #include +#include +#include +#include +#include +#include #include "clk.h" #include +/* Gate register bits */ +#define GATE_MANUAL BIT(20) +#define GATE_ENABLE_HWACG BIT(28) + +/* Gate register offsets range */ +#define GATE_OFF_START 0x2000 +#define GATE_OFF_END 0x2fff + +/** + * fsd_init_clocks - Set clocks initial configuration + * @np: CMU device tree node with "reg" property (CMU addr) + * @reg_offs: Register offsets array for clocks to init + * @reg_offs_len: Number of register offsets in reg_offs array + * + * Set manual control mode for all gate clocks. + */ +static void __init fsd_init_clocks(struct device_node *np, + const unsigned long *reg_offs, size_t reg_offs_len) +{ + void __iomem *reg_base; + size_t i; + + reg_base = of_iomap(np, 0); + if (!reg_base) + panic("%s: failed to map registers\n", __func__); + + for (i = 0; i < reg_offs_len; ++i) { + void __iomem *reg = reg_base + reg_offs[i]; + u32 val; + + /* Modify only gate clock registers */ + if (reg_offs[i] < GATE_OFF_START || reg_offs[i] > GATE_OFF_END) + continue; + + val = readl(reg); + val |= GATE_MANUAL; + val &= ~GATE_ENABLE_HWACG; + writel(val, reg); + } + + iounmap(reg_base); +} + /* Register Offset definitions for CMU_CMU (0x11c10000) */ #define PLL_LOCKTIME_PLL_SHARED0 0x0 #define PLL_LOCKTIME_PLL_SHARED1 0x4 @@ -306,3 +353,418 @@ static void __init fsd_clk_cmu_init(struct device_node *np) } CLK_OF_DECLARE(fsd_clk_cmu, "tesla,fsd-clock-cmu", fsd_clk_cmu_init); + +/* Register Offset definitions for CMU_PERIC (0x14010000) */ +#define PLL_CON0_PERIC_DMACLK_MUX 0x100 +#define PLL_CON0_PERIC_EQOS_BUSCLK_MUX 0x120 +#define PLL_CON0_PERIC_PCLK_MUX 0x140 +#define PLL_CON0_PERIC_TBUCLK_MUX 0x160 +#define PLL_CON0_SPI_CLK 0x180 +#define PLL_CON0_SPI_PCLK 0x1a0 +#define PLL_CON0_UART_CLK 0x1c0 +#define PLL_CON0_UART_PCLK 0x1e0 +#define MUX_PERIC_EQOS_PHYRXCLK 0x1000 +#define DIV_EQOS_BUSCLK 0x1800 +#define DIV_PERIC_MCAN_CLK 0x1804 +#define DIV_RGMII_CLK 0x1808 +#define DIV_RII_CLK 0x180c +#define DIV_RMII_CLK 0x1810 +#define DIV_SPI_CLK 0x1814 +#define DIV_UART_CLK 0x1818 +#define GAT_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I 0x2000 +#define GAT_GPIO_PERIC_IPCLKPORT_OSCCLK 0x2004 +#define GAT_PERIC_ADC0_IPCLKPORT_I_OSCCLK 0x2008 +#define GAT_PERIC_CMU_PERIC_IPCLKPORT_PCLK 0x200c +#define GAT_PERIC_PWM0_IPCLKPORT_I_OSCCLK 0x2010 +#define GAT_PERIC_PWM1_IPCLKPORT_I_OSCCLK 0x2014 +#define GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKM 0x2018 +#define GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKS 0x201c +#define GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKM 0x2020 +#define GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKS 0x2024 +#define GAT_AXI2APB_PERIC0_IPCLKPORT_ACLK 0x2028 +#define GAT_AXI2APB_PERIC1_IPCLKPORT_ACLK 0x202c +#define GAT_AXI2APB_PERIC2_IPCLKPORT_ACLK 0x2030 +#define GAT_BUS_D_PERIC_IPCLKPORT_DMACLK 0x2034 +#define GAT_BUS_D_PERIC_IPCLKPORT_EQOSCLK 0x2038 +#define GAT_BUS_D_PERIC_IPCLKPORT_MAINCLK 0x203c +#define GAT_BUS_P_PERIC_IPCLKPORT_EQOSCLK 0x2040 +#define GAT_BUS_P_PERIC_IPCLKPORT_MAINCLK 0x2044 +#define GAT_BUS_P_PERIC_IPCLKPORT_SMMUCLK 0x2048 +#define GAT_EQOS_TOP_IPCLKPORT_ACLK_I 0x204c +#define GAT_EQOS_TOP_IPCLKPORT_CLK_RX_I 0x2050 +#define GAT_EQOS_TOP_IPCLKPORT_HCLK_I 0x2054 +#define GAT_EQOS_TOP_IPCLKPORT_RGMII_CLK_I 0x2058 +#define GAT_EQOS_TOP_IPCLKPORT_RII_CLK_I 0x205c +#define GAT_EQOS_TOP_IPCLKPORT_RMII_CLK_I 0x2060 +#define GAT_GPIO_PERIC_IPCLKPORT_PCLK 0x2064 +#define GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_D 0x2068 +#define GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_P 0x206c +#define GAT_PERIC_ADC0_IPCLKPORT_PCLK_S0 0x2070 +#define GAT_PERIC_DMA0_IPCLKPORT_ACLK 0x2074 +#define GAT_PERIC_DMA1_IPCLKPORT_ACLK 0x2078 +#define GAT_PERIC_I2C0_IPCLKPORT_I_PCLK 0x207c +#define GAT_PERIC_I2C1_IPCLKPORT_I_PCLK 0x2080 +#define GAT_PERIC_I2C2_IPCLKPORT_I_PCLK 0x2084 +#define GAT_PERIC_I2C3_IPCLKPORT_I_PCLK 0x2088 +#define GAT_PERIC_I2C4_IPCLKPORT_I_PCLK 0x208c +#define GAT_PERIC_I2C5_IPCLKPORT_I_PCLK 0x2090 +#define GAT_PERIC_I2C6_IPCLKPORT_I_PCLK 0x2094 +#define GAT_PERIC_I2C7_IPCLKPORT_I_PCLK 0x2098 +#define GAT_PERIC_MCAN0_IPCLKPORT_CCLK 0x209c +#define GAT_PERIC_MCAN0_IPCLKPORT_PCLK 0x20a0 +#define GAT_PERIC_MCAN1_IPCLKPORT_CCLK 0x20a4 +#define GAT_PERIC_MCAN1_IPCLKPORT_PCLK 0x20a8 +#define GAT_PERIC_MCAN2_IPCLKPORT_CCLK 0x20ac +#define GAT_PERIC_MCAN2_IPCLKPORT_PCLK 0x20b0 +#define GAT_PERIC_MCAN3_IPCLKPORT_CCLK 0x20b4 +#define GAT_PERIC_MCAN3_IPCLKPORT_PCLK 0x20b8 +#define GAT_PERIC_PWM0_IPCLKPORT_I_PCLK_S0 0x20bc +#define GAT_PERIC_PWM1_IPCLKPORT_I_PCLK_S0 0x20c0 +#define GAT_PERIC_SMMU_IPCLKPORT_CCLK 0x20c4 +#define GAT_PERIC_SMMU_IPCLKPORT_PERIC_BCLK 0x20c8 +#define GAT_PERIC_SPI0_IPCLKPORT_I_PCLK 0x20cc +#define GAT_PERIC_SPI0_IPCLKPORT_I_SCLK_SPI 0x20d0 +#define GAT_PERIC_SPI1_IPCLKPORT_I_PCLK 0x20d4 +#define GAT_PERIC_SPI1_IPCLKPORT_I_SCLK_SPI 0x20d8 +#define GAT_PERIC_SPI2_IPCLKPORT_I_PCLK 0x20dc +#define GAT_PERIC_SPI2_IPCLKPORT_I_SCLK_SPI 0x20e0 +#define GAT_PERIC_TDM0_IPCLKPORT_HCLK_M 0x20e4 +#define GAT_PERIC_TDM0_IPCLKPORT_PCLK 0x20e8 +#define GAT_PERIC_TDM1_IPCLKPORT_HCLK_M 0x20ec +#define GAT_PERIC_TDM1_IPCLKPORT_PCLK 0x20f0 +#define GAT_PERIC_UART0_IPCLKPORT_I_SCLK_UART 0x20f4 +#define GAT_PERIC_UART0_IPCLKPORT_PCLK 0x20f8 +#define GAT_PERIC_UART1_IPCLKPORT_I_SCLK_UART 0x20fc +#define GAT_PERIC_UART1_IPCLKPORT_PCLK 0x2100 +#define GAT_SYSREG_PERI_IPCLKPORT_PCLK 0x2104 + +static const unsigned long peric_clk_regs[] __initconst = { + PLL_CON0_PERIC_DMACLK_MUX, + PLL_CON0_PERIC_EQOS_BUSCLK_MUX, + PLL_CON0_PERIC_PCLK_MUX, + PLL_CON0_PERIC_TBUCLK_MUX, + PLL_CON0_SPI_CLK, + PLL_CON0_SPI_PCLK, + PLL_CON0_UART_CLK, + PLL_CON0_UART_PCLK, + MUX_PERIC_EQOS_PHYRXCLK, + DIV_EQOS_BUSCLK, + DIV_PERIC_MCAN_CLK, + DIV_RGMII_CLK, + DIV_RII_CLK, + DIV_RMII_CLK, + DIV_SPI_CLK, + DIV_UART_CLK, + GAT_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I, + GAT_GPIO_PERIC_IPCLKPORT_OSCCLK, + GAT_PERIC_ADC0_IPCLKPORT_I_OSCCLK, + GAT_PERIC_CMU_PERIC_IPCLKPORT_PCLK, + GAT_PERIC_PWM0_IPCLKPORT_I_OSCCLK, + GAT_PERIC_PWM1_IPCLKPORT_I_OSCCLK, + GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKM, + GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKS, + GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKM, + GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKS, + GAT_AXI2APB_PERIC0_IPCLKPORT_ACLK, + GAT_AXI2APB_PERIC1_IPCLKPORT_ACLK, + GAT_AXI2APB_PERIC2_IPCLKPORT_ACLK, + GAT_BUS_D_PERIC_IPCLKPORT_DMACLK, + GAT_BUS_D_PERIC_IPCLKPORT_EQOSCLK, + GAT_BUS_D_PERIC_IPCLKPORT_MAINCLK, + GAT_BUS_P_PERIC_IPCLKPORT_EQOSCLK, + GAT_BUS_P_PERIC_IPCLKPORT_MAINCLK, + GAT_BUS_P_PERIC_IPCLKPORT_SMMUCLK, + GAT_EQOS_TOP_IPCLKPORT_ACLK_I, + GAT_EQOS_TOP_IPCLKPORT_CLK_RX_I, + GAT_EQOS_TOP_IPCLKPORT_HCLK_I, + GAT_EQOS_TOP_IPCLKPORT_RGMII_CLK_I, + GAT_EQOS_TOP_IPCLKPORT_RII_CLK_I, + GAT_EQOS_TOP_IPCLKPORT_RMII_CLK_I, + GAT_GPIO_PERIC_IPCLKPORT_PCLK, + GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_D, + GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_P, + GAT_PERIC_ADC0_IPCLKPORT_PCLK_S0, + GAT_PERIC_DMA0_IPCLKPORT_ACLK, + GAT_PERIC_DMA1_IPCLKPORT_ACLK, + GAT_PERIC_I2C0_IPCLKPORT_I_PCLK, + GAT_PERIC_I2C1_IPCLKPORT_I_PCLK, + GAT_PERIC_I2C2_IPCLKPORT_I_PCLK, + GAT_PERIC_I2C3_IPCLKPORT_I_PCLK, + GAT_PERIC_I2C4_IPCLKPORT_I_PCLK, + GAT_PERIC_I2C5_IPCLKPORT_I_PCLK, + GAT_PERIC_I2C6_IPCLKPORT_I_PCLK, + GAT_PERIC_I2C7_IPCLKPORT_I_PCLK, + GAT_PERIC_MCAN0_IPCLKPORT_CCLK, + GAT_PERIC_MCAN0_IPCLKPORT_PCLK, + GAT_PERIC_MCAN1_IPCLKPORT_CCLK, + GAT_PERIC_MCAN1_IPCLKPORT_PCLK, + GAT_PERIC_MCAN2_IPCLKPORT_CCLK, + GAT_PERIC_MCAN2_IPCLKPORT_PCLK, + GAT_PERIC_MCAN3_IPCLKPORT_CCLK, + GAT_PERIC_MCAN3_IPCLKPORT_PCLK, + GAT_PERIC_PWM0_IPCLKPORT_I_PCLK_S0, + GAT_PERIC_PWM1_IPCLKPORT_I_PCLK_S0, + GAT_PERIC_SMMU_IPCLKPORT_CCLK, + GAT_PERIC_SMMU_IPCLKPORT_PERIC_BCLK, + GAT_PERIC_SPI0_IPCLKPORT_I_PCLK, + GAT_PERIC_SPI0_IPCLKPORT_I_SCLK_SPI, + GAT_PERIC_SPI1_IPCLKPORT_I_PCLK, + GAT_PERIC_SPI1_IPCLKPORT_I_SCLK_SPI, + GAT_PERIC_SPI2_IPCLKPORT_I_PCLK, + GAT_PERIC_SPI2_IPCLKPORT_I_SCLK_SPI, + GAT_PERIC_TDM0_IPCLKPORT_HCLK_M, + GAT_PERIC_TDM0_IPCLKPORT_PCLK, + GAT_PERIC_TDM1_IPCLKPORT_HCLK_M, + GAT_PERIC_TDM1_IPCLKPORT_PCLK, + GAT_PERIC_UART0_IPCLKPORT_I_SCLK_UART, + GAT_PERIC_UART0_IPCLKPORT_PCLK, + GAT_PERIC_UART1_IPCLKPORT_I_SCLK_UART, + GAT_PERIC_UART1_IPCLKPORT_PCLK, + GAT_SYSREG_PERI_IPCLKPORT_PCLK, +}; + +static const struct samsung_fixed_rate_clock peric_fixed_clks[] __initconst = { + FRATE(PERIC_EQOS_PHYRXCLK, "eqos_phyrxclk", NULL, 0, 125000000), +}; + +/* List of parent clocks for Muxes in CMU_PERIC */ +PNAME(mout_peric_dmaclk_p) = { "fin_pll", "cmu_peric_shared1div4_dmaclk_gate" }; +PNAME(mout_peric_eqos_busclk_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" }; +PNAME(mout_peric_pclk_p) = { "fin_pll", "dout_cmu_peric_shared1div36" }; +PNAME(mout_peric_tbuclk_p) = { "fin_pll", "dout_cmu_peric_shared0div3_tbuclk" }; +PNAME(mout_peric_spi_clk_p) = { "fin_pll", "dout_cmu_peric_shared0div20" }; +PNAME(mout_peric_spi_pclk_p) = { "fin_pll", "dout_cmu_peric_shared1div36" }; +PNAME(mout_peric_uart_clk_p) = { "fin_pll", "dout_cmu_peric_shared1div4_dmaclk" }; +PNAME(mout_peric_uart_pclk_p) = { "fin_pll", "dout_cmu_peric_shared1div36" }; +PNAME(mout_peric_eqos_phyrxclk_p) = { "dout_peric_rgmii_clk", "eqos_phyrxclk" }; + +static const struct samsung_mux_clock peric_mux_clks[] __initconst = { + MUX(0, "mout_peric_dmaclk", mout_peric_dmaclk_p, PLL_CON0_PERIC_DMACLK_MUX, 4, 1), + MUX(0, "mout_peric_eqos_busclk", mout_peric_eqos_busclk_p, + PLL_CON0_PERIC_EQOS_BUSCLK_MUX, 4, 1), + MUX(0, "mout_peric_pclk", mout_peric_pclk_p, PLL_CON0_PERIC_PCLK_MUX, 4, 1), + MUX(0, "mout_peric_tbuclk", mout_peric_tbuclk_p, PLL_CON0_PERIC_TBUCLK_MUX, 4, 1), + MUX(0, "mout_peric_spi_clk", mout_peric_spi_clk_p, PLL_CON0_SPI_CLK, 4, 1), + MUX(0, "mout_peric_spi_pclk", mout_peric_spi_pclk_p, PLL_CON0_SPI_PCLK, 4, 1), + MUX(0, "mout_peric_uart_clk", mout_peric_uart_clk_p, PLL_CON0_UART_CLK, 4, 1), + MUX(0, "mout_peric_uart_pclk", mout_peric_uart_pclk_p, PLL_CON0_UART_PCLK, 4, 1), + MUX(PERIC_EQOS_PHYRXCLK_MUX, "mout_peric_eqos_phyrxclk", mout_peric_eqos_phyrxclk_p, + MUX_PERIC_EQOS_PHYRXCLK, 0, 1), +}; + +static const struct samsung_div_clock peric_div_clks[] __initconst = { + DIV(0, "dout_peric_eqos_busclk", "mout_peric_eqos_busclk", DIV_EQOS_BUSCLK, 0, 4), + DIV(0, "dout_peric_mcan_clk", "mout_peric_dmaclk", DIV_PERIC_MCAN_CLK, 0, 4), + DIV(PERIC_DOUT_RGMII_CLK, "dout_peric_rgmii_clk", "mout_peric_eqos_busclk", + DIV_RGMII_CLK, 0, 4), + DIV(0, "dout_peric_rii_clk", "dout_peric_rmii_clk", DIV_RII_CLK, 0, 4), + DIV(0, "dout_peric_rmii_clk", "dout_peric_rgmii_clk", DIV_RMII_CLK, 0, 4), + DIV(0, "dout_peric_spi_clk", "mout_peric_spi_clk", DIV_SPI_CLK, 0, 6), + DIV(0, "dout_peric_uart_clk", "mout_peric_uart_clk", DIV_UART_CLK, 0, 6), +}; + +static const struct samsung_gate_clock peric_gate_clks[] __initconst = { + GATE(PERIC_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I, "peric_eqos_top_ipclkport_clk_ptp_ref_i", + "fin_pll", GAT_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "peric_gpio_peric_ipclkport_oscclk", "fin_pll", GAT_GPIO_PERIC_IPCLKPORT_OSCCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_PCLK_ADCIF, "peric_adc0_ipclkport_i_oscclk", "fin_pll", + GAT_PERIC_ADC0_IPCLKPORT_I_OSCCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "peric_cmu_peric_ipclkport_pclk", "mout_peric_pclk", + GAT_PERIC_CMU_PERIC_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "peric_pwm0_ipclkport_i_oscclk", "fin_pll", GAT_PERIC_PWM0_IPCLKPORT_I_OSCCLK, 21, + CLK_IGNORE_UNUSED, 0), + GATE(0, "peric_pwm1_ipclkport_i_oscclk", "fin_pll", GAT_PERIC_PWM1_IPCLKPORT_I_OSCCLK, 21, + CLK_IGNORE_UNUSED, 0), + GATE(0, "peric_async_apb_dma0_ipclkport_pclkm", "mout_peric_dmaclk", + GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "peric_async_apb_dma0_ipclkport_pclks", "mout_peric_pclk", + GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "peric_async_apb_dma1_ipclkport_pclkm", "mout_peric_dmaclk", + GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "peric_async_apb_dma1_ipclkport_pclks", "mout_peric_pclk", + GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "peric_axi2apb_peric0_ipclkport_aclk", "mout_peric_pclk", + GAT_AXI2APB_PERIC0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "peric_axi2apb_peric1_ipclkport_aclk", "mout_peric_pclk", + GAT_AXI2APB_PERIC1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "peric_axi2apb_peric2_ipclkport_aclk", "mout_peric_pclk", + GAT_AXI2APB_PERIC2_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "peric_bus_d_peric_ipclkport_dmaclk", "mout_peric_dmaclk", + GAT_BUS_D_PERIC_IPCLKPORT_DMACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_BUS_D_PERIC_IPCLKPORT_EQOSCLK, "peric_bus_d_peric_ipclkport_eqosclk", + "dout_peric_eqos_busclk", GAT_BUS_D_PERIC_IPCLKPORT_EQOSCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "peric_bus_d_peric_ipclkport_mainclk", "mout_peric_tbuclk", + GAT_BUS_D_PERIC_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_BUS_P_PERIC_IPCLKPORT_EQOSCLK, "peric_bus_p_peric_ipclkport_eqosclk", + "dout_peric_eqos_busclk", GAT_BUS_P_PERIC_IPCLKPORT_EQOSCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "peric_bus_p_peric_ipclkport_mainclk", "mout_peric_pclk", + GAT_BUS_P_PERIC_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "peric_bus_p_peric_ipclkport_smmuclk", "mout_peric_tbuclk", + GAT_BUS_P_PERIC_IPCLKPORT_SMMUCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_EQOS_TOP_IPCLKPORT_ACLK_I, "peric_eqos_top_ipclkport_aclk_i", + "dout_peric_eqos_busclk", GAT_EQOS_TOP_IPCLKPORT_ACLK_I, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_EQOS_TOP_IPCLKPORT_CLK_RX_I, "peric_eqos_top_ipclkport_clk_rx_i", + "mout_peric_eqos_phyrxclk", GAT_EQOS_TOP_IPCLKPORT_CLK_RX_I, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_EQOS_TOP_IPCLKPORT_HCLK_I, "peric_eqos_top_ipclkport_hclk_i", + "dout_peric_eqos_busclk", GAT_EQOS_TOP_IPCLKPORT_HCLK_I, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_EQOS_TOP_IPCLKPORT_RGMII_CLK_I, "peric_eqos_top_ipclkport_rgmii_clk_i", + "dout_peric_rgmii_clk", GAT_EQOS_TOP_IPCLKPORT_RGMII_CLK_I, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "peric_eqos_top_ipclkport_rii_clk_i", "dout_peric_rii_clk", + GAT_EQOS_TOP_IPCLKPORT_RII_CLK_I, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "peric_eqos_top_ipclkport_rmii_clk_i", "dout_peric_rmii_clk", + GAT_EQOS_TOP_IPCLKPORT_RMII_CLK_I, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "peric_gpio_peric_ipclkport_pclk", "mout_peric_pclk", + GAT_GPIO_PERIC_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "peric_ns_brdg_peric_ipclkport_clk__psoc_peric__clk_peric_d", "mout_peric_tbuclk", + GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_D, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "peric_ns_brdg_peric_ipclkport_clk__psoc_peric__clk_peric_p", "mout_peric_pclk", + GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_P, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "peric_adc0_ipclkport_pclk_s0", "mout_peric_pclk", + GAT_PERIC_ADC0_IPCLKPORT_PCLK_S0, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_DMA0_IPCLKPORT_ACLK, "peric_dma0_ipclkport_aclk", "mout_peric_dmaclk", + GAT_PERIC_DMA0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_DMA1_IPCLKPORT_ACLK, "peric_dma1_ipclkport_aclk", "mout_peric_dmaclk", + GAT_PERIC_DMA1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_PCLK_HSI2C0, "peric_i2c0_ipclkport_i_pclk", "mout_peric_pclk", + GAT_PERIC_I2C0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_PCLK_HSI2C1, "peric_i2c1_ipclkport_i_pclk", "mout_peric_pclk", + GAT_PERIC_I2C1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_PCLK_HSI2C2, "peric_i2c2_ipclkport_i_pclk", "mout_peric_pclk", + GAT_PERIC_I2C2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_PCLK_HSI2C3, "peric_i2c3_ipclkport_i_pclk", "mout_peric_pclk", + GAT_PERIC_I2C3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_PCLK_HSI2C4, "peric_i2c4_ipclkport_i_pclk", "mout_peric_pclk", + GAT_PERIC_I2C4_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_PCLK_HSI2C5, "peric_i2c5_ipclkport_i_pclk", "mout_peric_pclk", + GAT_PERIC_I2C5_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_PCLK_HSI2C6, "peric_i2c6_ipclkport_i_pclk", "mout_peric_pclk", + GAT_PERIC_I2C6_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_PCLK_HSI2C7, "peric_i2c7_ipclkport_i_pclk", "mout_peric_pclk", + GAT_PERIC_I2C7_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_MCAN0_IPCLKPORT_CCLK, "peric_mcan0_ipclkport_cclk", "dout_peric_mcan_clk", + GAT_PERIC_MCAN0_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_MCAN0_IPCLKPORT_PCLK, "peric_mcan0_ipclkport_pclk", "mout_peric_pclk", + GAT_PERIC_MCAN0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_MCAN1_IPCLKPORT_CCLK, "peric_mcan1_ipclkport_cclk", "dout_peric_mcan_clk", + GAT_PERIC_MCAN1_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_MCAN1_IPCLKPORT_PCLK, "peric_mcan1_ipclkport_pclk", "mout_peric_pclk", + GAT_PERIC_MCAN1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_MCAN2_IPCLKPORT_CCLK, "peric_mcan2_ipclkport_cclk", "dout_peric_mcan_clk", + GAT_PERIC_MCAN2_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_MCAN2_IPCLKPORT_PCLK, "peric_mcan2_ipclkport_pclk", "mout_peric_pclk", + GAT_PERIC_MCAN2_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_MCAN3_IPCLKPORT_CCLK, "peric_mcan3_ipclkport_cclk", "dout_peric_mcan_clk", + GAT_PERIC_MCAN3_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_MCAN3_IPCLKPORT_PCLK, "peric_mcan3_ipclkport_pclk", "mout_peric_pclk", + GAT_PERIC_MCAN3_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_PWM0_IPCLKPORT_I_PCLK_S0, "peric_pwm0_ipclkport_i_pclk_s0", "mout_peric_pclk", + GAT_PERIC_PWM0_IPCLKPORT_I_PCLK_S0, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_PWM1_IPCLKPORT_I_PCLK_S0, "peric_pwm1_ipclkport_i_pclk_s0", "mout_peric_pclk", + GAT_PERIC_PWM1_IPCLKPORT_I_PCLK_S0, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "peric_smmu_ipclkport_cclk", "mout_peric_tbuclk", + GAT_PERIC_SMMU_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "peric_smmu_ipclkport_peric_bclk", "mout_peric_tbuclk", + GAT_PERIC_SMMU_IPCLKPORT_PERIC_BCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_PCLK_SPI0, "peric_spi0_ipclkport_i_pclk", "mout_peric_spi_pclk", + GAT_PERIC_SPI0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_SCLK_SPI0, "peric_spi0_ipclkport_i_sclk_spi", "dout_peric_spi_clk", + GAT_PERIC_SPI0_IPCLKPORT_I_SCLK_SPI, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_PCLK_SPI1, "peric_spi1_ipclkport_i_pclk", "mout_peric_spi_pclk", + GAT_PERIC_SPI1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_SCLK_SPI1, "peric_spi1_ipclkport_i_sclk_spi", "dout_peric_spi_clk", + GAT_PERIC_SPI1_IPCLKPORT_I_SCLK_SPI, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_PCLK_SPI2, "peric_spi2_ipclkport_i_pclk", "mout_peric_spi_pclk", + GAT_PERIC_SPI2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_SCLK_SPI2, "peric_spi2_ipclkport_i_sclk_spi", "dout_peric_spi_clk", + GAT_PERIC_SPI2_IPCLKPORT_I_SCLK_SPI, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_HCLK_TDM0, "peric_tdm0_ipclkport_hclk_m", "mout_peric_pclk", + GAT_PERIC_TDM0_IPCLKPORT_HCLK_M, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_PCLK_TDM0, "peric_tdm0_ipclkport_pclk", "mout_peric_pclk", + GAT_PERIC_TDM0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_HCLK_TDM1, "peric_tdm1_ipclkport_hclk_m", "mout_peric_pclk", + GAT_PERIC_TDM1_IPCLKPORT_HCLK_M, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_PCLK_TDM1, "peric_tdm1_ipclkport_pclk", "mout_peric_pclk", + GAT_PERIC_TDM1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_SCLK_UART0, "peric_uart0_ipclkport_i_sclk_uart", "dout_peric_uart_clk", + GAT_PERIC_UART0_IPCLKPORT_I_SCLK_UART, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_PCLK_UART0, "peric_uart0_ipclkport_pclk", "mout_peric_uart_pclk", + GAT_PERIC_UART0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_SCLK_UART1, "peric_uart1_ipclkport_i_sclk_uart", "dout_peric_uart_clk", + GAT_PERIC_UART1_IPCLKPORT_I_SCLK_UART, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_PCLK_UART1, "peric_uart1_ipclkport_pclk", "mout_peric_uart_pclk", + GAT_PERIC_UART1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "peric_sysreg_peri_ipclkport_pclk", "mout_peric_pclk", + GAT_SYSREG_PERI_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), +}; + +static const struct samsung_cmu_info peric_cmu_info __initconst = { + .mux_clks = peric_mux_clks, + .nr_mux_clks = ARRAY_SIZE(peric_mux_clks), + .div_clks = peric_div_clks, + .nr_div_clks = ARRAY_SIZE(peric_div_clks), + .gate_clks = peric_gate_clks, + .nr_gate_clks = ARRAY_SIZE(peric_gate_clks), + .fixed_clks = peric_fixed_clks, + .nr_fixed_clks = ARRAY_SIZE(peric_fixed_clks), + .nr_clk_ids = PERIC_NR_CLK, + .clk_regs = peric_clk_regs, + .nr_clk_regs = ARRAY_SIZE(peric_clk_regs), + .clk_name = "dout_cmu_pll_shared0_div4", +}; + +/** + * fsd_cmu_probe - Probe function for FSD platform clocks + * @pdev: Pointer to platform device + * + * Configure clock hierarchy for clock domains of FSD platform + */ +static int __init fsd_cmu_probe(struct platform_device *pdev) +{ + const struct samsung_cmu_info *info; + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + + info = of_device_get_match_data(dev); + fsd_init_clocks(np, info->clk_regs, info->nr_clk_regs); + samsung_cmu_register_one(np, info); + + /* Keep bus clock running, so it's possible to access CMU registers */ + if (info->clk_name) { + struct clk *bus_clk; + + bus_clk = clk_get(dev, info->clk_name); + if (IS_ERR(bus_clk)) { + pr_err("%s: could not find bus clock %s; err = %ld\n", + __func__, info->clk_name, PTR_ERR(bus_clk)); + } else { + clk_prepare_enable(bus_clk); + } + } + + return 0; +} + +/* CMUs which belong to Power Domains and need runtime PM to be implemented */ +static const struct of_device_id fsd_cmu_of_match[] = { + { + .compatible = "tesla,fsd-clock-peric", + .data = &peric_cmu_info, + }, { + }, +}; + +static struct platform_driver fsd_cmu_driver __refdata = { + .driver = { + .name = "fsd-cmu", + .of_match_table = fsd_cmu_of_match, + .suppress_bind_attrs = true, + }, + .probe = fsd_cmu_probe, +}; + +static int __init fsd_cmu_init(void) +{ + return platform_driver_register(&fsd_cmu_driver); +} +core_initcall(fsd_cmu_init); From patchwork Thu Jan 13 12:11:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alim Akhtar X-Patchwork-Id: 12712657 Return-Path: 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(Symantec Messaging Gateway) with SMTP id 4A.98.29871.6C910E16; Thu, 13 Jan 2022 21:23:34 +0900 (KST) Received: from Jaguar.sa.corp.samsungelectronics.net (unknown [107.108.73.139]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20220113122332epsmtip2b737c7ffb5e55295e50874b04af3c986~J0-qCJ9mT1245412454epsmtip2Y; Thu, 13 Jan 2022 12:23:31 +0000 (GMT) From: Alim Akhtar To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org List-Id: Cc: soc@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, olof@lixom.net, linus.walleij@linaro.org, catalin.marinas@arm.com, robh+dt@kernel.org, krzysztof.kozlowski@canonical.com, s.nawrocki@samsung.com, linux-samsung-soc@vger.kernel.org, pankaj.dubey@samsung.com, Alim Akhtar , linux-fsd@tesla.com, Shradha Todi , Jayati Sahu , Ajay Kumar Subject: [PATCH 05/23] clk: samsung: fsd: Add cmu_fsys0 clock information Date: Thu, 13 Jan 2022 17:41:25 +0530 Message-Id: <20220113121143.22280-6-alim.akhtar@samsung.com> X-Mailer: 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Cc: linux-fsd@tesla.com Signed-off-by: Pankaj Dubey Signed-off-by: Shradha Todi Signed-off-by: Jayati Sahu Signed-off-by: Ajay Kumar Signed-off-by: Alim Akhtar --- drivers/clk/samsung/clk-fsd.c | 302 ++++++++++++++++++++++++++++++++++ 1 file changed, 302 insertions(+) diff --git a/drivers/clk/samsung/clk-fsd.c b/drivers/clk/samsung/clk-fsd.c index 6da20966ba99..8a7a668eb4be 100644 --- a/drivers/clk/samsung/clk-fsd.c +++ b/drivers/clk/samsung/clk-fsd.c @@ -713,6 +713,305 @@ static const struct samsung_cmu_info peric_cmu_info __initconst = { .clk_name = "dout_cmu_pll_shared0_div4", }; +/* Register Offset definitions for CMU_FSYS0 (0x15010000) */ +#define PLL_CON0_CLKCMU_FSYS0_UNIPRO 0x100 +#define PLL_CON0_CLK_FSYS0_SLAVEBUSCLK 0x140 +#define PLL_CON0_EQOS_RGMII_125_MUX1 0x160 +#define DIV_CLK_UNIPRO 0x1800 +#define DIV_EQS_RGMII_CLK_125 0x1804 +#define DIV_PERIBUS_GRP 0x1808 +#define DIV_EQOS_RII_CLK2O5 0x180c +#define DIV_EQOS_RMIICLK_25 0x1810 +#define DIV_PCIE_PHY_OSCCLK 0x1814 +#define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I 0x2004 +#define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I 0x2008 +#define GAT_FSYS0_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK 0x200c +#define GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_OSCCLK 0x2010 +#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_XO 0x2014 +#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_IMMORTAL_CLK 0x2018 +#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_AUX_CLK_SOC 0x201c +#define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL24 0x2020 +#define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL26 0x2024 +#define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL24 0x2028 +#define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL26 0x202c +#define GAT_FSYS0_AHBBR_FSYS0_IPCLKPORT_HCLK 0x2038 +#define GAT_FSYS0_AXI2APB_FSYS0_IPCLKPORT_ACLK 0x203c +#define GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_MAINCLK 0x2040 +#define GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_PERICLK 0x2044 +#define GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_MAINCLK 0x2048 +#define GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_TCUCLK 0x204c +#define GAT_FSYS0_CPE425_IPCLKPORT_ACLK 0x2050 +#define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I 0x2054 +#define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I 0x2058 +#define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I 0x205c +#define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RII_CLK_I 0x2060 +#define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RMII_CLK_I 0x2064 +#define GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_PCLK 0x2068 +#define GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D 0x206c +#define GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D1 0x2070 +#define GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_P 0x2074 +#define GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_S 0x2078 +#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_I_APB_PCLK 0x207c +#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_SYSPLL 0x2080 +#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_APB_PCLK_0 0x2084 +#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_DBI_ACLK_SOC 0x2088 +#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK 0x208c +#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_MSTR_ACLK_SOC 0x2090 +#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_SLV_ACLK_SOC 0x2094 +#define GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_CCLK 0x2098 +#define GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_FSYS0_BCLK 0x209c +#define GAT_FSYS0_SYSREG_FSYS0_IPCLKPORT_PCLK 0x20a0 +#define GAT_FSYS0_UFS_TOP0_IPCLKPORT_HCLK_BUS 0x20a4 +#define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_ACLK 0x20a8 +#define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_CLK_UNIPRO 0x20ac +#define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_FMP_CLK 0x20b0 +#define GAT_FSYS0_UFS_TOP1_IPCLKPORT_HCLK_BUS 0x20b4 +#define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_ACLK 0x20b8 +#define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_CLK_UNIPRO 0x20bc +#define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_FMP_CLK 0x20c0 +#define GAT_FSYS0_RII_CLK_DIVGATE 0x20d4 + +static const unsigned long fsys0_clk_regs[] __initconst = { + PLL_CON0_CLKCMU_FSYS0_UNIPRO, + PLL_CON0_CLK_FSYS0_SLAVEBUSCLK, + PLL_CON0_EQOS_RGMII_125_MUX1, + DIV_CLK_UNIPRO, + DIV_EQS_RGMII_CLK_125, + DIV_PERIBUS_GRP, + DIV_EQOS_RII_CLK2O5, + DIV_EQOS_RMIICLK_25, + DIV_PCIE_PHY_OSCCLK, + GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I, + GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I, + GAT_FSYS0_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK, + GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_OSCCLK, + GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_XO, + GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_IMMORTAL_CLK, + GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_AUX_CLK_SOC, + GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL24, + GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL26, + GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL24, + GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL26, + GAT_FSYS0_AHBBR_FSYS0_IPCLKPORT_HCLK, + GAT_FSYS0_AXI2APB_FSYS0_IPCLKPORT_ACLK, + GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_MAINCLK, + GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_PERICLK, + GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_MAINCLK, + GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_TCUCLK, + GAT_FSYS0_CPE425_IPCLKPORT_ACLK, + GAT_FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I, + GAT_FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I, + GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I, + GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RII_CLK_I, + GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RMII_CLK_I, + GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_PCLK, + GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D, + GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D1, + GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_P, + GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_S, + GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_I_APB_PCLK, + GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_SYSPLL, + GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_APB_PCLK_0, + GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_DBI_ACLK_SOC, + GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, + GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_MSTR_ACLK_SOC, + GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_SLV_ACLK_SOC, + GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_CCLK, + GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_FSYS0_BCLK, + GAT_FSYS0_SYSREG_FSYS0_IPCLKPORT_PCLK, + GAT_FSYS0_UFS_TOP0_IPCLKPORT_HCLK_BUS, + GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_ACLK, + GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_CLK_UNIPRO, + GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_FMP_CLK, + GAT_FSYS0_UFS_TOP1_IPCLKPORT_HCLK_BUS, + GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_ACLK, + GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_CLK_UNIPRO, + GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_FMP_CLK, + GAT_FSYS0_RII_CLK_DIVGATE, +}; + +static const struct samsung_fixed_rate_clock fsys0_fixed_clks[] __initconst = { + FRATE(0, "pad_eqos0_phyrxclk", NULL, 0, 125000000), + FRATE(0, "i_mphy_refclk_ixtal26", NULL, 0, 26000000), + FRATE(0, "xtal_clk_pcie_phy", NULL, 0, 100000000), +}; + +/* List of parent clocks for Muxes in CMU_FSYS0 */ +PNAME(mout_fsys0_clkcmu_fsys0_unipro_p) = { "fin_pll", "dout_cmu_pll_shared0_div6" }; +PNAME(mout_fsys0_clk_fsys0_slavebusclk_p) = { "fin_pll", "dout_cmu_fsys0_shared1div4" }; +PNAME(mout_fsys0_eqos_rgmii_125_mux1_p) = { "fin_pll", "dout_cmu_fsys0_shared0div4" }; + +static const struct samsung_mux_clock fsys0_mux_clks[] __initconst = { + MUX(0, "mout_fsys0_clkcmu_fsys0_unipro", mout_fsys0_clkcmu_fsys0_unipro_p, + PLL_CON0_CLKCMU_FSYS0_UNIPRO, 4, 1), + MUX(0, "mout_fsys0_clk_fsys0_slavebusclk", mout_fsys0_clk_fsys0_slavebusclk_p, + PLL_CON0_CLK_FSYS0_SLAVEBUSCLK, 4, 1), + MUX(0, "mout_fsys0_eqos_rgmii_125_mux1", mout_fsys0_eqos_rgmii_125_mux1_p, + PLL_CON0_EQOS_RGMII_125_MUX1, 4, 1), +}; + +static const struct samsung_div_clock fsys0_div_clks[] __initconst = { + DIV(0, "dout_fsys0_clk_unipro", "mout_fsys0_clkcmu_fsys0_unipro", DIV_CLK_UNIPRO, 0, 4), + DIV(0, "dout_fsys0_eqs_rgmii_clk_125", "mout_fsys0_eqos_rgmii_125_mux1", + DIV_EQS_RGMII_CLK_125, 0, 4), + DIV(FSYS0_DOUT_FSYS0_PERIBUS_GRP, "dout_fsys0_peribus_grp", + "mout_fsys0_clk_fsys0_slavebusclk", DIV_PERIBUS_GRP, 0, 4), + DIV(0, "dout_fsys0_eqos_rii_clk2o5", "fsys0_rii_clk_divgate", DIV_EQOS_RII_CLK2O5, 0, 4), + DIV(0, "dout_fsys0_eqos_rmiiclk_25", "mout_fsys0_eqos_rgmii_125_mux1", + DIV_EQOS_RMIICLK_25, 0, 5), + DIV(0, "dout_fsys0_pcie_phy_oscclk", "mout_fsys0_eqos_rgmii_125_mux1", + DIV_PCIE_PHY_OSCCLK, 0, 4), +}; + +static const struct samsung_gate_clock fsys0_gate_clks[] __initconst = { + GATE(FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I, "fsys0_eqos_top0_ipclkport_clk_rx_i", + "pad_eqos0_phyrxclk", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I, 21, + CLK_IGNORE_UNUSED, 0), + GATE(PCIE_SUBCTRL_INST0_AUX_CLK_SOC, + "fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_aux_clk_soc", "fin_pll", + GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_AUX_CLK_SOC, 21, + CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys0_fsys0_cmu_fsys0_ipclkport_pclk", "dout_fsys0_peribus_grp", + GAT_FSYS0_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, + "fsys0_pcie_top_ipclkport_pcieg3_phy_x4_inst_0_pll_refclk_from_xo", + "xtal_clk_pcie_phy", + GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_XO, 21, + CLK_IGNORE_UNUSED, 0), + GATE(UFS0_MPHY_REFCLK_IXTAL24, "fsys0_ufs_top0_ipclkport_i_mphy_refclk_ixtal24", + "i_mphy_refclk_ixtal26", GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL24, 21, + CLK_IGNORE_UNUSED, 0), + GATE(UFS0_MPHY_REFCLK_IXTAL26, "fsys0_ufs_top0_ipclkport_i_mphy_refclk_ixtal26", + "i_mphy_refclk_ixtal26", GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL26, 21, + CLK_IGNORE_UNUSED, 0), + GATE(UFS1_MPHY_REFCLK_IXTAL24, "fsys0_ufs_top1_ipclkport_i_mphy_refclk_ixtal24", + "i_mphy_refclk_ixtal26", GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL24, 21, + CLK_IGNORE_UNUSED, 0), + GATE(UFS1_MPHY_REFCLK_IXTAL26, "fsys0_ufs_top1_ipclkport_i_mphy_refclk_ixtal26", + "i_mphy_refclk_ixtal26", GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL26, 21, + CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys0_ahbbr_fsys0_ipclkport_hclk", "dout_fsys0_peribus_grp", + GAT_FSYS0_AHBBR_FSYS0_IPCLKPORT_HCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys0_axi2apb_fsys0_ipclkport_aclk", "dout_fsys0_peribus_grp", + GAT_FSYS0_AXI2APB_FSYS0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys0_bus_d_fsys0_ipclkport_mainclk", "mout_fsys0_clk_fsys0_slavebusclk", + GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys0_bus_d_fsys0_ipclkport_periclk", "dout_fsys0_peribus_grp", + GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_PERICLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys0_bus_p_fsys0_ipclkport_mainclk", "dout_fsys0_peribus_grp", + GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys0_bus_p_fsys0_ipclkport_tcuclk", "mout_fsys0_eqos_rgmii_125_mux1", + GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_TCUCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys0_cpe425_ipclkport_aclk", "mout_fsys0_clk_fsys0_slavebusclk", + GAT_FSYS0_CPE425_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I, "fsys0_eqos_top0_ipclkport_aclk_i", + "dout_fsys0_peribus_grp", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I, 21, + CLK_IGNORE_UNUSED, 0), + GATE(FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I, "fsys0_eqos_top0_ipclkport_hclk_i", + "dout_fsys0_peribus_grp", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I, 21, + CLK_IGNORE_UNUSED, 0), + GATE(FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I, "fsys0_eqos_top0_ipclkport_rgmii_clk_i", + "dout_fsys0_eqs_rgmii_clk_125", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I, 21, + CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys0_eqos_top0_ipclkport_rii_clk_i", "dout_fsys0_eqos_rii_clk2o5", + GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RII_CLK_I, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys0_eqos_top0_ipclkport_rmii_clk_i", "dout_fsys0_eqos_rmiiclk_25", + GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RMII_CLK_I, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys0_gpio_fsys0_ipclkport_pclk", "dout_fsys0_peribus_grp", + GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys0_gpio_fsys0_ipclkport_oscclk", "fin_pll", + GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_OSCCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys0_ns_brdg_fsys0_ipclkport_clk__psoc_fsys0__clk_fsys0_d", + "mout_fsys0_clk_fsys0_slavebusclk", + GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D, 21, + CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys0_ns_brdg_fsys0_ipclkport_clk__psoc_fsys0__clk_fsys0_d1", + "mout_fsys0_eqos_rgmii_125_mux1", + GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D1, 21, + CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys0_ns_brdg_fsys0_ipclkport_clk__psoc_fsys0__clk_fsys0_p", + "dout_fsys0_peribus_grp", + GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_P, 21, + CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys0_ns_brdg_fsys0_ipclkport_clk__psoc_fsys0__clk_fsys0_s", + "mout_fsys0_clk_fsys0_slavebusclk", + GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_S, 21, + CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys0_pcie_top_ipclkport_pcieg3_phy_x4_inst_0_i_apb_pclk", + "dout_fsys0_peribus_grp", + GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_I_APB_PCLK, 21, + CLK_IGNORE_UNUSED, 0), + GATE(0, + "fsys0_pcie_top_ipclkport_pcieg3_phy_x4_inst_0_pll_refclk_from_syspll", + "dout_fsys0_pcie_phy_oscclk", + GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_SYSPLL, + 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys0_pcie_top_ipclkport_pipe_pal_inst_0_i_apb_pclk_0", "dout_fsys0_peribus_grp", + GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_APB_PCLK_0, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys0_pcie_top_ipclkport_pipe_pal_inst_0_i_immortal_clk", "fin_pll", + GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_IMMORTAL_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PCIE_SUBCTRL_INST0_DBI_ACLK_SOC, + "fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_dbi_aclk_soc", + "dout_fsys0_peribus_grp", + GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_DBI_ACLK_SOC, 21, + CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_i_driver_apb_clk", + "dout_fsys0_peribus_grp", + GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, 21, + CLK_IGNORE_UNUSED, 0), + GATE(PCIE_SUBCTRL_INST0_MSTR_ACLK_SOC, + "fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_mstr_aclk_soc", + "mout_fsys0_clk_fsys0_slavebusclk", + GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_MSTR_ACLK_SOC, 21, + CLK_IGNORE_UNUSED, 0), + GATE(PCIE_SUBCTRL_INST0_SLV_ACLK_SOC, + "fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_slv_aclk_soc", + "mout_fsys0_clk_fsys0_slavebusclk", + GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_SLV_ACLK_SOC, 21, + CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys0_smmu_fsys0_ipclkport_cclk", "mout_fsys0_eqos_rgmii_125_mux1", + GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys0_smmu_fsys0_ipclkport_fsys0_bclk", "mout_fsys0_clk_fsys0_slavebusclk", + GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_FSYS0_BCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys0_sysreg_fsys0_ipclkport_pclk", "dout_fsys0_peribus_grp", + GAT_FSYS0_SYSREG_FSYS0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(UFS0_TOP0_HCLK_BUS, "fsys0_ufs_top0_ipclkport_hclk_bus", "dout_fsys0_peribus_grp", + GAT_FSYS0_UFS_TOP0_IPCLKPORT_HCLK_BUS, 21, CLK_IGNORE_UNUSED, 0), + GATE(UFS0_TOP0_ACLK, "fsys0_ufs_top0_ipclkport_i_aclk", "dout_fsys0_peribus_grp", + GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(UFS0_TOP0_CLK_UNIPRO, "fsys0_ufs_top0_ipclkport_i_clk_unipro", "dout_fsys0_clk_unipro", + GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_CLK_UNIPRO, 21, CLK_IGNORE_UNUSED, 0), + GATE(UFS0_TOP0_FMP_CLK, "fsys0_ufs_top0_ipclkport_i_fmp_clk", "dout_fsys0_peribus_grp", + GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_FMP_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(UFS1_TOP1_HCLK_BUS, "fsys0_ufs_top1_ipclkport_hclk_bus", "dout_fsys0_peribus_grp", + GAT_FSYS0_UFS_TOP1_IPCLKPORT_HCLK_BUS, 21, CLK_IGNORE_UNUSED, 0), + GATE(UFS1_TOP1_ACLK, "fsys0_ufs_top1_ipclkport_i_aclk", "dout_fsys0_peribus_grp", + GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(UFS1_TOP1_CLK_UNIPRO, "fsys0_ufs_top1_ipclkport_i_clk_unipro", "dout_fsys0_clk_unipro", + GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_CLK_UNIPRO, 21, CLK_IGNORE_UNUSED, 0), + GATE(UFS1_TOP1_FMP_CLK, "fsys0_ufs_top1_ipclkport_i_fmp_clk", "dout_fsys0_peribus_grp", + GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_FMP_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys0_rii_clk_divgate", "dout_fsys0_eqos_rmiiclk_25", GAT_FSYS0_RII_CLK_DIVGATE, + 21, CLK_IGNORE_UNUSED, 0), + GATE(FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I, "fsys0_eqos_top0_ipclkport_clk_ptp_ref_i", + "fin_pll", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I, 21, CLK_IGNORE_UNUSED, 0), +}; + +static const struct samsung_cmu_info fsys0_cmu_info __initconst = { + .mux_clks = fsys0_mux_clks, + .nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks), + .div_clks = fsys0_div_clks, + .nr_div_clks = ARRAY_SIZE(fsys0_div_clks), + .gate_clks = fsys0_gate_clks, + .nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks), + .fixed_clks = fsys0_fixed_clks, + .nr_fixed_clks = ARRAY_SIZE(fsys0_fixed_clks), + .nr_clk_ids = FSYS0_NR_CLK, + .clk_regs = fsys0_clk_regs, + .nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs), + .clk_name = "dout_cmu_fsys0_shared1div4", +}; + /** * fsd_cmu_probe - Probe function for FSD platform clocks * @pdev: Pointer to platform device @@ -750,6 +1049,9 @@ static const struct of_device_id fsd_cmu_of_match[] = { { .compatible = "tesla,fsd-clock-peric", .data = &peric_cmu_info, + }, { + .compatible = "tesla,fsd-clock-fsys0", + .data = &fsys0_cmu_info, }, { }, }; From patchwork Thu Jan 13 12:11:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alim Akhtar X-Patchwork-Id: 12712658 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on 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5A.99.08738.AC910E16; Thu, 13 Jan 2022 21:23:38 +0900 (KST) Received: from Jaguar.sa.corp.samsungelectronics.net (unknown [107.108.73.139]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20220113122336epsmtip2dd77e2e3a5569e0bcc6db8c7670a975b~J0-t-pnJd1247412474epsmtip2k; Thu, 13 Jan 2022 12:23:36 +0000 (GMT) From: Alim Akhtar To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org List-Id: Cc: soc@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, olof@lixom.net, linus.walleij@linaro.org, catalin.marinas@arm.com, robh+dt@kernel.org, krzysztof.kozlowski@canonical.com, s.nawrocki@samsung.com, linux-samsung-soc@vger.kernel.org, pankaj.dubey@samsung.com, Alim Akhtar , linux-fsd@tesla.com, Ajay Kumar Subject: [PATCH 06/23] clk: samsung: fsd: Add cmu_fsys1 clock information Date: Thu, 13 Jan 2022 17:41:26 +0530 Message-Id: <20220113121143.22280-7-alim.akhtar@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: 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Cc: linux-fsd@tesla.com Signed-off-by: Pankaj Dubey Signed-off-by: Ajay Kumar Signed-off-by: Alim Akhtar --- drivers/clk/samsung/clk-fsd.c | 175 ++++++++++++++++++++++++++++++++++ 1 file changed, 175 insertions(+) diff --git a/drivers/clk/samsung/clk-fsd.c b/drivers/clk/samsung/clk-fsd.c index 8a7a668eb4be..d06afab39d37 100644 --- a/drivers/clk/samsung/clk-fsd.c +++ b/drivers/clk/samsung/clk-fsd.c @@ -1012,6 +1012,178 @@ static const struct samsung_cmu_info fsys0_cmu_info __initconst = { .clk_name = "dout_cmu_fsys0_shared1div4", }; +/* Register Offset definitions for CMU_FSYS1 (0x16810000) */ +#define PLL_CON0_ACLK_FSYS1_BUSP_MUX 0x100 +#define PLL_CON0_PCLKL_FSYS1_BUSP_MUX 0x180 +#define DIV_CLK_FSYS1_PHY0_OSCCLK 0x1800 +#define DIV_CLK_FSYS1_PHY1_OSCCLK 0x1804 +#define GAT_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK 0x2000 +#define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_AUXCLK 0x2004 +#define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_SOC_REF_CLK 0x2008 +#define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_AUXCLK 0x200c +#define GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_XTAL 0x202c +#define GAT_FSYS1_PHY0_OSCCLLK 0x2034 +#define GAT_FSYS1_PHY1_OSCCLK 0x2038 +#define GAT_FSYS1_AXI2APB_FSYS1_IPCLKPORT_ACLK 0x203c +#define GAT_FSYS1_BUS_D0_FSYS1_IPCLKPORT_MAINCLK 0x2040 +#define GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_M250CLK 0x2048 +#define GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_MAINCLK 0x204c +#define GAT_FSYS1_CPE425_0_FSYS1_IPCLKPORT_ACLK 0x2054 +#define GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_D0 0x205c +#define GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_S0 0x2064 +#define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_DBI_ACLK 0x206c +#define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_APB_CLK 0x2070 +#define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_DRIVER_APB_CLK 0x2074 +#define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_MSTR_ACLK 0x2078 +#define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_SLV_ACLK 0x207c +#define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_DBI_ACLK 0x2080 +#define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_I_DRIVER_APB_CLK 0x2084 +#define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_MSTR_ACLK 0x2088 +#define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_SLV_ACLK 0x208c +#define GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_APB_CLK 0x20a4 +#define GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_SOC_PLL 0x20a8 +#define GAT_FSYS1_SYSREG_FSYS1_IPCLKPORT_PCLK 0x20b4 +#define GAT_FSYS1_TBU0_FSYS1_IPCLKPORT_ACLK 0x20b8 + +static const unsigned long fsys1_clk_regs[] __initconst = { + PLL_CON0_ACLK_FSYS1_BUSP_MUX, + PLL_CON0_PCLKL_FSYS1_BUSP_MUX, + DIV_CLK_FSYS1_PHY0_OSCCLK, + DIV_CLK_FSYS1_PHY1_OSCCLK, + GAT_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK, + GAT_FSYS1_PCIE_LINK0_IPCLKPORT_AUXCLK, + GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_SOC_REF_CLK, + GAT_FSYS1_PCIE_LINK1_IPCLKPORT_AUXCLK, + GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_XTAL, + GAT_FSYS1_PHY0_OSCCLLK, + GAT_FSYS1_PHY1_OSCCLK, + GAT_FSYS1_AXI2APB_FSYS1_IPCLKPORT_ACLK, + GAT_FSYS1_BUS_D0_FSYS1_IPCLKPORT_MAINCLK, + GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_M250CLK, + GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_MAINCLK, + GAT_FSYS1_CPE425_0_FSYS1_IPCLKPORT_ACLK, + GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_D0, + GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_S0, + GAT_FSYS1_PCIE_LINK0_IPCLKPORT_DBI_ACLK, + GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_APB_CLK, + GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_DRIVER_APB_CLK, + GAT_FSYS1_PCIE_LINK0_IPCLKPORT_MSTR_ACLK, + GAT_FSYS1_PCIE_LINK0_IPCLKPORT_SLV_ACLK, + GAT_FSYS1_PCIE_LINK1_IPCLKPORT_DBI_ACLK, + GAT_FSYS1_PCIE_LINK1_IPCLKPORT_I_DRIVER_APB_CLK, + GAT_FSYS1_PCIE_LINK1_IPCLKPORT_MSTR_ACLK, + GAT_FSYS1_PCIE_LINK1_IPCLKPORT_SLV_ACLK, + GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_APB_CLK, + GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_SOC_PLL, + GAT_FSYS1_SYSREG_FSYS1_IPCLKPORT_PCLK, + GAT_FSYS1_TBU0_FSYS1_IPCLKPORT_ACLK, +}; + +static const struct samsung_fixed_rate_clock fsys1_fixed_clks[] __initconst = { + FRATE(0, "clk_fsys1_phy0_ref", NULL, 0, 100000000), + FRATE(0, "clk_fsys1_phy1_ref", NULL, 0, 100000000), +}; + +/* List of parent clocks for Muxes in CMU_FSYS1 */ +PNAME(mout_fsys1_pclkl_fsys1_busp_mux_p) = { "fin_pll", "dout_cmu_fsys1_shared0div8" }; +PNAME(mout_fsys1_aclk_fsys1_busp_mux_p) = { "fin_pll", "dout_cmu_fsys1_shared0div4" }; + +static const struct samsung_mux_clock fsys1_mux_clks[] __initconst = { + MUX(0, "mout_fsys1_pclkl_fsys1_busp_mux", mout_fsys1_pclkl_fsys1_busp_mux_p, + PLL_CON0_PCLKL_FSYS1_BUSP_MUX, 4, 1), + MUX(0, "mout_fsys1_aclk_fsys1_busp_mux", mout_fsys1_aclk_fsys1_busp_mux_p, + PLL_CON0_ACLK_FSYS1_BUSP_MUX, 4, 1), +}; + +static const struct samsung_div_clock fsys1_div_clks[] __initconst = { + DIV(0, "dout_fsys1_clk_fsys1_phy0_oscclk", "fsys1_phy0_osccllk", + DIV_CLK_FSYS1_PHY0_OSCCLK, 0, 4), + DIV(0, "dout_fsys1_clk_fsys1_phy1_oscclk", "fsys1_phy1_oscclk", + DIV_CLK_FSYS1_PHY1_OSCCLK, 0, 4), +}; + +static const struct samsung_gate_clock fsys1_gate_clks[] __initconst = { + GATE(0, "fsys1_cmu_fsys1_ipclkport_pclk", "mout_fsys1_pclkl_fsys1_busp_mux", + GAT_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys1_pcie_phy0_ipclkport_i_ref_xtal", "clk_fsys1_phy0_ref", + GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_XTAL, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys1_phy0_osccllk", "mout_fsys1_aclk_fsys1_busp_mux", + GAT_FSYS1_PHY0_OSCCLLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys1_phy1_oscclk", "mout_fsys1_aclk_fsys1_busp_mux", + GAT_FSYS1_PHY1_OSCCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys1_axi2apb_fsys1_ipclkport_aclk", "mout_fsys1_pclkl_fsys1_busp_mux", + GAT_FSYS1_AXI2APB_FSYS1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys1_bus_d0_fsys1_ipclkport_mainclk", "mout_fsys1_aclk_fsys1_busp_mux", + GAT_FSYS1_BUS_D0_FSYS1_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys1_bus_s0_fsys1_ipclkport_m250clk", "mout_fsys1_pclkl_fsys1_busp_mux", + GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_M250CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys1_bus_s0_fsys1_ipclkport_mainclk", "mout_fsys1_aclk_fsys1_busp_mux", + GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys1_cpe425_0_fsys1_ipclkport_aclk", "mout_fsys1_aclk_fsys1_busp_mux", + GAT_FSYS1_CPE425_0_FSYS1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys1_ns_brdg_fsys1_ipclkport_clk__psoc_fsys1__clk_fsys1_d0", + "mout_fsys1_aclk_fsys1_busp_mux", + GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_D0, 21, + CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys1_ns_brdg_fsys1_ipclkport_clk__psoc_fsys1__clk_fsys1_s0", + "mout_fsys1_aclk_fsys1_busp_mux", + GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_S0, 21, + CLK_IGNORE_UNUSED, 0), + GATE(PCIE_LINK0_IPCLKPORT_DBI_ACLK, "fsys1_pcie_link0_ipclkport_dbi_aclk", + "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK0_IPCLKPORT_DBI_ACLK, 21, + CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys1_pcie_link0_ipclkport_i_apb_clk", "mout_fsys1_pclkl_fsys1_busp_mux", + GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_APB_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys1_pcie_link0_ipclkport_i_soc_ref_clk", "fin_pll", + GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_SOC_REF_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys1_pcie_link0_ipclkport_i_driver_apb_clk", "mout_fsys1_pclkl_fsys1_busp_mux", + GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_DRIVER_APB_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PCIE_LINK0_IPCLKPORT_MSTR_ACLK, "fsys1_pcie_link0_ipclkport_mstr_aclk", + "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK0_IPCLKPORT_MSTR_ACLK, 21, + CLK_IGNORE_UNUSED, 0), + GATE(PCIE_LINK0_IPCLKPORT_SLV_ACLK, "fsys1_pcie_link0_ipclkport_slv_aclk", + "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK0_IPCLKPORT_SLV_ACLK, 21, + CLK_IGNORE_UNUSED, 0), + GATE(PCIE_LINK1_IPCLKPORT_DBI_ACLK, "fsys1_pcie_link1_ipclkport_dbi_aclk", + "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK1_IPCLKPORT_DBI_ACLK, 21, + CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys1_pcie_link1_ipclkport_i_driver_apb_clk", "mout_fsys1_pclkl_fsys1_busp_mux", + GAT_FSYS1_PCIE_LINK1_IPCLKPORT_I_DRIVER_APB_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PCIE_LINK1_IPCLKPORT_MSTR_ACLK, "fsys1_pcie_link1_ipclkport_mstr_aclk", + "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK1_IPCLKPORT_MSTR_ACLK, 21, + CLK_IGNORE_UNUSED, 0), + GATE(PCIE_LINK1_IPCLKPORT_SLV_ACLK, "fsys1_pcie_link1_ipclkport_slv_aclk", + "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK1_IPCLKPORT_SLV_ACLK, 21, + CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys1_pcie_phy0_ipclkport_i_apb_clk", "mout_fsys1_pclkl_fsys1_busp_mux", + GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_APB_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PCIE_LINK0_IPCLKPORT_AUX_ACLK, "fsys1_pcie_link0_ipclkport_auxclk", "fin_pll", + GAT_FSYS1_PCIE_LINK0_IPCLKPORT_AUXCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PCIE_LINK1_IPCLKPORT_AUX_ACLK, "fsys1_pcie_link1_ipclkport_auxclk", "fin_pll", + GAT_FSYS1_PCIE_LINK1_IPCLKPORT_AUXCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys1_pcie_phy0_ipclkport_i_ref_soc_pll", "dout_fsys1_clk_fsys1_phy0_oscclk", + GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_SOC_PLL, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys1_sysreg_fsys1_ipclkport_pclk", "mout_fsys1_pclkl_fsys1_busp_mux", + GAT_FSYS1_SYSREG_FSYS1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys1_tbu0_fsys1_ipclkport_aclk", "mout_fsys1_aclk_fsys1_busp_mux", + GAT_FSYS1_TBU0_FSYS1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), +}; + +static const struct samsung_cmu_info fsys1_cmu_info __initconst = { + .mux_clks = fsys1_mux_clks, + .nr_mux_clks = ARRAY_SIZE(fsys1_mux_clks), + .div_clks = fsys1_div_clks, + .nr_div_clks = ARRAY_SIZE(fsys1_div_clks), + .gate_clks = fsys1_gate_clks, + .nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks), + .fixed_clks = fsys1_fixed_clks, + .nr_fixed_clks = ARRAY_SIZE(fsys1_fixed_clks), + .nr_clk_ids = FSYS1_NR_CLK, + .clk_regs = fsys1_clk_regs, + .nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs), + .clk_name = "dout_cmu_fsys1_shared0div4", +}; + /** * fsd_cmu_probe - Probe function for FSD platform clocks * @pdev: Pointer to platform device @@ -1052,6 +1224,9 @@ static const struct of_device_id fsd_cmu_of_match[] = { }, { .compatible = "tesla,fsd-clock-fsys0", .data = &fsys0_cmu_info, + }, { + .compatible = "tesla,fsd-clock-fsys1", + .data = &fsys1_cmu_info, }, { }, }; From patchwork Thu Jan 13 12:11:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alim Akhtar X-Patchwork-Id: 12712660 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4477EC4332F for ; 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Thu, 13 Jan 2022 12:23:43 +0000 (GMT) Received: from epsmgms1p2.samsung.com (unknown [182.195.42.42]) by epsmtrp1.samsung.com (KnoxPortal) with ESMTP id 20220113122343epsmtrp18b3899c67c4ffe69eb6d2214a08f1cb0~J0-0W_H6U1911119111epsmtrp1_; Thu, 13 Jan 2022 12:23:43 +0000 (GMT) X-AuditID: b6c32a4a-dfbff7000000b6e6-50-61e019cfa495 Received: from epsmtip2.samsung.com ( [182.195.34.31]) by epsmgms1p2.samsung.com (Symantec Messaging Gateway) with SMTP id EC.99.08738.EC910E16; Thu, 13 Jan 2022 21:23:42 +0900 (KST) Received: from Jaguar.sa.corp.samsungelectronics.net (unknown [107.108.73.139]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20220113122340epsmtip24a687f32c1a61b3ca7cc0e7f91f54623~J0-xywX3y1245812458epsmtip2n; Thu, 13 Jan 2022 12:23:40 +0000 (GMT) From: Alim Akhtar To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org List-Id: Cc: soc@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, olof@lixom.net, linus.walleij@linaro.org, catalin.marinas@arm.com, robh+dt@kernel.org, krzysztof.kozlowski@canonical.com, s.nawrocki@samsung.com, linux-samsung-soc@vger.kernel.org, pankaj.dubey@samsung.com, Alim Akhtar , linux-fsd@tesla.com, Arjun K V , Tauseef Nomani Subject: [PATCH 07/23] clk: samsung: fsd: Add cmu_imem block clock information Date: Thu, 13 Jan 2022 17:41:27 +0530 Message-Id: <20220113121143.22280-8-alim.akhtar@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220113121143.22280-1-alim.akhtar@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprOJsWRmVeSWpSXmKPExsWy7bCmlu4FyQeJBk2bmCwezNvGZrF85S4W i/fLehgt5h85x2qx8e0PJospf5YzWWx6fI3V4mPPPVaLh6/CLS7vmsNmMeP8PiaLU9c/s1ks 2vqF3aJ17xF2i8Nv2lktHl//w2Zx6eRkFgdBjzXz1jB6zGroZfPYtKqTzePOtT1sHpuX1Htc OdHE6tG3ZRWjx7+muewenzfJBXBGZdtkpCampBYppOYl56dk5qXbKnkHxzvHm5oZGOoaWlqY KynkJeam2iq5+AToumXmAL2ipFCWmFMKFApILC5W0rezKcovLUlVyMgvLrFVSi1IySkwKdAr TswtLs1L18tLLbEyNDAwMgUqTMjOODnlLkvB8mbGih9TZ7A1MM4r7WLk5JAQMJG4fbCfvYuR i0NIYDejxOLF61hBEkICnxgllt1jhkh8ZpRY0jKFBabj6KMfbBCJXYwSEz/egHJamCTa/v1j B6liE9CWuDt9CxOILSLgJnGjsYMJpIhZYBWzxJu+o2AJYYEAiW3bj7GB2CwCqhK9s/aCNfMK 2Ei8/PESap28xOoNB4Du4ODgFLCVuLsqD2SOhMBaDolP53YxQtS4SEw5tQbKFpZ4dXwLO4Qt JfGyv40dpFdCIFuiZ5cxRLhGYum8Y1Dj7SUOXJnDAlLCLKApsX6XPkiYWYBPovf3EyaITl6J jjYhiGpVieZ3V6E6pSUmdnezQtgeEi//rIOG4gRGiTc7+lknMMrOQpi6gJFxFaNkakFxbnpq sWmBUV5qOTyikvNzNzGCU6iW1w7Ghw8+6B1iZOJgPMQowcGsJMLbX3Q/UYg3JbGyKrUoP76o NCe1+BCjKTDEJjJLiSbnA5N4Xkm8oYmlgYmZmZmJpbGZoZI47+n0DYlCAumJJanZqakFqUUw fUwcnFINTH4f/aZu+P5BwmGPZ45K7r3aSRd+vBUq8J5keWPf6mKXTw/uf3wh+PzDLD8dXi+l T+VsJTlt4dwzlRn3eN6vrf1wJPDrkzlLPvrV8ioWPyvlWhn/ZPP1vQpaG7QV911TNV3NMknc KjfJatHkHj01BcH6ffFXFAVsvrTwK8ku05iyTPWf8T2TjSK9jWnsvIe477I17Na0naD6eeYy HoVFDt9eT07PT949Y/F+rvtBj7uVRXISnjy8ZK0g5e1ge06w/Ddbz52i8MzWHHfLkr2C+4J+ f11y8c+uufrZc6/933DPuOXi93W3b57V+rHX5fGMV+dObg+c/kF/bvSHPZZZogL7D+znuBpV ufPdkYe9YU+VWIozEg21mIuKEwExtQxPKgQAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrNLMWRmVeSWpSXmKPExsWy7bCSvO45yQeJBsu7VSwezNvGZrF85S4W i/fLehgt5h85x2qx8e0PJospf5YzWWx6fI3V4mPPPVaLh6/CLS7vmsNmMeP8PiaLU9c/s1ks 2vqF3aJ17xF2i8Nv2lktHl//w2Zx6eRkFgdBjzXz1jB6zGroZfPYtKqTzePOtT1sHpuX1Htc OdHE6tG3ZRWjx7+muewenzfJBXBGcdmkpOZklqUW6dslcGWcnHKXpWB5M2PFj6kz2BoY55V2 MXJySAiYSBx99IOti5GLQ0hgB6NE765PbBAJaYnrGyewQ9jCEiv/PQezhQSamCSubhUGsdkE tCXuTt/CBGKLCHhItP27xwwyiFlgF7PEiv+rWUASwgJ+Ep83/wJrZhFQleidtRfM5hWwkXj5 4yULxAJ5idUbDgA1c3BwCthK3F2VB7HLRuLcq/VsExj5FjAyrGKUTC0ozk3PLTYsMMpLLdcr TswtLs1L10vOz93ECA5/La0djHtWfdA7xMjEwXiIUYKDWUmEt7/ofqIQb0piZVVqUX58UWlO avEhRmkOFiVx3gtdJ+OFBNITS1KzU1MLUotgskwcnFINTBaeoa4n5xvzutz3eLn2grq+00v1 I+5rhNvt/wrbPX9rbC7g7Psi6/J5ib/e011+GE+WSTijPefeJv3PhXpLQr3cPzw1PTdJf63V hjea6bdfRlfZ9t2+kX1Q44CR9xOeDOvCjIxe98/7Jt210/32Z31zltzBu3JMW58FsryoNoji qzTZ3HAp/l6R3gee4tTu39fm969xLqi8Vm4X0mBup8jSmh+yIk/xWrSF9CouQ77SnlOHDOVV ciVOKtnWP3FSZfDlmb37fZvZ1qRl7+ctrX180yJc7eKkg2sau/VTvs86O3X5VjXnHDGmx90c J5+sPz1r4zzuUyv/N6/7NfVVe2DwnhV3VQIWvG7IvFBlp8RSnJFoqMVcVJwIAG8A4PLuAgAA X-CMS-MailID: 20220113122343epcas5p23831143e4e8fb92be8ad362f4817c03b X-Msg-Generator: CA CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220113122343epcas5p23831143e4e8fb92be8ad362f4817c03b References: <20220113121143.22280-1-alim.akhtar@samsung.com> Adds cmu_imem clock related code, imem block contains IPs like WDT, DMA, TMU etc, these clocks are required for such IP function. Cc: linux-fsd@tesla.com Signed-off-by: Arjun K V Signed-off-by: Pankaj Dubey Signed-off-by: Tauseef Nomani Signed-off-by: Alim Akhtar --- drivers/clk/samsung/clk-fsd.c | 283 ++++++++++++++++++++++++++++++++++ 1 file changed, 283 insertions(+) diff --git a/drivers/clk/samsung/clk-fsd.c b/drivers/clk/samsung/clk-fsd.c index d06afab39d37..dc252e63099d 100644 --- a/drivers/clk/samsung/clk-fsd.c +++ b/drivers/clk/samsung/clk-fsd.c @@ -1184,6 +1184,289 @@ static const struct samsung_cmu_info fsys1_cmu_info __initconst = { .clk_name = "dout_cmu_fsys1_shared0div4", }; +/* Register Offset definitions for CMU_IMEM (0x10010000) */ +#define PLL_CON0_CLK_IMEM_ACLK 0x100 +#define PLL_CON0_CLK_IMEM_INTMEMCLK 0x120 +#define PLL_CON0_CLK_IMEM_TCUCLK 0x140 +#define DIV_OSCCLK_IMEM_TMUTSCLK 0x1800 +#define GAT_IMEM_IMEM_CMU_IMEM_IPCLKPORT_PCLK 0x2000 +#define GAT_IMEM_MCT_IPCLKPORT_OSCCLK__ALO 0x2004 +#define GAT_IMEM_OTP_CON_TOP_IPCLKPORT_I_OSCCLK 0x2008 +#define GAT_IMEM_RSTNSYNC_OSCCLK_IPCLKPORT_CLK 0x200c +#define GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK 0x2010 +#define GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS 0x2014 +#define GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK 0x2018 +#define GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS 0x201c +#define GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK 0x2020 +#define GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS 0x2024 +#define GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK 0x2028 +#define GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK_TS 0x202c +#define GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK 0x2030 +#define GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS 0x2034 +#define GAT_IMEM_WDT0_IPCLKPORT_CLK 0x2038 +#define GAT_IMEM_WDT1_IPCLKPORT_CLK 0x203c +#define GAT_IMEM_WDT2_IPCLKPORT_CLK 0x2040 +#define GAT_IMEM_ADM_AXI4ST_I0_IMEM_IPCLKPORT_ACLKM 0x2044 +#define GAT_IMEM_ADM_AXI4ST_I1_IMEM_IPCLKPORT_ACLKM 0x2048 +#define GAT_IMEM_ADM_AXI4ST_I2_IMEM_IPCLKPORT_ACLKM 0x204c +#define GAT_IMEM_ADS_AXI4ST_I0_IMEM_IPCLKPORT_ACLKS 0x2050 +#define GAT_IMEM_ADS_AXI4ST_I1_IMEM_IPCLKPORT_ACLKS 0x2054 +#define GAT_IMEM_ADS_AXI4ST_I2_IMEM_IPCLKPORT_ACLKS 0x2058 +#define GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKM 0x205c +#define GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKS 0x2060 +#define GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKM 0x2064 +#define GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKS 0x2068 +#define GAT_IMEM_AXI2APB_IMEMP0_IPCLKPORT_ACLK 0x206c +#define GAT_IMEM_AXI2APB_IMEMP1_IPCLKPORT_ACLK 0x2070 +#define GAT_IMEM_BUS_D_IMEM_IPCLKPORT_MAINCLK 0x2074 +#define GAT_IMEM_BUS_P_IMEM_IPCLKPORT_MAINCLK 0x2078 +#define GAT_IMEM_BUS_P_IMEM_IPCLKPORT_PERICLK 0x207c +#define GAT_IMEM_BUS_P_IMEM_IPCLKPORT_TCUCLK 0x2080 +#define GAT_IMEM_DMA0_IPCLKPORT_ACLK 0x2084 +#define GAT_IMEM_DMA1_IPCLKPORT_ACLK 0x2088 +#define GAT_IMEM_GIC500_INPUT_SYNC_IPCLKPORT_CLK 0x208c +#define GAT_IMEM_GIC_IPCLKPORT_CLK 0x2090 +#define GAT_IMEM_INTMEM_IPCLKPORT_ACLK 0x2094 +#define GAT_IMEM_MAILBOX_SCS_CA72_IPCLKPORT_PCLK 0x2098 +#define GAT_IMEM_MAILBOX_SMS_CA72_IPCLKPORT_PCLK 0x209c +#define GAT_IMEM_MCT_IPCLKPORT_PCLK 0x20a0 +#define GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_D 0x20a4 +#define GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_TCU 0x20a8 +#define GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSOC_IMEM__CLK_IMEM_P 0x20ac +#define GAT_IMEM_OTP_CON_TOP_IPCLKPORT_PCLK 0x20b0 +#define GAT_IMEM_RSTNSYNC_ACLK_IPCLKPORT_CLK 0x20b4 +#define GAT_IMEM_RSTNSYNC_INTMEMCLK_IPCLKPORT_CLK 0x20b8 +#define GAT_IMEM_RSTNSYNC_TCUCLK_IPCLKPORT_CLK 0x20bc +#define GAT_IMEM_SFRIF_TMU0_IMEM_IPCLKPORT_PCLK 0x20c0 +#define GAT_IMEM_SFRIF_TMU1_IMEM_IPCLKPORT_PCLK 0x20c4 +#define GAT_IMEM_SYSREG_IMEM_IPCLKPORT_PCLK 0x20c8 +#define GAT_IMEM_TBU_IMEM_IPCLKPORT_ACLK 0x20cc +#define GAT_IMEM_TCU_IPCLKPORT_ACLK 0x20d0 +#define GAT_IMEM_WDT0_IPCLKPORT_PCLK 0x20d4 +#define GAT_IMEM_WDT1_IPCLKPORT_PCLK 0x20d8 +#define GAT_IMEM_WDT2_IPCLKPORT_PCLK 0x20dc + +static const unsigned long imem_clk_regs[] __initconst = { + PLL_CON0_CLK_IMEM_ACLK, + PLL_CON0_CLK_IMEM_INTMEMCLK, + PLL_CON0_CLK_IMEM_TCUCLK, + DIV_OSCCLK_IMEM_TMUTSCLK, + GAT_IMEM_IMEM_CMU_IMEM_IPCLKPORT_PCLK, + GAT_IMEM_MCT_IPCLKPORT_OSCCLK__ALO, + GAT_IMEM_OTP_CON_TOP_IPCLKPORT_I_OSCCLK, + GAT_IMEM_RSTNSYNC_OSCCLK_IPCLKPORT_CLK, + GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK, + GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS, + GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK, + GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS, + GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK, + GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS, + GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK, + GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK_TS, + GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK, + GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS, + GAT_IMEM_WDT0_IPCLKPORT_CLK, + GAT_IMEM_WDT1_IPCLKPORT_CLK, + GAT_IMEM_WDT2_IPCLKPORT_CLK, + GAT_IMEM_ADM_AXI4ST_I0_IMEM_IPCLKPORT_ACLKM, + GAT_IMEM_ADM_AXI4ST_I1_IMEM_IPCLKPORT_ACLKM, + GAT_IMEM_ADM_AXI4ST_I2_IMEM_IPCLKPORT_ACLKM, + GAT_IMEM_ADS_AXI4ST_I0_IMEM_IPCLKPORT_ACLKS, + GAT_IMEM_ADS_AXI4ST_I1_IMEM_IPCLKPORT_ACLKS, + GAT_IMEM_ADS_AXI4ST_I2_IMEM_IPCLKPORT_ACLKS, + GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKM, + GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKS, + GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKM, + GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKS, + GAT_IMEM_AXI2APB_IMEMP0_IPCLKPORT_ACLK, + GAT_IMEM_AXI2APB_IMEMP1_IPCLKPORT_ACLK, + GAT_IMEM_BUS_D_IMEM_IPCLKPORT_MAINCLK, + GAT_IMEM_BUS_P_IMEM_IPCLKPORT_MAINCLK, + GAT_IMEM_BUS_P_IMEM_IPCLKPORT_PERICLK, + GAT_IMEM_BUS_P_IMEM_IPCLKPORT_TCUCLK, + GAT_IMEM_DMA0_IPCLKPORT_ACLK, + GAT_IMEM_DMA1_IPCLKPORT_ACLK, + GAT_IMEM_GIC500_INPUT_SYNC_IPCLKPORT_CLK, + GAT_IMEM_GIC_IPCLKPORT_CLK, + GAT_IMEM_INTMEM_IPCLKPORT_ACLK, + GAT_IMEM_MAILBOX_SCS_CA72_IPCLKPORT_PCLK, + GAT_IMEM_MAILBOX_SMS_CA72_IPCLKPORT_PCLK, + GAT_IMEM_MCT_IPCLKPORT_PCLK, + GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_D, + GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_TCU, + GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSOC_IMEM__CLK_IMEM_P, + GAT_IMEM_OTP_CON_TOP_IPCLKPORT_PCLK, + GAT_IMEM_RSTNSYNC_ACLK_IPCLKPORT_CLK, + GAT_IMEM_RSTNSYNC_INTMEMCLK_IPCLKPORT_CLK, + GAT_IMEM_RSTNSYNC_TCUCLK_IPCLKPORT_CLK, + GAT_IMEM_SFRIF_TMU0_IMEM_IPCLKPORT_PCLK, + GAT_IMEM_SFRIF_TMU1_IMEM_IPCLKPORT_PCLK, + GAT_IMEM_SYSREG_IMEM_IPCLKPORT_PCLK, + GAT_IMEM_TBU_IMEM_IPCLKPORT_ACLK, + GAT_IMEM_TCU_IPCLKPORT_ACLK, + GAT_IMEM_WDT0_IPCLKPORT_PCLK, + GAT_IMEM_WDT1_IPCLKPORT_PCLK, + GAT_IMEM_WDT2_IPCLKPORT_PCLK, +}; + +PNAME(mout_imem_clk_imem_tcuclk_p) = { "fin_pll", "dout_cmu_imem_tcuclk" }; +PNAME(mout_imem_clk_imem_aclk_p) = { "fin_pll", "dout_cmu_imem_aclk" }; +PNAME(mout_imem_clk_imem_intmemclk_p) = { "fin_pll", "dout_cmu_imem_dmaclk" }; + +static const struct samsung_mux_clock imem_mux_clks[] __initconst = { + MUX(0, "mout_imem_clk_imem_tcuclk", mout_imem_clk_imem_tcuclk_p, + PLL_CON0_CLK_IMEM_TCUCLK, 4, 1), + MUX(0, "mout_imem_clk_imem_aclk", mout_imem_clk_imem_aclk_p, PLL_CON0_CLK_IMEM_ACLK, 4, 1), + MUX(0, "mout_imem_clk_imem_intmemclk", mout_imem_clk_imem_intmemclk_p, + PLL_CON0_CLK_IMEM_INTMEMCLK, 4, 1), +}; + +static const struct samsung_div_clock imem_div_clks[] __initconst = { + DIV(0, "dout_imem_oscclk_imem_tmutsclk", "fin_pll", DIV_OSCCLK_IMEM_TMUTSCLK, 0, 4), +}; + +static const struct samsung_gate_clock imem_gate_clks[] __initconst = { + GATE(0, "imem_imem_cmu_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk", + GAT_IMEM_IMEM_CMU_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_otp_con_top_ipclkport_i_oscclk", "fin_pll", + GAT_IMEM_OTP_CON_TOP_IPCLKPORT_I_OSCCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_tmu_top_ipclkport_i_clk", "fin_pll", + GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_tmu_gt_ipclkport_i_clk", "fin_pll", + GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_tmu_cpu0_ipclkport_i_clk", "fin_pll", + GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_tmu_gpu_ipclkport_i_clk", "fin_pll", + GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_mct_ipclkport_oscclk__alo", "fin_pll", + GAT_IMEM_MCT_IPCLKPORT_OSCCLK__ALO, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_wdt0_ipclkport_clk", "fin_pll", + GAT_IMEM_WDT0_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_wdt1_ipclkport_clk", "fin_pll", + GAT_IMEM_WDT1_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_wdt2_ipclkport_clk", "fin_pll", + GAT_IMEM_WDT2_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS, "imem_tmu_cpu0_ipclkport_i_clk_ts", + "dout_imem_oscclk_imem_tmutsclk", + GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0), + GATE(IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS, "imem_tmu_cpu2_ipclkport_i_clk_ts", + "dout_imem_oscclk_imem_tmutsclk", + GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0), + GATE(IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS, "imem_tmu_gpu_ipclkport_i_clk_ts", + "dout_imem_oscclk_imem_tmutsclk", + GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0), + GATE(IMEM_TMU_GT_IPCLKPORT_I_CLK_TS, "imem_tmu_gt_ipclkport_i_clk_ts", + "dout_imem_oscclk_imem_tmutsclk", + GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0), + GATE(IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS, "imem_tmu_top_ipclkport_i_clk_ts", + "dout_imem_oscclk_imem_tmutsclk", + GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_adm_axi4st_i0_imem_ipclkport_aclkm", "mout_imem_clk_imem_aclk", + GAT_IMEM_ADM_AXI4ST_I0_IMEM_IPCLKPORT_ACLKM, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_adm_axi4st_i1_imem_ipclkport_aclkm", "mout_imem_clk_imem_aclk", + GAT_IMEM_ADM_AXI4ST_I1_IMEM_IPCLKPORT_ACLKM, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_adm_axi4st_i2_imem_ipclkport_aclkm", "mout_imem_clk_imem_aclk", + GAT_IMEM_ADM_AXI4ST_I2_IMEM_IPCLKPORT_ACLKM, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_ads_axi4st_i0_imem_ipclkport_aclks", "mout_imem_clk_imem_aclk", + GAT_IMEM_ADS_AXI4ST_I0_IMEM_IPCLKPORT_ACLKS, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_ads_axi4st_i1_imem_ipclkport_aclks", "mout_imem_clk_imem_aclk", + GAT_IMEM_ADS_AXI4ST_I1_IMEM_IPCLKPORT_ACLKS, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_ads_axi4st_i2_imem_ipclkport_aclks", "mout_imem_clk_imem_aclk", + GAT_IMEM_ADS_AXI4ST_I2_IMEM_IPCLKPORT_ACLKS, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_async_dma0_ipclkport_pclkm", "mout_imem_clk_imem_tcuclk", + GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_async_dma0_ipclkport_pclks", "mout_imem_clk_imem_aclk", + GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_async_dma1_ipclkport_pclkm", "mout_imem_clk_imem_tcuclk", + GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_async_dma1_ipclkport_pclks", "mout_imem_clk_imem_aclk", + GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_axi2apb_imemp0_ipclkport_aclk", "mout_imem_clk_imem_aclk", + GAT_IMEM_AXI2APB_IMEMP0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_axi2apb_imemp1_ipclkport_aclk", "mout_imem_clk_imem_aclk", + GAT_IMEM_AXI2APB_IMEMP1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_bus_d_imem_ipclkport_mainclk", "mout_imem_clk_imem_tcuclk", + GAT_IMEM_BUS_D_IMEM_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_bus_p_imem_ipclkport_mainclk", "mout_imem_clk_imem_aclk", + GAT_IMEM_BUS_P_IMEM_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_bus_p_imem_ipclkport_pericclk", "mout_imem_clk_imem_aclk", + GAT_IMEM_BUS_P_IMEM_IPCLKPORT_PERICLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_bus_p_imem_ipclkport_tcuclk", "mout_imem_clk_imem_tcuclk", + GAT_IMEM_BUS_P_IMEM_IPCLKPORT_TCUCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(IMEM_DMA0_IPCLKPORT_ACLK, "imem_dma0_ipclkport_aclk", "mout_imem_clk_imem_tcuclk", + GAT_IMEM_DMA0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0), + GATE(IMEM_DMA1_IPCLKPORT_ACLK, "imem_dma1_ipclkport_aclk", "mout_imem_clk_imem_tcuclk", + GAT_IMEM_DMA1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0), + GATE(0, "imem_gic500_input_sync_ipclkport_clk", "mout_imem_clk_imem_aclk", + GAT_IMEM_GIC500_INPUT_SYNC_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_gic_ipclkport_clk", "mout_imem_clk_imem_aclk", + GAT_IMEM_GIC_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_intmem_ipclkport_aclk", "mout_imem_clk_imem_intmemclk", + GAT_IMEM_INTMEM_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_mailbox_scs_ca72_ipclkport_pclk", "mout_imem_clk_imem_aclk", + GAT_IMEM_MAILBOX_SCS_CA72_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_mailbox_sms_ca72_ipclkport_pclk", "mout_imem_clk_imem_aclk", + GAT_IMEM_MAILBOX_SMS_CA72_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(IMEM_MCT_PCLK, "imem_mct_ipclkport_pclk", "mout_imem_clk_imem_aclk", + GAT_IMEM_MCT_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_ns_brdg_imem_ipclkport_clk__psco_imem__clk_imem_d", + "mout_imem_clk_imem_tcuclk", + GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_D, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_ns_brdg_imem_ipclkport_clk__psco_imem__clk_imem_tcu", + "mout_imem_clk_imem_tcuclk", + GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_TCU, 21, + CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_ns_brdg_imem_ipclkport_clk__psoc_imem__clk_imem_p", "mout_imem_clk_imem_aclk", + GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSOC_IMEM__CLK_IMEM_P, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_otp_con_top_ipclkport_pclk", "mout_imem_clk_imem_aclk", + GAT_IMEM_OTP_CON_TOP_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_rstnsync_aclk_ipclkport_clk", "mout_imem_clk_imem_aclk", + GAT_IMEM_RSTNSYNC_ACLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_rstnsync_oscclk_ipclkport_clk", "fin_pll", + GAT_IMEM_RSTNSYNC_OSCCLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_rstnsync_intmemclk_ipclkport_clk", "mout_imem_clk_imem_intmemclk", + GAT_IMEM_RSTNSYNC_INTMEMCLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_rstnsync_tcuclk_ipclkport_clk", "mout_imem_clk_imem_tcuclk", + GAT_IMEM_RSTNSYNC_TCUCLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_sfrif_tmu0_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk", + GAT_IMEM_SFRIF_TMU0_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_sfrif_tmu1_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk", + GAT_IMEM_SFRIF_TMU1_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_tmu_cpu2_ipclkport_i_clk", "fin_pll", + GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_sysreg_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk", + GAT_IMEM_SYSREG_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_tbu_imem_ipclkport_aclk", "mout_imem_clk_imem_tcuclk", + GAT_IMEM_TBU_IMEM_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_tcu_ipclkport_aclk", "mout_imem_clk_imem_tcuclk", + GAT_IMEM_TCU_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(IMEM_WDT0_IPCLKPORT_PCLK, "imem_wdt0_ipclkport_pclk", "mout_imem_clk_imem_aclk", + GAT_IMEM_WDT0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(IMEM_WDT1_IPCLKPORT_PCLK, "imem_wdt1_ipclkport_pclk", "mout_imem_clk_imem_aclk", + GAT_IMEM_WDT1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(IMEM_WDT2_IPCLKPORT_PCLK, "imem_wdt2_ipclkport_pclk", "mout_imem_clk_imem_aclk", + GAT_IMEM_WDT2_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), +}; + +static const struct samsung_cmu_info imem_cmu_info __initconst = { + .mux_clks = imem_mux_clks, + .nr_mux_clks = ARRAY_SIZE(imem_mux_clks), + .div_clks = imem_div_clks, + .nr_div_clks = ARRAY_SIZE(imem_div_clks), + .gate_clks = imem_gate_clks, + .nr_gate_clks = ARRAY_SIZE(imem_gate_clks), + .nr_clk_ids = IMEM_NR_CLK, + .clk_regs = imem_clk_regs, + .nr_clk_regs = ARRAY_SIZE(imem_clk_regs), +}; + +static void __init fsd_clk_imem_init(struct device_node *np) +{ + samsung_cmu_register_one(np, &imem_cmu_info); +} + +CLK_OF_DECLARE(fsd_clk_imem, "tesla,fsd-clock-imem", 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s.nawrocki@samsung.com, linux-samsung-soc@vger.kernel.org, pankaj.dubey@samsung.com, Alim Akhtar , linux-fsd@tesla.com, Smitha T Murthy Subject: [PATCH 08/23] clk: samsung: fsd: Add cmu_mfc block clock information Date: Thu, 13 Jan 2022 17:41:28 +0530 Message-Id: <20220113121143.22280-9-alim.akhtar@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220113121143.22280-1-alim.akhtar@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprIJsWRmVeSWpSXmKPExsWy7bCmhu4lyQeJBlM2mVg8mLeNzeL9sh5G i/lHzrFabHz7g8liyp/lTBabHl9jtfjYc4/V4uGrcIvLu+awWcw4v4/J4tT1z2wWi7Z+Ybdo 3XuE3eLwm3ZWi7t7tjFaPL7+h81BwGPNvDWMHrMaetk8Nq3qZPO4c20Pm8fmJfUeV040sXr0 bVnF6PGvaS67x+dNcgGcUdk2GamJKalFCql5yfkpmXnptkrewfHO8aZmBoa6hpYW5koKeYm5 qbZKLj4Bum6ZOUBfKCmUJeaUAoUCEouLlfTtbIryS0tSFTLyi0tslVILUnIKTAr0ihNzi0vz 0vXyUkusDA0MjEyBChOyM248/c9cMNO4Yk7DY7YGxnU6XYycHBICJhK9TxYxdjFycQgJ7GaU 2D57PjOE84lR4tztHVCZb4wSSza0MsG03P41nQkisZdR4tPPG2wQTguTxMr3u9lBqtgEtCXu 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X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220113122346epcas5p41a7d6712c07544e99795ef5465f1f106 References: <20220113121143.22280-1-alim.akhtar@samsung.com> This patch adds clock related to MFC IP. Cc: linux-fsd@tesla.com Signed-off-by: Smitha T Murthy Signed-off-by: Pankaj Dubey Signed-off-by: Alim Akhtar --- drivers/clk/samsung/clk-fsd.c | 121 ++++++++++++++++++++++++++++++++++ 1 file changed, 121 insertions(+) diff --git a/drivers/clk/samsung/clk-fsd.c b/drivers/clk/samsung/clk-fsd.c index dc252e63099d..927b310ce4a4 100644 --- a/drivers/clk/samsung/clk-fsd.c +++ b/drivers/clk/samsung/clk-fsd.c @@ -1467,6 +1467,124 @@ static void __init fsd_clk_imem_init(struct device_node *np) CLK_OF_DECLARE(fsd_clk_imem, "tesla,fsd-clock-imem", fsd_clk_imem_init); +/* Register Offset definitions for CMU_MFC (0x12810000) */ +#define PLL_LOCKTIME_PLL_MFC 0x0 +#define PLL_CON0_PLL_MFC 0x100 +#define MUX_MFC_BUSD 0x1000 +#define MUX_MFC_BUSP 0x1008 +#define DIV_MFC_BUSD_DIV4 0x1800 +#define GAT_MFC_CMU_MFC_IPCLKPORT_PCLK 0x2000 +#define GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKM 0x2004 +#define GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKS 0x2008 +#define GAT_MFC_AXI2APB_MFC_IPCLKPORT_ACLK 0x200c +#define GAT_MFC_MFC_IPCLKPORT_ACLK 0x2010 +#define GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_D 0x2018 +#define GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_P 0x201c +#define GAT_MFC_PPMU_MFCD0_IPCLKPORT_ACLK 0x2028 +#define GAT_MFC_PPMU_MFCD0_IPCLKPORT_PCLK 0x202c +#define GAT_MFC_PPMU_MFCD1_IPCLKPORT_ACLK 0x2030 +#define GAT_MFC_PPMU_MFCD1_IPCLKPORT_PCLK 0x2034 +#define GAT_MFC_SYSREG_MFC_IPCLKPORT_PCLK 0x2038 +#define GAT_MFC_TBU_MFCD0_IPCLKPORT_CLK 0x203c +#define GAT_MFC_TBU_MFCD1_IPCLKPORT_CLK 0x2040 +#define GAT_MFC_BUSD_DIV4_GATE 0x2044 +#define GAT_MFC_BUSD_GATE 0x2048 + +static const unsigned long mfc_clk_regs[] __initconst = { + PLL_LOCKTIME_PLL_MFC, + PLL_CON0_PLL_MFC, + MUX_MFC_BUSD, + MUX_MFC_BUSP, + DIV_MFC_BUSD_DIV4, + GAT_MFC_CMU_MFC_IPCLKPORT_PCLK, + GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKM, + GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKS, + GAT_MFC_AXI2APB_MFC_IPCLKPORT_ACLK, + GAT_MFC_MFC_IPCLKPORT_ACLK, + GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_D, + GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_P, + GAT_MFC_PPMU_MFCD0_IPCLKPORT_ACLK, + GAT_MFC_PPMU_MFCD0_IPCLKPORT_PCLK, + GAT_MFC_PPMU_MFCD1_IPCLKPORT_ACLK, + GAT_MFC_PPMU_MFCD1_IPCLKPORT_PCLK, + GAT_MFC_SYSREG_MFC_IPCLKPORT_PCLK, + GAT_MFC_TBU_MFCD0_IPCLKPORT_CLK, + GAT_MFC_TBU_MFCD1_IPCLKPORT_CLK, + GAT_MFC_BUSD_DIV4_GATE, + GAT_MFC_BUSD_GATE, +}; + +static const struct samsung_pll_rate_table pll_mfc_rate_table[] __initconst = { + PLL_35XX_RATE(24 * MHZ, 666000000, 111, 4, 0), +}; + +static const struct samsung_pll_clock mfc_pll_clks[] __initconst = { + PLL(pll_142xx, 0, "fout_pll_mfc", "fin_pll", + PLL_LOCKTIME_PLL_MFC, PLL_CON0_PLL_MFC, pll_mfc_rate_table), +}; + +PNAME(mout_mfc_pll_p) = { "fin_pll", "fout_pll_mfc" }; +PNAME(mout_mfc_busp_p) = { "fin_pll", "dout_mfc_busd_div4" }; +PNAME(mout_mfc_busd_p) = { "fin_pll", "mfc_busd_gate" }; + +static const struct samsung_mux_clock mfc_mux_clks[] __initconst = { + MUX(0, "mout_mfc_pll", mout_mfc_pll_p, PLL_CON0_PLL_MFC, 4, 1), + MUX(0, "mout_mfc_busp", mout_mfc_busp_p, MUX_MFC_BUSP, 0, 1), + MUX(0, "mout_mfc_busd", mout_mfc_busd_p, MUX_MFC_BUSD, 0, 1), +}; + +static const struct samsung_div_clock mfc_div_clks[] __initconst = { + DIV(0, "dout_mfc_busd_div4", "mfc_busd_div4_gate", DIV_MFC_BUSD_DIV4, 0, 4), +}; + +static const struct samsung_gate_clock mfc_gate_clks[] __initconst = { + GATE(0, "mfc_cmu_mfc_ipclkport_pclk", "mout_mfc_busp", + GAT_MFC_CMU_MFC_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "mfc_as_p_mfc_ipclkport_pclkm", "mout_mfc_busd", + GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "mfc_as_p_mfc_ipclkport_pclks", "mout_mfc_busp", + GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "mfc_axi2apb_mfc_ipclkport_aclk", "mout_mfc_busp", + GAT_MFC_AXI2APB_MFC_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(MFC_MFC_IPCLKPORT_ACLK, "mfc_mfc_ipclkport_aclk", "mout_mfc_busd", + GAT_MFC_MFC_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "mfc_ns_brdg_mfc_ipclkport_clk__pmfc__clk_mfc_d", "mout_mfc_busd", + GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_D, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "mfc_ns_brdg_mfc_ipclkport_clk__pmfc__clk_mfc_p", "mout_mfc_busp", + GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_P, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "mfc_ppmu_mfcd0_ipclkport_aclk", "mout_mfc_busd", + GAT_MFC_PPMU_MFCD0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "mfc_ppmu_mfcd0_ipclkport_pclk", "mout_mfc_busp", + GAT_MFC_PPMU_MFCD0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "mfc_ppmu_mfcd1_ipclkport_aclk", "mout_mfc_busd", + GAT_MFC_PPMU_MFCD1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "mfc_ppmu_mfcd1_ipclkport_pclk", "mout_mfc_busp", + GAT_MFC_PPMU_MFCD1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "mfc_sysreg_mfc_ipclkport_pclk", "mout_mfc_busp", + GAT_MFC_SYSREG_MFC_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "mfc_tbu_mfcd0_ipclkport_clk", "mout_mfc_busd", + GAT_MFC_TBU_MFCD0_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "mfc_tbu_mfcd1_ipclkport_clk", "mout_mfc_busd", + GAT_MFC_TBU_MFCD1_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "mfc_busd_div4_gate", "mout_mfc_pll", + GAT_MFC_BUSD_DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "mfc_busd_gate", "mout_mfc_pll", GAT_MFC_BUSD_GATE, 21, CLK_IS_CRITICAL, 0), +}; + +static const struct samsung_cmu_info mfc_cmu_info __initconst = { + .pll_clks = mfc_pll_clks, + .nr_pll_clks = ARRAY_SIZE(mfc_pll_clks), + .mux_clks = mfc_mux_clks, + .nr_mux_clks = ARRAY_SIZE(mfc_mux_clks), + .div_clks = mfc_div_clks, + .nr_div_clks = ARRAY_SIZE(mfc_div_clks), + .gate_clks = mfc_gate_clks, + .nr_gate_clks = ARRAY_SIZE(mfc_gate_clks), + .nr_clk_ids = MFC_NR_CLK, + .clk_regs = mfc_clk_regs, + .nr_clk_regs = ARRAY_SIZE(mfc_clk_regs), +}; + /** * fsd_cmu_probe - Probe function for FSD platform clocks * @pdev: Pointer to platform device @@ -1510,6 +1628,9 @@ static const struct of_device_id fsd_cmu_of_match[] = { }, { .compatible = "tesla,fsd-clock-fsys1", .data = &fsys1_cmu_info, + }, { + .compatible = "tesla,fsd-clock-mfc", + .data = &mfc_cmu_info, }, { }, }; From patchwork Thu Jan 13 12:11:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alim Akhtar X-Patchwork-Id: 12712661 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2A187C433F5 for ; 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Thu, 13 Jan 2022 12:23:51 +0000 (GMT) Received: from epsmgms1p2.samsung.com (unknown [182.195.42.42]) by epsmtrp1.samsung.com (KnoxPortal) with ESMTP id 20220113122351epsmtrp10f689a5eef907ae19acf0d8add9ae610~J0-758t6e1911119111epsmtrp1E; Thu, 13 Jan 2022 12:23:51 +0000 (GMT) X-AuditID: b6c32a49-b01ff70000001917-b1-61e019d71973 Received: from epsmtip2.samsung.com ( [182.195.34.31]) by epsmgms1p2.samsung.com (Symantec Messaging Gateway) with SMTP id 5F.99.08738.6D910E16; Thu, 13 Jan 2022 21:23:50 +0900 (KST) Received: from Jaguar.sa.corp.samsungelectronics.net (unknown [107.108.73.139]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20220113122348epsmtip2ac650a69adb0a9658f1cec68c74ef1c8~J0-5XOlk_1131511315epsmtip2F; Thu, 13 Jan 2022 12:23:48 +0000 (GMT) From: Alim Akhtar To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org List-Id: Cc: soc@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, olof@lixom.net, linus.walleij@linaro.org, catalin.marinas@arm.com, robh+dt@kernel.org, krzysztof.kozlowski@canonical.com, s.nawrocki@samsung.com, linux-samsung-soc@vger.kernel.org, pankaj.dubey@samsung.com, Alim Akhtar , linux-fsd@tesla.com, Sathyakam M Subject: [PATCH 09/23] clk: samsung: fsd: Add cam_csi block clock information Date: Thu, 13 Jan 2022 17:41:29 +0530 Message-Id: <20220113121143.22280-10-alim.akhtar@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220113121143.22280-1-alim.akhtar@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupnk+LIzCtJLcpLzFFi42LZdlhTU/eG5INEgz55iwfztrFZvF/Ww2gx /8g5VouNb38wWUz5s5zJYtPja6wWH3vusVo8fBVucXnXHDaLGef3MVmcuv6ZzWLR1i/sFq17 j7BbHH7Tzmrx5chrRovH1/+wOQh4rJm3htFjVkMvm8emVZ1sHneu7WHz2Lyk3uPKiSZWj74t qxg9/jXNZff4vEkugDMq2yYjNTEltUghNS85PyUzL91WyTs43jne1MzAUNfQ0sJcSSEvMTfV VsnFJ0DXLTMH6AklhbLEnFKgUEBicbGSvp1NUX5pSapCRn5xia1SakFKToFJgV5xYm5xaV66 Xl5qiZWhgYGRKVBhQnZG2+N77AWN8RWLnn1nbmDcEtLFyMkhIWAicW5fJ3sXIxeHkMBuRomP T+6xQTifGCXuTnnJCOF8ZpSY+6OfCablbVsvG4gtJLCLUWLaVT+IohYmiY6NR5lBEmwC2hJ3 p28BaxARcJO40djBBFLELNDALNEy9x9YkbCAv8T6hVeAbA4OFgFViZfPK0HCvAK2EseXXGWF WCYvsXrDAbASTqD43VV5IGMkBJZySDQ3H2OHqHGReNf1gw3CFpZ4dXwLVFxK4mV/GztIr4RA tkTPLmOIcI3E0nnHWCBse4kDV+awgJQwC2hKrN+lDxJmFuCT6P39hAmik1eio00IolpVovnd VahOaYmJ3d1QR3pIrNz3lxUSChMYJb7fes4+gVF2FsLUBYyMqxglUwuKc9NTi00LDPNSy+HR lJyfu4kRnDK1PHcw3n3wQe8QIxMH4yFGCQ5mJRHe/qL7iUK8KYmVValF+fFFpTmpxYcYTYEB NpFZSjQ5H5i080riDU0sDUzMzMxMLI3NDJXEeU+nb0gUEkhPLEnNTk0tSC2C6WPi4JRqYJpg GN68bIbq0fc+C0q+hz29VBd1a0V4/Tk9rsqVLAd9VDeGtb4PMun8uVT1a5h4zzfRroq0KluR xz073Rmrd504/X1loodq+ITbN6/Vnk598PVgxOU5C1PCLezY0n7vnM99Q6JuYcYBkSN+YtHz XrcfWyQr9m1x+oN12cXeH0Izti2UnxDf90ZN+ctMzvqd57drfXmsqXfNvKfogN88zlwrd56m rCx50V2fs5L0bbg/Jmx+8+fX/7NFIW9s3lx/x3jk6TGlbKXg76rKkY0cor6vVzd1/UhzLEr5 fq7fYlXznm8zf+WcZ+bXltXt4pnOfNtcvGH3llUxmsZGqjcnn2iMl7Cw/3D2aSNrIadhhxJL cUaioRZzUXEiAI6aHIsiBAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrKLMWRmVeSWpSXmKPExsWy7bCSvO41yQeJBh87tS0ezNvGZvF+WQ+j xfwj51gtNr79wWQx5c9yJotNj6+xWnzsucdq8fBVuMXlXXPYLGac38dkcer6ZzaLRVu/sFu0 7j3CbnH4TTurxZcjrxktHl//w+Yg4LFm3hpGj1kNvWwem1Z1snncubaHzWPzknqPKyeaWD36 tqxi9PjXNJfd4/MmuQDOKC6blNSczLLUIn27BK6Mtsf32Asa4ysWPfvO3MC4JaSLkZNDQsBE 4m1bL1sXIxeHkMAORomv34+yQySkJa5vnABlC0us/PecHaKoiUni1qlrzCAJNgFtibvTtzCB 2CICHhJt/+4xgxQxC0xglvi/YQILSEJYwFfi9u3DQN0cHCwCqhIvn1eChHkFbCWOL7nKCrFA XmL1hgPMICWcQPG7q/JAwkICNhLnXq1nm8DIt4CRYRWjZGpBcW56brFhgVFearlecWJucWle ul5yfu4mRnDIa2ntYNyz6oPeIUYmDsZDjBIczEoivP1F9xOFeFMSK6tSi/Lji0pzUosPMUpz sCiJ817oOhkvJJCeWJKanZpakFoEk2Xi4JRqYOqMClwg/85/U9L9H5eKIpqlXBRcPS+8bPzz +XoR+wm9XTWh7O1PGFn3ZO38PeHe3riZqTNVOGuXTmNbnj5/a+7WJ5Lqf59qpGxpsGcPYw39 cJdH+ZJkO+dM8erPn2bpp9tsvdjNVMiwurftnM0fL86In28XBkivtJ62P8/iZVw/U2foogen +1b8n3ws2FzigsAN7nurr79lTDbfwNDDG8lR7zV767aNXDXnG76835LfaxQ/+cFheY35E6bp Cr1bXuF62TfVdmbludD1bmJFNgGRLywNuwRMXnffLj2dLWSxvpMv2cbdL0J2gi3f03LlpT3m 6+InnJqm9P6i74KJXfmvT32R4/+zr8bk8Mx/k5VYijMSDbWYi4oTAV+RbaDoAgAA X-CMS-MailID: 20220113122351epcas5p45f49a559af9f6d0c6ba573594f95561d X-Msg-Generator: CA CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220113122351epcas5p45f49a559af9f6d0c6ba573594f95561d References: <20220113121143.22280-1-alim.akhtar@samsung.com> Adds clocks for BLK_CAM_CSI block, this is needed for CSI to work. Cc: linux-fsd@tesla.com Signed-off-by: Sathyakam M Signed-off-by: Pankaj Dubey Signed-off-by: Alim Akhtar --- drivers/clk/samsung/clk-fsd.c | 207 ++++++++++++++++++++++++++++++++++ 1 file changed, 207 insertions(+) diff --git a/drivers/clk/samsung/clk-fsd.c b/drivers/clk/samsung/clk-fsd.c index 927b310ce4a4..1bed8c7eb605 100644 --- a/drivers/clk/samsung/clk-fsd.c +++ b/drivers/clk/samsung/clk-fsd.c @@ -1585,6 +1585,210 @@ static const struct samsung_cmu_info mfc_cmu_info __initconst = { .nr_clk_regs = ARRAY_SIZE(mfc_clk_regs), }; +/* Register Offset definitions for CMU_CAM_CSI (0x12610000) */ +#define PLL_LOCKTIME_PLL_CAM_CSI 0x0 +#define PLL_CON0_PLL_CAM_CSI 0x100 +#define DIV_CAM_CSI0_ACLK 0x1800 +#define DIV_CAM_CSI1_ACLK 0x1804 +#define DIV_CAM_CSI2_ACLK 0x1808 +#define DIV_CAM_CSI_BUSD 0x180c +#define DIV_CAM_CSI_BUSP 0x1810 +#define GAT_CAM_CSI_CMU_CAM_CSI_IPCLKPORT_PCLK 0x2000 +#define GAT_CAM_AXI2APB_CAM_CSI_IPCLKPORT_ACLK 0x2004 +#define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI0 0x2008 +#define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI1 0x200c +#define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI2 0x2010 +#define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_SOC_NOC 0x2014 +#define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__NOC 0x2018 +#define GAT_CAM_CSI0_0_IPCLKPORT_I_ACLK 0x201c +#define GAT_CAM_CSI0_0_IPCLKPORT_I_PCLK 0x2020 +#define GAT_CAM_CSI0_1_IPCLKPORT_I_ACLK 0x2024 +#define GAT_CAM_CSI0_1_IPCLKPORT_I_PCLK 0x2028 +#define GAT_CAM_CSI0_2_IPCLKPORT_I_ACLK 0x202c +#define GAT_CAM_CSI0_2_IPCLKPORT_I_PCLK 0x2030 +#define GAT_CAM_CSI0_3_IPCLKPORT_I_ACLK 0x2034 +#define GAT_CAM_CSI0_3_IPCLKPORT_I_PCLK 0x2038 +#define GAT_CAM_CSI1_0_IPCLKPORT_I_ACLK 0x203c +#define GAT_CAM_CSI1_0_IPCLKPORT_I_PCLK 0x2040 +#define GAT_CAM_CSI1_1_IPCLKPORT_I_ACLK 0x2044 +#define GAT_CAM_CSI1_1_IPCLKPORT_I_PCLK 0x2048 +#define GAT_CAM_CSI1_2_IPCLKPORT_I_ACLK 0x204c +#define GAT_CAM_CSI1_2_IPCLKPORT_I_PCLK 0x2050 +#define GAT_CAM_CSI1_3_IPCLKPORT_I_ACLK 0x2054 +#define GAT_CAM_CSI1_3_IPCLKPORT_I_PCLK 0x2058 +#define GAT_CAM_CSI2_0_IPCLKPORT_I_ACLK 0x205c +#define GAT_CAM_CSI2_0_IPCLKPORT_I_PCLK 0x2060 +#define GAT_CAM_CSI2_1_IPCLKPORT_I_ACLK 0x2064 +#define GAT_CAM_CSI2_1_IPCLKPORT_I_PCLK 0x2068 +#define GAT_CAM_CSI2_2_IPCLKPORT_I_ACLK 0x206c +#define GAT_CAM_CSI2_2_IPCLKPORT_I_PCLK 0x2070 +#define GAT_CAM_CSI2_3_IPCLKPORT_I_ACLK 0x2074 +#define GAT_CAM_CSI2_3_IPCLKPORT_I_PCLK 0x2078 +#define GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_D 0x207c +#define GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_P 0x2080 +#define GAT_CAM_SYSREG_CAM_CSI_IPCLKPORT_PCLK 0x2084 +#define GAT_CAM_TBU_CAM_CSI_IPCLKPORT_ACLK 0x2088 + +static const unsigned long cam_csi_clk_regs[] __initconst = { + PLL_LOCKTIME_PLL_CAM_CSI, + PLL_CON0_PLL_CAM_CSI, + DIV_CAM_CSI0_ACLK, + DIV_CAM_CSI1_ACLK, + DIV_CAM_CSI2_ACLK, + DIV_CAM_CSI_BUSD, + DIV_CAM_CSI_BUSP, + GAT_CAM_CSI_CMU_CAM_CSI_IPCLKPORT_PCLK, + GAT_CAM_AXI2APB_CAM_CSI_IPCLKPORT_ACLK, + GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI0, + GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI1, + GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI2, + GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_SOC_NOC, + GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__NOC, + GAT_CAM_CSI0_0_IPCLKPORT_I_ACLK, + GAT_CAM_CSI0_0_IPCLKPORT_I_PCLK, + GAT_CAM_CSI0_1_IPCLKPORT_I_ACLK, + GAT_CAM_CSI0_1_IPCLKPORT_I_PCLK, + GAT_CAM_CSI0_2_IPCLKPORT_I_ACLK, + GAT_CAM_CSI0_2_IPCLKPORT_I_PCLK, + GAT_CAM_CSI0_3_IPCLKPORT_I_ACLK, + GAT_CAM_CSI0_3_IPCLKPORT_I_PCLK, + GAT_CAM_CSI1_0_IPCLKPORT_I_ACLK, + GAT_CAM_CSI1_0_IPCLKPORT_I_PCLK, + GAT_CAM_CSI1_1_IPCLKPORT_I_ACLK, + GAT_CAM_CSI1_1_IPCLKPORT_I_PCLK, + GAT_CAM_CSI1_2_IPCLKPORT_I_ACLK, + GAT_CAM_CSI1_2_IPCLKPORT_I_PCLK, + GAT_CAM_CSI1_3_IPCLKPORT_I_ACLK, + GAT_CAM_CSI1_3_IPCLKPORT_I_PCLK, + GAT_CAM_CSI2_0_IPCLKPORT_I_ACLK, + GAT_CAM_CSI2_0_IPCLKPORT_I_PCLK, + GAT_CAM_CSI2_1_IPCLKPORT_I_ACLK, + GAT_CAM_CSI2_1_IPCLKPORT_I_PCLK, + GAT_CAM_CSI2_2_IPCLKPORT_I_ACLK, + GAT_CAM_CSI2_2_IPCLKPORT_I_PCLK, + GAT_CAM_CSI2_3_IPCLKPORT_I_ACLK, + GAT_CAM_CSI2_3_IPCLKPORT_I_PCLK, + GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_D, + GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_P, + GAT_CAM_SYSREG_CAM_CSI_IPCLKPORT_PCLK, + GAT_CAM_TBU_CAM_CSI_IPCLKPORT_ACLK, +}; + +static const struct samsung_pll_rate_table pll_cam_csi_rate_table[] __initconst = { + PLL_35XX_RATE(24 * MHZ, 1066000000, 533, 12, 0), +}; + +static const struct samsung_pll_clock cam_csi_pll_clks[] __initconst = { + PLL(pll_142xx, 0, "fout_pll_cam_csi", "fin_pll", + PLL_LOCKTIME_PLL_CAM_CSI, PLL_CON0_PLL_CAM_CSI, pll_cam_csi_rate_table), +}; + +PNAME(mout_cam_csi_pll_p) = { "fin_pll", "fout_pll_cam_csi" }; + +static const struct samsung_mux_clock cam_csi_mux_clks[] __initconst = { + MUX(0, "mout_cam_csi_pll", mout_cam_csi_pll_p, PLL_CON0_PLL_CAM_CSI, 4, 1), +}; + +static const struct samsung_div_clock cam_csi_div_clks[] __initconst = { + DIV(0, "dout_cam_csi0_aclk", "mout_cam_csi_pll", DIV_CAM_CSI0_ACLK, 0, 4), + DIV(0, "dout_cam_csi1_aclk", "mout_cam_csi_pll", DIV_CAM_CSI1_ACLK, 0, 4), + DIV(0, "dout_cam_csi2_aclk", "mout_cam_csi_pll", DIV_CAM_CSI2_ACLK, 0, 4), + DIV(0, "dout_cam_csi_busd", "mout_cam_csi_pll", DIV_CAM_CSI_BUSD, 0, 4), + DIV(0, "dout_cam_csi_busp", "mout_cam_csi_pll", DIV_CAM_CSI_BUSP, 0, 4), +}; + +static const struct samsung_gate_clock cam_csi_gate_clks[] __initconst = { + GATE(0, "cam_csi_cmu_cam_csi_ipclkport_pclk", "dout_cam_csi_busp", + GAT_CAM_CSI_CMU_CAM_CSI_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cam_axi2apb_cam_csi_ipclkport_aclk", "dout_cam_csi_busp", + GAT_CAM_AXI2APB_CAM_CSI_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_csi0", "dout_cam_csi0_aclk", + GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI0, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_csi1", "dout_cam_csi1_aclk", + GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI1, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_csi2", "dout_cam_csi2_aclk", + GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI2, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_soc_noc", "dout_cam_csi_busd", + GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_SOC_NOC, 21, + CLK_IGNORE_UNUSED, 0), + GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__noc", "dout_cam_csi_busd", + GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__NOC, 21, CLK_IGNORE_UNUSED, 0), + GATE(CAM_CSI0_0_IPCLKPORT_I_ACLK, "cam_csi0_0_ipclkport_i_aclk", "dout_cam_csi0_aclk", + GAT_CAM_CSI0_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cam_csi0_0_ipclkport_i_pclk", "dout_cam_csi_busp", + GAT_CAM_CSI0_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CAM_CSI0_1_IPCLKPORT_I_ACLK, "cam_csi0_1_ipclkport_i_aclk", "dout_cam_csi0_aclk", + GAT_CAM_CSI0_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cam_csi0_1_ipclkport_i_pclk", "dout_cam_csi_busp", + GAT_CAM_CSI0_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CAM_CSI0_2_IPCLKPORT_I_ACLK, "cam_csi0_2_ipclkport_i_aclk", "dout_cam_csi0_aclk", + GAT_CAM_CSI0_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cam_csi0_2_ipclkport_i_pclk", "dout_cam_csi_busp", + GAT_CAM_CSI0_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CAM_CSI0_3_IPCLKPORT_I_ACLK, "cam_csi0_3_ipclkport_i_aclk", "dout_cam_csi0_aclk", + GAT_CAM_CSI0_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cam_csi0_3_ipclkport_i_pclk", "dout_cam_csi_busp", + GAT_CAM_CSI0_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CAM_CSI1_0_IPCLKPORT_I_ACLK, "cam_csi1_0_ipclkport_i_aclk", "dout_cam_csi1_aclk", + GAT_CAM_CSI1_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cam_csi1_0_ipclkport_i_pclk", "dout_cam_csi_busp", + GAT_CAM_CSI1_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CAM_CSI1_1_IPCLKPORT_I_ACLK, "cam_csi1_1_ipclkport_i_aclk", "dout_cam_csi1_aclk", + GAT_CAM_CSI1_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cam_csi1_1_ipclkport_i_pclk", "dout_cam_csi_busp", + GAT_CAM_CSI1_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CAM_CSI1_2_IPCLKPORT_I_ACLK, "cam_csi1_2_ipclkport_i_aclk", "dout_cam_csi1_aclk", + GAT_CAM_CSI1_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cam_csi1_2_ipclkport_i_pclk", "dout_cam_csi_busp", + GAT_CAM_CSI1_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CAM_CSI1_3_IPCLKPORT_I_ACLK, "cam_csi1_3_ipclkport_i_aclk", "dout_cam_csi1_aclk", + GAT_CAM_CSI1_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cam_csi1_3_ipclkport_i_pclk", "dout_cam_csi_busp", + GAT_CAM_CSI1_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CAM_CSI2_0_IPCLKPORT_I_ACLK, "cam_csi2_0_ipclkport_i_aclk", "dout_cam_csi2_aclk", + GAT_CAM_CSI2_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cam_csi2_0_ipclkport_i_pclk", "dout_cam_csi_busp", + GAT_CAM_CSI2_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CAM_CSI2_1_IPCLKPORT_I_ACLK, "cam_csi2_1_ipclkport_i_aclk", "dout_cam_csi2_aclk", + GAT_CAM_CSI2_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cam_csi2_1_ipclkport_i_pclk", "dout_cam_csi_busp", + GAT_CAM_CSI2_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CAM_CSI2_2_IPCLKPORT_I_ACLK, "cam_csi2_2_ipclkport_i_aclk", "dout_cam_csi2_aclk", + GAT_CAM_CSI2_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cam_csi2_2_ipclkport_i_pclk", "dout_cam_csi_busp", + GAT_CAM_CSI2_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CAM_CSI2_3_IPCLKPORT_I_ACLK, "cam_csi2_3_ipclkport_i_aclk", "dout_cam_csi2_aclk", + GAT_CAM_CSI2_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cam_csi2_3_ipclkport_i_pclk", "dout_cam_csi_busp", + GAT_CAM_CSI2_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cam_ns_brdg_cam_csi_ipclkport_clk__psoc_cam_csi__clk_cam_csi_d", + "dout_cam_csi_busd", + GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_D, 21, + CLK_IGNORE_UNUSED, 0), + GATE(0, "cam_ns_brdg_cam_csi_ipclkport_clk__psoc_cam_csi__clk_cam_csi_p", + "dout_cam_csi_busp", + GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_P, 21, + CLK_IGNORE_UNUSED, 0), + GATE(0, "cam_sysreg_cam_csi_ipclkport_pclk", "dout_cam_csi_busp", + GAT_CAM_SYSREG_CAM_CSI_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cam_tbu_cam_csi_ipclkport_aclk", "dout_cam_csi_busd", + GAT_CAM_TBU_CAM_CSI_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), +}; + +static const struct samsung_cmu_info cam_csi_cmu_info __initconst = { + .pll_clks = cam_csi_pll_clks, + .nr_pll_clks = ARRAY_SIZE(cam_csi_pll_clks), + .mux_clks = cam_csi_mux_clks, + .nr_mux_clks = ARRAY_SIZE(cam_csi_mux_clks), + .div_clks = cam_csi_div_clks, + .nr_div_clks = ARRAY_SIZE(cam_csi_div_clks), + .gate_clks = cam_csi_gate_clks, + .nr_gate_clks = ARRAY_SIZE(cam_csi_gate_clks), + .nr_clk_ids = CAM_CSI_NR_CLK, + .clk_regs = cam_csi_clk_regs, + .nr_clk_regs = ARRAY_SIZE(cam_csi_clk_regs), +}; + /** * fsd_cmu_probe - Probe function for FSD platform clocks * @pdev: Pointer to platform device @@ -1631,6 +1835,9 @@ static const struct of_device_id fsd_cmu_of_match[] = { }, { .compatible = "tesla,fsd-clock-mfc", .data = &mfc_cmu_info, + }, { + .compatible = "tesla,fsd-clock-cam_csi", + .data = &cam_csi_cmu_info, }, { }, }; From patchwork Thu Jan 13 12:11:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alim Akhtar X-Patchwork-Id: 12712662 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org 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Jaguar.sa.corp.samsungelectronics.net (unknown [107.108.73.139]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20220113122352epsmtip2a4388db5d0a06d9505fca78827532767~J0-9HEeD-1246412464epsmtip2n; Thu, 13 Jan 2022 12:23:52 +0000 (GMT) From: Alim Akhtar To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org List-Id: Cc: soc@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, olof@lixom.net, linus.walleij@linaro.org, catalin.marinas@arm.com, robh+dt@kernel.org, krzysztof.kozlowski@canonical.com, s.nawrocki@samsung.com, linux-samsung-soc@vger.kernel.org, pankaj.dubey@samsung.com, Alim Akhtar , linux-fsd@tesla.com Subject: [PATCH 10/23] dt-bindings: pinctrl: samsung: Add compatible for Tesla FSD SoC Date: Thu, 13 Jan 2022 17:41:30 +0530 Message-Id: <20220113121143.22280-11-alim.akhtar@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220113121143.22280-1-alim.akhtar@samsung.com> X-Brightmail-Tracker: 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The pinctrl hardware IP is similar to what found on most of the exynos series of SoC, so this new compatible is added in samsung pinctrl binding. Cc: linux-fsd@tesla.com Signed-off-by: Alim Akhtar --- Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt index b8b475967ff9..ba972998a0e4 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt @@ -24,6 +24,7 @@ Required Properties: - "samsung,exynos7-pinctrl": for Exynos7 compatible pin-controller. - "samsung,exynos850-pinctrl": for Exynos850 compatible pin-controller. - "samsung,exynosautov9-pinctrl": for ExynosAutov9 compatible pin-controller. + - "tesla,fsd-pinctrl": for Tesla FSD SoC compatible pin-controller. - reg: Base address of the pin controller hardware module and length of the address space it occupies. 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Thu, 13 Jan 2022 21:23:59 +0900 (KST) Received: from Jaguar.sa.corp.samsungelectronics.net (unknown [107.108.73.139]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20220113122356epsmtip2f3a3294d6d6b19894d6e7424a91f856a~J1AAdgRU01245812458epsmtip2p; Thu, 13 Jan 2022 12:23:55 +0000 (GMT) From: Alim Akhtar To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org List-Id: Cc: soc@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, olof@lixom.net, linus.walleij@linaro.org, catalin.marinas@arm.com, robh+dt@kernel.org, krzysztof.kozlowski@canonical.com, s.nawrocki@samsung.com, linux-samsung-soc@vger.kernel.org, pankaj.dubey@samsung.com, Alim Akhtar , linux-fsd@tesla.com, Ajay Kumar Subject: [PATCH 11/23] pinctrl: samsung: add FSD SoC specific data Date: Thu, 13 Jan 2022 17:41:31 +0530 Message-Id: <20220113121143.22280-12-alim.akhtar@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220113121143.22280-1-alim.akhtar@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprIJsWRmVeSWpSXmKPExsWy7bCmlu4DyQeJBkdX2VgceH+QxeLBvG1s Fu+X9TBazD9yjtVi49sfTBZT/ixnstj0+Bqrxceee6wWD1+FW1zeNYfNYsb5fUwWp65/ZrNY tPULu0Xr3iPsFofftLNaPL7+h81BwGPNvDWMHrMaetk8Nq3qZPO4c20Pm8fmJfUeV040sXr0 bVnF6PGvaS67x+dNcgGcUdk2GamJKalFCql5yfkpmXnptkrewfHO8aZmBoa6hpYW5koKeYm5 qbZKLj4Bum6ZOUBfKCmUJeaUAoUCEouLlfTtbIryS0tSFTLyi0tslVILUnIKTAr0ihNzi0vz 0vXyUkusDA0MjEyBChOyMw6smMtScEajonfHNPYGxunKXYycHBICJhKzfv9g7WLk4hAS2M0o cWDDbmYI5xOjxL/+5UwQzmdGiY2zFjDCtDzq3gzVsotRYt776+wgCSGBFiaJL6dkQWw2AW2J u9O3MIHYIgJuEjcaO8AmMQu0MkvMb93ODJIQFnCS2PHyPRuIzSKgKvH39DmwDbwCthJT+jZB bZOXWL3hAFA9BwcnUPzuqjyQORICKzkkzkx/wAJR4yLRfPU9K4QtLPHq+BZ2CFtK4mV/GztI r4RAtkTPLmOIcI3E0nnHoFrtJQ5cmcMCUsIsoCmxfpc+SJhZgE+i9/cTJohOXomONiGIalWJ 5ndXoTqlJSZ2d0Mt9ZD4vqqBBRIkExglNr95zTyBUXYWwtQFjIyrGCVTC4pz01OLTQuM8lLL 4fGUnJ+7iRGcNrW8djA+fPBB7xAjEwfjIUYJDmYlEd7+ovuJQrwpiZVVqUX58UWlOanFhxhN gSE2kVlKNDkfmLjzSuINTSwNTMzMzEwsjc0MlcR5T6dvSBQSSE8sSc1OTS1ILYLpY+LglGpg 6rsVqsAraFe7Z67Ax2XlSqee6D6sX/Zn88cdc0+JB1Q/k10T1Pen6u61Q1/ZAmfIuhSvrL3d 9GibeslxlUPNtevF3vbbX5d/NW2JOOMVHreOV8e9PQ7IH16oob3k6f1YLwb+NcX6mparFv94 U11SmeY+fU7VbdkW42n2cyUuC5q/K9ru3te1ZRHfy53290OeMT57sMJ7v93F4GsPvl3/naOY 5+6XlasYNK2kMJ+xJ8Ko+IEIo8XNj1m3bkTs8636O3nt0YwdrPxcLHcSM/MjizY1ycqEH19a XZpT2597eOka5ycdyQefl/Ty6mtLrZt4bOommZK85GsmLacUqhWDdBTE5R53uV5fdFL6wKkF SizFGYmGWsxFxYkAcfvH/SQEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrGLMWRmVeSWpSXmKPExsWy7bCSvO59yQeJBiefqFgceH+QxeLBvG1s Fu+X9TBazD9yjtVi49sfTBZT/ixnstj0+Bqrxceee6wWD1+FW1zeNYfNYsb5fUwWp65/ZrNY tPULu0Xr3iPsFofftLNaPL7+h81BwGPNvDWMHrMaetk8Nq3qZPO4c20Pm8fmJfUeV040sXr0 bVnF6PGvaS67x+dNcgGcUVw2Kak5mWWpRfp2CVwZB1bMZSk4o1HRu2MaewPjdOUuRk4OCQET iUfdm1m7GLk4hAR2MEp07drBBpGQlri+cQI7hC0ssfLfc3aIoiYmial3pjCCJNgEtCXuTt/C BGKLCHhItP27xwxSxCwwlVli1YYuZpCEsICTxI6X78GmsgioSvw9fQ6smVfAVmJK3yZGiA3y Eqs3HACq5+DgBIrfXZUHEhYSsJE492o92wRGvgWMDKsYJVMLinPTc4sNC4zyUsv1ihNzi0vz 0vWS83M3MYKDXktrB+OeVR/0DjEycTAeYpTgYFYS4e0vup8oxJuSWFmVWpQfX1Sak1p8iFGa g0VJnPdC18l4IYH0xJLU7NTUgtQimCwTB6dUA9P+veujmV7lW0zMTRfMOL4y+czebMfoFV4Z 3R/Wi3daz+nZXrqb52KK+u2ZVx/FXNOIes27Kj/3wME3u5o+Wi7q63+df/WEAPu88/b3GDS9 i3g4+CT+6vtYBW2INmj4+EXC5EdsxofnFkviuxoNbh23W72INyZQwPPZDZat11NeqzTf+b65 Zcq1I4zZPpPvvYw/YHg+68rLk0eYdi8qPf2z76XGhWu3zlopBTXc/GL7as/ujJRrj6OF2wvL BBg6Py7lYGZxEuObcOP38mzlLt/TbCnnJxZsjT8Tcf4Ff5xZ0599DnuOyx+PniHIZPVHffrG aUY7zqss6U0wmMG9bI1xxsyjkjVJm6b9OJyZ+S9UiaU4I9FQi7moOBEA+ndbjukCAAA= X-CMS-MailID: 20220113122400epcas5p34363ba8f477b4c273d601d0b64324afa X-Msg-Generator: CA CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220113122400epcas5p34363ba8f477b4c273d601d0b64324afa References: <20220113121143.22280-1-alim.akhtar@samsung.com> This patch adds Tesla FSD SoC specific data to enable pinctrl. FSD SoC has similar pinctrl controller as found in the most samsung/exynos SoCs. Cc: linux-fsd@tesla.com Signed-off-by: Ajay Kumar Signed-off-by: Alim Akhtar Acked-by: Linus Walleij --- .../pinctrl/samsung/pinctrl-exynos-arm64.c | 71 +++++++++++++++++++ drivers/pinctrl/samsung/pinctrl-samsung.c | 2 + drivers/pinctrl/samsung/pinctrl-samsung.h | 1 + 3 files changed, 74 insertions(+) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c index 6b77fd24571e..b9175b4911ac 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c @@ -646,3 +646,74 @@ const struct samsung_pinctrl_of_match_data exynosautov9_of_data __initconst = { .ctrl = exynosautov9_pin_ctrl, .num_ctrl = ARRAY_SIZE(exynosautov9_pin_ctrl), }; + +/* + * Pinctrl driver data for Tesla FSD SoC. FSD SoC includes three + * gpio/pin-mux/pinconfig controllers. + */ + +/* pin banks of FSD pin-controller 0 (FSYS) */ +static const struct samsung_pin_bank_data fsd_pin_banks0[] __initconst = { + EXYNOS850_PIN_BANK_EINTG(7, 0x00, "gpf0", 0x00), + EXYNOS850_PIN_BANK_EINTG(8, 0x20, "gpf1", 0x04), + EXYNOS850_PIN_BANK_EINTG(3, 0x40, "gpf6", 0x08), + EXYNOS850_PIN_BANK_EINTG(2, 0x60, "gpf4", 0x0c), + EXYNOS850_PIN_BANK_EINTG(6, 0x80, "gpf5", 0x10), +}; + +/* pin banks of FSD pin-controller 1 (PERIC) */ +static const struct samsung_pin_bank_data fsd_pin_banks1[] __initconst = { + EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpc8", 0x00), + EXYNOS850_PIN_BANK_EINTG(7, 0x020, "gpf2", 0x04), + EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpf3", 0x08), + EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpd0", 0x0c), + EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpb0", 0x10), + EXYNOS850_PIN_BANK_EINTG(8, 0x0a0, "gpb1", 0x14), + EXYNOS850_PIN_BANK_EINTG(8, 0x0c0, "gpb4", 0x18), + EXYNOS850_PIN_BANK_EINTG(4, 0x0e0, "gpb5", 0x1c), + EXYNOS850_PIN_BANK_EINTG(8, 0x100, "gpb6", 0x20), + EXYNOS850_PIN_BANK_EINTG(8, 0x120, "gpb7", 0x24), + EXYNOS850_PIN_BANK_EINTG(5, 0x140, "gpd1", 0x28), + EXYNOS850_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c), + EXYNOS850_PIN_BANK_EINTG(7, 0x180, "gpd3", 0x30), + EXYNOS850_PIN_BANK_EINTG(8, 0x1a0, "gpg0", 0x34), + EXYNOS850_PIN_BANK_EINTG(8, 0x1c0, "gpg1", 0x38), + EXYNOS850_PIN_BANK_EINTG(8, 0x1e0, "gpg2", 0x3c), + EXYNOS850_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40), + EXYNOS850_PIN_BANK_EINTG(8, 0x220, "gpg4", 0x44), + EXYNOS850_PIN_BANK_EINTG(8, 0x240, "gpg5", 0x48), + EXYNOS850_PIN_BANK_EINTG(8, 0x260, "gpg6", 0x4c), + EXYNOS850_PIN_BANK_EINTG(8, 0x280, "gpg7", 0x50), +}; + +/* pin banks of FSD pin-controller 2 (PMU) */ +static const struct samsung_pin_bank_data fsd_pin_banks2[] __initconst = { + EXYNOS850_PIN_BANK_EINTN(3, 0x00, "gpq0"), +}; + +const struct samsung_pin_ctrl fsd_pin_ctrl[] __initconst = { + { + /* pin-controller instance 0 FSYS0 data */ + .pin_banks = fsd_pin_banks0, + .nr_banks = ARRAY_SIZE(fsd_pin_banks0), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 1 PERIC data */ + .pin_banks = fsd_pin_banks1, + .nr_banks = ARRAY_SIZE(fsd_pin_banks1), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 2 PMU data */ + .pin_banks = fsd_pin_banks2, + .nr_banks = ARRAY_SIZE(fsd_pin_banks2), + }, +}; + +const struct samsung_pinctrl_of_match_data fsd_of_data __initconst = { + .ctrl = fsd_pin_ctrl, + .num_ctrl = ARRAY_SIZE(fsd_pin_ctrl), +}; diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index 23f355ae9ca0..4b348c038f7a 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -1268,6 +1268,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = { .data = &exynos850_of_data }, { .compatible = "samsung,exynosautov9-pinctrl", .data = &exynosautov9_of_data }, + { .compatible = "tesla,fsd-pinctrl", + .data = &fsd_of_data }, #endif #ifdef CONFIG_PINCTRL_S3C64XX { .compatible = "samsung,s3c64xx-pinctrl", diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h index 547968a31aed..43d8a8a139c3 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -341,6 +341,7 @@ extern const struct samsung_pinctrl_of_match_data exynos5433_of_data; extern const struct samsung_pinctrl_of_match_data exynos7_of_data; extern const struct samsung_pinctrl_of_match_data exynos850_of_data; extern const struct samsung_pinctrl_of_match_data exynosautov9_of_data; +extern const struct samsung_pinctrl_of_match_data fsd_of_data; extern const struct samsung_pinctrl_of_match_data s3c64xx_of_data; extern const struct samsung_pinctrl_of_match_data s3c2412_of_data; extern const struct samsung_pinctrl_of_match_data s3c2416_of_data; From patchwork Thu Jan 13 12:11:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alim Akhtar X-Patchwork-Id: 12712664 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8CA95C43217 for ; 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Thu, 13 Jan 2022 12:24:04 +0000 (GMT) Received: from epsmgms1p1new.samsung.com (unknown [182.195.42.41]) by epsmtrp1.samsung.com (KnoxPortal) with ESMTP id 20220113122404epsmtrp12067e84df56a8022e5df48c606c0232a~J1AIEw8p71911119111epsmtrp1V; Thu, 13 Jan 2022 12:24:04 +0000 (GMT) X-AuditID: b6c32a49-b13ff70000001917-cc-61e019e4a2d5 Received: from epsmtip2.samsung.com ( [182.195.34.31]) by epsmgms1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id 21.A8.29871.3E910E16; Thu, 13 Jan 2022 21:24:03 +0900 (KST) Received: from Jaguar.sa.corp.samsungelectronics.net (unknown [107.108.73.139]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20220113122401epsmtip254c6116eb94f14a9ffb459ee92f517d3~J1AFXm4yK1245212452epsmtip2r; Thu, 13 Jan 2022 12:24:01 +0000 (GMT) From: Alim Akhtar To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org List-Id: Cc: soc@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, olof@lixom.net, linus.walleij@linaro.org, catalin.marinas@arm.com, robh+dt@kernel.org, krzysztof.kozlowski@canonical.com, s.nawrocki@samsung.com, linux-samsung-soc@vger.kernel.org, pankaj.dubey@samsung.com, Alim Akhtar , linux-fsd@tesla.com Subject: [PATCH 12/23] dt-bindings: add vendor prefix for Tesla Date: Thu, 13 Jan 2022 17:41:32 +0530 Message-Id: <20220113121143.22280-13-alim.akhtar@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220113121143.22280-1-alim.akhtar@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupik+LIzCtJLcpLzFFi42LZdlhTQ/ep5INEg50eFg/mbWOzeL+sh9Fi /pFzrBYb3/5gspjyZzmTxabH11gtPvbcY7V4+Crc4vKuOWwWM87vY7I4df0zm8WirV/YLVr3 HmG3OPymndXi8fU/bA78HmvmrWH0mNXQy+axaVUnm8eda3vYPDYvqfe4cqKJ1aNvyypGj39N c9k9Pm+SC+CMyrbJSE1MSS1SSM1Lzk/JzEu3VfIOjneONzUzMNQ1tLQwV1LIS8xNtVVy8QnQ dcvMAbpfSaEsMacUKBSQWFyspG9nU5RfWpKqkJFfXGKrlFqQklNgUqBXnJhbXJqXrpeXWmJl aGBgZApUmJCd0b7nHHvBBraKrVcvsjYwbmftYuTkkBAwkdizYRpLFyMXh5DAbkaJtz3NTBDO J0aJQ033GCGcb4wSHdOXMncxcoC1HFiiAxHfyygxf3o3M4TTwiQx+8ozdpC5bALaEnenb2EC sUUE3CRuNHaAjWUWuMck8eNwAzNIQljAXuLMzh3sIFNZBFQlrn/NBAnzCthKTH96gA3iPnmJ 1RsOgC3mBIrfXZUHMkZCYCGHxKf+XqgfXCQ+nV3JAmELS7w6voUdwpaSeNnfxg5xdLZEzy5j iHCNxNJ5x6DK7SUOXJnDAlLCLKApsX6XPkiYWYBPovf3EyaITl6JjjYhiGpVieZ3V6E6pSUm dndDHeAhMftcLzskFCYwShz5+phlAqPsLISpCxgZVzFKphYU56anFpsWGOallsOjKTk/dxMj OFFqee5gvPvgg94hRiYOxkOMEhzMSiK8/UX3E4V4UxIrq1KL8uOLSnNSiw8xmgIDbCKzlGhy PjBV55XEG5pYGpiYmZmZWBqbGSqJ855O35AoJJCeWJKanZpakFoE08fEwSnVwMRvrHuvwWBp 4GRPLy4rY7OogGWlm7pb9h2Y5b2+iJl7n/K6c0FXNS2m+k/pKS5aEep1+Vtkn3rWyQfiSQsT GOQW9J0JX3xa7+Tifz7umXvO3b56MGWG1BdXu4k2U6PWV3JovZmh+bUsv3vH2gsH/+2oe+4R MPum+kObpXNrp6nbOho6Z2XpiEbPefObsc/Ux+/6bx3Wso7Ywg0cF45Of+Eq77Lp8f/I5Blv e6rS6uS3K/UK91r9XNxemRXZWrhOK2pRZNTUw3y8Z57lezTYXVjmydBy7frl0/uNGwKmbOJd y67+69Dtr5yr5OJnTrrh8dHglYOpZd63eSmTPy1xPnPWbsKLc672D/IOxs5Us1JiKc5INNRi LipOBABPs5J0HQQAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrPLMWRmVeSWpSXmKPExsWy7bCSvO5jyQeJBh0zzSwezNvGZvF+WQ+j xfwj51gtNr79wWQx5c9yJotNj6+xWnzsucdq8fBVuMXlXXPYLGac38dkcer6ZzaLRVu/sFu0 7j3CbnH4TTurxePrf9gc+D3WzFvD6DGroZfNY9OqTjaPO9f2sHlsXlLvceVEE6tH35ZVjB7/ muaye3zeJBfAGcVlk5Kak1mWWqRvl8CV0b7nHHvBBraKrVcvsjYwbmftYuTgkBAwkTiwRKeL kYtDSGA3o8S+vjnMXYycQHFpiesbJ7BD2MISK/89Z4coamKS2HvkFRNIgk1AW+Lu9C1gtoiA h0Tbv3vMIEXMAm+YJP7fn8MCkhAWsJc4s3MHO8g2FgFVietfM0HCvAK2EtOfHmCDWCAvsXrD AWaQEk6g+N1VeSBhIQEbiXOv1rNNYORbwMiwilEytaA4Nz232LDAMC+1XK84Mbe4NC9dLzk/ dxMjOMy1NHcwbl/1Qe8QIxMH4yFGCQ5mJRHe/qL7iUK8KYmVValF+fFFpTmpxYcYpTlYlMR5 L3SdjBcSSE8sSc1OTS1ILYLJMnFwSjUwuRjGNHyYePKJe3Ujz8xLn7unbDAW51P4tsdG0ZVJ 8bf8sohoqRq7AgPrh3avz+eJfUySettZy+a4TS6jbnn6vxtOC1b7W7wryj6/L//0v7zEjlX+ vx703Xy0sCyBW9YmPFzn9mTdeQ4PdgnYHTnS2P1HLJ81vGTTzC+Sbu/8JS6zqoVGvdv0Wjfp Qd6xvhnzVLSPFZ2oXr6o4VdGrNi2CONrW5TZL2dv37thi89W3y8vRdcJrfK5l5Tz6yTX1BLz NfODlSzWRK81Y9K35LPl3XF8R941kac/OA5OXVu2Vsv+mtPN3DzG7A2C56UlnXIDGqdUqB3J mhQ3e67ClNyZu7oPlUUueHfYbb3LSrunSizFGYmGWsxFxYkAG30VH+ICAAA= X-CMS-MailID: 20220113122404epcas5p4aa1c3ac09510eb55cce5fdd0791993a6 X-Msg-Generator: CA CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220113122404epcas5p4aa1c3ac09510eb55cce5fdd0791993a6 References: <20220113121143.22280-1-alim.akhtar@samsung.com> Add vendor prefix for the Tesla (https://www.tesla.com) Cc: linux-fsd@tesla.com Signed-off-by: Alim Akhtar Reviewed-by: Krzysztof Kozlowski Reviewed-by: Linus Walleij --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 66d6432fd781..af71d00f1092 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1189,6 +1189,8 @@ patternProperties: description: Shenzhen Techstar Electronics Co., Ltd. "^terasic,.*": description: Terasic Inc. + "^tesla,.*": + description: Tesla, Inc. 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Thu, 13 Jan 2022 21:24:07 +0900 (KST) Received: from Jaguar.sa.corp.samsungelectronics.net (unknown [107.108.73.139]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20220113122406epsmtip272720627aeb46c098502890f3fd7631e~J1AJrgq7T1246112461epsmtip2S; Thu, 13 Jan 2022 12:24:05 +0000 (GMT) From: Alim Akhtar To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org List-Id: Cc: soc@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, olof@lixom.net, linus.walleij@linaro.org, catalin.marinas@arm.com, robh+dt@kernel.org, krzysztof.kozlowski@canonical.com, s.nawrocki@samsung.com, linux-samsung-soc@vger.kernel.org, pankaj.dubey@samsung.com, Alim Akhtar , linux-fsd@tesla.com Subject: [PATCH 13/23] dt-bindings: arm: add Tesla FSD ARM SoC Date: Thu, 13 Jan 2022 17:41:33 +0530 Message-Id: <20220113121143.22280-14-alim.akhtar@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220113121143.22280-1-alim.akhtar@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupik+LIzCtJLcpLzFFi42LZdlhTQ/eF5INEgz1LJC0ezNvGZvF+WQ+j xfwj51gtNr79wWQx5c9yJotNj6+xWnzsucdq8fBVuMXlXXPYLGac38dkcer6ZzaLRVu/sFu0 7j3CbnH4TTurxePrf9gc+D3WzFvD6DGroZfNY9OqTjaPO9f2sHlsXlLvceVEE6tH35ZVjB7/ muaye3zeJBfAGZVtk5GamJJapJCal5yfkpmXbqvkHRzvHG9qZmCoa2hpYa6kkJeYm2qr5OIT oOuWmQP0gJJCWWJOKVAoILG4WEnfzqYov7QkVSEjv7jEVim1ICWnwKRArzgxt7g0L10vL7XE ytDAwMgUqDAhO2Px5bnMBb84Kk48P8/SwLiZvYuRk0NCwETi+t3pQDYXh5DAbkaJM7t3MIEk hAQ+MUp86GWBSHxmlFj4tJ21i5EDrOPcM6j4LkaJs8unMkM4LUwSE/a3sIB0swloS9ydvgVs koiAm8SNxg4mkCJmgXtMEj8ONzCDJIQF7CS+z34HdgeLgKrEjQOfwWxeAVuJZ6uXskLcJy+x esMBZpDNnEDxu6vyQOZICCzkkDi+ZTNUjYvEptM7GCFsYYlXx7dA/SYl8fndXjaIq7MlenYZ Q4RrJJbOO8YCYdtLHLgyhwWkhFlAU2L9Ln2QMLMAn0Tv7ydMEJ28Eh1tQhDVqhLN765CdUpL TOzuhjrAQ+LVk9+skHCbwChxYbXaBEbZWQhDFzAyrmKUTC0ozk1PLTYtMMxLLYfHUnJ+7iZG cKLU8tzBePfBB71DjEwcjIcYJTiYlUR4+4vuJwrxpiRWVqUW5ccXleakFh9iNAUG2ERmKdHk fGCqziuJNzSxNDAxMzMzsTQ2M1QS5z2dviFRSCA9sSQ1OzW1ILUIpo+Jg1OqgWnrdNUZfS49 r5OUFl2LkVY/0fsuJbXMLGxiV/qs2Qs3ehh9s001NWhgUiuImJ9X5L1syxt5zltRx2MtxRcJ MLzzkl9x3CSu0kYjQNd8wYG7H70n3ZXL/180Z0Vo7cQLt9wuKBhqK8RtWiNUvP31Vn1d4YT7 37LqjH7ePsB4+thTg4/fFZ6ZT+CQcnhU9N+vW+b3u74nh/hfJKw/vGPNpePFmZ9nd+0r+dXU xbak+bRLmMzJyB3xl3yn2ZzonCmXvdlevMn1iHzU411dhiZzN804L7TlwmKdml3nYrMeG35u C5ZIu/6I0cJZW+GQ7Krqfr4txrnRlg/nnLaelR6cbB479dPDKX63tfVdnV5NV1ZiKc5INNRi LipOBADrP3JsHQQAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrALMWRmVeSWpSXmKPExsWy7bCSvO5zyQeJBteW6Vo8mLeNzeL9sh5G i/lHzrFabHz7g8liyp/lTBabHl9jtfjYc4/V4uGrcIvLu+awWcw4v4/J4tT1z2wWi7Z+Ybdo 3XuE3eLwm3ZWi8fX/7A58HusmbeG0WNWQy+bx6ZVnWwed67tYfPYvKTe48qJJlaPvi2rGD3+ Nc1l9/i8SS6AM4rLJiU1J7MstUjfLoErY/HlucwFvzgqTjw/z9LAuJm9i5GDQ0LAROLcM5Yu Ri4OIYEdjBKPNq9i62LkBIpLS1zfOIEdwhaWWPnvOTtEUROTxMrr+5hAEmwC2hJ3p28Bs0UE PCTa/t1jBiliFnjDJPH//hwWkISwgJ3E99nvwCaxCKhK3DjwGczmFbCVeLZ6KSvEBnmJ1RsO MINcxAkUv7sqDyQsJGAjce7VerYJjHwLGBlWMUqmFhTnpucWGxYY5aWW6xUn5haX5qXrJefn bmIEB7qW1g7GPas+6B1iZOJgPMQowcGsJMLbX3Q/UYg3JbGyKrUoP76oNCe1+BCjNAeLkjjv ha6T8UIC6YklqdmpqQWpRTBZJg5OqQami53SyQf5Um7WPXL5cu/4RccPL8v/bdpyXXrGD++V O+zuXSovmjFRUYRhZXsxW4T/oTn32O4t/veqyKTsf+xykcVSlw0Ffx9ljOTx+fJOIvQGZ+CD bznbZYt36bzf3yE3XTEpoGXphPeiWy1vPUjTbmDYvDs3/qr0Tpm5z6pyTn3bVhcQx2fNoFfb YXKu4MHv6NvMj5nmHOcOkdxlMS3yztHe5IMnWXIa2XrlKlh+tx5ruvR+57qieQ7aqkxTDgo1 MFy2Em5ddVEgxTKv5vtEKxfxVYwpdwT6k3mdBdpUX1dLORq6bjpfuWEXt/jXb8sFHEK5ns2t mTihZ4Hy5XYG5wP2NQrO9qo5jfobjU4qsRRnJBpqMRcVJwIAhtq/CeMCAAA= X-CMS-MailID: 20220113122408epcas5p45053d1bf0acf2d8233a98b6c1abab6eb X-Msg-Generator: CA CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220113122408epcas5p45053d1bf0acf2d8233a98b6c1abab6eb References: <20220113121143.22280-1-alim.akhtar@samsung.com> Add device tree bindings for the Tesla FSD ARM SoC. Cc: linux-fsd@tesla.com Signed-off-by: Alim Akhtar --- .../devicetree/bindings/arm/tesla.yaml | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/tesla.yaml diff --git a/Documentation/devicetree/bindings/arm/tesla.yaml b/Documentation/devicetree/bindings/arm/tesla.yaml new file mode 100644 index 000000000000..9f89cde76c85 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tesla.yaml @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/tesla.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Tesla Full Self Driving(FSD) platforms device tree bindings + +maintainers: + - Alim Akhtar + - linux-fsd@tesla.com + +properties: + $nodename: + const: '/' + compatible: + oneOf: + + - description: FSD SoC board + items: + - const: tesla,fsd + +additionalProperties: true + +... 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Thu, 13 Jan 2022 21:24:13 +0900 (KST) Received: from Jaguar.sa.corp.samsungelectronics.net (unknown [107.108.73.139]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20220113122409epsmtip26fdb3e9080e0e4a40f8499b36b004fd0~J1ANTP3n01247412474epsmtip2v; Thu, 13 Jan 2022 12:24:09 +0000 (GMT) From: Alim Akhtar To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org List-Id: Cc: soc@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, olof@lixom.net, linus.walleij@linaro.org, catalin.marinas@arm.com, robh+dt@kernel.org, krzysztof.kozlowski@canonical.com, s.nawrocki@samsung.com, linux-samsung-soc@vger.kernel.org, pankaj.dubey@samsung.com, Alim Akhtar , linux-fsd@tesla.com, Arjun K V , Aswani Reddy , Ajay Kumar , Sriranjani P , Chandrasekar R , Shashank Prashar Subject: [PATCH 14/23] arm64: dts: fsd: Add initial device tree support Date: Thu, 13 Jan 2022 17:41:34 +0530 Message-Id: <20220113121143.22280-15-alim.akhtar@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220113121143.22280-1-alim.akhtar@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrNJsWRmVeSWpSXmKPExsWy7bCmlu47yQeJBj+P61gceH+QxeLBvG1s FstX7mKxOLR5K7vF+2U9jBbzj5xjtdj49geTxZQ/y5ksNj2+xmrxseceq8XDV+EWl3fNYbOY cX4fk8Wp65/ZLBZt/cJuMevCDlaL1r1H2C0Ov2lntZi3Yy6jxePrf9gsbr9Zx+og6rFm3hpG j1kNvWwem1Z1snncubaHzWPzknqPKyeaWD36tqxi9PjXNJfd4/MmuQDOqGybjNTElNQihdS8 5PyUzLx0WyXv4HjneFMzA0NdQ0sLcyWFvMTcVFslF58AXbfMHKD3lBTKEnNKgUIBicXFSvp2 NkX5pSWpChn5xSW2SqkFKTkFJgV6xYm5xaV56Xp5qSVWhgYGRqZAhQnZGa8urmcuOHqNseLR tfAGxo1LGbsYOTkkBEwkFkzdwtTFyMUhJLCbUeL94k2MEM4nRokD3/axQzifGSW2b3jDDNNy +/8DNojELkaJNcd2s0I4LUwSk47PBRvMJqAtcXc6yGBODhEBN4kbjR1gNrPAeRaJac3iILaw gLtE06wtrCA2i4CqxM+dk8B6eQVsJZ7enMQCsU1eYvWGA0CbOTg4geJ3V+WB7JIQOMMhsfn1 K6gnXCR6359jh7CFJV4d3wJlS0m87G9jB+mVEMiW6NllDBGukVg67xjUeHuJA1fmsICUMAto SqzfpQ9xJZ9E7+8nTBCdvBIdbUIQ1aoSze+uQnVKS0zs7maFsD0kjt48Bw2FCYwSm3YtYp/A KDsLYeoCRsZVjJKpBcW56anFpgVGeanl8IhKzs/dxAhOtVpeOxgfPvigd4iRiYPxEKMEB7OS CG9/0f1EId6UxMqq1KL8+KLSnNTiQ4ymwBCbyCwlmpwPTPZ5JfGGJpYGJmZmZiaWxmaGSuK8 p9M3JAoJpCeWpGanphakFsH0MXFwSjUwubloMIQ2u8jys1v+9TXJSovnnuI7jX9n/7oP/kab JixhWRkkUZ7ePq1hqVDi+s0PnTiWHGE3rO20u/Ze/exi4eC7xn0q6VUPA/PMymosrjxcpK2c /Nw+1WX//GkaE90stO8pbClzifCb4vf8rEfGn6tXjxhW5tdyXX+wvmPynYnvkiL36tn7bjh4 0dhi8uzt5p+jGI8flIw6z8rkP6O881LEP9XJ4u9j19o635PSPL5b8q69aazMvXn5O9gfKij+ kystZmDcHWH/4OJkhlCe4OyQF1U5T/o3uHwTfP3R4aaobl3InnMpYtFyJYen7Vw8zT/wedbN KTu/s2rlLd/38EqqV9z9+237Vq3f76SrxFKckWioxVxUnAgA/SfUmz4EAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrALMWRmVeSWpSXmKPExsWy7bCSvO5byQeJBm+XyFgceH+QxeLBvG1s FstX7mKxOLR5K7vF+2U9jBbzj5xjtdj49geTxZQ/y5ksNj2+xmrxseceq8XDV+EWl3fNYbOY cX4fk8Wp65/ZLBZt/cJuMevCDlaL1r1H2C0Ov2lntZi3Yy6jxePrf9gsbr9Zx+og6rFm3hpG j1kNvWwem1Z1snncubaHzWPzknqPKyeaWD36tqxi9PjXNJfd4/MmuQDOKC6blNSczLLUIn27 BK6MVxfXMxccvcZY8ehaeAPjxqWMXYycHBICJhK3/z9g62Lk4hAS2MEo8eXQYhaIhLTE9Y0T 2CFsYYmV/56zQxQ1MUls+NUK1s0moC1xd/oWJhBbRMBDou3fPWaQImaBxywSV76+YwZJCAu4 SzTN2sIKYrMIqEr83DkJrJlXwFbi6c1JUNvkJVZvOABUz8HBCRS/uyoPJCwkYCNx7tV6tgmM fAsYGVYxSqYWFOem5xYbFhjlpZbrFSfmFpfmpesl5+duYgRHipbWDsY9qz7oHWJk4mA8xCjB wawkwttfdD9RiDclsbIqtSg/vqg0J7X4EKM0B4uSOO+FrpPxQgLpiSWp2ampBalFMFkmDk6p Bqb16QFxb9t9Mj6wf9twbNZ/1WkPjknum1eYKCIb5diRbfioa6deSz7Lg71n9k+5lca4WCDk wV61nNCKLmGxp4aWglWbdJcxFxZt2DBb4MKBL6arNrz3j7F9mdQt86J28prg1Md+rza7R6o7 Pub9Xa8TLcg7ebnW3Ti2W2dtGg71iR1W2qax9NahtRXXeRXPG93j93xxbk1LofYDm6nePqzX r/LqiYdX3TmUqVJiGnJ5tsx7nfyOZZFTOcIOzd53SPxXzY0lvJanZxtONr/mpbi2pae7ymiB os0CR+F7YTkX/GQ3eTYkBD3KNrjL3BISPO/AotTTb6bG3MniFfyo/L3m9qGMGUoCVT0m8pWu eUosxRmJhlrMRcWJADFUle4DAwAA X-CMS-MailID: 20220113122413epcas5p46cb2cafb73936c423017240f98f72845 X-Msg-Generator: CA CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220113122413epcas5p46cb2cafb73936c423017240f98f72845 References: <20220113121143.22280-1-alim.akhtar@samsung.com> Add initial device tree support for "Full Self-Driving" (FSD) SoC This SoC contain three clusters of four cortex-a72 CPUs and various peripheral IPs. Cc: linux-fsd@tesla.com Signed-off-by: Arjun K V Signed-off-by: Aswani Reddy Signed-off-by: Ajay Kumar Signed-off-by: Sriranjani P Signed-off-by: Chandrasekar R Signed-off-by: Shashank Prashar Signed-off-by: Alim Akhtar Reported-by: kernel test robot --- MAINTAINERS | 8 + arch/arm64/Kconfig.platforms | 6 + arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/tesla/Makefile | 3 + arch/arm64/boot/dts/tesla/fsd.dts | 140 ++++++ arch/arm64/boot/dts/tesla/fsd.dtsi | 715 +++++++++++++++++++++++++++++ 6 files changed, 873 insertions(+) create mode 100644 arch/arm64/boot/dts/tesla/Makefile create mode 100644 arch/arm64/boot/dts/tesla/fsd.dts create mode 100644 arch/arm64/boot/dts/tesla/fsd.dtsi diff --git a/MAINTAINERS b/MAINTAINERS index fb18ce7168aa..02d56909c5e2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2726,6 +2726,14 @@ S: Maintained F: Documentation/devicetree/bindings/media/tegra-cec.txt F: drivers/media/cec/platform/tegra/ +ARM/TESLA FSD SoC SUPPORT +M: Alim Akhtar +M: linux-fsd@tesla.com +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +L: linux-samsung-soc@vger.kernel.org +S: Maintained +F: arch/arm64/boot/dts/tesla* + ARM/TETON BGA MACHINE SUPPORT M: "Mark F. Brown" L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 54e3910e8b9b..bb8a047c2359 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -267,6 +267,12 @@ config ARCH_TEGRA help This enables support for the NVIDIA Tegra SoC family. +config ARCH_TESLA_FSD + bool "ARMv8 based Tesla platform" + select ARCH_EXYNOS + help + Support for ARMv8 based Tesla platforms. + config ARCH_SPRD bool "Spreadtrum SoC platform" help diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index 639e01a4d855..1ba04e31a438 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -27,6 +27,7 @@ subdir-y += rockchip subdir-y += socionext subdir-y += sprd subdir-y += synaptics +subdir-y += tesla subdir-y += ti subdir-y += toshiba subdir-y += xilinx diff --git a/arch/arm64/boot/dts/tesla/Makefile b/arch/arm64/boot/dts/tesla/Makefile new file mode 100644 index 000000000000..a9818cda6b08 --- /dev/null +++ b/arch/arm64/boot/dts/tesla/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_TESLA_FSD) += \ + fsd.dtb diff --git a/arch/arm64/boot/dts/tesla/fsd.dts b/arch/arm64/boot/dts/tesla/fsd.dts new file mode 100644 index 000000000000..e9bbd3284de9 --- /dev/null +++ b/arch/arm64/boot/dts/tesla/fsd.dts @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Tesla FSD board device tree source + * + * Copyright (c) 2017-2021 Samsung Electronics Co., Ltd. + * https://www.samsung.com + * Copyright (c) 2017-2021 Tesla, Inc. + * https://www.tesla.com + */ + +/dts-v1/; +#include "fsd.dtsi" + +/ { + model = "Tesla Full Self-Driving (FSD) SoC"; + compatible = "tesla,fsd"; + + aliases { + serial0 = &serial_0; + serial1 = &serial_1; + }; + + chosen { + stdout-path = &serial_0; + linux,initrd-start = <0xE0000000>; + linux,initrd-end = <0xE4F00000>; + bootargs = "console=ttySAC0,115200n8 + earlycon=exynos4210,0x14180000 root=/dev/ram0 + init=/linuxrc"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x2 0x00000000>; + }; +}; + +&fin_pll { + clock-frequency = <24000000>; +}; + +&serial_0 { + status = "okay"; +}; + +&serial_1 { + status = "okay"; +}; + +&clock_cmu { + status = "okay"; +}; + +&clock_imem { + status = "okay"; +}; + +&clock_peric { + status = "okay"; +}; + +&smmu_isp { + status = "okay"; +}; + +&clock_fsys0 { + status = "okay"; +}; + +&clock_fsys1 { + status = "okay"; +}; + +&smmu_peric { + status = "okay"; +}; + +&smmu_imem { + status = "okay"; +}; + +&smmu_fsys0 { + status = "okay"; +}; + +&hsi2c_0 { + status = "okay"; +}; + +&hsi2c_1 { + status = "okay"; +}; + +&hsi2c_2 { + status = "okay"; +}; + +&hsi2c_3 { + status = "okay"; +}; + +&hsi2c_4 { + status = "okay"; +}; + +&hsi2c_5 { + status = "okay"; +}; + +&hsi2c_6 { + status = "okay"; +}; + +&hsi2c_7 { + status = "okay"; +}; + +&pwm_0 { + status = "okay"; +}; + +&pwm_1 { + status = "okay"; +}; + +&mdma0 { + status = "okay"; +}; + +&mdma1 { + status = "okay"; +}; + +&pdma0 { + status = "okay"; +}; + +&pdma1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi new file mode 100644 index 000000000000..47cd9f20566e --- /dev/null +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi @@ -0,0 +1,715 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Tesla Full Self-Driving SoC device tree source + * + * Copyright (c) 2017-2022 Samsung Electronics Co., Ltd. + * https://www.samsung.com + * Copyright (c) 2017-2022 Tesla, Inc. + * https://www.tesla.com + */ + +#include +#include + +/ { + compatible = "tesla,fsd"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + watchdog0 = &watchdog_0; + watchdog1 = &watchdog_1; + watchdog2 = &watchdog_2; + hsi2c0 = &hsi2c_0; + hsi2c1 = &hsi2c_1; + hsi2c2 = &hsi2c_2; + hsi2c3 = &hsi2c_3; + hsi2c4 = &hsi2c_4; + hsi2c5 = &hsi2c_5; + hsi2c6 = &hsi2c_6; + hsi2c7 = &hsi2c_7; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpucl0_0>; + }; + core1 { + cpu = <&cpucl0_1>; + }; + core2 { + cpu = <&cpucl0_2>; + }; + core3 { + cpu = <&cpucl0_3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpucl1_0>; + }; + core1 { + cpu = <&cpucl1_1>; + }; + core2 { + cpu = <&cpucl1_2>; + }; + core3 { + cpu = <&cpucl1_3>; + }; + }; + + cluster2 { + core0 { + cpu = <&cpucl2_0>; + }; + core1 { + cpu = <&cpucl2_1>; + }; + core2 { + cpu = <&cpucl2_2>; + }; + core3 { + cpu = <&cpucl2_3>; + }; + }; + }; + + /* Cluster 0 */ + cpucl0_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x000>; + enable-method = "psci"; + clock-frequency = <2400000000>; + cpu-idle-states = <&CPU_SLEEP>; + next-level-cache = <&L2_0>; + }; + + cpucl0_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x001>; + enable-method = "psci"; + clock-frequency = <2400000000>; + cpu-idle-states = <&CPU_SLEEP>; + next-level-cache = <&L2_0>; + }; + + cpucl0_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x002>; + enable-method = "psci"; + clock-frequency = <2400000000>; + cpu-idle-states = <&CPU_SLEEP>; + next-level-cache = <&L2_0>; + }; + + cpucl0_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x003>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP>; + next-level-cache = <&L2_0>; + }; + + /* Cluster 1 */ + cpucl1_0: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x100>; + enable-method = "psci"; + clock-frequency = <2400000000>; + cpu-idle-states = <&CPU_SLEEP>; + next-level-cache = <&L2_0>; + }; + + cpucl1_1: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x101>; + enable-method = "psci"; + clock-frequency = <2400000000>; + cpu-idle-states = <&CPU_SLEEP>; + next-level-cache = <&L2_0>; + }; + + cpucl1_2: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x102>; + enable-method = "psci"; + clock-frequency = <2400000000>; + cpu-idle-states = <&CPU_SLEEP>; + next-level-cache = <&L2_0>; + }; + + cpucl1_3: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x103>; + enable-method = "psci"; + clock-frequency = <2400000000>; + cpu-idle-states = <&CPU_SLEEP>; + next-level-cache = <&L2_0>; + }; + + /* Cluster 2 */ + cpucl2_0: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x200>; + enable-method = "psci"; + clock-frequency = <2400000000>; + cpu-idle-states = <&CPU_SLEEP>; + next-level-cache = <&L2_0>; + }; + + cpucl2_1: cpu@201 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x201>; + enable-method = "psci"; + clock-frequency = <2400000000>; + cpu-idle-states = <&CPU_SLEEP>; + next-level-cache = <&L2_0>; + }; + + cpucl2_2: cpu@202 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x202>; + enable-method = "psci"; + clock-frequency = <2400000000>; + cpu-idle-states = <&CPU_SLEEP>; + next-level-cache = <&L2_0>; + }; + + cpucl2_3: cpu@203 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x203>; + enable-method = "psci"; + clock-frequency = <2400000000>; + cpu-idle-states = <&CPU_SLEEP>; + next-level-cache = <&L2_0>; + }; + + idle-states { + entry-method = "arm,psci"; + + CPU_SLEEP: cpu-sleep { + idle-state-name = "c2"; + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <30>; + exit-latency-us = <75>; + min-residency-us = <300>; + status = "okay"; + }; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + arm-pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-affinity = <&cpucl0_0>, <&cpucl0_1>, <&cpucl0_2>, + <&cpucl0_3>, <&cpucl1_0>, <&cpucl1_1>, + <&cpucl1_2>, <&cpucl1_3>, <&cpucl2_0>, + <&cpucl2_1>, <&cpucl2_2>, <&cpucl2_3>; + }; + + psci { + compatible = "arm,psci"; + method = "smc"; + cpu_on = <0xC4000003>; + cpu_suspend = <0xC4000001>; + cpu_off = <0x84000002>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + fin_pll: clock { + compatible = "fixed-clock"; + clock-output-names = "fin_pll"; + #clock-cells = <0>; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0x0 0x0 0x18000000>; + dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>; + + gic: interrupt-controller@10400000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x10400000 0x0 0x10000>, /* GICD */ + <0x0 0x10600000 0x0 0x200000>; /* GICR_RD+GICR_SGI */ + }; + + smmu_isp: iommu@12100000 { + compatible = "arm,mmu-500"; + reg = <0x0 0x12100000 0x0 0x10000>; + #iommu-cells = <2>; + #global-interrupts = <11>; + interrupts = , /* Global secure fault */ + , /* Global non-secure fault */ + , /* Combined secure interrupt */ + , /* Combined non-secure interrupt */ + /* Performance counter interrupts */ + , /* for CAM_CSI */ + , /* for CAM_DP_0 */ + , /* for CAM_DP_1 */ + , /* for CAM_ISP_0 */ + , /* for CAM_ISP_1 */ + , /* for CAM_MFC_0 */ + , /* for CAM_MFC_1 */ + /* Per context non-secure context interrupts, 0-7 interrupts */ + , /* for CONTEXT_0 */ + , /* for CONTEXT_1 */ + , /* for CONTEXT_2 */ + , /* for CONTEXT_3 */ + , /* for CONTEXT_4 */ + , /* for CONTEXT_5 */ + , /* for CONTEXT_6 */ + ; /* for CONTEXT_7 */ + status = "disabled"; + }; + + smmu_imem: iommu@10200000 { + compatible = "arm,mmu-500"; + reg = <0x0 0x10200000 0x0 0x10000>; + #iommu-cells = <2>; + #global-interrupts = <7>; + interrupts = , /* Global secure fault */ + , /* Global non-secure fault */ + , /* Combined secure interrupt */ + , /* Combined non-secure interrupt */ + /* Performance counter interrupts */ + , /* for FSYS1_0 */ + , /* for FSYS1_1 */ + , /* for IMEM_0 */ + /* Per context non-secure context interrupts, 0-3 interrupts */ + , /* for CONTEXT_0 */ + , /* for CONTEXT_1 */ + , /* for CONTEXT_2 */ + ; /* for CONTEXT_3 */ + status = "disabled"; + }; + + smmu_peric: iommu@14900000 { + compatible = "arm,mmu-500"; + reg = <0x0 0x14900000 0x0 0x10000>; + #iommu-cells = <2>; + #global-interrupts = <5>; + interrupts = , /* Global secure fault */ + , /* Global non-secure fault */ + , /* Combined secure interrupt */ + , /* Combined non-secure interrupt */ + /* Performance counter interrupts */ + , /* for PERIC */ + /* Per context non-secure context interrupts, 0-1 interrupts */ + , /* for CONTEXT_0 */ + ; /* for CONTEXT_1 */ + status = "disabled"; + }; + + smmu_fsys0: iommu@15450000 { + compatible = "arm,mmu-500"; + reg = <0x0 0x15450000 0x0 0x10000>; + #iommu-cells = <2>; + #global-interrupts = <5>; + interrupts = , /* Global secure fault */ + , /* Global non-secure fault */ + , /* Combined secure interrupt */ + , /* Combined non-secure interrupt */ + /* Performance counter interrupts */ + , /* for FSYS0 */ + /* Per context non-secure context interrupts, 0-1 interrupts */ + , /* for CONTEXT_0 */ + ; /* for CONTEXT_1 */ + status = "disabled"; + }; + + clock_cmu: clock-controller@11C10000 { + compatible = "tesla,fsd-clock-cmu"; + reg = <0x0 0x11C10000 0x0 0x3000>; + #clock-cells = <1>; + clocks = <&fin_pll>; + clock-names = "fin_pll"; + status = "disabled"; + }; + + clock_imem: clock-controller@10010000 { + compatible = "tesla,fsd-clock-imem"; + reg = <0x0 0x10010000 0x0 0x3000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&clock_cmu DOUT_CMU_IMEM_TCUCLK>, + <&clock_cmu DOUT_CMU_IMEM_ACLK>, + <&clock_cmu DOUT_CMU_IMEM_DMACLK>; + clock-names = "fin_pll", + "dout_cmu_imem_tcuclk", + "dout_cmu_imem_aclk", + "dout_cmu_imem_dmaclk"; + status = "disabled"; + }; + + clock_peric: clock-controller@14010000 { + compatible = "tesla,fsd-clock-peric"; + reg = <0x0 0x14010000 0x0 0x3000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&clock_cmu DOUT_CMU_PLL_SHARED0_DIV4>, + <&clock_cmu DOUT_CMU_PERIC_SHARED1DIV36>, + <&clock_cmu DOUT_CMU_PERIC_SHARED0DIV3_TBUCLK>, + <&clock_cmu DOUT_CMU_PERIC_SHARED0DIV20>, + <&clock_cmu DOUT_CMU_PERIC_SHARED1DIV4_DMACLK>; + clock-names = "fin_pll", + "dout_cmu_pll_shared0_div4", + "dout_cmu_peric_shared1div36", + "dout_cmu_peric_shared0div3_tbuclk", + "dout_cmu_peric_shared0div20", + "dout_cmu_peric_shared1div4_dmaclk"; + status = "disabled"; + }; + + clock_fsys0: clock-controller@15010000 { + compatible = "tesla,fsd-clock-fsys0"; + reg = <0x0 0x15010000 0x0 0x3000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&clock_cmu DOUT_CMU_PLL_SHARED0_DIV6>, + <&clock_cmu DOUT_CMU_FSYS0_SHARED1DIV4>, + <&clock_cmu DOUT_CMU_FSYS0_SHARED0DIV4>; + clock-names = "fin_pll", + "dout_cmu_pll_shared0_div6", + "dout_cmu_fsys0_shared1div4", + "dout_cmu_fsys0_shared0div4"; + status = "disabled"; + }; + + clock_fsys1: clock-controller@16810000 { + compatible = "tesla,fsd-clock-fsys1"; + reg = <0x0 0x16810000 0x0 0x3000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV8>, + <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV4>; + clock-names = "fin_pll", + "dout_cmu_fsys1_shared0div8", + "dout_cmu_fsys1_shared0div4"; + status = "disabled"; + }; + + clock_mfc: clock-controller@12810000 { + compatible = "tesla,fsd-clock-mfc"; + reg = <0x0 0x12810000 0x0 0x3000>; + #clock-cells = <1>; + clocks = <&fin_pll>; + clock-names = "fin_pll"; + status = "disabled"; + }; + + clock_csi: clock-controller@12610000 { + compatible = "tesla,fsd-clock-cam_csi"; + reg = <0x0 0x12610000 0x0 0x3000>; + #clock-cells = <1>; + clocks = <&fin_pll>; + clock-names = "fin_pll"; + status = "disabled"; + }; + + mdma0: mdma@10100000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0x10100000 0x0 0x1000>; + interrupts = ; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + clocks = <&clock_imem IMEM_DMA0_IPCLKPORT_ACLK>; + clock-names = "apb_pclk"; + iommus = <&smmu_imem 0x800 0x0>; + status = "disabled"; + }; + + mdma1: mdma@10110000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0x10110000 0x0 0x1000>; + interrupts = ; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + clocks = <&clock_imem IMEM_DMA1_IPCLKPORT_ACLK>; + clock-names = "apb_pclk"; + iommus = <&smmu_imem 0x801 0x0>; + status = "disabled"; + }; + + pdma0: pdma@14280000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0x14280000 0x0 0x1000>; + interrupts = ; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + clocks = <&clock_peric PERIC_DMA0_IPCLKPORT_ACLK>; + clock-names = "apb_pclk"; + iommus = <&smmu_peric 0x2 0x0>; + status = "disabled"; + }; + + pdma1: pdma@14290000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0x14290000 0x0 0x1000>; + interrupts = ; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + clocks = <&clock_peric PERIC_DMA1_IPCLKPORT_ACLK>; + clock-names = "apb_pclk"; + iommus = <&smmu_peric 0x1 0x0>; + status = "disabled"; + }; + + mct: mct@10040000 { + compatible = "samsung,exynos4210-mct"; + reg = <0x0 0x10040000 0x0 0x800>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&fin_pll>, <&clock_imem IMEM_MCT_PCLK>; + clock-names = "fin_pll", "mct"; + }; + + serial_0: serial@14180000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x0 0x14180000 0x0 0x100>; + interrupts = ; + dmas = <&pdma1 0>, <&pdma1 1>; + dma-names = "tx", "rx"; + clocks = <&clock_peric PERIC_PCLK_UART0>, + <&clock_peric PERIC_SCLK_UART0>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + + serial_1: serial@14190000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x0 0x14190000 0x0 0x100>; + interrupts = ; + dmas = <&pdma1 2>, <&pdma1 3>; + dma-names = "tx", "rx"; + clocks = <&clock_peric PERIC_PCLK_UART1>, + <&clock_peric PERIC_SCLK_UART1>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + + pmu_system_controller: system-controller@11400000 { + compatible = "samsung,exynos7-pmu", "syscon"; + reg = <0x0 0x11400000 0x0 0x5000>; + }; + + watchdog_0: watchdog@100A0000 { + compatible = "samsung,exynos7-wdt"; + reg = <0x0 0x100A0000 0x0 0x100>; + interrupts = ; + samsung,syscon-phandle = <&pmu_system_controller>; + clocks = <&fin_pll>; + clock-names = "watchdog"; + interrupt-mode = <1>; + }; + + watchdog_1: watchdog@100B0000 { + compatible = "samsung,exynos7-wdt"; + reg = <0x0 0x100B0000 0x0 0x100>; + interrupts = ; + samsung,syscon-phandle = <&pmu_system_controller>; + clocks = <&fin_pll>; + clock-names = "watchdog"; + interrupt-mode = <1>; + }; + + watchdog_2: watchdog@100C0000 { + compatible = "samsung,exynos7-wdt"; + reg = <0x0 0x100C0000 0x0 0x100>; + interrupts = ; + samsung,syscon-phandle = <&pmu_system_controller>; + clocks = <&fin_pll>; + clock-names = "watchdog"; + interrupt-mode = <1>; + }; + + pwm_0: pwm@14100000 { + compatible = "samsung,exynos4210-pwm"; + reg = <0x0 0x14100000 0x0 0x100>; + samsung,pwm-outputs = <0>, <1>, <2>, <3>; + #pwm-cells = <3>; + clocks = <&clock_peric PERIC_PWM0_IPCLKPORT_I_PCLK_S0>; + clock-names = "timers"; + status = "disabled"; + }; + + pwm_1: pwm@14110000 { + compatible = "samsung,exynos4210-pwm"; + reg = <0x0 0x14110000 0x0 0x100>; + samsung,pwm-outputs = <0>, <1>, <2>, <3>; + #pwm-cells = <3>; + clocks = <&clock_peric PERIC_PWM1_IPCLKPORT_I_PCLK_S0>; + clock-names = "timers"; + status = "disabled"; + }; + + hsi2c_0: hsi2c@14200000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x0 0x14200000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c0_bus>; + clocks = <&clock_peric PERIC_PCLK_HSI2C0>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_1: hsi2c@14210000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x0 0x14210000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c1_bus>; + clocks = <&clock_peric PERIC_PCLK_HSI2C1>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_2: hsi2c@14220000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x0 0x14220000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c2_bus>; + clocks = <&clock_peric PERIC_PCLK_HSI2C2>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_3: hsi2c@14230000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x0 0x14230000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c3_bus>; + clocks = <&clock_peric PERIC_PCLK_HSI2C3>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_4: hsi2c@14240000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x0 0x14240000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c4_bus>; + clocks = <&clock_peric PERIC_PCLK_HSI2C4>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_5: hsi2c@14250000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x0 0x14250000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c5_bus>; + clocks = <&clock_peric PERIC_PCLK_HSI2C5>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_6: hsi2c@14260000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x0 0x14260000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c6_bus>; + clocks = <&clock_peric PERIC_PCLK_HSI2C6>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_7: hsi2c@14270000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x0 0x14270000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c7_bus>; + clocks = <&clock_peric PERIC_PCLK_HSI2C7>; + clock-names = "hsi2c"; + status = "disabled"; + }; + }; +}; From patchwork Thu Jan 13 12:11:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alim Akhtar X-Patchwork-Id: 12712667 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CAF95C433FE for ; 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Thu, 13 Jan 2022 12:24:17 +0000 (GMT) Received: from epsmgms1p2.samsung.com (unknown [182.195.42.42]) by epsmtrp1.samsung.com (KnoxPortal) with ESMTP id 20220113122417epsmtrp1a0423814f8cb642f851514c078a4cefa~J1AUhkW8B1991219912epsmtrp1a; Thu, 13 Jan 2022 12:24:17 +0000 (GMT) X-AuditID: b6c32a49-b01ff70000001917-e7-61e019f14ae9 Received: from epsmtip2.samsung.com ( [182.195.34.31]) by epsmgms1p2.samsung.com (Symantec Messaging Gateway) with SMTP id 9C.A9.08738.1F910E16; Thu, 13 Jan 2022 21:24:17 +0900 (KST) Received: from Jaguar.sa.corp.samsungelectronics.net (unknown [107.108.73.139]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20220113122415epsmtip2cffd8df2dc31d7f828fa7c97d630def9~J1ASNhc1-1245412454epsmtip2d; Thu, 13 Jan 2022 12:24:15 +0000 (GMT) From: Alim Akhtar To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org List-Id: Cc: soc@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, olof@lixom.net, linus.walleij@linaro.org, catalin.marinas@arm.com, robh+dt@kernel.org, krzysztof.kozlowski@canonical.com, s.nawrocki@samsung.com, linux-samsung-soc@vger.kernel.org, pankaj.dubey@samsung.com, Alim Akhtar , linux-fsd@tesla.com, Shashank Prashar , Aswani Reddy Subject: [PATCH 15/23] arm64: dts: fsd: Add initial pinctrl support Date: Thu, 13 Jan 2022 17:41:35 +0530 Message-Id: <20220113121143.22280-16-alim.akhtar@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220113121143.22280-1-alim.akhtar@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprKJsWRmVeSWpSXmKPExsWy7bCmhu5HyQeJBg/2qlg8mLeNzeLQ5q3s Fu+X9TBazD9yjtVi49sfTBZT/ixnstj0+Bqrxceee6wWD1+FW1zeNYfNYsb5fUwWp65/ZrNY tPULu0Xr3iPsFofftLNazNsxl9Hi8fU/bA6CHmvmrWH0mNXQy+axaVUnm8eda3vYPDYvqfe4 cqKJ1aNvyypGj39Nc9k9Pm+SC+CMyrbJSE1MSS1SSM1Lzk/JzEu3VfIOjneONzUzMNQ1tLQw V1LIS8xNtVVy8QnQdcvMAXpFSaEsMacUKBSQWFyspG9nU5RfWpKqkJFfXGKrlFqQklNgUqBX nJhbXJqXrpeXWmJlaGBgZApUmJCd0Xj1AXPBd+eKa1sOsDUwTjTrYuTgkBAwkVjzO6mLkYtD SGA3o8SJX9MZIZxPjBIzVi+Ccj4zSrz/exnI4QTr6J+1lRUisYtR4vm3m2wQTguTxLauW+wg VWwC2hJ3p29hArFFBNwkbjR2MIEUMQtsZpaYt3w1WEJYwFni8qNbjCCHsAioSpzq5QcJ8wrY SvxsXcQGsU1eYvWGA8wgJZxA8bur8kDGSAhs4ZBYsHEvK0SNi8TeHwug6oUlXh3fwg5hS0m8 7G9jh/gzW6JnlzFEuEZi6bxjLBC2vcSBK3NYQEqYBTQl1u/SBwkzC/BJ9P5+wgTRySvR0SYE Ua0q0fzuKlSntMTE7m6oAzwk7q69ygwJhQmMEhu7dzFNYJSdhTB1ASPjKkbJ1ILi3PTUYtMC w7zUcng0JefnbmIEp08tzx2Mdx980DvEyMTBeIhRgoNZSYS3v+h+ohBvSmJlVWpRfnxRaU5q 8SFGU2CATWSWEk3OBybwvJJ4QxNLAxMzMzMTS2MzQyVx3tPpGxKFBNITS1KzU1MLUotg+pg4 OKUamBrFYtZ4113um2bwKXBN+HLvSaoaN/R4jHLYBT4b7Nk1mdGh/MrHGQU+WXPmtnTM/lBX YORwN8dv75KpR19ZVxbZB5iKHVhe7F5/j5n7YaH1iaVfg95uXmMgM79D95Sq8Aszkdg4hrSi G/bLJBqS/j/JflSwleHTOrdVx978CHeui+692Fl97EqQ+E2B/pwSlmzPpBYOsSvy585fNohb YqzNa8O1nfOqp/dzXrNN3iv85ojOeS0Q4PCnteCyRtjWbUyObafsLhlNL7tz0C5C+Hvblo3z Gj8VMik1110+9TJv1RKhRXsevLrZZ/l1+mXxV8YvLvb+Mv0ncvvDqWWTNy3YI8kq5x6yo8WB v6SuRomlOCPRUIu5qDgRALkWb6AoBAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrFLMWRmVeSWpSXmKPExsWy7bCSvO5HyQeJBr0TOC0ezNvGZnFo81Z2 i/fLehgt5h85x2qx8e0PJospf5YzWWx6fI3V4mPPPVaLh6/CLS7vmsNmMeP8PiaLU9c/s1ks 2vqF3aJ17xF2i8Nv2lkt5u2Yy2jx+PofNgdBjzXz1jB6zGroZfPYtKqTzePOtT1sHpuX1Htc OdHE6tG3ZRWjx7+muewenzfJBXBGcdmkpOZklqUW6dslcGU0Xn3AXPDdueLalgNsDYwTzboY OTkkBEwk+mdtZe1i5OIQEtjBKLG37zkjREJa4vrGCewQtrDEyn/P2SGKmpgk1i+5zgaSYBPQ lrg7fQsTiC0i4CHR9u8eM0gRs8BhZolXz7azgCSEBZwlLj+6BTSVg4NFQFXiVC8/SJhXwFbi Z+siNogF8hKrNxxgBinhBIrfXZUHEhYSsJE492o92wRGvgWMDKsYJVMLinPTc4sNC4zyUsv1 ihNzi0vz0vWS83M3MYKDX0trB+OeVR/0DjEycTAeYpTgYFYS4e0vup8oxJuSWFmVWpQfX1Sa k1p8iFGag0VJnPdC18l4IYH0xJLU7NTUgtQimCwTB6dUA1OqaZNs9v83x6c9+9lwr/D5iyl8 GyfHngpc6SGmJnmIxVJJ9UK2r9flqjMKb3YuvpD/7cVXsSUdtrZ6j44on5+wxE9Op2Ut15Gv Jd1fIldV7bjb/4s55+NSvbb7zNIpjbMX/03zjnr5calgv49PyM1Ku7dMYna1Jjobz0y+8+Ru Vt2iqbptukaPDZvNarLCb7G+7nmqekf4Sp3N7dPP4hd65z96y/CR+ZPoPvYTgTktN518def+ jorIt79wt1HY4ezKduuDyeaWPKqTPu2d8LTgnXzMPrk5ZYsE52j0LA+PPu1eam6g2qPAtkcp J++xB/OU6fYlRdaNvw5HKtl+2ZNov+Pf4WtuaiX9Fw3spyuxFGckGmoxFxUnAgByxDjH7QIA AA== X-CMS-MailID: 20220113122417epcas5p47398a5190cdf4c574c6f1762918b549f X-Msg-Generator: CA CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220113122417epcas5p47398a5190cdf4c574c6f1762918b549f References: <20220113121143.22280-1-alim.akhtar@samsung.com> Add initial pin configuration nodes for FSD SoC. Cc: linux-fsd@tesla.com Signed-off-by: Shashank Prashar Signed-off-by: Aswani Reddy Signed-off-by: Alim Akhtar --- arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi | 338 +++++++++++++++++++++ arch/arm64/boot/dts/tesla/fsd.dtsi | 22 ++ 2 files changed, 360 insertions(+) create mode 100644 arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi diff --git a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi new file mode 100644 index 000000000000..ec8d944af636 --- /dev/null +++ b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi @@ -0,0 +1,338 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Tesla Full Self-Driving SoC device tree source + * + * Copyright (c) 2017-2021 Samsung Electronics Co., Ltd. + * https://www.samsung.com + * Copyright (c) 2017-2021 Tesla, Inc. + * https://www.tesla.com + */ + +#include + +&pinctrl_fsys0 { + + gpf0: gpf0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf1: gpf1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf6: gpf6 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf4: gpf4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf5: gpf5 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +&pinctrl_peric { + + gpc8: gpc8 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf2: gpf2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf3: gpf3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd0: gpd0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb0: gpb0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb1: gpb1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb4: gpb4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb5: gpb5 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb6: gpb6 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb7: gpb7 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd1: gpd1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd2: gpd2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd3: gpd3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg0: gpg0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg1: gpg1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg2: gpg2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg3: gpg3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg4: gpg4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg5: gpg5 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg6: gpg6 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg7: gpg7 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + pwm0_out: pwm0-out { + samsung,pins = "gpb6-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pwm1_out: pwm1-out { + samsung,pins = "gpb6-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + hs_i2c0_bus: hs-i2c0-bus { + samsung,pins = "gpb0-0", "gpb0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + hs_i2c1_bus: hs-i2c1-bus { + samsung,pins = "gpb0-2", "gpb0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + hs_i2c2_bus: hs-i2c2-bus { + samsung,pins = "gpb0-4", "gpb0-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + hs_i2c3_bus: hs-i2c3-bus { + samsung,pins = "gpb0-6", "gpb0-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + hs_i2c4_bus: hs-i2c4-bus { + samsung,pins = "gpb1-0", "gpb1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + hs_i2c5_bus: hs-i2c5-bus { + samsung,pins = "gpb1-2", "gpb1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + hs_i2c6_bus: hs-i2c6-bus { + samsung,pins = "gpb1-4", "gpb1-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + hs_i2c7_bus: hs-i2c7-bus { + samsung,pins = "gpb1-6", "gpb1-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart0_data: uart0-data { + samsung,pins = "gpb7-0", "gpb7-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart1_data: uart1-data { + samsung,pins = "gpb7-4", "gpb7-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spi0_bus: spi0-bus { + samsung,pins = "gpb4-0", "gpb4-2", "gpb4-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spi1_bus: spi1-bus { + samsung,pins = "gpb4-4", "gpb4-6", "gpb4-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spi2_bus: spi2-bus { + samsung,pins = "gpb5-0", "gpb5-2", "gpb5-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pinctrl_pmu { + + gpq0: gpq0 { + gpio-controller; + #gpio-cells = <2>; + }; +}; diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi index 47cd9f20566e..811186e5ba4d 100644 --- a/arch/arm64/boot/dts/tesla/fsd.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi @@ -29,6 +29,9 @@ hsi2c5 = &hsi2c_5; hsi2c6 = &hsi2c_6; hsi2c7 = &hsi2c_7; + pinctrl0 = &pinctrl_fsys0; + pinctrl1 = &pinctrl_peric; + pinctrl2 = &pinctrl_pmu; }; cpus { @@ -711,5 +714,24 @@ clock-names = "hsi2c"; status = "disabled"; }; + + pinctrl_fsys0: pinctrl@15020000 { + compatible = "tesla,fsd-pinctrl"; + reg = <0x0 0x15020000 0x0 0x1000>; + interrupts = ; + }; + + pinctrl_peric: pinctrl@141F0000 { + compatible = "tesla,fsd-pinctrl"; + reg = <0x0 0x141F0000 0x0 0x1000>; + interrupts = ; + }; + + pinctrl_pmu: pinctrl@114F0000 { + compatible = "tesla,fsd-pinctrl"; + reg = <0x0 0x114F0000 0x0 0x1000>; + }; }; }; + +#include "fsd-pinctrl.dtsi" From patchwork Thu Jan 13 12:11:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alim Akhtar X-Patchwork-Id: 12712668 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BC4C3C433EF for ; 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Thu, 13 Jan 2022 12:24:21 +0000 (GMT) Received: from epsmgms1p1new.samsung.com (unknown [182.195.42.41]) by epsmtrp2.samsung.com (KnoxPortal) with ESMTP id 20220113122421epsmtrp2d8416854b3c94f9977137b0a9eae6fe3~J1AYT0LNo3204332043epsmtrp2h; Thu, 13 Jan 2022 12:24:21 +0000 (GMT) X-AuditID: b6c32a49-b13ff70000001917-f0-61e019f57512 Received: from epsmtip2.samsung.com ( [182.195.34.31]) by epsmgms1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id A8.A8.29871.5F910E16; Thu, 13 Jan 2022 21:24:21 +0900 (KST) Received: from Jaguar.sa.corp.samsungelectronics.net (unknown [107.108.73.139]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20220113122418epsmtip237d5a08bd1757eacdb1745b38bfe60ea~J1AVpsE2L1246812468epsmtip2C; Thu, 13 Jan 2022 12:24:18 +0000 (GMT) From: Alim Akhtar To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org List-Id: Cc: soc@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, olof@lixom.net, linus.walleij@linaro.org, catalin.marinas@arm.com, robh+dt@kernel.org, krzysztof.kozlowski@canonical.com, s.nawrocki@samsung.com, linux-samsung-soc@vger.kernel.org, pankaj.dubey@samsung.com, Alim Akhtar , linux-fsd@tesla.com Subject: [PATCH 16/23] arm64: defconfig: Enable Tesla FSD SoC Date: Thu, 13 Jan 2022 17:41:36 +0530 Message-Id: <20220113121143.22280-17-alim.akhtar@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220113121143.22280-1-alim.akhtar@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFuphk+LIzCtJLcpLzFFi42LZdlhTU/eb5INEg1v3mSwezNvGZvF+WQ+j xfwj51gtNr79wWQx5c9yJotNj6+xWnzsucdq8fBVuMXlXXPYLGac38dkcer6ZzaLRVu/sFu0 7j3CbnH4TTurxePrf9gc+D3WzFvD6DGroZfNY9OqTjaPO9f2sHlsXlLvceVEE6tH35ZVjB7/ muaye3zeJBfAGZVtk5GamJJapJCal5yfkpmXbqvkHRzvHG9qZmCoa2hpYa6kkJeYm2qr5OIT oOuWmQP0gJJCWWJOKVAoILG4WEnfzqYov7QkVSEjv7jEVim1ICWnwKRArzgxt7g0L10vL7XE ytDAwMgUqDAhO2NS40Gmgp8sFc2tG1kbGBezdDFyckgImEh8vDiftYuRi0NIYDejxPknP1kg nE+MEtNm3oDKfGOUOD75MHMXIwdYy4mNHhDxvYwSO/c3skM4LUwSu25PYAWZyyagLXF3+hYm EFtEwE3iRmMHE0gRs8A9JokfhxuYQRLCArYSZ78/A7NZBFQl1l6/DdbACxJ/8QPqQHmJ1RsO gG3mBIrfXZUHMkdCYC6HxNlD71ghalwklix8yAZhC0u8Or6FHcKWkvj8bi8bxNXZEj27jCHC NRJL5x2DGm8vceDKHBaQEmYBTYn1u/RBwswCfBK9v58wQXTySnS0CUFUq0o0v7sK1SktMbG7 G+oAD4nVPbugYTWBUeLLv93sExhlZyFMXcDIuIpRMrWgODc9tdi0wDAvtRweT8n5uZsYwclS y3MH490HH/QOMTJxMB5ilOBgVhLh7S+6nyjEm5JYWZValB9fVJqTWnyI0RQYYhOZpUST84Hp Oq8k3tDE0sDEzMzMxNLYzFBJnPd0+oZEIYH0xJLU7NTUgtQimD4mDk6pBia1C+62Vh98zos5 ue8/vF/h97NVZzIkX7trzBaXORicPePx7BeK37q2Fz9e/lxR4ITTApZkprp5Uzp/e+tM+vXe 8pv7m36LLT0J2bWHGiMjS5mnJR7Qb5x+0/n1zMsur+acv/3Ig9lBq9v+6v01vcc8VLvL1rtw TX90+oB1lFX6ir/XW3ce9+LRXrvo8kU+8Yh45mcnrJijg5UfxaR4H0iRfseteMeej2+z1uLS Zs5ba8t8QjbpZl/cZt7HXubtua9DfmLv7HKRibscTfjXPTrN282gw7208EX9Fs0Hradm76xW U/PeO+HbPc8W9XubYnTWVF/968Us+b2/V/KRi4yJc5cu69yHaTZ75jpdL1ViKc5INNRiLipO BAAIPbMQHwQAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrPLMWRmVeSWpSXmKPExsWy7bCSvO5XyQeJBs27hSwezNvGZvF+WQ+j xfwj51gtNr79wWQx5c9yJotNj6+xWnzsucdq8fBVuMXlXXPYLGac38dkcer6ZzaLRVu/sFu0 7j3CbnH4TTurxePrf9gc+D3WzFvD6DGroZfNY9OqTjaPO9f2sHlsXlLvceVEE6tH35ZVjB7/ muaye3zeJBfAGcVlk5Kak1mWWqRvl8CVManxIFPBT5aK5taNrA2Mi1m6GDk4JARMJE5s9Ohi 5OQQEtjNKDHtlx2ILSEgLXF94wR2CFtYYuW/50A2F1BNE5NEx5JOZpAEm4C2xN3pW5hAbBEB D4m2f/eYQYqYBd4wSfy/P4cFJCEsYCtx9vszsAYWAVWJtddvgzXwgsRf/GCB2CAvsXrDAWaQ gziB4ndX5UEcZCNx7tV6tgmMfAsYGVYxSqYWFOem5xYbFhjmpZbrFSfmFpfmpesl5+duYgSH uZbmDsbtqz7oHWJk4mA8xCjBwawkwttfdD9RiDclsbIqtSg/vqg0J7X4EKM0B4uSOO+FrpPx QgLpiSWp2ampBalFMFkmDk6pBqb1gpuKO9dmttwK07hdpBcm9bbX5qW73Z6TAaLpqbOfP5hT VXGyjfHK/+3Jv27ETLvz6NiKmS5ffmucuTF90UKuNZUqivWJTL57BS+uyM3S8877Ffvt43n7 DQVPtVkvHckXvbbnTeSSff81QsXe3DKqWKn5Yz7jjQqmG9J1Rn4v5EJ2fLohYjrtGIdyq9Xd UvH6/l12k7wmcIo+T5uwM7Cocf6BOTlqZf8eln87ueLCFrZmI10NQfPiv/UKH57U69sFhAst Z3FkjUkw2+b/7Kb4t/DZiXO3x578cu5pw9Qm/8nXH4mdEj69Mr575fW1ld8F7N7bNWhFXfyQ 6hKU+kvEvn2n3V/NsPL4wKapDceVWIozEg21mIuKEwEtTqaB4gIAAA== X-CMS-MailID: 20220113122421epcas5p1af8422fc992801ced57e0439b48ad08e X-Msg-Generator: CA CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220113122421epcas5p1af8422fc992801ced57e0439b48ad08e References: <20220113121143.22280-1-alim.akhtar@samsung.com> This patch enables the Tesla FSD SoC in arm64 defconfig. Cc: linux-fsd@tesla.com Signed-off-by: Alim Akhtar --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index f2e2b9bdd702..6e6f26eb54ab 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -54,6 +54,7 @@ CONFIG_ARCH_SEATTLE=y CONFIG_ARCH_INTEL_SOCFPGA=y CONFIG_ARCH_SYNQUACER=y CONFIG_ARCH_TEGRA=y +CONFIG_ARCH_TESLA_FSD=y CONFIG_ARCH_SPRD=y CONFIG_ARCH_THUNDER=y CONFIG_ARCH_THUNDER2=y From patchwork Thu Jan 13 12:11:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alim Akhtar X-Patchwork-Id: 12712669 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 25F30C433F5 for ; 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Thu, 13 Jan 2022 12:24:27 +0000 (GMT) Received: from epsmgms1p1new.samsung.com (unknown [182.195.42.41]) by epsmtrp2.samsung.com (KnoxPortal) with ESMTP id 20220113122427epsmtrp28e9526019818269cd8fdff94c051f120~J1AeFReUR3235332353epsmtrp2T; Thu, 13 Jan 2022 12:24:27 +0000 (GMT) X-AuditID: b6c32a49-b01ff70000001917-fd-61e019fb900d Received: from epsmtip2.samsung.com ( [182.195.34.31]) by epsmgms1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id FA.A8.29871.BF910E16; Thu, 13 Jan 2022 21:24:27 +0900 (KST) Received: from Jaguar.sa.corp.samsungelectronics.net (unknown [107.108.73.139]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20220113122423epsmtip298768b2223b43fd5d57cfa740a145cdc~J1AaOHOXy1245212452epsmtip2z; Thu, 13 Jan 2022 12:24:23 +0000 (GMT) From: Alim Akhtar To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org List-Id: Cc: soc@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, olof@lixom.net, linus.walleij@linaro.org, catalin.marinas@arm.com, robh+dt@kernel.org, krzysztof.kozlowski@canonical.com, s.nawrocki@samsung.com, linux-samsung-soc@vger.kernel.org, pankaj.dubey@samsung.com, Alim Akhtar , linux-fsd@tesla.com, Adithya K V Subject: [PATCH 17/23] Documentation: bindings: Add fsd spi compatible in dt-bindings document Date: Thu, 13 Jan 2022 17:41:37 +0530 Message-Id: <20220113121143.22280-18-alim.akhtar@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220113121143.22280-1-alim.akhtar@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprAJsWRmVeSWpSXmKPExsWy7bCmpu5vyQeJBlu2G1scmPCK1eLBvG1s Fu+X9TBazD9yjtVi49sfTBZT/ixnstj0+Bqrxceee6wWD1+FW1zeNYfNYsb5fUwWp65/ZrNY tPULu0Xr3iPsFofftLNaPL7+h81BwGPNvDWMHrMaetk8Nq3qZPO4c20Pm8fmJfUeV040sXr0 bVnF6PGvaS67x+dNcgGcUdk2GamJKalFCql5yfkpmXnptkrewfHO8aZmBoa6hpYW5koKeYm5 qbZKLj4Bum6ZOUBfKCmUJeaUAoUCEouLlfTtbIryS0tSFTLyi0tslVILUnIKTAr0ihNzi0vz 0vXyUkusDA0MjEyBChOyMzqOzWEpWMRR8WbTSaYGxg72LkZODgkBE4kp7/aygdhCArsZJdqb HCHsT4wSrX8juhi5gOxvjBK/Xp5mhGlYtr2XFSKxl1Fi19ytTBBOC5PE3bPHwarYBLQl7k7f wgRiiwi4Sdxo7AArYhZoYZaYfHQmM0hCWCBB4s/8W2A2i4CqxOGtv8Fu4hWwlXj/qYUNYp28 xOoNB4BqODg4geJ3V+WBzJEQWMohsfTzSxaIGheJSxNXQ9ULS7w6vgXqNymJz2C/cQDZ2RI9 u4whwjUSS+cdg2q1lzhwZQ4LSAmzgKbE+l36IGFmAT6J3t9PmCA6eSU62oQgqlUlmt9dheqU lpjY3c0KYXtInFvwhRkSDBMYJb423GWewCg7C2HqAkbGVYySqQXFuempxaYFhnmp5fBoSs7P 3cQITppanjsY7z74oHeIkYmD8RCjBAezkghvf9H9RCHelMTKqtSi/Pii0pzU4kOMpsAQm8gs JZqcD0zbeSXxhiaWBiZmZmYmlsZmhkrivKfTNyQKCaQnlqRmp6YWpBbB9DFxcEo1MAXEvQo8 OdnQ4YoFz/eTFZNSp/J93bFIWufKx56CtJa1WjtKmB7lcdcvnSqbnKug557qvfAY33Pmkypd 73nOR6lwbOxUNmX+eFvvx9Sns6ffyxWavpxBPYLBu7y4QvOmZBTDhN9GistLsjTTirWVaz2O Lg/oMpn0WzWi2CYzcKrZ7Ld7ys8sk0r7M7MoYqKIsQrTcvbjQWq2bJ03u29Nc0iUf1r+mc/b keeyun5rqufKjvrpFgxmcg5cHfUdX+QXbXV34pR3+1m296tS6R7hxTeY/5g7Mi/MORgyXeFy x/M0Tq0z8zqqkufX7e9MeczEEeZ6s2vRXqag1rxs7xcP4wwWWG/IkYtzce5ctkCJpTgj0VCL uag4EQBaNLr6IwQAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrGLMWRmVeSWpSXmKPExsWy7bCSvO5vyQeJBk1vpS0OTHjFavFg3jY2 i/fLehgt5h85x2qx8e0PJospf5YzWWx6fI3V4mPPPVaLh6/CLS7vmsNmMeP8PiaLU9c/s1ks 2vqF3aJ17xF2i8Nv2lktHl//w+Yg4LFm3hpGj1kNvWwem1Z1snncubaHzWPzknqPKyeaWD36 tqxi9PjXNJfd4/MmuQDOKC6blNSczLLUIn27BK6MjmNzWAoWcVS82XSSqYGxg72LkZNDQsBE Ytn2XtYuRi4OIYHdjBLnpl1lg0hIS1zfOAGqSFhi5b/n7BBFTUwS975fZwZJsAloS9ydvoUJ xBYR8JBo+3ePGaSIWWAKs8Tm/9/BioQF4iTa721lBbFZBFQlDm/9DTaVV8BW4v2nFqht8hKr NxwAqufg4ASK312VBxIWErCROPdqPdsERr4FjAyrGCVTC4pz03OLDQsM81LL9YoTc4tL89L1 kvNzNzGCg15Lcwfj9lUf9A4xMnEwHmKU4GBWEuHtL7qfKMSbklhZlVqUH19UmpNafIhRmoNF SZz3QtfJeCGB9MSS1OzU1ILUIpgsEwenVAPTamkt24+mjidzgiYzzUxbL3E87uYtxY/SPNdP PVLbaXplvkTNPTPuB/9C7C8VP39YeET0y/JZJWmhdy+/XnDCsz1K//SN7OOylsxfU3le9qZ5 X9l0iK0oqXHZ0Qs50xOUd+ayMDbtN3+baqvivMyA0ebvhI15HLvV1h57xul4iOuG4RQ9We4v vTHXapYUnnv8is/3v2XDdsdHxfs+iqx1P+p62mVPLPsJf/ufpzTCek9zHo2d03ewqlesY46Y 6dHdq7bHVVyYuy5XZMozsZa7uSISehJFX17uUmjT99RiLv4yN5J1WdXujGO7xCL05+34+tap YJbRkpXzDjdMrEwsVgnSfVDI9bNO4vbj7aH7lViKMxINtZiLihMBUYWKCOkCAAA= X-CMS-MailID: 20220113122427epcas5p1885d8b3b735e8f127b6694a309796e5a X-Msg-Generator: CA CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220113122427epcas5p1885d8b3b735e8f127b6694a309796e5a References: <20220113121143.22280-1-alim.akhtar@samsung.com> This patch adds spi controller dt-binding compatible information for Tesla Full Self-Driving SoC. Cc: linux-fsd@tesla.com Signed-off-by: Adithya K V Signed-off-by: Alim Akhtar --- Documentation/devicetree/bindings/spi/spi-samsung.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/spi/spi-samsung.txt b/Documentation/devicetree/bindings/spi/spi-samsung.txt index 49028a4f5df1..3af2408454b4 100644 --- a/Documentation/devicetree/bindings/spi/spi-samsung.txt +++ b/Documentation/devicetree/bindings/spi/spi-samsung.txt @@ -11,6 +11,7 @@ Required SoC Specific Properties: - samsung,s5pv210-spi: for s5pv210 and s5pc110 platforms - samsung,exynos5433-spi: for exynos5433 compatible controllers - samsung,exynos7-spi: for exynos7 platforms + - tesla,fsd-spi: spi controller support for Tesla Full Self-Driving SoC - reg: physical base address of the controller and length of memory mapped region. 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Thu, 13 Jan 2022 21:24:35 +0900 (KST) Received: from Jaguar.sa.corp.samsungelectronics.net (unknown [107.108.73.139]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20220113122432epsmtip2b951016c0b47fc016c330f3f43374ced~J1AiHp_WF1131511315epsmtip2O; Thu, 13 Jan 2022 12:24:32 +0000 (GMT) From: Alim Akhtar To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org List-Id: Cc: soc@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, olof@lixom.net, linus.walleij@linaro.org, catalin.marinas@arm.com, robh+dt@kernel.org, krzysztof.kozlowski@canonical.com, s.nawrocki@samsung.com, linux-samsung-soc@vger.kernel.org, pankaj.dubey@samsung.com, Alim Akhtar , linux-fsd@tesla.com, broonie@kernel.org, linux-spi@vger.kernel.org, Aswani Reddy Subject: [PATCH 18/23] spi: s3c64xx: Add spi port configuration for Tesla FSD SoC Date: Thu, 13 Jan 2022 17:41:38 +0530 Message-Id: <20220113121143.22280-19-alim.akhtar@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220113121143.22280-1-alim.akhtar@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprFJsWRmVeSWpSXmKPExsWy7bCmli6z1INEg12fDSwezNvGZnFo81Z2 i6kPn7BZvF/Ww2gx/8g5VouNb38wWUz5s5zJYtPja6wWH3vusVo8fBVucXnXHDaLGef3MVk0 frzJbnHq+mc2i0Vbv7BbtO49wm5x+E07q8Xj63/YHIQ81sxbw+gxq6GXzWPTqk42jzvX9rB5 bF5S73HlRBOrR9+WVYwe/5rmsnt83iQXwBmVbZORmpiSWqSQmpecn5KZl26r5B0c7xxvamZg qGtoaWGupJCXmJtqq+TiE6DrlpkD9I+SQlliTilQKCCxuFhJ386mKL+0JFUhI7+4xFYptSAl p8CkQK84Mbe4NC9dLy+1xMrQwMDIFKgwITvj1M9NLAXzuStOTzvL1sC4mbOLkZNDQsBE4lBb FwuILSSwm1Gi4U1EFyMXkP2JUWLLpz9MEM43RomPT24xwnTc//uSHSKxl1Fi4onTzBBOC5PE /z/3wKrYBLQl7k7fwgRiiwi4Sdxo7AAbxSywg1ni5PUlbCAJYYFgiUNbT4EVsQioSsz6uwPM 5hWwlZhyt4UJYp28xOoNB4A2cHBwAsXvrsoDmSMhsIVD4tqtJ2wgcQkBF4l//50hyoUlXh3f wg5hS0m87G9jhyjJlujZZQwRrpFYOu8YC4RtL3HgyhwWkBJmAU2J9bv0QcLMAnwSvb+fMEF0 8kp0tAlBVKtKNL+7CtUpLTGxu5sVwvaQmPDsMQskFCYwSmz/f5x1AqPsLISpCxgZVzFKphYU 56anFpsWGOellsOjKTk/dxMjOJFqee9gfPTgg94hRiYOxkOMEhzMSiK8/UX3E4V4UxIrq1KL 8uOLSnNSiw8xmgIDbCKzlGhyPjCV55XEG5pYGpiYmZmZWBqbGSqJ855K35AoJJCeWJKanZpa kFoE08fEwSnVwCT5rYTh2LeWQzFnlynOUXgtNSf1eBKffOrq+kc18jbz97+01X+jevrBqXVt NqK/luR/UzF4WKfJdTImdePEiMZJGuttGgtrdusFPNi54mtSvqhVQ/O/L8w5p5e8WxnW++Ng OsP+VTqpd2SnbbiyKZi92blq/f6gc1OuHmp+PG/r3gbLT7Wft/5s3evZadfTKhMx333nk+dx M7fonZeW0PnYdGfC4xeCj6MkY4y7FVosp16KNKxdyXamo1ZNutrP8LZKV+fdj3x1ksIOU7f6 yrwMalLr++ji05X42Sr1yIeYqXwGn9s9zPrX13coy0StZ/T6mfko2NrUUdxUUnYui4ToZJYz nyuNFtc3NElvVmIpzkg01GIuKk4EAGhpTdAtBAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrALMWRmVeSWpSXmKPExsWy7bCSvC6z1INEg39/BCwezNvGZnFo81Z2 i6kPn7BZvF/Ww2gx/8g5VouNb38wWUz5s5zJYtPja6wWH3vusVo8fBVucXnXHDaLGef3MVk0 frzJbnHq+mc2i0Vbv7BbtO49wm5x+E07q8Xj63/YHIQ81sxbw+gxq6GXzWPTqk42jzvX9rB5 bF5S73HlRBOrR9+WVYwe/5rmsnt83iQXwBnFZZOSmpNZllqkb5fAlXHq5yaWgvncFaennWVr YNzM2cXIySEhYCJx/+9L9i5GLg4hgd2MElfPb2SFSEhLXN84gR3CFpZY+e85VFETk8SLlS1g CTYBbYm707cwgdgiAh4Sbf/uMYMUMQucYpZ43dsAViQsECix49k9sKksAqoSs/7uAGvgFbCV mHK3hQlig7zE6g0HgJo5ODiB4ndX5YGEhQRsJM69Ws82gZFvASPDKkbJ1ILi3PTcYsMCw7zU cr3ixNzi0rx0veT83E2M4EjQ0tzBuH3VB71DjEwcjIcYJTiYlUR4+4vuJwrxpiRWVqUW5ccX leakFh9ilOZgURLnvdB1Ml5IID2xJDU7NbUgtQgmy8TBKdXAtCixjOPV2+lOFV1NfzZN2rDW kpWPaeETiXa/LtePN1cYpyW/WyFwRs5DmDNGOaH5bcBFATmJcD/+jxK/MmQj782sWMHfkrb3 kz+DdEi3YDMT7y3RYPk8tUU+H5UCNIz2882b+PvHC1leCa9vHmE3IpgbvnHcXybb0/DyJfNB 8WZB1+Pf7jvaOgYUVVzN8ZxstX6ruERbk9fpD+pxFS+kp7/Qm/Qh4NYLEwO9o14CLSl5Lu2R ttdaOk/l3WpLXq+17rt78JQJ3S9CpHa4nnzzM/zNT2vPWo8DxVtXsq69zhv65xavgmhfuPTC z22Z341kldRP8DEEhPry3ssQkFo+J2KSc37qurzyT96L/yixFGckGmoxFxUnAgDiIswg8wIA AA== X-CMS-MailID: 20220113122435epcas5p18e6a2699f193b9e1287588278a570235 X-Msg-Generator: CA CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220113122435epcas5p18e6a2699f193b9e1287588278a570235 References: <20220113121143.22280-1-alim.akhtar@samsung.com> This patch adds compatible and port configuration for spi controller for Tesla Full Self-Driving SoC. Cc: linux-fsd@tesla.com Cc: broonie@kernel.org Cc: linux-spi@vger.kernel.org Signed-off-by: Aswani Reddy Signed-off-by: Alim Akhtar --- drivers/spi/spi-s3c64xx.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 8755cd85e83c..8d0c1f03ab7a 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -1442,6 +1442,16 @@ static const struct s3c64xx_spi_port_config exynos5433_spi_port_config = { .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, }; +static struct s3c64xx_spi_port_config fsd_spi_port_config = { + .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f, 0x7f, 0x7f}, + .rx_lvl_offset = 15, + .tx_st_done = 25, + .high_speed = true, + .clk_from_cmu = true, + .clk_ioclk = false, + .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, +}; + static const struct platform_device_id s3c64xx_spi_driver_ids[] = { { .name = "s3c2443-spi", @@ -1472,6 +1482,9 @@ static const struct of_device_id s3c64xx_spi_dt_match[] = { { .compatible = "samsung,exynos5433-spi", .data = (void *)&exynos5433_spi_port_config, }, + { .compatible = "tesla,fsd-spi", + .data = (void *)&fsd_spi_port_config, + }, { }, }; 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Thu, 13 Jan 2022 21:24:39 +0900 (KST) Received: from Jaguar.sa.corp.samsungelectronics.net (unknown [107.108.73.139]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20220113122437epsmtip233b09db131f4887133c69a08e6707f52~J1AmkAnhh1245812458epsmtip2u; Thu, 13 Jan 2022 12:24:36 +0000 (GMT) From: Alim Akhtar To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org List-Id: Cc: soc@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, olof@lixom.net, linus.walleij@linaro.org, catalin.marinas@arm.com, robh+dt@kernel.org, krzysztof.kozlowski@canonical.com, s.nawrocki@samsung.com, linux-samsung-soc@vger.kernel.org, pankaj.dubey@samsung.com, Aswani Reddy , linux-fsd@tesla.com, Alim Akhtar Subject: [PATCH 19/23] arm64: dts: fsd: Add SPI device nodes Date: Thu, 13 Jan 2022 17:41:39 +0530 Message-Id: <20220113121143.22280-20-alim.akhtar@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220113121143.22280-1-alim.akhtar@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprIJsWRmVeSWpSXmKPExsWy7bCmui6H1INEg/89IhYP5m1jszi0eSu7 xftlPYwW84+cY7XY+PYHk8WUP8uZLDY9vsZq8bHnHqvFw1fhFpd3zWGzmHF+H5PFqeuf2SwW bf3CbtG69wi7xeE37awWj6//YXMQ8Fgzbw2jx6yGXjaPTas62TzuXNvD5rF5Sb3HlRNNrB59 W1Yxevxrmsvu8XmTXABnVLZNRmpiSmqRQmpecn5KZl66rZJ3cLxzvKmZgaGuoaWFuZJCXmJu qq2Si0+ArltmDtAXSgpliTmlQKGAxOJiJX07m6L80pJUhYz84hJbpdSClJwCkwK94sTc4tK8 dL281BIrQwMDI1OgwoTsjDdP1jIWbBGvWHnsLUsD4w6hLkZODgkBE4mpp2aydTFycQgJ7GaU 2LHrNCOE84lRYs+6newQzjdGiWuLV7LCtJx/9YIVIrGXUeLPvWVQVS1MEme7FoNVsQloS9yd voUJxBYRcJO40djBBFLELNDOLHFnwl6whLCAjUTHnwawBhYBVYnG+x/B4rwCthK9P78wQayT l1i94QBzFyMHBydQ/O6qPJA5EgILOSTeHe2FqnGROHmjhxnCFpZ4dXwLO4QtJfH53V42kF4J gWyJnl3GEOEaiaXzjrFA2PYSB67MYQEpYRbQlFi/Sx8kzCzAJ9H7+wkTRCevREcbNLhUJZrf XYXqlJaY2N3NClHiIXFkgxQkFCYwSuz8toxxAqPsLIShCxgZVzFKphYU56anFpsWGOellsPj KTk/dxMjOG1qee9gfPTgg94hRiYOxkOMEhzMSiK8/UX3E4V4UxIrq1KL8uOLSnNSiw8xmgID bCKzlGhyPjBx55XEG5pYGpiYmZmZWBqbGSqJ855K35AoJJCeWJKanZpakFoE08fEwSnVwFTS sW/jlB89P5oO9a6LmV/imBEyQ8on3Ddm20u+uj7G155zrgWzZ76912Nyhveo6j7xQ/PbPJc0 p/lNumq8SedF9SPHiLxHr+wn7a1abzl3ed3m3LNS6mmJbK5MpjUFkz7kvev10VT58fw0s/np jLNbk31b+m5/zXcyXKbaMfFD8X2F6O29b28ti17usX33W8vcexf2B+SdX2F3kmvi1KRM2VOd wbJd7VtunCqVfWPtEX0nlKW51lzQU8cjTm/CyWd5Dw5t9v/hOufPLLPXiedmbzjwa/7H8Ce/ +VN9w819Om9rCdy59vXnMreDV4RVL3DHHFP8fW3GAr+rWx68P1zEvuuInGrRxep/U99vrTZR YinOSDTUYi4qTgQAReeKIyQEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrKLMWRmVeSWpSXmKPExsWy7bCSvC671INEgx0LLS0ezNvGZnFo81Z2 i/fLehgt5h85x2qx8e0PJospf5YzWWx6fI3V4mPPPVaLh6/CLS7vmsNmMeP8PiaLU9c/s1ks 2vqF3aJ17xF2i8Nv2lktHl//w+Yg4LFm3hpGj1kNvWwem1Z1snncubaHzWPzknqPKyeaWD36 tqxi9PjXNJfd4/MmuQDOKC6blNSczLLUIn27BK6MN0/WMhZsEa9YeewtSwPjDqEuRk4OCQET ifOvXrB2MXJxCAnsZpT4vvcqE0RCWuL6xgnsELawxMp/z8FsIYEmJompy0RBbDYBbYm707eA 1YsIeEi0/bvHDDKIWWA6s8SBbd9YQBLCAjYSHX8aWEFsFgFVicb7H8EaeAVsJXp/foFaJi+x esMBoGYODk6g+N1VeRC7bCTOvVrPNoGRbwEjwypGydSC4tz03GLDAsO81HK94sTc4tK8dL3k /NxNjOCQ19Lcwbh91Qe9Q4xMHIyHGCU4mJVEePuL7icK8aYkVlalFuXHF5XmpBYfYpTmYFES 573QdTJeSCA9sSQ1OzW1ILUIJsvEwSnVwCT56IqDMo+hRunVtjV9b8qUArY48bxv2vKtc36w a+DJhpfK795fqQhn1Hr4PTPm/My5T+//1dH1bjOqmv2qK+mr2dZ/m1hq+lxX5Uc8af3uHSXC 1iK1NLx4dbf576lJlvz73TunJz/08Koru3yoLeRMwLpPTYVHsi/0FfVmNcvzsHtvNbPVCfr/ 69aVkrTdR0+ZP9h4Sla0L2D73c65NSEODGWPzCKSL7AYLAu8prv55ZpboYzSL+sV/aqmT8rK fmw/uX9nv/jllaoGyp5SPssudZw7ua1Aj417zZ4Pvbmb/vfd6BNezhtYlVL9114jf1nzssdf b6SuNs2N/zUtl1/qVUzxvk7vaMO+t1lBSizFGYmGWsxFxYkA49qwZ+gCAAA= X-CMS-MailID: 20220113122440epcas5p4651d7cb2fc6d6a70fd5eaab5eadcf996 X-Msg-Generator: CA CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220113122440epcas5p4651d7cb2fc6d6a70fd5eaab5eadcf996 References: <20220113121143.22280-1-alim.akhtar@samsung.com> From: Aswani Reddy This patch add device tree node for SPI IPs and needed GPIO pin configurations needed for SPI IP Cc: linux-fsd@tesla.com Signed-off-by: Aswani Reddy Signed-off-by: Alim Akhtar Reviewed-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/tesla/fsd.dts | 12 +++++++ arch/arm64/boot/dts/tesla/fsd.dtsi | 57 ++++++++++++++++++++++++++++++ 2 files changed, 69 insertions(+) diff --git a/arch/arm64/boot/dts/tesla/fsd.dts b/arch/arm64/boot/dts/tesla/fsd.dts index e9bbd3284de9..7f3bb6212e50 100644 --- a/arch/arm64/boot/dts/tesla/fsd.dts +++ b/arch/arm64/boot/dts/tesla/fsd.dts @@ -138,3 +138,15 @@ &pdma1 { status = "okay"; }; + +&spi_0 { + status = "okay"; +}; + +&spi_1 { + status = "okay"; +}; + +&spi_2 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi index 811186e5ba4d..7e687c6f74f6 100644 --- a/arch/arm64/boot/dts/tesla/fsd.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi @@ -32,6 +32,9 @@ pinctrl0 = &pinctrl_fsys0; pinctrl1 = &pinctrl_peric; pinctrl2 = &pinctrl_pmu; + spi0 = &spi_0; + spi1 = &spi_1; + spi2 = &spi_2; }; cpus { @@ -731,6 +734,60 @@ compatible = "tesla,fsd-pinctrl"; reg = <0x0 0x114F0000 0x0 0x1000>; }; + + spi_0: spi@14140000 { + compatible = "tesla,fsd-spi"; + reg = <0x0 0x14140000 0x0 0x100>; + interrupts = ; + dmas = <&pdma1 4>, <&pdma1 5>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock_peric PERIC_PCLK_SPI0>, + <&clock_peric PERIC_SCLK_SPI0>; + clock-names = "spi", "spi_busclk0"; + samsung,spi-src-clk = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_bus>; + num-cs = <1>; + status = "disabled"; + }; + + spi_1: spi@14150000 { + compatible = "tesla,fsd-spi"; + reg = <0x0 0x14150000 0x0 0x100>; + interrupts = ; + dmas = <&pdma1 6>, <&pdma1 7>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock_peric PERIC_PCLK_SPI1>, + <&clock_peric PERIC_SCLK_SPI1>; + clock-names = "spi", "spi_busclk0"; + samsung,spi-src-clk = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_bus>; + num-cs = <1>; + status = "disabled"; + }; + + spi_2: spi@14160000 { + compatible = "tesla,fsd-spi"; + reg = <0x0 0x14160000 0x0 0x100>; + interrupts = ; + dmas = <&pdma1 8>, <&pdma1 9>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock_peric PERIC_PCLK_SPI2>, + <&clock_peric PERIC_SCLK_SPI2>; + clock-names = "spi", "spi_busclk0"; + samsung,spi-src-clk = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_bus>; + num-cs = <1>; + status = "disabled"; + }; }; }; From patchwork Thu Jan 13 12:11:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alim Akhtar X-Patchwork-Id: 12712672 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 54E4EC433F5 for ; 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Thu, 13 Jan 2022 12:24:47 +0000 (GMT) Received: from epsmgms1p1new.samsung.com (unknown [182.195.42.41]) by epsmtrp1.samsung.com (KnoxPortal) with ESMTP id 20220113122447epsmtrp1e2680c4d350b073e6192b8fe5c44d809~J1AwVjv3y1991219912epsmtrp1y; Thu, 13 Jan 2022 12:24:47 +0000 (GMT) X-AuditID: b6c32a4a-de5ff7000000b6e6-d7-61e01a10e44a Received: from epsmtip2.samsung.com ( [182.195.34.31]) by epsmgms1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id 9F.A8.29871.F0A10E16; Thu, 13 Jan 2022 21:24:47 +0900 (KST) Received: from Jaguar.sa.corp.samsungelectronics.net (unknown [107.108.73.139]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20220113122443epsmtip2015c63604999f1c4f8f68a32b71e32a0~J1AtBdtnA1246412464epsmtip2r; Thu, 13 Jan 2022 12:24:43 +0000 (GMT) From: Alim Akhtar To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org List-Id: Cc: soc@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, olof@lixom.net, linus.walleij@linaro.org, catalin.marinas@arm.com, robh+dt@kernel.org, krzysztof.kozlowski@canonical.com, s.nawrocki@samsung.com, linux-samsung-soc@vger.kernel.org, pankaj.dubey@samsung.com, Alim Akhtar , linux-fsd@tesla.com, Tamseel Shams Subject: [PATCH 20/23] dt-bindings: iio: adc: exynos-adc: Add ADC-V3 variant Date: Thu, 13 Jan 2022 17:41:40 +0530 Message-Id: <20220113121143.22280-21-alim.akhtar@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220113121143.22280-1-alim.akhtar@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprEJsWRmVeSWpSXmKPExsWy7bCmlq6A1INEg7PbOSwezNvGZvF+WQ+j xfwj51gtNr79wWQx5c9yJotNj6+xWnzsucdq8fBVuMXlXXPYLGac38dkcbd1MbvFqeuf2SwW bf3CbtG69wi7xeE37awWj6//YXMQ8Fgzbw2jx6yGXjaPTas62TzuXNvD5rF5Sb3HlRNNrB59 W1Yxevxrmsvu8XmTXABnVLZNRmpiSmqRQmpecn5KZl66rZJ3cLxzvKmZgaGuoaWFuZJCXmJu qq2Si0+ArltmDtAXSgpliTmlQKGAxOJiJX07m6L80pJUhYz84hJbpdSClJwCkwK94sTc4tK8 dL281BIrQwMDI1OgwoTsjB13t7EXnGWveP9jHXMD41S2LkZODgkBE4lJf5cC2VwcQgK7GSU+ z2qCcj4xSvx9MpcVwvnGKLHwxwsmmJb1T7YzQiT2Mkos/vCVBcJpYZLoe7mEGaSKTUBb4u70 LWAdIgJuEjcaO5hAipgFmpkl5k08yAKSEBbwkXgycTVYA4uAqsS0/9fBGngFbCUWLXrCDLFO XmL1hgNANgcHJ1D87qo8kDkSAis5JF6eaGWFqHGRmL73BQuELSzx6vgWdghbSuJlfxs7SK+E QLZEzy5jiHCNxNJ5x6DK7SUOXJnDAlLCLKApsX6XPkiYWYBPovf3EyaITl6JjjYhiGpVieZ3 V6E6pSUmdndDHeAhMW/3MWjITQCG3JEDrBMYZWchTF3AyLiKUTK1oDg3PbXYtMAoL7UcHlHJ +bmbGMGJU8trB+PDBx/0DjEycTAeYpTgYFYS4e0vup8oxJuSWFmVWpQfX1Sak1p8iNEUGGIT maVEk/OBqTuvJN7QxNLAxMzMzMTS2MxQSZz3dPqGRCGB9MSS1OzU1ILUIpg+Jg5OqQYmreeJ 8y7wTUqWfXzdzuXJqwVPZZ4VNdg6Tkhm/X7S+FzrtDAdnZT/svwHZheIWq02OWiZbRYz4/Ln RbdTfnJM1IvYovx9dz5/8Z9Z1ZZb8icfEXmeaCAYvy6B2WKm+Lyru5gudwY2PdjxMGgFb2Pv 9WuiLvN/RD6/r/nqf8HELTc/ytQ4e/IFLr7aJsX84mlztbhlUNsf16nxfMWcbxwNt21iqv69 M1HN80neZz2Ogi9nHhyt0Z/Q7rRy8opLR8VsbTOOl9yYne2nWef3z56Fd5Zm1k3Zx6FfJjqL /PnCyXvUmdE3jyN3wdabZwKj71xf+bBg/ayHd1M+bPkfEXh/6YXjMSd5T79emPDZrdr8phJL cUaioRZzUXEiALdp1rolBAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrGLMWRmVeSWpSXmKPExsWy7bCSvC6/1INEg54fHBYP5m1js3i/rIfR Yv6Rc6wWG9/+YLKY8mc5k8Wmx9dYLT723GO1ePgq3OLyrjlsFjPO72OyuNu6mN3i1PXPbBaL tn5ht2jde4Td4vCbdlaLx9f/sDkIeKyZt4bRY1ZDL5vHplWdbB53ru1h89i8pN7jyokmVo++ LasYPf41zWX3+LxJLoAzissmJTUnsyy1SN8ugStjx91t7AVn2Sve/1jH3MA4la2LkZNDQsBE Yv2T7YxdjFwcQgK7GSUentzECJGQlri+cQI7hC0ssfLfc3aIoiYmif+PvoIVsQloS9ydvoUJ xBYR8JBo+3ePGaSIWWAys8T0F7NZQRLCAj4STyauZgaxWQRUJab9vw7WwCtgK7Fo0RNmiA3y Eqs3HACyOTg4geJ3V+WBhIUEbCTOvVrPNoGRbwEjwypGydSC4tz03GLDAsO81HK94sTc4tK8 dL3k/NxNjOCg19Lcwbh91Qe9Q4xMHIyHGCU4mJVEePuL7icK8aYkVlalFuXHF5XmpBYfYpTm YFES573QdTJeSCA9sSQ1OzW1ILUIJsvEwSnVwHRGxf13nV3ah6RZTWIFXPPMj/fxySy/ysPz 6uZ25+TXa3tq3B3jXy53Ta71fXXGUTpAV+t52QWtF41b7211tJJv0qhudL9d0fcprFryQLNU RnXpBx7xNzOuz7QsN7s785Scp6rn6gM+WrHyXr+UD55dO1n09qLTIkdsfJ60TzRZOTVq9vWb K+q2XzKYzdDjPXex/MTdZv1ndYT7rZ5H2jxlVn/3UMPo6dS7s+fP816kxtciyZ/3/bx02VEt wx2qHzuF3nMvafrBM3nOioOvr3X6ft+tcfNxc5goa9GeK5P2JBU+e5qkElZisOslT/PP8Cd8 RZIvV3ockS7lFTzgJ1O86RfvhCOz7606sej8ngolluKMREMt5qLiRAAj1Nio6QIAAA== X-CMS-MailID: 20220113122447epcas5p266d44c8df143229d22dfa700c285a786 X-Msg-Generator: CA CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220113122447epcas5p266d44c8df143229d22dfa700c285a786 References: <20220113121143.22280-1-alim.akhtar@samsung.com> This patch adds a new compatible string for exynos's ADC-V3 variant. Cc: linux-fsd@tesla.com Signed-off-by: Tamseel Shams Signed-off-by: Alim Akhtar --- .../devicetree/bindings/iio/adc/samsung,exynos-adc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml b/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml index 81c87295912c..9303053759ca 100644 --- a/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml @@ -14,6 +14,7 @@ properties: enum: - samsung,exynos-adc-v1 # Exynos5250 - samsung,exynos-adc-v2 + - samsung,exynos-adc-v3 - samsung,exynos3250-adc - samsung,exynos4212-adc # Exynos4212 and Exynos4412 - samsung,exynos7-adc From patchwork Thu Jan 13 12:11:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alim Akhtar X-Patchwork-Id: 12712673 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7B870C433F5 for ; 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Thu, 13 Jan 2022 12:24:52 +0000 (GMT) Received: from epsmgms1p1new.samsung.com (unknown [182.195.42.41]) by epsmtrp1.samsung.com (KnoxPortal) with ESMTP id 20220113122452epsmtrp14ba050598d95dfded2ba253dd5b92c3d~J1A0i4RdX2009320093epsmtrp1B; Thu, 13 Jan 2022 12:24:52 +0000 (GMT) X-AuditID: b6c32a49-b13ff70000001917-2a-61e01a14cb84 Received: from epsmtip2.samsung.com ( [182.195.34.31]) by epsmgms1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id E0.B8.29871.31A10E16; Thu, 13 Jan 2022 21:24:51 +0900 (KST) Received: from Jaguar.sa.corp.samsungelectronics.net (unknown [107.108.73.139]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20220113122448epsmtip25b5a0b0f3b13357571a8679d99b5e964~J1AxdzOLs1247412474epsmtip21; Thu, 13 Jan 2022 12:24:48 +0000 (GMT) From: Alim Akhtar To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org List-Id: Cc: soc@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, olof@lixom.net, linus.walleij@linaro.org, catalin.marinas@arm.com, robh+dt@kernel.org, krzysztof.kozlowski@canonical.com, s.nawrocki@samsung.com, linux-samsung-soc@vger.kernel.org, pankaj.dubey@samsung.com, Alim Akhtar , linux-fsd@tesla.com, jic23@kernel.org, linux-iio@vger.kernel.org, Tamseel Shams Subject: [PATCH 21/23] iio: adc: exynos-adc: Add support for ADC V3 controller Date: Thu, 13 Jan 2022 17:41:41 +0530 Message-Id: <20220113121143.22280-22-alim.akhtar@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220113121143.22280-1-alim.akhtar@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprBJsWRmVeSWpSXmKPExsWy7bCmpq6I1INEg9+vRCwezNvGZvF+WQ+j xfwj51gtHjStYrLY+PYHk8WUP8uZLDY9vsZq8bHnHqvFw1fhFvOOvGOxuLxrDpvFjPP7mCzu ti5mtzh1/TObxaKtX9gtWvceYbc4/Kad1eLx9T9sDkIea+atYfSY1dDL5rFpVSebx51re9g8 Ni+p97hyoonVo2/LKkaPf01z2T0+b5IL4IzKtslITUxJLVJIzUvOT8nMS7dV8g6Od443NTMw 1DW0tDBXUshLzE21VXLxCdB1y8wB+kdJoSwxpxQoFJBYXKykb2dTlF9akqqQkV9cYquUWpCS U2BSoFecmFtcmpeul5daYmVoYGBkClSYkJ1xb+0D5oJzyhWzX/A3MF6U7WLk5JAQMJHYMucx O4gtJLCbUeL/H4MuRi4g+xOjxK2H19ggEt8YJdbt1oBrWLGXCaJoL6PE1+V9UE4Lk8T6M+8Y QarYBLQl7k7fwgRiiwi4Sdxo7AArYhbYxCwx7ewdsH3CAgESk1b8ZQWxWQRUJX6vbAdr4BWw lTg69xU7xDp5idUbDjB3MXJwcALF767KA5kjIbCFQ+L25LdMEDUuEhtbexghbGGJV8e3QPVK Sbzsb2MH6ZUQyJbo2WUMEa6RWDrvGAuEbS9x4MocFpASZgFNifW79EHCzAJ8Er2/nzBBdPJK dLQJQVSrSjS/uwrVKS0xsbubFaLEQ6Lvky8kFCYwSpw+eZJtAqPsLIShCxgZVzFKphYU56an FpsWGOallsMjKTk/dxMjOIlqee5gvPvgg94hRiYOxkOMEhzMSiK8/UX3E4V4UxIrq1KL8uOL SnNSiw8xmgIDbCKzlGhyPjCN55XEG5pYGpiYmZmZWBqbGSqJ855O35AoJJCeWJKanZpakFoE 08fEwSnVwGS9QGTH1kULFgv2BR37LZ4j/+f7uT7R08+rjWzyZ1klb3u/7ajexS2Hiw0Xcjyz UDsUX6SY9TVIeSu/2gzFUmP3uj/HHf7suL+Jk13n/JtPBjGfz50JW8+3JiTcJnWj5fwFDimy ghfvsud6+kQcua1tsburKsNTc7X9vbfduhazmPfdPXDHdFWXW2pweK6G/7dvz7/N2/jexc3I tFcj+vXhS2tyn/qFasTWb21//X53VaDuqcO3zKIk6padum3k9ODhfUMeuafJHK2hb/ZekN7p oyTdpvUnxVLkedHPr/EPl373lZjjuPlkjfYl/aZnl7nXWidlv7Pa/1Ip4eNOy6RTv3Iqnfg/ Hw/4u/vvDx4lluKMREMt5qLiRABlDZCuKwQAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrPLMWRmVeSWpSXmKPExsWy7bCSvK6w1INEg98bVSwezNvGZvF+WQ+j xfwj51gtHjStYrLY+PYHk8WUP8uZLDY9vsZq8bHnHqvFw1fhFvOOvGOxuLxrDpvFjPP7mCzu ti5mtzh1/TObxaKtX9gtWvceYbc4/Kad1eLx9T9sDkIea+atYfSY1dDL5rFpVSebx51re9g8 Ni+p97hyoonVo2/LKkaPf01z2T0+b5IL4IzisklJzcksSy3St0vgyri39gFzwTnlitkv+BsY L8p2MXJySAiYSGxZsZepi5GLQ0hgN6PEwjNvWSES0hLXN05gh7CFJVb+e84OUdTEJHHm+nkm kASbgLbE3elbwGwRAQ+Jtn/3mEGKmAWOMEtsP3mSBSQhLOAnMfHvNbAiFgFVid8r28FsXgFb iaNzX0FtkJdYveEAUDMHBydQ/O6qPJCwkICNxLlX69kmMPItYGRYxSiZWlCcm55bbFhgmJda rlecmFtcmpeul5yfu4kRHAdamjsYt6/6oHeIkYmD8RCjBAezkghvf9H9RCHelMTKqtSi/Pii 0pzU4kOM0hwsSuK8F7pOxgsJpCeWpGanphakFsFkmTg4pRqYGgTburXyTgQy8/+YZPEkxsTl ULKDenRV0fyb07hT/XgmZ3tL/pozPeEJ38lMgcnv3K5eXub/Zu/269uSQ48ZKNW3SxiIefg6 rljirDj5PN+/tjc26r+tPrJZLHvmtudCi3e3feFqI34bv8l2/VKcNzyKl4mmBkxb+L2K79z/ yel7+lZr7zqQ88LaoPnG0uJ16tdeHP+X8XZu9QrRFddqFecU3vNyFyvvj/44ZXqNteKENad2 T1cL+/D7vEUxZ4X7qs1aN+2r1nu3Rt3YN9X13C+n1GdtV5OMNz1s09wya/fEP19cVlm/nLet xtDD79FB58R9kbsjP5zvCqma3ZcXzl+p3+/T/DOEX1BsQn+eEktxRqKhFnNRcSIAEBg6fvIC AAA= X-CMS-MailID: 20220113122452epcas5p201a3a87d0e9c0e9f449a90ed62de1f1c X-Msg-Generator: CA CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220113122452epcas5p201a3a87d0e9c0e9f449a90ed62de1f1c References: <20220113121143.22280-1-alim.akhtar@samsung.com> Exynos's ADC-V3 has some difference in registers set, number of programmable channels (16 channel) etc. This patch adds support for ADC-V3 controller version. Cc: linux-fsd@tesla.com Cc: jic23@kernel.org Cc: linux-iio@vger.kernel.org Signed-off-by: Tamseel Shams Signed-off-by: Alim Akhtar --- drivers/iio/adc/exynos_adc.c | 74 +++++++++++++++++++++++++++++++++++- 1 file changed, 72 insertions(+), 2 deletions(-) diff --git a/drivers/iio/adc/exynos_adc.c b/drivers/iio/adc/exynos_adc.c index 3b3868aa2533..61752e798fd6 100644 --- a/drivers/iio/adc/exynos_adc.c +++ b/drivers/iio/adc/exynos_adc.c @@ -55,6 +55,11 @@ #define ADC_V2_INT_ST(x) ((x) + 0x14) #define ADC_V2_VER(x) ((x) + 0x20) +/* ADC_V3 register definitions */ +#define ADC_V3_DAT(x) ((x) + 0x08) +#define ADC_V3_DAT_SUM(x) ((x) + 0x0C) +#define ADC_V3_DBG_DATA(x) ((x) + 0x1C) + /* Bit definitions for ADC_V1 */ #define ADC_V1_CON_RES (1u << 16) #define ADC_V1_CON_PRSCEN (1u << 14) @@ -92,6 +97,7 @@ /* Bit definitions for ADC_V2 */ #define ADC_V2_CON1_SOFT_RESET (1u << 2) +#define ADC_V2_CON1_SOFT_NON_RESET (1u << 1) #define ADC_V2_CON2_OSEL (1u << 10) #define ADC_V2_CON2_ESEL (1u << 9) @@ -100,6 +106,7 @@ #define ADC_V2_CON2_ACH_SEL(x) (((x) & 0xF) << 0) #define ADC_V2_CON2_ACH_MASK 0xF +#define MAX_ADC_V3_CHANNELS 16 #define MAX_ADC_V2_CHANNELS 10 #define MAX_ADC_V1_CHANNELS 8 #define MAX_EXYNOS3250_ADC_CHANNELS 2 @@ -164,6 +171,7 @@ struct exynos_adc_data { void (*exit_hw)(struct exynos_adc *info); void (*clear_irq)(struct exynos_adc *info); void (*start_conv)(struct exynos_adc *info, unsigned long addr); + irqreturn_t (*adc_isr)(int irq, void *dev_id); }; static void exynos_adc_unprepare_clk(struct exynos_adc *info) @@ -484,6 +492,59 @@ static const struct exynos_adc_data exynos7_adc_data = { .start_conv = exynos_adc_v2_start_conv, }; +static void exynos_adc_v3_init_hw(struct exynos_adc *info) +{ + u32 con2; + + writel(ADC_V2_CON1_SOFT_RESET, ADC_V2_CON1(info->regs)); + + writel(ADC_V2_CON1_SOFT_NON_RESET, ADC_V2_CON1(info->regs)); + + con2 = ADC_V2_CON2_C_TIME(6); + writel(con2, ADC_V2_CON2(info->regs)); + + /* Enable interrupts */ + writel(1, ADC_V2_INT_EN(info->regs)); +} + +static void exynos_adc_v3_exit_hw(struct exynos_adc *info) +{ + u32 con2; + + con2 = readl(ADC_V2_CON2(info->regs)); + con2 &= ~ADC_V2_CON2_C_TIME(7); + writel(con2, ADC_V2_CON2(info->regs)); + + /* Disable interrupts */ + writel(0, ADC_V2_INT_EN(info->regs)); +} + +static irqreturn_t exynos_adc_v3_isr(int irq, void *dev_id) +{ + struct exynos_adc *info = (struct exynos_adc *)dev_id; + u32 mask = info->data->mask; + + info->value = readl(ADC_V3_DAT(info->regs)) & mask; + + if (info->data->clear_irq) + info->data->clear_irq(info); + + complete(&info->completion); + + return IRQ_HANDLED; +} + +static const struct exynos_adc_data exynos_adc_v3_adc_data = { + .num_channels = MAX_ADC_V3_CHANNELS, + .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */ + + .init_hw = exynos_adc_v3_init_hw, + .exit_hw = exynos_adc_v3_exit_hw, + .clear_irq = exynos_adc_v2_clear_irq, + .start_conv = exynos_adc_v2_start_conv, + .adc_isr = exynos_adc_v3_isr, +}; + static const struct of_device_id exynos_adc_match[] = { { .compatible = "samsung,s3c2410-adc", @@ -518,6 +579,9 @@ static const struct of_device_id exynos_adc_match[] = { }, { .compatible = "samsung,exynos7-adc", .data = &exynos7_adc_data, + }, { + .compatible = "samsung,exynos-adc-v3", + .data = &exynos_adc_v3_adc_data, }, {}, }; @@ -719,6 +783,12 @@ static const struct iio_chan_spec exynos_adc_iio_channels[] = { ADC_CHANNEL(7, "adc7"), ADC_CHANNEL(8, "adc8"), ADC_CHANNEL(9, "adc9"), + ADC_CHANNEL(10, "adc10"), + ADC_CHANNEL(11, "adc11"), + ADC_CHANNEL(12, "adc12"), + ADC_CHANNEL(13, "adc13"), + ADC_CHANNEL(14, "adc14"), + ADC_CHANNEL(15, "adc15"), }; static int exynos_adc_remove_devices(struct device *dev, void *c) @@ -885,8 +955,8 @@ static int exynos_adc_probe(struct platform_device *pdev) mutex_init(&info->lock); - ret = request_irq(info->irq, exynos_adc_isr, - 0, dev_name(&pdev->dev), info); + ret = request_irq(info->irq, info->data->adc_isr ? info->data->adc_isr : + exynos_adc_isr, 0, dev_name(&pdev->dev), info); if (ret < 0) { dev_err(&pdev->dev, "failed requesting irq, irq = %d\n", info->irq); From patchwork Thu Jan 13 12:11:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alim Akhtar X-Patchwork-Id: 12712674 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C2642C433F5 for ; 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Thu, 13 Jan 2022 12:24:56 +0000 (GMT) Received: from epsmgms1p2.samsung.com (unknown [182.195.42.42]) by epsmtrp1.samsung.com (KnoxPortal) with ESMTP id 20220113122456epsmtrp1e4a57807c0189ba6a67b00291a54298a~J1A4vpfXE2009320093epsmtrp1D; Thu, 13 Jan 2022 12:24:56 +0000 (GMT) X-AuditID: b6c32a49-b01ff70000001917-35-61e01a189812 Received: from epsmtip2.samsung.com ( [182.195.34.31]) by epsmgms1p2.samsung.com (Symantec Messaging Gateway) with SMTP id 93.B9.08738.81A10E16; Thu, 13 Jan 2022 21:24:56 +0900 (KST) Received: from Jaguar.sa.corp.samsungelectronics.net (unknown [107.108.73.139]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20220113122453epsmtip2278c805cc6a7a9404a5cbed7bb323a8f~J1A2IUeYk1246112461epsmtip2X; Thu, 13 Jan 2022 12:24:53 +0000 (GMT) From: Alim Akhtar To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org List-Id: Cc: soc@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, olof@lixom.net, linus.walleij@linaro.org, catalin.marinas@arm.com, robh+dt@kernel.org, krzysztof.kozlowski@canonical.com, s.nawrocki@samsung.com, linux-samsung-soc@vger.kernel.org, pankaj.dubey@samsung.com, Alim Akhtar , linux-fsd@tesla.com, Tamseel Shams Subject: [PATCH 22/23] arm64: dts: fsd: Add ADC device tree node Date: Thu, 13 Jan 2022 17:41:42 +0530 Message-Id: <20220113121143.22280-23-alim.akhtar@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220113121143.22280-1-alim.akhtar@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprAJsWRmVeSWpSXmKPExsWy7bCmlq6E1INEg6st1hYP5m1js3i/rIfR Yv6Rc6wWG9/+YLKY8mc5k8Wmx9dYLT723GO1ePgq3OLyrjlsFjPO72OyuNu6mN3i1PXPbBaL tn5ht2jde4Td4vCbdlaLx9f/sDkIeKyZt4bRY1ZDL5vHplWdbB53ru1h89i8pN7jyokmVo++ LasYPf41zWX3+LxJLoAzKtsmIzUxJbVIITUvOT8lMy/dVsk7ON453tTMwFDX0NLCXEkhLzE3 1VbJxSdA1y0zB+gLJYWyxJxSoFBAYnGxkr6dTVF+aUmqQkZ+cYmtUmpBSk6BSYFecWJucWle ul5eaomVoYGBkSlQYUJ2xu6T29kLurkq/r65xtLAuISji5GTQ0LARGLurOtMXYxcHEICuxkl ztyczgbhfGKU+LThNTOE85lR4l3zRBaYllXrr7JCJHYxShx88guqv4VJ4uyhRiaQKjYBbYm7 07eA2SICbhI3GjvAipgFmpkl5k08CDSKg0NYwEHi1YwAEJNFQFXi7343kHJeAVuJ022XmCGW yUus3nCAGaSEEyh+d1UeyBQJgZUcEh0TvzBB1LhI7Py6mhHCFpZ4dXwLO4QtJfGyv40dpFdC IFuiZ5cxRLhGYum8Y1C/2EscuDIH7BhmAU2J9bv0QcLMAnwSvb+fMEF08kp0tAlBVKtKNL+7 CtUpLTGxu5sVwvaQ2LRpDiMkECYwSpxasIp1AqPsLISpCxgZVzFKphYU56anFpsWGOallsOj KTk/dxMjOGlqee5gvPvgg94hRiYOxkOMEhzMSiK8/UX3E4V4UxIrq1KL8uOLSnNSiw8xmgID bCKzlGhyPjBt55XEG5pYGpiYmZmZWBqbGSqJ855O35AoJJCeWJKanZpakFoE08fEwSnVwKQx 5Wi/0RUX09NlzXNb2MJ+ntaNNv6azXu78r/+5QyBbROmXl5159sCu3Clg/9eCMo9+cAfFmXH Hb3z4+SEJK9mj0chjI0btuV1Txeoj3NTnTo/vCl/QmM2w0Z1r0bJrpkBp6r3P9BgW8T281rG G1v3q507uuOPMn2pfKVrvWk3+wJFEX3+wmQuOwbhBQcZCj8sT5bLmrYwK2hxJlcyyzxr8w6L /ae/neN7cU5ZyyfP9bF37QOHfW031r/8felT1Yfg56JHk3KOhex9ZDalvfvB3Vs7zoVxMH+X NPzWL//Pwcomqu/kF/9LKmaHPi9ft/b/oRddc4J/e/+/vHTToh2ffG+8UnuTePel0+vZ3g+U WIozEg21mIuKEwGBNSk7IwQAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrCLMWRmVeSWpSXmKPExsWy7bCSvK6E1INEgwUr2CwezNvGZvF+WQ+j xfwj51gtNr79wWQx5c9yJotNj6+xWnzsucdq8fBVuMXlXXPYLGac38dkcbd1MbvFqeuf2SwW bf3CbtG69wi7xeE37awWj6//YXMQ8Fgzbw2jx6yGXjaPTas62TzuXNvD5rF5Sb3HlRNNrB59 W1Yxevxrmsvu8XmTXABnFJdNSmpOZllqkb5dAlfG7pPb2Qu6uSr+vrnG0sC4hKOLkZNDQsBE YtX6q6xdjFwcQgI7GCWuv5rJBpGQlri+cQI7hC0ssfLfc3aIoiYmiabm02BFbALaEnenb2EC sUUEPCTa/t1jBiliFpjMLDH9xWygsRwcwgIOEq9mBICYLAKqEn/3u4GU8wrYSpxuu8QMMV9e YvWGA8wgJZxA8bur8kDCQgI2EuderWebwMi3gJFhFaNkakFxbnpusWGBUV5quV5xYm5xaV66 XnJ+7iZGcMBrae1g3LPqg94hRiYOxkOMEhzMSiK8/UX3E4V4UxIrq1KL8uOLSnNSiw8xSnOw KInzXug6GS8kkJ5YkpqdmlqQWgSTZeLglGpg8li34Oq6z0KrClU/HeXP8HuwcnPRcm+fW3HF PgJpH6c25B4+LyHw88olpZ6T/EUuh78WyinOjIj+MClJW3HNya/S6wT3CsYvtNpkMmWObZ79 vQl851x3V9xO5Tq5geVz6TGNhoaYcN6n3xf8Mn5yenL97T2+FW5Lc6STZLlfHC8+3qHjXvVK 35h31boP4hv4pvJe/sb7LF5GxuLkpdc/VPnPHstavHHpHbuq1/IrAh6tPbgmwJXFfFUR09+4 /+w2G5Pu3p2woWXdHY/s5UedfZtPlGjy7Kg+131+Rvaio3pVGhUGlt89Hns8sviYKqIc9MzU /X/dfVVFyYbD3XuUebYEPxFcbPF7z91bsb8dzyixFGckGmoxFxUnAgBdqSO25wIAAA== X-CMS-MailID: 20220113122456epcas5p35f6406ab03af58d2e56b0b7304d4d002 X-Msg-Generator: CA CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220113122456epcas5p35f6406ab03af58d2e56b0b7304d4d002 References: <20220113121143.22280-1-alim.akhtar@samsung.com> This patch adds ADC device tree node and enables the same on fsd platform. Cc: linux-fsd@tesla.com Signed-off-by: Tamseel Shams Signed-off-by: Alim Akhtar --- arch/arm64/boot/dts/tesla/fsd.dts | 4 ++++ arch/arm64/boot/dts/tesla/fsd.dtsi | 11 +++++++++++ 2 files changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/tesla/fsd.dts b/arch/arm64/boot/dts/tesla/fsd.dts index 7f3bb6212e50..dd6c75fc3221 100644 --- a/arch/arm64/boot/dts/tesla/fsd.dts +++ b/arch/arm64/boot/dts/tesla/fsd.dts @@ -150,3 +150,7 @@ &spi_2 { status = "okay"; }; + +&adc { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi index 7e687c6f74f6..058a9d381aed 100644 --- a/arch/arm64/boot/dts/tesla/fsd.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi @@ -788,6 +788,17 @@ num-cs = <1>; status = "disabled"; }; + + adc: adc@141A0000 { + compatible = "samsung,exynos-adc-v3"; + reg = <0x0 0x141A0000 0x0 0x100>; + interrupts = ; + clocks = <&clock_peric PERIC_PCLK_ADCIF>; + clock-names = "adc"; + #io-channel-cells = <1>; + io-channel-ranges; + status = "disabled"; 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Thu, 13 Jan 2022 21:25:01 +0900 (KST) Received: from Jaguar.sa.corp.samsungelectronics.net (unknown [107.108.73.139]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20220113122459epsmtip2e5b4002f52af13c0bc060d4cb53c7683~J1A7RzPuN1246812468epsmtip2J; Thu, 13 Jan 2022 12:24:59 +0000 (GMT) From: Alim Akhtar To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org List-Id: Cc: soc@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, olof@lixom.net, linus.walleij@linaro.org, catalin.marinas@arm.com, robh+dt@kernel.org, krzysztof.kozlowski@canonical.com, s.nawrocki@samsung.com, linux-samsung-soc@vger.kernel.org, pankaj.dubey@samsung.com, Aswani Reddy , linux-fsd@tesla.com, Alim Akhtar Subject: [PATCH 23/23] clocksource: exynos_mct: Add support for handling three clusters Date: Thu, 13 Jan 2022 17:41:43 +0530 Message-Id: <20220113121143.22280-24-alim.akhtar@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220113121143.22280-1-alim.akhtar@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprAJsWRmVeSWpSXmKPExsWy7bCmlq6c1INEg/VfRCwezNvGZnFo81Z2 i/fLehgt5h85x2qx8e0PJospf5YzWWx6fI3V4mPPPVaLh6/CLS7vmsNmMeP8PiaLU9c/s1ks 2vqF3aJ17xF2i8Nv2lktHl//w+Yg4LFm3hpGj1kNvWwem1Z1snncubaHzWPzknqPKyeaWD36 tqxi9PjXNJfd4/MmuQDOqGybjNTElNQihdS85PyUzLx0WyXv4HjneFMzA0NdQ0sLcyWFvMTc VFslF58AXbfMHKAvlBTKEnNKgUIBicXFSvp2NkX5pSWpChn5xSW2SqkFKTkFJgV6xYm5xaV5 6Xp5qSVWhgYGRqZAhQnZGTeXv2cqeMJeseXdDtYGxn1sXYycHBICJhK7p/eygthCArsZJT7N re5i5AKyPzFKtK34ygzhfGOU+DF9GSNMx7PDG9khEnsZJe6+7IFyWpgkVrW3soBUsQloS9yd voUJxBYRcJO40djBBFLELNDOLHFnwl4gh4NDWCBS4tgqc5AaFgFViUu7v4HdwStgK/Fx2SGo bfISqzccYAYp5wSK312VBzJGQmAph8Sir5dZIWpcJM5s3swCYQtLvDq+hR3ClpL4/G4vG0iv hEC2RM8uY4hwjcTSecegyu0lDlyZwwJSwiygKbF+lz5ImFmAT6L39xMmiE5eiY42IYhqVYnm d1ehOqUlJnZ3Qx3gITGpYys0FCYwShw+e419AqPsLISpCxgZVzFKphYU56anFpsWGOallsOj KTk/dxMjOGlqee5gvPvgg94hRiYOxkOMEhzMSiK8/UX3E4V4UxIrq1KL8uOLSnNSiw8xmgJD bCKzlGhyPjBt55XEG5pYGpiYmZmZWBqbGSqJ855O35AoJJCeWJKanZpakFoE08fEwSnVwNSv NeNB7xGtNb7FB1o3Tvt7YPPEVVFNN6b3HGBTWc6437VJTGWmMjPvC8aNSuFLyh7siAyxzpNI 6MwX/3S+w3+zv8GKxPlxNb/38Mr9Y+Xx2SfI8OxH3NrMvhmdrw9X5hycHPlXnuEOR4tfZaT5 x45VJrnZ55/ZPLOZwhInxmTEIece9Mpb4FbcFm+dOeuYeHZqGSZqhdotrGMKyZzje9hn6cGL eY/0WPa/3ZLyJVRq62GTLIZzj/5zznp5vo3zuRbrnAdtfiVv1x5iyUv6osnRFtaq7SQZ7bm5 6r/omtWzzBLS7LJeZ8qaBu2/tKBMdEdRX9VDWbfX226fk33m9yElUWrada438+sKFzRzKbEU ZyQaajEXFScCAPi3N+0jBAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrCLMWRmVeSWpSXmKPExsWy7bCSvK6s1INEg32zVC0ezNvGZnFo81Z2 i/fLehgt5h85x2qx8e0PJospf5YzWWx6fI3V4mPPPVaLh6/CLS7vmsNmMeP8PiaLU9c/s1ks 2vqF3aJ17xF2i8Nv2lktHl//w+Yg4LFm3hpGj1kNvWwem1Z1snncubaHzWPzknqPKyeaWD36 tqxi9PjXNJfd4/MmuQDOKC6blNSczLLUIn27BK6Mm8vfMxU8Ya/Y8m4HawPjPrYuRk4OCQET iWeHN7J3MXJxCAnsZpR4cfAfVEJa4vrGCewQtrDEyn/PwWwhgSYmia+7TEBsNgFtibvTtzCB 2CICHhJt/+4xgwxiFpjOLHFg2zeWLkYODmGBcIn9fZ4gNSwCqhKXdn9jBbF5BWwlPi47xAgx X15i9YYDzCDlnEDxu6vyIFbZSJx7tZ5tAiPfAkaGVYySqQXFuem5xYYFhnmp5XrFibnFpXnp esn5uZsYwQGvpbmDcfuqD3qHGJk4GA8xSnAwK4nw9hfdTxTiTUmsrEotyo8vKs1JLT7EKM3B oiTOe6HrZLyQQHpiSWp2ampBahFMlomDU6qBKVtCMUj4/q1jm4O6V9st4F3CH1lg3CARo/FO Jy013OjaW8fFFftlHos+u5bFsHSDFFdfnG3U3s7FvK3T0n+7nzSMuBWspW77sXu+/7LLU36L Hk566KD5beua4FVfBJJ/CkvFS3IY3WEIanbeJ/Poh9PZvO//2q8v2cFpsqE/yv5U7I2mvnmW Z0Kskq5Es6eFm8yblnWa50Lb96abbE/abh1JfX/5lZF77ZXeQxskgpMlg91P/apP6hafL/++ 8/n0J1krjz/ZqGi8SLZUXH/67Ls2zyz37b+yzGAOv9viWX71nOdXRz4ra/KSramsnXFiy1TG WVb68yNLuW559Xoz+t7/HDNxO9OUlcopfUttlFiKMxINtZiLihMBC8F3kOcCAAA= X-CMS-MailID: 20220113122502epcas5p37747b0c5c242c0571d294b9245963a1c X-Msg-Generator: CA CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220113122502epcas5p37747b0c5c242c0571d294b9245963a1c References: <20220113121143.22280-1-alim.akhtar@samsung.com> From: Aswani Reddy This patch adds support for handling thress clusters (upto 12 CPUs) Cc: linux-fsd@tesla.com Signed-off-by: Aswani Reddy Signed-off-by: Alim Akhtar --- drivers/clocksource/exynos_mct.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c index 5e3e96d3d1b9..ba3af940a687 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c @@ -78,6 +78,10 @@ enum { MCT_L5_IRQ, MCT_L6_IRQ, MCT_L7_IRQ, + MCT_L8_IRQ, + MCT_L9_IRQ, + MCT_L10_IRQ, + MCT_L11_IRQ, MCT_NR_IRQS, }; @@ -89,7 +93,7 @@ static int mct_irqs[MCT_NR_IRQS]; struct mct_clock_event_device { struct clock_event_device evt; unsigned long base; - char name[10]; + char name[11]; }; static void exynos4_mct_write(unsigned int value, unsigned long offset)