From patchwork Thu Jan 13 14:48:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12712816 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F2BECC433F5 for ; Thu, 13 Jan 2022 14:48:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235773AbiAMOsB (ORCPT ); Thu, 13 Jan 2022 09:48:01 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:19844 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235772AbiAMOsB (ORCPT ); Thu, 13 Jan 2022 09:48:01 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1642085281; x=1673621281; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Cn32FVsFXj7kfAuzJ2kdL23yH/APr88N4Syy5Ekn8OM=; b=zZRlmmwYzMH00kshQxD9Tb5uPnMV3qN92552dOqPr4ehw/mCzdg6I4j2 rFgyCyE4o2T/HH2orVEARIdO33m4Bdb+wuE/XZvenDkpeBkBMZoSPAsI5 g95Oj6Wbw3oLzU2qgAUMl2euCJgmJRvq/CcSRDNr1Nz8iCSlzBGKfwo72 27wUehWQPTRKQgSJ2Rj4TGFQ5xP+QeRF/0Cg1zY8ZKQEKYHn3QvAZ1PQV kaZxxIHFFjxIR7yAzJrVaE44x+8ppKPY551Z78ojbQUC+0OIDRAZ0uW+9 el6Av4neyJluM8ltvEaoz+BtO/dnmw2GyxNtRn5qVj/cc/nJ4Je08Mvo7 w==; IronPort-SDR: fhquOLUgqGAvIcJkV2498oPQ6QQ7zP3v7mekOLklhyq1LekwwggcAVs0+xjrfgZ6mukC52xtSf vSLQ5bY0A6mJnx7mcyHhrSTUllwlY1EYJJZ6FjHLyNEJCT1EBcv2/uSgX8RVBGO/dgdGeDXX96 nHws1Rz7K0Ysj32+GLRHD7HkFOt08poGmDqCct+cmnyf+CcHaqL33a9jzcykTAiNm7uPsumKCQ EVplH+y2VqRHIWP8I0LsGMorosP3wJbF/FasQZ306vOxfG0EfYnMrJ7OXpNdSmC+5uVGNBxnsJ bJZhRVV61vMUFPcucJ2E8tPq X-IronPort-AV: E=Sophos;i="5.88,286,1635231600"; d="scan'208";a="150108166" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 Jan 2022 07:47:59 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Thu, 13 Jan 2022 07:47:58 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Thu, 13 Jan 2022 07:47:55 -0700 From: Claudiu Beznea To: , , , , , , CC: , , , , Claudiu Beznea Subject: [PATCH v2 01/10] ARM: at91: ddr: remove CONFIG_SOC_SAMA7 dependency Date: Thu, 13 Jan 2022 16:48:51 +0200 Message-ID: <20220113144900.906370-2-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220113144900.906370-1-claudiu.beznea@microchip.com> References: <20220113144900.906370-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Remove CONFIG_SOC_SAMA7 dependency to avoid having #ifdef preprocessor directives in driver code (arch/arm/mach-at91/pm.c). This prepares the code for next commits. Signed-off-by: Claudiu Beznea --- include/soc/at91/sama7-ddr.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/include/soc/at91/sama7-ddr.h b/include/soc/at91/sama7-ddr.h index f6542584ca13..13b47e26cdbe 100644 --- a/include/soc/at91/sama7-ddr.h +++ b/include/soc/at91/sama7-ddr.h @@ -11,8 +11,6 @@ #ifndef __SAMA7_DDR_H__ #define __SAMA7_DDR_H__ -#ifdef CONFIG_SOC_SAMA7 - /* DDR3PHY */ #define DDR3PHY_PIR (0x04) /* DDR3PHY PHY Initialization Register */ #define DDR3PHY_PIR_DLLBYP (1 << 17) /* DLL Bypass */ @@ -75,6 +73,4 @@ #define UDDRC_PCTRL_3 (0x6A0) /* UDDRC Port 3 Control Register */ #define UDDRC_PCTRL_4 (0x750) /* UDDRC Port 4 Control Register */ -#endif /* CONFIG_SOC_SAMA7 */ - #endif /* __SAMA7_DDR_H__ */ From patchwork Thu Jan 13 14:48:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12712817 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22276C4332F for ; Thu, 13 Jan 2022 14:48:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235782AbiAMOsD (ORCPT ); Thu, 13 Jan 2022 09:48:03 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:31589 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235778AbiAMOsC (ORCPT ); Thu, 13 Jan 2022 09:48:02 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1642085282; x=1673621282; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=DSaF+rce8x7D+Hdysx6zQcXry3snwSGAnsCyiWnFVNw=; b=HqFKY67xUV+laPC/39dsTeoSlOp/t/WIJDHkmaV27sfqEa7eWHoh+9+2 HXhcCeihomJaT7DToSKhzfGEFhiKqscxhLrRJ2aDQZhIvaHmiDtMoGkfR KJIeXGkP188sNzLwABlGkq1hkUSDF3y0Zem1LA4FMMtWpkWLOf6kR797Z 0iAmDrtkwn1Gdpj+nBfZqYbaSITZS+p55QFIQSlr4iZxZE77driD4EzJm C08vlsKBx4j0vOwaEfdFU/cjkNEUHwzMdmtJrGTZL2t//67CrXgVcwvpq kf/2Eq7ZCHpiy1jJ2oKWv+FZXgo3GRlUtFP8fBpF6GDMwa0uLebp66py3 w==; IronPort-SDR: /kdMeHcO7FdvdUxY8sX5s/Ek+BSN30m/Tvr3/0D4DnmjldLEVxpVbU9uI8XTqYvDfxZ83mpnF/ cSrHIoJfzsgWAh+bY2yecOfDJ4LrOzIMp59zNRIpU3sPSElrlKOsr+EhKtfUb5bjFj6WR2fCto +4oZJ8dBqmG5KuChvh+6BeVTpBPgCNngnzrqxVQZtcP243rQa43MDDyNRCr42z65YSB+Z03oR/ cCS7sD/Z77SDQxeEatAqLiw8fr6mHd1t7pCiCqSpIC4k7/Rvt2B4vZ+vV/h5QTB3BxEWIlqzEW UwscTB8lGikMIJvdo4GN/gVL X-IronPort-AV: E=Sophos;i="5.88,286,1635231600"; d="scan'208";a="158557502" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 Jan 2022 07:48:01 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Thu, 13 Jan 2022 07:48:01 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Thu, 13 Jan 2022 07:47:58 -0700 From: Claudiu Beznea To: , , , , , , CC: , , , , Claudiu Beznea Subject: [PATCH v2 02/10] ARM: at91: ddr: align macro definitions Date: Thu, 13 Jan 2022 16:48:52 +0200 Message-ID: <20220113144900.906370-3-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220113144900.906370-1-claudiu.beznea@microchip.com> References: <20220113144900.906370-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Align all macro definitions. Signed-off-by: Claudiu Beznea --- include/soc/at91/sama7-ddr.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/soc/at91/sama7-ddr.h b/include/soc/at91/sama7-ddr.h index 13b47e26cdbe..817b360efbb8 100644 --- a/include/soc/at91/sama7-ddr.h +++ b/include/soc/at91/sama7-ddr.h @@ -13,11 +13,11 @@ /* DDR3PHY */ #define DDR3PHY_PIR (0x04) /* DDR3PHY PHY Initialization Register */ -#define DDR3PHY_PIR_DLLBYP (1 << 17) /* DLL Bypass */ +#define DDR3PHY_PIR_DLLBYP (1 << 17) /* DLL Bypass */ #define DDR3PHY_PIR_ITMSRST (1 << 4) /* Interface Timing Module Soft Reset */ -#define DDR3PHY_PIR_DLLLOCK (1 << 2) /* DLL Lock */ +#define DDR3PHY_PIR_DLLLOCK (1 << 2) /* DLL Lock */ #define DDR3PHY_PIR_DLLSRST (1 << 1) /* DLL Soft Rest */ -#define DDR3PHY_PIR_INIT (1 << 0) /* Initialization Trigger */ +#define DDR3PHY_PIR_INIT (1 << 0) /* Initialization Trigger */ #define DDR3PHY_PGCR (0x08) /* DDR3PHY PHY General Configuration Register */ #define DDR3PHY_PGCR_CKDV1 (1 << 13) /* CK# Disable Value */ @@ -65,7 +65,7 @@ #define UDDRC_SWSTAT_SW_DONE_ACK (1 << 0) /* Register programming done */ #define UDDRC_PSTAT (0x3FC) /* UDDRC Port Status Register */ -#define UDDRC_PSTAT_ALL_PORTS (0x1F001F) /* Read + writes outstanding transactions on all ports */ +#define UDDRC_PSTAT_ALL_PORTS (0x1F001F) /* Read + writes outstanding transactions on all ports */ #define UDDRC_PCTRL_0 (0x490) /* UDDRC Port 0 Control Register */ #define UDDRC_PCTRL_1 (0x540) /* UDDRC Port 1 Control Register */ From patchwork Thu Jan 13 14:48:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12712818 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 43E60C4332F for ; Thu, 13 Jan 2022 14:48:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235794AbiAMOsI (ORCPT ); Thu, 13 Jan 2022 09:48:08 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:31589 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235800AbiAMOsF (ORCPT ); Thu, 13 Jan 2022 09:48:05 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1642085285; x=1673621285; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8B+mjGEHiWRvOo09WcjQMA43OD+N7/Tq2fPJzC7/86M=; b=QVs41uZG8auz1+IFt1uF+8xoERLZB51H3OmjBXfdmQvxTyoquz4Uwy8p A2HlxetBt3eDfkpynPLoUNtG2iFBUNBJGWtY1QdZvTi4YgMmuUge+3L6Q +dOaFf1AeRjNB0JN+H2WEcnPpLD8QUsKaO6MbcxvziqvMu+zuv5zdHxsO FLOqCTcl7uldpvX+1wm2NuUddU2uF9FBHtVqz3B0ESLp9YbixD8TdOTx3 sUuJ/DazXScOh5YrFr55ZoiSBftZzNwJUn1p1p+qhncid6Vu1GlcbIl3t d2kyQzGVuQBSaDPCEQm7TD4w1XyqMT340GhDItBXDvCUviOf8+CKwJF3Y A==; IronPort-SDR: x5fH9fXkDlx/sXNG4ZpdDTYwDS6Je59q4Tu3bZITHBYf86MfWCalZcTv97QA90DW9pSdw0ctPV 0ZHmWspbloYi6m9cGbAub9oQz8OYCpcy1YNhMykZSm/noZuu2P8r5vqeMY5/VqFxp4sAOCojBP YHfQe54NS24//kf7r+ykoDTzdjHaPAFwgyoVEmUAFTTohDzFoI4q6Ag4OAmjzzInw8ld0jBFym 32Lp7AB1v36lyP4CVkAxtfWV02AA/DOYylpP1MDjdw+czk9F5EDDyRcFO06pryfIjYQ+JwPa7e 0uwQPYAeCVVf7Npt6DF6VVGl X-IronPort-AV: E=Sophos;i="5.88,286,1635231600"; d="scan'208";a="158557508" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 Jan 2022 07:48:04 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Thu, 13 Jan 2022 07:48:04 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Thu, 13 Jan 2022 07:48:02 -0700 From: Claudiu Beznea To: , , , , , , CC: , , , , Claudiu Beznea Subject: [PATCH v2 03/10] ARM: at91: ddr: fix typo to align with datasheet naming Date: Thu, 13 Jan 2022 16:48:53 +0200 Message-ID: <20220113144900.906370-4-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220113144900.906370-1-claudiu.beznea@microchip.com> References: <20220113144900.906370-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Fix typo on UDDRC_PWRCTL.SELFREF_SW bitmask to align with datasheet naming. Signed-off-by: Claudiu Beznea --- arch/arm/mach-at91/pm_suspend.S | 4 ++-- include/soc/at91/sama7-ddr.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S index fdb4f63ecde4..abe4ced33eda 100644 --- a/arch/arm/mach-at91/pm_suspend.S +++ b/arch/arm/mach-at91/pm_suspend.S @@ -159,7 +159,7 @@ sr_ena_1: /* Switch to self-refresh. */ ldr tmp1, [r2, #UDDRC_PWRCTL] - orr tmp1, tmp1, #UDDRC_PWRCTRL_SELFREF_SW + orr tmp1, tmp1, #UDDRC_PWRCTL_SELFREF_SW str tmp1, [r2, #UDDRC_PWRCTL] sr_ena_2: @@ -276,7 +276,7 @@ sr_dis_5: /* Trigger self-refresh exit. */ ldr tmp1, [r2, #UDDRC_PWRCTL] - bic tmp1, tmp1, #UDDRC_PWRCTRL_SELFREF_SW + bic tmp1, tmp1, #UDDRC_PWRCTL_SELFREF_SW str tmp1, [r2, #UDDRC_PWRCTL] sr_dis_6: diff --git a/include/soc/at91/sama7-ddr.h b/include/soc/at91/sama7-ddr.h index 817b360efbb8..fee1b11bddca 100644 --- a/include/soc/at91/sama7-ddr.h +++ b/include/soc/at91/sama7-ddr.h @@ -53,7 +53,7 @@ #define UDDRC_STAT_OPMODE_MSK (0x7 << 0) /* Operating mode mask */ #define UDDRC_PWRCTL (0x30) /* UDDRC Low Power Control Register */ -#define UDDRC_PWRCTRL_SELFREF_SW (1 << 5) /* Software self-refresh */ +#define UDDRC_PWRCTL_SELFREF_SW (1 << 5) /* Software self-refresh */ #define UDDRC_DFIMISC (0x1B0) /* UDDRC DFI Miscellaneous Control Register */ #define UDDRC_DFIMISC_DFI_INIT_COMPLETE_EN (1 << 0) /* PHY initialization complete enable signal */ From patchwork Thu Jan 13 14:48:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12712819 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7CB0CC433EF for ; Thu, 13 Jan 2022 14:48:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235830AbiAMOsO (ORCPT ); Thu, 13 Jan 2022 09:48:14 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:31589 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235791AbiAMOsI (ORCPT ); Thu, 13 Jan 2022 09:48:08 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1642085288; x=1673621288; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cpKxdtwy7Ox5Jspj12nGljBMXStsy5iD5Lt1+j43mkI=; b=M2XdIhHByRrPM9DLlgfgGH3FpCAcKqYNmZSAeanB0+ZAWkjxhqAJSjgD 7fuiRCKh51T7QxNVh8NGIPUqhQf+LmEl/c5UFpqYq7xu/w3tEOotDUB6w O5l7wYu4k2L9UOkmESE3Wse3tpRnp/6czx4EppxMZVKCkRDTVDEUcxFk0 Nn9VX8N3gZsUqDE09Do/CgDErehgNo+cPPnzIHyJXEefLiQlaPD9uV7Fm RAFa+ojCXnFq5yTEnkaY+PWO0VhLzGquiRd3Za6xP5IqdWOoJ/40ENJeq zSQ2kbTBtAiUnjxwJroXeQDUzzgFd90E6onm42+gGA4hkaibg/XVQLQwH g==; IronPort-SDR: l25eMLLmgkkG50NGqSakJ+63kGv8LZzXzzZ5yAaC9psEOjUcqRV8asD51bVC2J/cZlbPxL076U N7yz6ifnfauTQGaXkD1Zz5li6ybwQR0PPWnhHdnlgrmiM1/N7zmo1agrwFW2hJ5g45yjolVVJ1 9Mv1BxMGXJZvdVYfsrf9/stGM0DvJFBvzf9K2BLLS4Vffs4YrQHWZ6O9ecFILAklFEOPQfK00O 9fW5IeksDKMBDTGDY2o/U1mSuw5usuEB+zQpFesEeoYKz0t4rzA/LJlnwKHVYHF7atGnUwLl5D OfUV6z/Nwp+DZdZoLecV308A X-IronPort-AV: E=Sophos;i="5.88,286,1635231600"; d="scan'208";a="158557517" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 Jan 2022 07:48:07 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Thu, 13 Jan 2022 07:48:07 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Thu, 13 Jan 2022 07:48:05 -0700 From: Claudiu Beznea To: , , , , , , CC: , , , , Claudiu Beznea Subject: [PATCH v2 04/10] ARM: at91: PM: add cpu idle support for sama7g5 Date: Thu, 13 Jan 2022 16:48:54 +0200 Message-ID: <20220113144900.906370-5-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220113144900.906370-1-claudiu.beznea@microchip.com> References: <20220113144900.906370-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add CPU idle support for SAMA7G5. Support will make use of PMC_CPU_RATIO register to divide the CPU clock by 16 before switching it to idle and use automatic self-refresh option of DDR controller. Signed-off-by: Claudiu Beznea Acked-by: Stephen Boyd --- arch/arm/mach-at91/pm.c | 27 ++++++++++++++++++++++++++- include/linux/clk/at91_pmc.h | 4 ++++ include/soc/at91/sama7-ddr.h | 1 + 3 files changed, 31 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index dd6f4ce3f766..0fd609e26615 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -605,6 +605,30 @@ static void at91sam9_sdram_standby(void) at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1); } +static void sama7g5_standby(void) +{ + int pwrtmg, ratio; + + pwrtmg = readl(soc_pm.data.ramc[0] + UDDRC_PWRCTL); + ratio = readl(soc_pm.data.pmc + AT91_PMC_RATIO); + + /* + * Place RAM into self-refresh after a maximum idle clocks. The maximum + * idle clocks is configured by bootloader in + * UDDRC_PWRMGT.SELFREF_TO_X32. + */ + writel(pwrtmg | UDDRC_PWRCTL_SELFREF_EN, + soc_pm.data.ramc[0] + UDDRC_PWRCTL); + /* Divide CPU clock by 16. */ + writel(ratio & ~AT91_PMC_RATIO_RATIO, soc_pm.data.pmc + AT91_PMC_RATIO); + + cpu_do_idle(); + + /* Restore previous configuration. */ + writel(ratio, soc_pm.data.pmc + AT91_PMC_RATIO); + writel(pwrtmg, soc_pm.data.ramc[0] + UDDRC_PWRCTL); +} + struct ramc_info { void (*idle)(void); unsigned int memctrl; @@ -615,6 +639,7 @@ static const struct ramc_info ramc_infos[] __initconst = { { .idle = at91sam9_sdram_standby, .memctrl = AT91_MEMCTRL_SDRAMC}, { .idle = at91_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR}, { .idle = sama5d3_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR}, + { .idle = sama7g5_standby, }, }; static const struct of_device_id ramc_ids[] __initconst = { @@ -622,7 +647,7 @@ static const struct of_device_id ramc_ids[] __initconst = { { .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] }, { .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] }, { .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] }, - { .compatible = "microchip,sama7g5-uddrc", }, + { .compatible = "microchip,sama7g5-uddrc", .data = &ramc_infos[4], }, { /*sentinel*/ } }; diff --git a/include/linux/clk/at91_pmc.h b/include/linux/clk/at91_pmc.h index ccb3f034bfa9..3484309b59bf 100644 --- a/include/linux/clk/at91_pmc.h +++ b/include/linux/clk/at91_pmc.h @@ -78,6 +78,10 @@ #define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */ #define AT91_CKGR_PLLAR 0x28 /* PLL A Register */ + +#define AT91_PMC_RATIO 0x2c /* Processor clock ratio register [SAMA7G5 only] */ +#define AT91_PMC_RATIO_RATIO (0xf) /* CPU clock ratio. */ + #define AT91_CKGR_PLLBR 0x2c /* PLL B Register */ #define AT91_PMC_DIV (0xff << 0) /* Divider */ #define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ diff --git a/include/soc/at91/sama7-ddr.h b/include/soc/at91/sama7-ddr.h index fee1b11bddca..9e17247474fa 100644 --- a/include/soc/at91/sama7-ddr.h +++ b/include/soc/at91/sama7-ddr.h @@ -53,6 +53,7 @@ #define UDDRC_STAT_OPMODE_MSK (0x7 << 0) /* Operating mode mask */ #define UDDRC_PWRCTL (0x30) /* UDDRC Low Power Control Register */ +#define UDDRC_PWRCTL_SELFREF_EN (1 << 0) /* Automatic self-refresh */ #define UDDRC_PWRCTL_SELFREF_SW (1 << 5) /* Software self-refresh */ #define UDDRC_DFIMISC (0x1B0) /* UDDRC DFI Miscellaneous Control Register */ From patchwork Thu Jan 13 14:48:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12712821 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BBAD1C433F5 for ; Thu, 13 Jan 2022 14:48:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235821AbiAMOsS (ORCPT ); Thu, 13 Jan 2022 09:48:18 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:49479 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235828AbiAMOsN (ORCPT ); Thu, 13 Jan 2022 09:48:13 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1642085293; x=1673621293; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ETLnfefiwEYOdcgZaQpwwBczz13QcWsMBfwE7C7NDns=; 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Thu, 13 Jan 2022 07:48:10 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Thu, 13 Jan 2022 07:48:08 -0700 From: Claudiu Beznea To: , , , , , , CC: , , , , Claudiu Beznea Subject: [PATCH v2 05/10] ARM: at91: Kconfig: select PM_OPP Date: Thu, 13 Jan 2022 16:48:55 +0200 Message-ID: <20220113144900.906370-6-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220113144900.906370-1-claudiu.beznea@microchip.com> References: <20220113144900.906370-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Select PM_OPP. This is requested for CPUFreq driver. Signed-off-by: Claudiu Beznea --- arch/arm/mach-at91/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 02f6b108fd5d..279810381256 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -63,6 +63,7 @@ config SOC_SAMA7G5 select HAVE_AT91_GENERATED_CLK select HAVE_AT91_SAM9X60_PLL select HAVE_AT91_UTMI + select PM_OPP select SOC_SAMA7 help Select this if you are using one of Microchip's SAMA7G5 family SoC. From patchwork Thu Jan 13 14:48:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12712820 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2314EC433FE for ; Thu, 13 Jan 2022 14:48:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235840AbiAMOsR (ORCPT ); Thu, 13 Jan 2022 09:48:17 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:19880 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235801AbiAMOsO (ORCPT ); Thu, 13 Jan 2022 09:48:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1642085294; x=1673621294; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=qzxL53+xCwUlzzE+c5h3xp0iY0GwHksZEGL+kIYmI/c=; b=tlJt+YYE5Nto4VakTfacNyrIfIR1bZMpO9bEG11al8bShyEOMY/YL2IJ Kb6P94o4Jwsx4Vjqylbk0Ngpt/hn92age4Xzr6g3kooYc7953lRgDYr5b 1EKFeLhTqzEPvWP1iKo/a7/oAXaFfp7V1pdeVBClOKK05iK81167APFz6 JYoL3tY5n4QljfAuSWE1+uSDlLELD0O7aRegqd5svqYiwUi2+WuLCHFgn BnIlSYVyQGC2cLM8kP3g3YB/TEPBhbNzEffzT8DYS1FcwxOTIn8NFund4 KWUV5/ZwaXC0o8leE8ZA8D5YEidt7KruTzwUtYhbYjXwVz7ZKnA/NnUi5 A==; IronPort-SDR: BPtLW3vol1O10wBtDTdU/osMfjW67K7iAB5k1pKez50+5jPucwUS0EZrWSckGbBNjqy/jFfq2N 2j5GaDyRCRyD9xRGlOvi+B4s1AHd3vERmEq+eS0mcZLGO+9SfkS6z5cKlAqwOGTjEDvsFAZ+AG P6d6gaoG9thkSHQXVo/NSWpvtiVEhoYt/CAC5xAKkwbvuZtFYK7szGF36s+AHrfOXu2C8IXgnc XUS5bnGaasttb+DJb+JMqoCnmupYmd94ZUDW8ufY1xW2d1WSX6Zp3wLGmmL/SrIpuxju90tKPk vrpC7eLj1FSanHBjxIuvEtV2 X-IronPort-AV: E=Sophos;i="5.88,286,1635231600"; d="scan'208";a="150108218" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 Jan 2022 07:48:14 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Thu, 13 Jan 2022 07:48:14 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Thu, 13 Jan 2022 07:48:11 -0700 From: Claudiu Beznea To: , , , , , , CC: , , , , Claudiu Beznea Subject: [PATCH v2 06/10] ARM: dts: at91: fix low limit for CPU regulator Date: Thu, 13 Jan 2022 16:48:56 +0200 Message-ID: <20220113144900.906370-7-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220113144900.906370-1-claudiu.beznea@microchip.com> References: <20220113144900.906370-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Fix low limit for CPU regulator. Otherwise setting voltages lower than 1.125V will not be allowed (CPUFreq will not be allowed to set proper voltages on proper frequencies). Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/at91-sama7g5ek.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/at91-sama7g5ek.dts b/arch/arm/boot/dts/at91-sama7g5ek.dts index 0e1975c6812e..50f0fc3064cc 100644 --- a/arch/arm/boot/dts/at91-sama7g5ek.dts +++ b/arch/arm/boot/dts/at91-sama7g5ek.dts @@ -236,7 +236,7 @@ regulator-state-mem { vddcpu: VDD_OTHER { regulator-name = "VDD_OTHER"; - regulator-min-microvolt = <1125000>; + regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1850000>; regulator-initial-mode = <2>; regulator-allowed-modes = <2>, <4>; From patchwork Thu Jan 13 14:48:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12712822 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2FFE8C433FE for ; Thu, 13 Jan 2022 14:48:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235811AbiAMOsV (ORCPT ); Thu, 13 Jan 2022 09:48:21 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:31616 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235842AbiAMOsS (ORCPT ); Thu, 13 Jan 2022 09:48:18 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1642085298; x=1673621298; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=e/cwdosIfY/Ui806k1VNdWFJdNXS6zlz9aSSIH3faKE=; b=GLIh9KgRuduoXDG5kSXfyQacrvAO6XI0UVXb37MArRQIxK+bbYdIckIO f1kkq+8otZ5hkkzSVL+jtLRKFK3f3aokXOPrKdv9C36UwOLiNhuxNebqa xP/aLOfV2N6aJWILDoUwi2O9zF1ptn97rFPOv0aUonnWD+OMSpLnw8Ant GHtWLXZl8eTcLRJNuGJfFHVqsbXu/1lvtO/czarPhMtJ7a+S6yzYQL4fj zNFlQI9QGzFnCmVUj6O9JMP3/sYReeN5OAbn41cLsgDHyjRUYHoP5gw3+ rtT1Qyz+5ecrVF7MwcV/LmUUtCwNLTX1Dt2SNS4aYSaO3EtIa7lFYFSl9 w==; IronPort-SDR: 47nOygoVvRVtF5FQl/YUZhdAz+JeUn+1Tlh7BvNuUto9F4AOlwiUM+KrJQaoBfqa4+77IyFnyC /t4vuFslxy25BY0cLcxlyln5wiCXwZWNahaIIKr0eFLjKsSNfim+tlSda4BdsZIwI/a7BJg+C7 Va4CorZvCgUgu/ziugvXJJJW4C7/siVs6DUMjVlcexUAxq3oQH6gYSnWPWiT0GnzYqnxvtWMqX psjIe8qUN+lAsH9vN1QsCfrFXEBwM/07PPFhBuw9C9bmGAPgE/LLG+VnwFiYojOmL5bpQ+v96h FRXGKPoG97pl7EbpDm565hWb X-IronPort-AV: E=Sophos;i="5.88,286,1635231600"; d="scan'208";a="158557547" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 Jan 2022 07:48:17 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Thu, 13 Jan 2022 07:48:17 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Thu, 13 Jan 2022 07:48:14 -0700 From: Claudiu Beznea To: , , , , , , CC: , , , , Claudiu Beznea Subject: [PATCH v2 07/10] ARM: dts: at91: sama7g5ek: set regulator voltages for standby state Date: Thu, 13 Jan 2022 16:48:57 +0200 Message-ID: <20220113144900.906370-8-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220113144900.906370-1-claudiu.beznea@microchip.com> References: <20220113144900.906370-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Set regulator voltages for standby state to avoid wrong behavior of system while in standby. The CPU voltage has been chosen as being the one corresponding to OPP=600MHz. Next commit will set the 600MHz OPP as the suspend OPP. Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/at91-sama7g5ek.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/at91-sama7g5ek.dts b/arch/arm/boot/dts/at91-sama7g5ek.dts index 50f0fc3064cc..e48da0a053ec 100644 --- a/arch/arm/boot/dts/at91-sama7g5ek.dts +++ b/arch/arm/boot/dts/at91-sama7g5ek.dts @@ -185,6 +185,7 @@ vdd_3v3: VDD_IO { regulator-state-standby { regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; regulator-mode = <4>; }; @@ -225,6 +226,7 @@ vddcore: VDD_CORE { regulator-state-standby { regulator-on-in-suspend; + regulator-suspend-voltage = <1150000>; regulator-mode = <4>; }; @@ -245,6 +247,7 @@ vddcpu: VDD_OTHER { regulator-state-standby { regulator-on-in-suspend; + regulator-suspend-voltage = <1050000>; regulator-mode = <4>; }; @@ -261,6 +264,7 @@ vldo1: LDO1 { regulator-always-on; regulator-state-standby { + regulator-suspend-voltage = <1800000>; regulator-on-in-suspend; }; @@ -275,6 +279,7 @@ vldo2: LDO2 { regulator-max-microvolt = <3700000>; regulator-state-standby { + regulator-suspend-voltage = <1800000>; regulator-on-in-suspend; }; From patchwork Thu Jan 13 14:48:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12712823 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BC845C4332F for ; Thu, 13 Jan 2022 14:48:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235862AbiAMOsX (ORCPT ); Thu, 13 Jan 2022 09:48:23 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:49494 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235864AbiAMOsV (ORCPT ); Thu, 13 Jan 2022 09:48:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1642085301; x=1673621301; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wmrtV7L4VuwJz3LYKvfoOqzB/oLK+AvKPspo/IXOTRg=; b=tVAZxe1RJCudlrkQPTNp98/rpiFJDp2/0/IOdCm6eoxMKjsab95pQ3dc smKk66+56XpaMiVBCkebcZ254iwzuCigjlUcUMsWrBcr5TBpbkcrlF5x0 MO/hz0r4GcZBYyysYJ/ntLgiVCP5m0TnTBHGkVSDKi+cmz1YJqQ2R2UFw f2/DJ3ZE47lXmQ8Bqb5f/zMyqToYFT7qOH2VYoTvfo174PKsvqPW7co12 mvnt7s11dVBLVftxBjYm6wiIgBsMD+cjBjV4w9rg8DTXDRgtlRPR4e9TH exMiqt+NEedCD41BLvUb4x3vEH1iILsCbXbqyP9MTWf1yEg+fRFLecaBo g==; IronPort-SDR: Y01vov0CloqVmI6zO3T7KbNSL5Hl3HF4+oSWEEjMWgG0z6GDUTn+CBefmhWH5dyYToI4g12tfT HsJvZcicu4/8cwgzf25hCd3gyXJYUgfnQHj9RLb5i5iwHI62Xd2e3ucLGYJCnutqOmt3AMCmcX 8qXr0bMVsElenA70OpY6I0pbBaT8Hj3XvgfGVv+y6xJrdRNZPxi4gP7hYOkCP9Jm67Xk/vzVgC HLrBptyFgn+sNLafXl61SLpKl8XXsjciHqgTJotXLAGUy5rIz6YJOAgbwh2R+jNLVupXhPWrVB HSDW+pV7/b/pe8n69MYavpOC X-IronPort-AV: E=Sophos;i="5.88,286,1635231600"; d="scan'208";a="149554008" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 Jan 2022 07:48:20 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Thu, 13 Jan 2022 07:48:20 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Thu, 13 Jan 2022 07:48:17 -0700 From: Claudiu Beznea To: , , , , , , CC: , , , , Claudiu Beznea Subject: [PATCH v2 08/10] ARM: dts: at91: sama7g5: add opps Date: Thu, 13 Jan 2022 16:48:58 +0200 Message-ID: <20220113144900.906370-9-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220113144900.906370-1-claudiu.beznea@microchip.com> References: <20220113144900.906370-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add OPPs for SAMA7G5 along with clock for CPU. Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/sama7g5.dtsi | 38 ++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi index 7039311bf678..21694519155e 100644 --- a/arch/arm/boot/dts/sama7g5.dtsi +++ b/arch/arm/boot/dts/sama7g5.dtsi @@ -30,6 +30,44 @@ cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x0>; + clocks = <&pmc PMC_TYPE_CORE PMC_CPUPLL>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; + }; + }; + + cpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-90000000 { + opp-hz = /bits/ 64 <90000000>; + opp-microvolt = <1050000 1050000 1225000>; + clock-latency-ns = <320000>; + }; + + opp-250000000 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <1050000 1050000 1225000>; + clock-latency-ns = <320000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1050000 1050000 1225000>; + clock-latency-ns = <320000>; + opp-suspend; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1150000 1125000 1225000>; + clock-latency-ns = <320000>; + }; + + opp-1000000002 { + opp-hz = /bits/ 64 <1000000002>; + opp-microvolt = <1250000 1225000 1300000>; + clock-latency-ns = <320000>; }; }; From patchwork Thu Jan 13 14:48:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12712824 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C4442C433FE for ; Thu, 13 Jan 2022 14:48:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229870AbiAMOs3 (ORCPT ); Thu, 13 Jan 2022 09:48:29 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:19904 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235791AbiAMOsY (ORCPT ); Thu, 13 Jan 2022 09:48:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1642085304; x=1673621304; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=bDlilDU1skIyaD7A5u8m29rcVwAwQx5M9HD/l01CDFo=; b=2h3Xvd3rWyUy7KoezCN/kRBWE9Y624W7UwktKK6xRPoTCEHc+xJ4jjdJ Jf7bXDwcEkCP4X4xzf38XaxLXDNFtqd+drUpt0nKmRKu87PBaOMuApomJ su5dBTciHS0fTxjA3ZuB2rynQTksMpxrcYRyibd6/9JlDSoimFtaWJGiK AuTHSFTvBPhS9U9hKRfbO9A7gLQ1UZKmg2lF71exUEdEEYmzcAzi5VCyz dqiPYy+15IVvKbtsaS/NrYEU+1KTy8uZ0p480dWl/lL5aRw4d03h2mEcN ClQ90i5dihvgFOAWyh4/1ywJierodsEOQ26nGXZnAwzGdSsnx7jKdvBmz A==; IronPort-SDR: fn1VzKeICIFExi/unB8UW687rfNdm9rrvris/JE4fKrGQ2h79X/rMTiQhD5mb8FBs48oEBs98T M9SAuHTha5uErxTLyMeASAoIeGbsaVL3KbUtVsxtpvNGqNpivXcVn4X5+EcYidSBeC6IlMOh5W SkJKNeVnQlw0ACTJygmVYKBlV8Nh/yD86pcI/xfq0sNflKfUcIqYo71sZIDFnikdOsbkFVKy7m cm80LfhbUEVldqTzHCPBjkMuTK4A5+RsR/1BNUFnIq6ndl/sMNt4wb/egR6R2VUpMqskxMAxM0 Wv4Xc5VUf3qgsSff9P7fp8J5 X-IronPort-AV: E=Sophos;i="5.88,286,1635231600"; d="scan'208";a="150108244" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 Jan 2022 07:48:24 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Thu, 13 Jan 2022 07:48:23 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Thu, 13 Jan 2022 07:48:20 -0700 From: Claudiu Beznea To: , , , , , , CC: , , , , Claudiu Beznea Subject: [PATCH v2 09/10] ARM: configs: at91: sama7: enable cpu idle Date: Thu, 13 Jan 2022 16:48:59 +0200 Message-ID: <20220113144900.906370-10-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220113144900.906370-1-claudiu.beznea@microchip.com> References: <20220113144900.906370-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Enable CPU idle support for SAMA7 config. Signed-off-by: Claudiu Beznea --- arch/arm/configs/sama7_defconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/configs/sama7_defconfig b/arch/arm/configs/sama7_defconfig index 938aae4bd80b..95c2a7ed4816 100644 --- a/arch/arm/configs/sama7_defconfig +++ b/arch/arm/configs/sama7_defconfig @@ -26,6 +26,7 @@ CONFIG_FORCE_MAX_ZONEORDER=15 CONFIG_UACCESS_WITH_MEMCPY=y # CONFIG_ATAGS is not set CONFIG_CMDLINE="console=ttyS0,115200 earlyprintk ignore_loglevel" +CONFIG_CPU_IDLE=y CONFIG_VFP=y CONFIG_NEON=y CONFIG_KERNEL_MODE_NEON=y @@ -33,7 +34,6 @@ CONFIG_MODULES=y CONFIG_MODULE_FORCE_LOAD=y CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y -# CONFIG_BLK_DEV_BSG is not set CONFIG_PARTITION_ADVANCED=y # CONFIG_EFI_PARTITION is not set # CONFIG_COREDUMP is not set @@ -90,6 +90,7 @@ CONFIG_BLK_DEV_RAM_SIZE=8192 CONFIG_EEPROM_AT24=y CONFIG_SCSI=y CONFIG_BLK_DEV_SD=y +# CONFIG_BLK_DEV_BSG is not set CONFIG_NETDEVICES=y CONFIG_MACB=y CONFIG_MICREL_PHY=y From patchwork Thu Jan 13 14:49:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12712825 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9E44C433FE for ; Thu, 13 Jan 2022 14:48:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235897AbiAMOsb (ORCPT ); Thu, 13 Jan 2022 09:48:31 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:49512 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235878AbiAMOs1 (ORCPT ); Thu, 13 Jan 2022 09:48:27 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1642085307; x=1673621307; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lEArm4L3rzKNYcbWHVsHPV1Ug//Fk01TwtXeWoxZlLg=; b=FF6Pnt6+wsEPhuGxHBukvVkYhiRMDDHV9pl8mpsz1g/oTkAV35yqhiK4 9SaUdu7aByQeQgRm9SdLA5ekoRsXITpHr2Imv8Uhxbdexl5Q4EmOWDF2T eCcOf0HGjFBAnfn9K4uxl+nKXsZRA0Yga0fwPDyyG+bKh7D48iyhRb3ld FYvqrcHSdJX8s9NT955l6mwkf3mg0YX9KigM8KWoSnEKhlJm2xAofZW5z ziJDncXFeiVz4FB6w97RgCNTyoEgYRft1oh2dAbCgKFwjS408Qvypkjrj plNBA2yoPgurQ1BpfWi4hN2rocp/DilxOvtPa/X47bT+JdhdkWIFSBSyJ Q==; IronPort-SDR: YGM0nHaHAI2bAtgvwl598GXQEWbb0V/t6ql6Z3K500t0G2iBrkapz6toIuhG+cjg1sycrPDeQV vmo5XpNUfwNJZSW6qvn6aoYvO7Teujk3G+3rOVCBmZAd2N2HYkCGSo9wmHBbbfaoxB3OurRgZU KwCM2hMyRwi3J7BotMHLOgS6t+BPrMwoNbyS8gtPibbdVRqWFp9pe73uBld207toyxk6Q3VsO/ hp4YFDfGsTFqOwxXydzW9nLYzGSVBvDqWGveKjnMgAaHG/o1PjYfP9z6QPxr3FAIQvwuDkrOsT LnON+71vVuRFPAOiGVyihvOv X-IronPort-AV: E=Sophos;i="5.88,286,1635231600"; d="scan'208";a="149554035" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 Jan 2022 07:48:26 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Thu, 13 Jan 2022 07:48:26 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Thu, 13 Jan 2022 07:48:23 -0700 From: Claudiu Beznea To: , , , , , , CC: , , , , Claudiu Beznea Subject: [PATCH v2 10/10] ARM: configs: at91: sama7: add config for cpufreq Date: Thu, 13 Jan 2022 16:49:00 +0200 Message-ID: <20220113144900.906370-11-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220113144900.906370-1-claudiu.beznea@microchip.com> References: <20220113144900.906370-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add config flags for CPUFreq. This includes enabling CPUFreq support, CPUFreq DT driver and governors, default one being the conservative governor. Signed-off-by: Claudiu Beznea --- arch/arm/configs/sama7_defconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/configs/sama7_defconfig b/arch/arm/configs/sama7_defconfig index 95c2a7ed4816..689e9afcb5b2 100644 --- a/arch/arm/configs/sama7_defconfig +++ b/arch/arm/configs/sama7_defconfig @@ -26,6 +26,12 @@ CONFIG_FORCE_MAX_ZONEORDER=15 CONFIG_UACCESS_WITH_MEMCPY=y # CONFIG_ATAGS is not set CONFIG_CMDLINE="console=ttyS0,115200 earlyprintk ignore_loglevel" +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPUFREQ_DT=y CONFIG_CPU_IDLE=y CONFIG_VFP=y CONFIG_NEON=y