From patchwork Tue Jan 18 17:25:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Cameron X-Patchwork-Id: 12716736 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34F8DC433EF for ; Tue, 18 Jan 2022 17:25:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346665AbiARRZV (ORCPT ); Tue, 18 Jan 2022 12:25:21 -0500 Received: from frasgout.his.huawei.com ([185.176.79.56]:4428 "EHLO frasgout.his.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243633AbiARRZT (ORCPT ); Tue, 18 Jan 2022 12:25:19 -0500 Received: from fraeml706-chm.china.huawei.com (unknown [172.18.147.200]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4JdbDg06yDz67Vhh; Wed, 19 Jan 2022 01:22:11 +0800 (CST) Received: from lhreml710-chm.china.huawei.com (10.201.108.61) by fraeml706-chm.china.huawei.com (10.206.15.55) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.21; Tue, 18 Jan 2022 18:25:16 +0100 Received: from SecurePC-101-06.china.huawei.com (10.122.247.231) by lhreml710-chm.china.huawei.com (10.201.108.61) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.21; Tue, 18 Jan 2022 17:25:16 +0000 From: Jonathan Cameron To: , Martin Mares , Bjorn Helgaas CC: Ira Weiny , Dan Williams , Subject: [PATCH 1/1] pciutils: Add decode support for Data Object Exchange Extended Capability Date: Tue, 18 Jan 2022 17:25:15 +0000 Message-ID: <20220118172515.18839-1-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.32.0 MIME-Version: 1.0 X-Originating-IP: [10.122.247.231] X-ClientProxiedBy: lhreml740-chm.china.huawei.com (10.201.108.190) To lhreml710-chm.china.huawei.com (10.201.108.61) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org PCI Data Object Exchange [1] provides a mailbox interface used as the transport for various protocols defined by PCI-SIG and others. Make the limited information in config space available. Note the Read/Write Mailbox registers themselves are not currently parsed as the usefulness of accessing one dword of a protocol is probably limited. In future, operating systems may provide means to safely query the supported protocols, but those have not yet been defined. Example output: Capabilities: [190 v1] Data Object Exchange DOECap: IntSup:+ Interrupt Message Number: 001 DOECtl: IntEn:- DOESta: Busy:- IntSta:- Error:- ObjectReady:- [1] Data Object Exchange (DOE) ECN, approved 12 March 2020 Signed-off-by: Jonathan Cameron --- lib/header.h | 15 +++ ls-ecaps.c | 38 +++++++ tests/cap-doe | 302 ++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 355 insertions(+) diff --git a/lib/header.h b/lib/header.h index d4b40aa..85414bc 100644 --- a/lib/header.h +++ b/lib/header.h @@ -252,6 +252,7 @@ #define PCI_EXT_CAP_ID_LMR 0x27 /* Lane Margining at Receiver */ #define PCI_EXT_CAP_ID_HIER_ID 0x28 /* Hierarchy ID */ #define PCI_EXT_CAP_ID_NPEM 0x29 /* Native PCIe Enclosure Management */ +#define PCI_EXT_CAP_ID_DOE 0x2e /* Data Object Exchange */ /*** Definitions of capabilities ***/ @@ -1253,6 +1254,20 @@ #define PCI_L1PM_SUBSTAT_CTL1_ASPM_L11 0x8 /* ASPM L1.1 Enable */ #define PCI_L1PM_SUBSTAT_CTL2 0xC /* L1 PM Substate Control 2 */ +/* Data Object Exchange Extended Capability */ +#define PCI_DOE_CAP 0x4 /* DOE Capabilities Register */ +#define PCI_DOE_CAP_INT_SUPP 0x1 /* Interrupt Support */ +#define PCI_DOE_CAP_INT_MSG(x) (((x) >> 1) & 0x7ff) /* DOE Interrupt Message Number */ +#define PCI_DOE_CTL 0x8 /* DOE Control Register */ +#define PCI_DOE_CTL_ABORT 0x1 /* DOE Abort */ +#define PCI_DOE_CTL_INT 0x2 /* DOE Interrupt Enable */ +#define PCI_DOE_CTL_GO 0x80000000 /* DOE Go */ +#define PCI_DOE_STS 0xC /* DOE Status Register */ +#define PCI_DOE_STS_BUSY 0x1 /* DOE Busy */ +#define PCI_DOE_STS_INT 0x2 /* DOE Interrupt Status */ +#define PCI_DOE_STS_ERROR 0x3 /* DOE Error */ +#define PCI_DOE_STS_OBJECT_READY 0x80000000 /* Data Object Ready */ + /* * The PCI interface treats multi-function devices as independent * devices. The slot/function address of each device is encoded diff --git a/ls-ecaps.c b/ls-ecaps.c index 99c55ff..dd328c3 100644 --- a/ls-ecaps.c +++ b/ls-ecaps.c @@ -992,6 +992,41 @@ cap_rebar(struct device *d, int where, int virtual) } } +static void +cap_doe(struct device *d, int where) +{ + u32 l; + + printf("Data Object Exchange\n"); + + if (verbose < 2) + return; + + if (!config_fetch(d, where + PCI_DOE_CAP, 0x14)) + { + printf("\t\t\n"); + return; + } + + l = get_conf_long(d, where + PCI_DOE_CAP); + printf("\t\tDOECap: IntSup:%c\n", + FLAG(l, PCI_DOE_CAP_INT_SUPP)); + if (l & PCI_DOE_CAP_INT_SUPP) + printf("\t\t\tInterrupt Message Number: %03x\n", + PCI_DOE_CAP_INT_MSG(l)); + + l = get_conf_long(d, where + PCI_DOE_CTL); + printf("\t\tDOECtl: IntEn:%c\n", + FLAG(l, PCI_DOE_CTL_INT)); + + l = get_conf_long(d, where + PCI_DOE_STS); + printf("\t\tDOESta: Busy:%c IntSta:%c Error:%c ObjectReady:%c\n", + FLAG(l, PCI_DOE_STS_BUSY), + FLAG(l, PCI_DOE_STS_INT), + FLAG(l, PCI_DOE_STS_ERROR), + FLAG(l, PCI_DOE_STS_OBJECT_READY)); +} + void show_ext_caps(struct device *d, int type) { @@ -1139,6 +1174,9 @@ show_ext_caps(struct device *d, int type) case PCI_EXT_CAP_ID_NPEM: printf("Native PCIe Enclosure Management \n"); break; + case PCI_EXT_CAP_ID_DOE: + cap_doe(d, where); + break; default: printf("Extended Capability ID %#02x\n", id); break; diff --git a/tests/cap-doe b/tests/cap-doe new file mode 100644 index 0000000..4edc3e7 --- /dev/null +++ b/tests/cap-doe @@ -0,0 +1,302 @@ +df:00.0 Memory controller [0502]: Intel Corporation Device 0d93 (rev 01) (prog-if 10) + Subsystem: Red Hat, Inc. Device 1100 + Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- + Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR-