From patchwork Wed Jan 19 13:40:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Stach X-Patchwork-Id: 12717541 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 45484C433F5 for ; Wed, 19 Jan 2022 13:42:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=0Slzd10cD6y+CbpwIIsOE2490MIrGg6ERvc4xqXqCDo=; b=rZZTLtRB1vJpYm 2NHDS4yoy+glN+XCuflQsMcC43UtYsP9/0PFh4iIcOpcwlsAy5M39gSBk3iCEF99UROa6nXxvY9Vv 9lmjpYDs3uSWHG8bQY086W0vCRtrMzCt09ggzQ7+d8keBPbheyKxyBDbYNShg9wYVqZwtHssZMOqA 0h4ARItexw37xnPHRJiI8NRMDeytOuF4OsuvYINGvSnAN1cyYZdGWr+UI9wH6H3BPUbVVZqLAmNVT W1GdjWWvXyDuYRbkNBL0B3CJsK5Yr1CSv6BFNtPAMVYJs/n7MZ2Ll1PXTkL8M8cE0diJBcbpl+Sa6 oq1WZX8beHTDMjc2MZsw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nABCt-005fPt-0i; Wed, 19 Jan 2022 13:40:59 +0000 Received: from metis.ext.pengutronix.de ([2001:67c:670:201:290:27ff:fe1d:cc33]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nABCU-005fJL-Rx for linux-arm-kernel@lists.infradead.org; Wed, 19 Jan 2022 13:40:36 +0000 Received: from dude03.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::39]) by metis.ext.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1nABCO-0006Kr-Uo; Wed, 19 Jan 2022 14:40:29 +0100 From: Lucas Stach To: Shawn Guo , Rob Herring Cc: Pengutronix Kernel Team , NXP Linux Team , Fabio Estevam , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, patchwork-lst@pengutronix.de Subject: [PATCH 1/9] soc: imx: gpcv2: add PGC control register indirection Date: Wed, 19 Jan 2022 14:40:19 +0100 Message-Id: <20220119134027.2931945-2-l.stach@pengutronix.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220119134027.2931945-1-l.stach@pengutronix.de> References: <20220119134027.2931945-1-l.stach@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:1101:1d::39 X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220119_054034_928933_AB3BFBA5 X-CRM114-Status: GOOD ( 15.68 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The PGC control registers in the shared (not per-PGC) region of the GPC address space have different offsets on i.MX8MP to make space for additional interrupt control registers. Signed-off-by: Lucas Stach --- drivers/soc/imx/gpcv2.c | 43 ++++++++++++++++++++++++++++++----------- 1 file changed, 32 insertions(+), 11 deletions(-) diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index b8d52d8d29db..03d988b900ce 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -184,9 +184,17 @@ #define GPC_PGC_CTRL_PCR BIT(0) +struct imx_pgc_regs { + u16 map; + u16 pup; + u16 pdn; + u16 hsk; +}; + struct imx_pgc_domain { struct generic_pm_domain genpd; struct regmap *regmap; + const struct imx_pgc_regs *regs; struct regulator *regulator; struct reset_control *reset; struct clk_bulk_data *clks; @@ -210,6 +218,7 @@ struct imx_pgc_domain_data { const struct imx_pgc_domain *domains; size_t domains_num; const struct regmap_access_table *reg_access_table; + const struct imx_pgc_regs *pgc_regs; }; static inline struct imx_pgc_domain * @@ -249,14 +258,14 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd) if (domain->bits.pxx) { /* request the domain to power up */ - regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PUP_REQ, + regmap_update_bits(domain->regmap, domain->regs->pup, domain->bits.pxx, domain->bits.pxx); /* * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait * for PUP_REQ/PDN_REQ bit to be cleared */ ret = regmap_read_poll_timeout(domain->regmap, - GPC_PU_PGC_SW_PUP_REQ, reg_val, + domain->regs->pup, reg_val, !(reg_val & domain->bits.pxx), 0, USEC_PER_MSEC); if (ret) { @@ -278,11 +287,11 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd) /* request the ADB400 to power up */ if (domain->bits.hskreq) { - regmap_update_bits(domain->regmap, GPC_PU_PWRHSK, + regmap_update_bits(domain->regmap, domain->regs->hsk, domain->bits.hskreq, domain->bits.hskreq); /* - * ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PWRHSK, reg_val, + * ret = regmap_read_poll_timeout(domain->regmap, domain->regs->hsk, reg_val, * (reg_val & domain->bits.hskack), 0, * USEC_PER_MSEC); * Technically we need the commented code to wait handshake. But that needs @@ -329,10 +338,10 @@ static int imx_pgc_power_down(struct generic_pm_domain *genpd) /* request the ADB400 to power down */ if (domain->bits.hskreq) { - regmap_clear_bits(domain->regmap, GPC_PU_PWRHSK, + regmap_clear_bits(domain->regmap, domain->regs->hsk, domain->bits.hskreq); - ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PWRHSK, + ret = regmap_read_poll_timeout(domain->regmap, domain->regs->hsk, reg_val, !(reg_val & domain->bits.hskack), 0, USEC_PER_MSEC); @@ -350,14 +359,14 @@ static int imx_pgc_power_down(struct generic_pm_domain *genpd) } /* request the domain to power down */ - regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PDN_REQ, + regmap_update_bits(domain->regmap, domain->regs->pdn, domain->bits.pxx, domain->bits.pxx); /* * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait * for PUP_REQ/PDN_REQ bit to be cleared */ ret = regmap_read_poll_timeout(domain->regmap, - GPC_PU_PGC_SW_PDN_REQ, reg_val, + domain->regs->pdn, reg_val, !(reg_val & domain->bits.pxx), 0, USEC_PER_MSEC); if (ret) { @@ -441,10 +450,18 @@ static const struct regmap_access_table imx7_access_table = { .n_yes_ranges = ARRAY_SIZE(imx7_yes_ranges), }; +static const struct imx_pgc_regs imx7_pgc_regs = { + .map = GPC_PGC_CPU_MAPPING, + .pup = GPC_PU_PGC_SW_PUP_REQ, + .pdn = GPC_PU_PGC_SW_PDN_REQ, + .hsk = GPC_PU_PWRHSK, +}; + static const struct imx_pgc_domain_data imx7_pgc_domain_data = { .domains = imx7_pgc_domains, .domains_num = ARRAY_SIZE(imx7_pgc_domains), .reg_access_table = &imx7_access_table, + .pgc_regs = &imx7_pgc_regs, }; static const struct imx_pgc_domain imx8m_pgc_domains[] = { @@ -613,6 +630,7 @@ static const struct imx_pgc_domain_data imx8m_pgc_domain_data = { .domains = imx8m_pgc_domains, .domains_num = ARRAY_SIZE(imx8m_pgc_domains), .reg_access_table = &imx8m_access_table, + .pgc_regs = &imx7_pgc_regs, }; static const struct imx_pgc_domain imx8mm_pgc_domains[] = { @@ -802,6 +820,7 @@ static const struct imx_pgc_domain_data imx8mm_pgc_domain_data = { .domains = imx8mm_pgc_domains, .domains_num = ARRAY_SIZE(imx8mm_pgc_domains), .reg_access_table = &imx8mm_access_table, + .pgc_regs = &imx7_pgc_regs, }; static const struct imx_pgc_domain imx8mn_pgc_domains[] = { @@ -867,6 +886,7 @@ static const struct imx_pgc_domain_data imx8mn_pgc_domain_data = { .domains = imx8mn_pgc_domains, .domains_num = ARRAY_SIZE(imx8mn_pgc_domains), .reg_access_table = &imx8mn_access_table, + .pgc_regs = &imx7_pgc_regs, }; static int imx_pgc_domain_probe(struct platform_device *pdev) @@ -899,7 +919,7 @@ static int imx_pgc_domain_probe(struct platform_device *pdev) pm_runtime_enable(domain->dev); if (domain->bits.map) - regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, + regmap_update_bits(domain->regmap, domain->regs->map, domain->bits.map, domain->bits.map); ret = pm_genpd_init(&domain->genpd, NULL, true); @@ -925,7 +945,7 @@ static int imx_pgc_domain_probe(struct platform_device *pdev) pm_genpd_remove(&domain->genpd); out_domain_unmap: if (domain->bits.map) - regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, + regmap_update_bits(domain->regmap, domain->regs->map, domain->bits.map, 0); pm_runtime_disable(domain->dev); @@ -940,7 +960,7 @@ static int imx_pgc_domain_remove(struct platform_device *pdev) pm_genpd_remove(&domain->genpd); if (domain->bits.map) - regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, + regmap_update_bits(domain->regmap, domain->regs->map, domain->bits.map, 0); pm_runtime_disable(domain->dev); @@ -1071,6 +1091,7 @@ static int imx_gpcv2_probe(struct platform_device *pdev) domain = pd_pdev->dev.platform_data; domain->regmap = regmap; + domain->regs = domain_data->pgc_regs; domain->genpd.power_on = imx_pgc_power_up; domain->genpd.power_off = imx_pgc_power_down; From patchwork Wed Jan 19 13:40:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Stach X-Patchwork-Id: 12717543 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 00D1DC433EF for ; Wed, 19 Jan 2022 13:42:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Fl6RxZSOq53KurVBUnbt2ExCknqKQzrdcWeDBhN7cJw=; b=MpncafaSM4oTiK rDCuP7RHPOZNimeuJO5K/JHna2y3rd2XRsLyTZR/5dZhy8WCzXpgiEZK7bXiJ9nOsCc8p24l+BZ7m sKQy1xeWsUnBJi1NKLKamMef4IRfvYexaOf6aOqWsYKQ4pILXN67ZRxbhiIuCURH6TG2b1UpRkWkS LsTIzRwqVzgxal1Y4H7Rqwfvr5B5Ey6GkewV33jpTFWJ+bUwAfvYb6hU7bbaR+iPnWkhElb8nlVfJ WVen9g8P6BPxvYPePnulP+g7/Vn/kzSaCLKSqUsIzaWmKwyZTZa6D7oBoNHE7EDqfDzP+O1kiV4QB yza+5Q2+f6augI5p/MxA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nABDF-005fX3-NJ; Wed, 19 Jan 2022 13:41:21 +0000 Received: from metis.ext.pengutronix.de ([2001:67c:670:201:290:27ff:fe1d:cc33]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nABCW-005fKJ-OA for linux-arm-kernel@lists.infradead.org; Wed, 19 Jan 2022 13:40:38 +0000 Received: from dude03.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::39]) by metis.ext.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1nABCP-0006Kr-Fk; Wed, 19 Jan 2022 14:40:29 +0100 From: Lucas Stach To: Shawn Guo , Rob Herring Cc: Pengutronix Kernel Team , NXP Linux Team , Fabio Estevam , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, patchwork-lst@pengutronix.de Subject: [PATCH 2/9] dt-bindings: power: add defines for i.MX8MP power domain Date: Wed, 19 Jan 2022 14:40:20 +0100 Message-Id: <20220119134027.2931945-3-l.stach@pengutronix.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220119134027.2931945-1-l.stach@pengutronix.de> References: <20220119134027.2931945-1-l.stach@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:1101:1d::39 X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220119_054036_870142_05143D34 X-CRM114-Status: GOOD ( 14.37 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This adds the DT defines for the GPC power domains found on the i.MX8MP SoC. Signed-off-by: Lucas Stach --- .../bindings/power/fsl,imx-gpcv2.yaml | 2 ++ include/dt-bindings/power/imx8mp-power.h | 29 +++++++++++++++++++ 2 files changed, 31 insertions(+) create mode 100644 include/dt-bindings/power/imx8mp-power.h diff --git a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml b/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml index 01bdda167eef..747622bdc57b 100644 --- a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml +++ b/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml @@ -28,6 +28,7 @@ properties: - fsl,imx8mn-gpc - fsl,imx8mq-gpc - fsl,imx8mm-gpc + - fsl,imx8mp-gpc reg: maxItems: 1 @@ -57,6 +58,7 @@ properties: include/dt-bindings/power/imx7-power.h for fsl,imx7d-gpc and include/dt-bindings/power/imx8m-power.h for fsl,imx8mq-gpc include/dt-bindings/power/imx8mm-power.h for fsl,imx8mm-gpc + include/dt-bindings/power/imx8mp-power.h for fsl,imx8mp-gpc maxItems: 1 clocks: diff --git a/include/dt-bindings/power/imx8mp-power.h b/include/dt-bindings/power/imx8mp-power.h new file mode 100644 index 000000000000..7c67689e4faf --- /dev/null +++ b/include/dt-bindings/power/imx8mp-power.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (C) 2020 Pengutronix, Sascha Hauer + */ + +#ifndef __DT_BINDINGS_IMX8MP_POWER_DOMAIN_POWER_H__ +#define __DT_BINDINGS_IMX8MP_POWER_DOMAIN_POWER_H__ + +#define IMX8MP_POWER_DOMAIN_MIPI_PHY1 0 +#define IMX8MP_POWER_DOMAIN_PCIE_PHY 1 +#define IMX8MP_POWER_DOMAIN_USB1_PHY 2 +#define IMX8MP_POWER_DOMAIN_USB2_PHY 3 +#define IMX8MP_POWER_DOMAIN_MLMIX 4 +#define IMX8MP_POWER_DOMAIN_AUDIOMIX 5 +#define IMX8MP_POWER_DOMAIN_GPU2D 6 +#define IMX8MP_POWER_DOMAIN_GPUMIX 7 +#define IMX8MP_POWER_DOMAIN_VPUMIX 8 +#define IMX8MP_POWER_DOMAIN_GPU3D 9 +#define IMX8MP_POWER_DOMAIN_MEDIAMIX 10 +#define IMX8MP_POWER_DOMAIN_VPU_G1 11 +#define IMX8MP_POWER_DOMAIN_VPU_G2 12 +#define IMX8MP_POWER_DOMAIN_VPU_VC8000E 13 +#define IMX8MP_POWER_DOMAIN_HDMIMIX 14 +#define IMX8MP_POWER_DOMAIN_HDMI_PHY 15 +#define IMX8MP_POWER_DOMAIN_MIPI_PHY2 16 +#define IMX8MP_POWER_DOMAIN_HSIOMIX 17 +#define IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP 18 + +#endif From patchwork Wed Jan 19 13:40:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Stach X-Patchwork-Id: 12717544 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 878C5C433EF for ; Wed, 19 Jan 2022 13:42:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=i0D7wK2z8qgaZsmROVn4yURTI/SghgMngxddBpxzpwU=; b=DQSO8C8BZbLDcm AX44O85/khJhLd4ICsLeq1ai9l68s4LQPOkGox+2DvF4/RFSz+AE0jVgqRs4JdSxe/SYFRT7zJoNa 8RqDFx5o68Kyb4PcpXoD3cCbqLFNnKtcv4DjQCzOLnhmlT2xOvisPcQOWZ27z9aOYek6fvYg81Qd/ HfVH1Pp9pzgH6K556HSAROA3H/wvCPYEg6H7RTXTg7PwwZek1tJy+S74yP8+nzcE2n7rb+nuWA+Co vvNKOVA4nVGa2of1yDZ180Sk0nl4AYaTuUTQQncJjMfGB5Bwhxd5Ttt5LgBuvxTTvpneVdEdkFJvg 3W2nBlBsSZ0uNqo61heg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nABDS-005fcN-Vz; Wed, 19 Jan 2022 13:41:35 +0000 Received: from metis.ext.pengutronix.de ([2001:67c:670:201:290:27ff:fe1d:cc33]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nABCW-005fKE-0t for linux-arm-kernel@lists.infradead.org; Wed, 19 Jan 2022 13:40:38 +0000 Received: from dude03.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::39]) by metis.ext.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1nABCQ-0006Kr-0y; Wed, 19 Jan 2022 14:40:30 +0100 From: Lucas Stach To: Shawn Guo , Rob Herring Cc: Pengutronix Kernel Team , NXP Linux Team , Fabio Estevam , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, patchwork-lst@pengutronix.de Subject: [PATCH 3/9] soc: imx: gpcv2: add support for i.MX8MP power domains Date: Wed, 19 Jan 2022 14:40:21 +0100 Message-Id: <20220119134027.2931945-4-l.stach@pengutronix.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220119134027.2931945-1-l.stach@pengutronix.de> References: <20220119134027.2931945-1-l.stach@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:1101:1d::39 X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220119_054036_417580_19075E7D X-CRM114-Status: GOOD ( 17.68 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This adds driver support for all the GPC power domains found on the i.MX8MP SoC. Signed-off-by: Lucas Stach --- drivers/soc/imx/gpcv2.c | 387 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 386 insertions(+), 1 deletion(-) diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index 03d988b900ce..736160a7882a 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -21,10 +21,12 @@ #include #include #include +#include #define GPC_LPCR_A_CORE_BSC 0x000 #define GPC_PGC_CPU_MAPPING 0x0ec +#define IMX8MP_GPC_PGC_CPU_MAPPING 0x1cc #define IMX7_USB_HSIC_PHY_A_CORE_DOMAIN BIT(6) #define IMX7_USB_OTG2_PHY_A_CORE_DOMAIN BIT(5) @@ -65,6 +67,29 @@ #define IMX8MN_OTG1_A53_DOMAIN BIT(4) #define IMX8MN_MIPI_A53_DOMAIN BIT(2) +#define IMX8MP_MEDIA_ISPDWP_A53_DOMAIN BIT(20) +#define IMX8MP_HSIOMIX_A53_DOMAIN BIT(19) +#define IMX8MP_MIPI_PHY2_A53_DOMAIN BIT(18) +#define IMX8MP_HDMI_PHY_A53_DOMAIN BIT(17) +#define IMX8MP_HDMIMIX_A53_DOMAIN BIT(16) +#define IMX8MP_VPU_VC8000E_A53_DOMAIN BIT(15) +#define IMX8MP_VPU_G2_A53_DOMAIN BIT(14) +#define IMX8MP_VPU_G1_A53_DOMAIN BIT(13) +#define IMX8MP_MEDIAMIX_A53_DOMAIN BIT(12) +#define IMX8MP_GPU3D_A53_DOMAIN BIT(11) +#define IMX8MP_VPUMIX_A53_DOMAIN BIT(10) +#define IMX8MP_GPUMIX_A53_DOMAIN BIT(9) +#define IMX8MP_GPU2D_A53_DOMAIN BIT(8) +#define IMX8MP_AUDIOMIX_A53_DOMAIN BIT(7) +#define IMX8MP_MLMIX_A53_DOMAIN BIT(6) +#define IMX8MP_USB2_PHY_A53_DOMAIN BIT(5) +#define IMX8MP_USB1_PHY_A53_DOMAIN BIT(4) +#define IMX8MP_PCIE_PHY_A53_DOMAIN BIT(3) +#define IMX8MP_MIPI_PHY1_A53_DOMAIN BIT(2) + +#define IMX8MP_GPC_PU_PGC_SW_PUP_REQ 0x0d8 +#define IMX8MP_GPC_PU_PGC_SW_PDN_REQ 0x0e4 + #define GPC_PU_PGC_SW_PUP_REQ 0x0f8 #define GPC_PU_PGC_SW_PDN_REQ 0x104 @@ -107,8 +132,30 @@ #define IMX8MN_OTG1_SW_Pxx_REQ BIT(2) #define IMX8MN_MIPI_SW_Pxx_REQ BIT(0) +#define IMX8MP_DDRMIX_Pxx_REQ BIT(19) +#define IMX8MP_MEDIA_ISP_DWP_Pxx_REQ BIT(18) +#define IMX8MP_HSIOMIX_Pxx_REQ BIT(17) +#define IMX8MP_MIPI_PHY2_Pxx_REQ BIT(16) +#define IMX8MP_HDMI_PHY_Pxx_REQ BIT(15) +#define IMX8MP_HDMIMIX_Pxx_REQ BIT(14) +#define IMX8MP_VPU_VC8K_Pxx_REQ BIT(13) +#define IMX8MP_VPU_G2_Pxx_REQ BIT(12) +#define IMX8MP_VPU_G1_Pxx_REQ BIT(11) +#define IMX8MP_MEDIMIX_Pxx_REQ BIT(10) +#define IMX8MP_GPU_3D_Pxx_REQ BIT(9) +#define IMX8MP_VPU_MIX_SHARE_LOGIC_Pxx_REQ BIT(8) +#define IMX8MP_GPU_SHARE_LOGIC_Pxx_REQ BIT(7) +#define IMX8MP_GPU_2D_Pxx_REQ BIT(6) +#define IMX8MP_AUDIOMIX_Pxx_REQ BIT(5) +#define IMX8MP_MLMIX_Pxx_REQ BIT(4) +#define IMX8MP_USB2_PHY_Pxx_REQ BIT(3) +#define IMX8MP_USB1_PHY_Pxx_REQ BIT(2) +#define IMX8MP_PCIE_PHY_SW_Pxx_REQ BIT(1) +#define IMX8MP_MIPI_PHY1_SW_Pxx_REQ BIT(0) + #define GPC_M4_PU_PDN_FLG 0x1bc +#define IMX8MP_GPC_PU_PWRHSK 0x190 #define GPC_PU_PWRHSK 0x1fc #define IMX8M_GPU_HSK_PWRDNACKN BIT(26) @@ -118,7 +165,6 @@ #define IMX8M_VPU_HSK_PWRDNREQN BIT(5) #define IMX8M_DISP_HSK_PWRDNREQN BIT(4) - #define IMX8MM_GPUMIX_HSK_PWRDNACKN BIT(29) #define IMX8MM_GPU_HSK_PWRDNACKN (BIT(27) | BIT(28)) #define IMX8MM_VPUMIX_HSK_PWRDNACKN BIT(26) @@ -137,6 +183,21 @@ #define IMX8MN_DISPMIX_HSK_PWRDNREQN BIT(7) #define IMX8MN_HSIO_HSK_PWRDNREQN BIT(5) +#define IMX8MP_MEDIAMIX_PWRDNACKN BIT(3) +#define IMX8MP_HDMIMIX_PWRDNACKN BIT(29) +#define IMX8MP_HSIOMIX_PWRDNACKN BIT(28) +#define IMX8MP_VPUMIX_PWRDNACKN BIT(26) +#define IMX8MP_GPUMIX_PWRDNACKN BIT(25) +#define IMX8MP_MLMIX_PWRDNACKN (BIT(23) | BIT(24)) +#define IMX8MP_AUDIOMIX_PWRDNACKN (BIT(20) | BIT(31)) +#define IMX8MP_MEDIAMIX_PWRDNREQN BIT(14) +#define IMX8MP_HDMIMIX_PWRDNREQN BIT(13) +#define IMX8MP_HSIOMIX_PWRDNREQN BIT(12) +#define IMX8MP_VPUMIX_PWRDNREQN BIT(10) +#define IMX8MP_GPUMIX_PWRDNREQN BIT(9) +#define IMX8MP_MLMIX_PWRDNREQN (BIT(7) | BIT(8)) +#define IMX8MP_AUDIOMIX_PWRDNREQN (BIT(4) | BIT(15)) + /* * The PGC offset values in Reference Manual * (Rev. 1, 01/2018 and the older ones) GPC chapter's @@ -179,6 +240,28 @@ #define IMX8MN_PGC_GPUMIX 23 #define IMX8MN_PGC_DISPMIX 26 +#define IMX8MP_PGC_NOC 9 +#define IMX8MP_PGC_MIPI1 12 +#define IMX8MP_PGC_PCIE 13 +#define IMX8MP_PGC_USB1 14 +#define IMX8MP_PGC_USB2 15 +#define IMX8MP_PGC_MLMIX 16 +#define IMX8MP_PGC_AUDIOMIX 17 +#define IMX8MP_PGC_GPU2D 18 +#define IMX8MP_PGC_GPUMIX 19 +#define IMX8MP_PGC_VPUMIX 20 +#define IMX8MP_PGC_GPU3D 21 +#define IMX8MP_PGC_MEDIAMIX 22 +#define IMX8MP_PGC_VPU_G1 23 +#define IMX8MP_PGC_VPU_G2 24 +#define IMX8MP_PGC_VPU_VC8000E 25 +#define IMX8MP_PGC_HDMIMIX 26 +#define IMX8MP_PGC_HDMI 27 +#define IMX8MP_PGC_MIPI2 28 +#define IMX8MP_PGC_HSIOMIX 29 +#define IMX8MP_PGC_MEDIA_ISP_DWP 30 +#define IMX8MP_PGC_DDRMIX 31 + #define GPC_PGC_CTRL(n) (0x800 + (n) * 0x40) #define GPC_PGC_SR(n) (GPC_PGC_CTRL(n) + 0xc) @@ -212,6 +295,9 @@ struct imx_pgc_domain { const int voltage; const bool keep_clocks; struct device *dev; + + unsigned int pgc_sw_pup_reg; + unsigned int pgc_sw_pdn_reg; }; struct imx_pgc_domain_data { @@ -823,6 +909,303 @@ static const struct imx_pgc_domain_data imx8mm_pgc_domain_data = { .pgc_regs = &imx7_pgc_regs, }; +static const struct imx_pgc_domain imx8mp_pgc_domains[] = { + [IMX8MP_POWER_DOMAIN_MIPI_PHY1] = { + .genpd = { + .name = "mipi-phy1", + }, + .bits = { + .pxx = IMX8MP_MIPI_PHY1_SW_Pxx_REQ, + .map = IMX8MP_MIPI_PHY1_A53_DOMAIN, + }, + .pgc = BIT(IMX8MP_PGC_MIPI1), + }, + + [IMX8MP_POWER_DOMAIN_PCIE_PHY] = { + .genpd = { + .name = "pcie-phy1", + }, + .bits = { + .pxx = IMX8MP_PCIE_PHY_SW_Pxx_REQ, + .map = IMX8MP_PCIE_PHY_A53_DOMAIN, + }, + .pgc = BIT(IMX8MP_PGC_PCIE), + }, + + [IMX8MP_POWER_DOMAIN_USB1_PHY] = { + .genpd = { + .name = "usb-otg1", + }, + .bits = { + .pxx = IMX8MP_USB1_PHY_Pxx_REQ, + .map = IMX8MP_USB1_PHY_A53_DOMAIN, + }, + .pgc = BIT(IMX8MP_PGC_USB1), + }, + + [IMX8MP_POWER_DOMAIN_USB2_PHY] = { + .genpd = { + .name = "usb-otg2", + }, + .bits = { + .pxx = IMX8MP_USB2_PHY_Pxx_REQ, + .map = IMX8MP_USB2_PHY_A53_DOMAIN, + }, + .pgc = BIT(IMX8MP_PGC_USB2), + }, + + [IMX8MP_POWER_DOMAIN_MLMIX] = { + .genpd = { + .name = "mlmix", + }, + .bits = { + .pxx = IMX8MP_MLMIX_Pxx_REQ, + .map = IMX8MP_MLMIX_A53_DOMAIN, + .hskreq = IMX8MP_MLMIX_PWRDNREQN, + .hskack = IMX8MP_MLMIX_PWRDNACKN, + }, + .pgc = BIT(IMX8MP_PGC_MLMIX), + .keep_clocks = true, + }, + + [IMX8MP_POWER_DOMAIN_AUDIOMIX] = { + .genpd = { + .name = "audiomix", + }, + .bits = { + .pxx = IMX8MP_AUDIOMIX_Pxx_REQ, + .map = IMX8MP_AUDIOMIX_A53_DOMAIN, + .hskreq = IMX8MP_AUDIOMIX_PWRDNREQN, + .hskack = IMX8MP_AUDIOMIX_PWRDNACKN, + }, + .pgc = BIT(IMX8MP_PGC_AUDIOMIX), + .keep_clocks = true, + }, + + [IMX8MP_POWER_DOMAIN_GPU2D] = { + .genpd = { + .name = "gpu2d", + }, + .bits = { + .pxx = IMX8MP_GPU_2D_Pxx_REQ, + .map = IMX8MP_GPU2D_A53_DOMAIN, + }, + .pgc = BIT(IMX8MP_PGC_GPU2D), + }, + + [IMX8MP_POWER_DOMAIN_GPUMIX] = { + .genpd = { + .name = "gpumix", + }, + .bits = { + .pxx = IMX8MP_GPU_SHARE_LOGIC_Pxx_REQ, + .map = IMX8MP_GPUMIX_A53_DOMAIN, + .hskreq = IMX8MP_GPUMIX_PWRDNREQN, + .hskack = IMX8MP_GPUMIX_PWRDNACKN, + }, + .pgc = BIT(IMX8MP_PGC_GPUMIX), + .keep_clocks = true, + }, + + [IMX8MP_POWER_DOMAIN_VPUMIX] = { + .genpd = { + .name = "vpumix", + }, + .bits = { + .pxx = IMX8MP_VPU_MIX_SHARE_LOGIC_Pxx_REQ, + .map = IMX8MP_VPUMIX_A53_DOMAIN, + .hskreq = IMX8MP_VPUMIX_PWRDNREQN, + .hskack = IMX8MP_VPUMIX_PWRDNACKN, + }, + .pgc = BIT(IMX8MP_PGC_VPUMIX), + .keep_clocks = true, + }, + + [IMX8MP_POWER_DOMAIN_GPU3D] = { + .genpd = { + .name = "gpu3d", + }, + .bits = { + .pxx = IMX8MP_GPU_3D_Pxx_REQ, + .map = IMX8MP_GPU3D_A53_DOMAIN, + }, + .pgc = BIT(IMX8MP_PGC_GPU3D), + }, + + [IMX8MP_POWER_DOMAIN_MEDIAMIX] = { + .genpd = { + .name = "mediamix", + }, + .bits = { + .pxx = IMX8MP_MEDIMIX_Pxx_REQ, + .map = IMX8MP_MEDIAMIX_A53_DOMAIN, + .hskreq = IMX8MP_MEDIAMIX_PWRDNREQN, + .hskack = IMX8MP_MEDIAMIX_PWRDNACKN, + }, + .pgc = BIT(IMX8MP_PGC_MEDIAMIX), + .keep_clocks = true, + }, + + [IMX8MP_POWER_DOMAIN_VPU_G1] = { + .genpd = { + .name = "vpu-g1", + }, + .bits = { + .pxx = IMX8MP_VPU_G1_Pxx_REQ, + .map = IMX8MP_VPU_G1_A53_DOMAIN, + }, + .pgc = BIT(IMX8MP_PGC_VPU_G1), + }, + + [IMX8MP_POWER_DOMAIN_VPU_G2] = { + .genpd = { + .name = "vpu-g2", + }, + .bits = { + .pxx = IMX8MP_VPU_G2_Pxx_REQ, + .map = IMX8MP_VPU_G2_A53_DOMAIN + }, + .pgc = BIT(IMX8MP_PGC_VPU_G2), + }, + + [IMX8MP_POWER_DOMAIN_VPU_VC8000E] = { + .genpd = { + .name = "vpu-h1", + }, + .bits = { + .pxx = IMX8MP_VPU_VC8K_Pxx_REQ, + .map = IMX8MP_VPU_VC8000E_A53_DOMAIN, + }, + .pgc = BIT(IMX8MP_PGC_VPU_VC8000E), + }, + + [IMX8MP_POWER_DOMAIN_HDMIMIX] = { + .genpd = { + .name = "hdmimix", + }, + .bits = { + .pxx = IMX8MP_HDMIMIX_Pxx_REQ, + .map = IMX8MP_HDMIMIX_A53_DOMAIN, + .hskreq = IMX8MP_HDMIMIX_PWRDNREQN, + .hskack = IMX8MP_HDMIMIX_PWRDNACKN, + }, + .pgc = BIT(IMX8MP_PGC_HDMIMIX), + .keep_clocks = true, + }, + + [IMX8MP_POWER_DOMAIN_HDMI_PHY] = { + .genpd = { + .name = "hdmi-phy", + }, + .bits = { + .pxx = IMX8MP_HDMI_PHY_Pxx_REQ, + .map = IMX8MP_HDMI_PHY_A53_DOMAIN, + }, + .pgc = BIT(IMX8MP_PGC_HDMI), + }, + + [IMX8MP_POWER_DOMAIN_MIPI_PHY2] = { + .genpd = { + .name = "mipi-phy2", + }, + .bits = { + .pxx = IMX8MP_MIPI_PHY2_Pxx_REQ, + .map = IMX8MP_MIPI_PHY2_A53_DOMAIN, + }, + .pgc = BIT(IMX8MP_PGC_MIPI2), + }, + + [IMX8MP_POWER_DOMAIN_HSIOMIX] = { + .genpd = { + .name = "hsiomix", + }, + .bits = { + .pxx = IMX8MP_HSIOMIX_Pxx_REQ, + .map = IMX8MP_HSIOMIX_A53_DOMAIN, + .hskreq = IMX8MP_HSIOMIX_PWRDNREQN, + .hskack = IMX8MP_HSIOMIX_PWRDNACKN, + }, + .pgc = BIT(IMX8MP_PGC_HSIOMIX), + .keep_clocks = true, + }, + + [IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP] = { + .genpd = { + .name = "mediamix-isp-dwp", + }, + .bits = { + .pxx = IMX8MP_MEDIA_ISP_DWP_Pxx_REQ, + .map = IMX8MP_MEDIA_ISPDWP_A53_DOMAIN, + }, + .pgc = BIT(IMX8MP_PGC_MEDIA_ISP_DWP), + }, +}; + +static const struct regmap_range imx8mp_yes_ranges[] = { + regmap_reg_range(GPC_LPCR_A_CORE_BSC, + IMX8MP_GPC_PGC_CPU_MAPPING), + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_NOC), + GPC_PGC_SR(IMX8MP_PGC_NOC)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MIPI1), + GPC_PGC_SR(IMX8MP_PGC_MIPI1)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_PCIE), + GPC_PGC_SR(IMX8MP_PGC_PCIE)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_USB1), + GPC_PGC_SR(IMX8MP_PGC_USB1)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_USB2), + GPC_PGC_SR(IMX8MP_PGC_USB2)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MLMIX), + GPC_PGC_SR(IMX8MP_PGC_MLMIX)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_AUDIOMIX), + GPC_PGC_SR(IMX8MP_PGC_AUDIOMIX)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_GPU2D), + GPC_PGC_SR(IMX8MP_PGC_GPU2D)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_GPUMIX), + GPC_PGC_SR(IMX8MP_PGC_GPUMIX)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPUMIX), + GPC_PGC_SR(IMX8MP_PGC_VPUMIX)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_GPU3D), + GPC_PGC_SR(IMX8MP_PGC_GPU3D)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MEDIAMIX), + GPC_PGC_SR(IMX8MP_PGC_MEDIAMIX)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPU_G1), + GPC_PGC_SR(IMX8MP_PGC_VPU_G1)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPU_G2), + GPC_PGC_SR(IMX8MP_PGC_VPU_G2)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPU_VC8000E), + GPC_PGC_SR(IMX8MP_PGC_VPU_VC8000E)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_HDMIMIX), + GPC_PGC_SR(IMX8MP_PGC_HDMIMIX)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_HDMI), + GPC_PGC_SR(IMX8MP_PGC_HDMI)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MIPI2), + GPC_PGC_SR(IMX8MP_PGC_MIPI2)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_HSIOMIX), + GPC_PGC_SR(IMX8MP_PGC_HSIOMIX)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MEDIA_ISP_DWP), + GPC_PGC_SR(IMX8MP_PGC_MEDIA_ISP_DWP)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_DDRMIX), + GPC_PGC_SR(IMX8MP_PGC_DDRMIX)), +}; + +static const struct regmap_access_table imx8mp_access_table = { + .yes_ranges = imx8mp_yes_ranges, + .n_yes_ranges = ARRAY_SIZE(imx8mp_yes_ranges), +}; + +static const struct imx_pgc_regs imx8mp_pgc_regs = { + .map = IMX8MP_GPC_PGC_CPU_MAPPING, + .pup = IMX8MP_GPC_PU_PGC_SW_PUP_REQ, + .pdn = IMX8MP_GPC_PU_PGC_SW_PDN_REQ, + .hsk = IMX8MP_GPC_PU_PWRHSK, +}; +static const struct imx_pgc_domain_data imx8mp_pgc_domain_data = { + .domains = imx8mp_pgc_domains, + .domains_num = ARRAY_SIZE(imx8mp_pgc_domains), + .reg_access_table = &imx8mp_access_table, + .pgc_regs = &imx8mp_pgc_regs, +}; + static const struct imx_pgc_domain imx8mn_pgc_domains[] = { [IMX8MN_POWER_DOMAIN_HSIOMIX] = { .genpd = { @@ -1092,6 +1475,7 @@ static int imx_gpcv2_probe(struct platform_device *pdev) domain = pd_pdev->dev.platform_data; domain->regmap = regmap; domain->regs = domain_data->pgc_regs; + domain->genpd.power_on = imx_pgc_power_up; domain->genpd.power_off = imx_pgc_power_down; @@ -1113,6 +1497,7 @@ static const struct of_device_id imx_gpcv2_dt_ids[] = { { .compatible = "fsl,imx7d-gpc", .data = &imx7_pgc_domain_data, }, { .compatible = "fsl,imx8mm-gpc", .data = &imx8mm_pgc_domain_data, }, { .compatible = "fsl,imx8mn-gpc", .data = &imx8mn_pgc_domain_data, }, + { .compatible = "fsl,imx8mp-gpc", .data = &imx8mp_pgc_domain_data, }, { .compatible = "fsl,imx8mq-gpc", .data = &imx8m_pgc_domain_data, }, { } }; From patchwork Wed Jan 19 13:40:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Stach X-Patchwork-Id: 12717540 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BAFA4C433EF for ; Wed, 19 Jan 2022 13:41:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=nE2q0c+57//gWnY640FGwzeFxazvg3Su4CZf2baQzf8=; b=1R4zEa0aViQai4 6idV5DtYEd80RN37+ZJEo/c95QLACe+wy2eIarp5Y4rpbzmqtwXcjThQ3sYRhCOyNsK24xEk+EJ40 aDqCGDHR1L8cRMDSAfjYlrgP1vDBkaGLqJc8Gd9/3DbxW0JZUINKE4pSlQ7kKFtbtcF/ydGp2mbOu EBzZT5xg0hWZTPwcDHAmR+hjzJxUHMF+RDjKDo+OJ6BfOODfEwqiDYY9NiuI4Gi5vO4afGTmXGc4N ajXYppAlg6QcEZJ+u7Tj3sC2eCWzrp7oyGERpS0L+yqzmSW3DqKKYpAAAr+gmJ36r0M/AdfpiF890 lMzG1LOQZVh/ksRjff9w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nABCi-005fOh-SN; Wed, 19 Jan 2022 13:40:48 +0000 Received: from metis.ext.pengutronix.de ([2001:67c:670:201:290:27ff:fe1d:cc33]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nABCV-005fJN-1i for linux-arm-kernel@lists.infradead.org; Wed, 19 Jan 2022 13:40:36 +0000 Received: from dude03.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::39]) by metis.ext.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1nABCQ-0006Kr-Id; Wed, 19 Jan 2022 14:40:30 +0100 From: Lucas Stach To: Shawn Guo , Rob Herring Cc: Pengutronix Kernel Team , NXP Linux Team , Fabio Estevam , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, patchwork-lst@pengutronix.de Subject: [PATCH 4/9] dt-bindings: power: imx8mp: add defines for HSIO blk-ctrl domains Date: Wed, 19 Jan 2022 14:40:22 +0100 Message-Id: <20220119134027.2931945-5-l.stach@pengutronix.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220119134027.2931945-1-l.stach@pengutronix.de> References: <20220119134027.2931945-1-l.stach@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:1101:1d::39 X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220119_054035_128887_64415FCC X-CRM114-Status: UNSURE ( 9.96 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This adds the defines for the power domains provided by the HSIO blk-ctrl on the i.MX8MP. Signed-off-by: Lucas Stach --- include/dt-bindings/power/imx8mp-power.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/dt-bindings/power/imx8mp-power.h b/include/dt-bindings/power/imx8mp-power.h index 7c67689e4faf..9f90c40a2c6c 100644 --- a/include/dt-bindings/power/imx8mp-power.h +++ b/include/dt-bindings/power/imx8mp-power.h @@ -26,4 +26,10 @@ #define IMX8MP_POWER_DOMAIN_HSIOMIX 17 #define IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP 18 +#define IMX8MP_HSIOBLK_PD_USB 0 +#define IMX8MP_HSIOBLK_PD_USB_PHY1 1 +#define IMX8MP_HSIOBLK_PD_USB_PHY2 2 +#define IMX8MP_HSIOBLK_PD_PCIE 3 +#define IMX8MP_HSIOBLK_PD_PCIE_PHY 4 + #endif From patchwork Wed Jan 19 13:40:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Stach X-Patchwork-Id: 12717542 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E651AC433EF for ; Wed, 19 Jan 2022 13:42:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=9M1v7OsT3Bo/5Ce1zsnlq2kcqeummKeaZOwDD1qa/7M=; b=cshs65TmUUg9pH wSTZ3aDkRtJtJCJuvBBDqRzrIscrY3+QtSGdyUtfv3d1id9nvG/itfS5/VqbCgH1qM/F+A5l0Vg6h /5gVLuJ4dhK6Yh6iTqM4c+dUTJQbPSqmNEgOhYiHCwjnuG23X38E7NUgg2YQ2gN5XhccPc/RAe0WL XiXazgyuJYTyQRIToa8Gt0jQQey+0JFZdSOvzh/koWKr8KlHUCfuHq/aEr0ZzYWMD1N8Jo/IXp6Nb iiukcbGrZOVMYwodEy9A1qgYItqnFGIqsdflZX3nW2HttR1mfaSeXKHzyB7P0aOGGhhnBsexDanOU CQcM3GKBcodSqqE16KFw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nABD3-005fSw-F2; Wed, 19 Jan 2022 13:41:09 +0000 Received: from metis.ext.pengutronix.de ([2001:67c:670:201:290:27ff:fe1d:cc33]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nABCV-005fJw-Sd for linux-arm-kernel@lists.infradead.org; Wed, 19 Jan 2022 13:40:37 +0000 Received: from dude03.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::39]) by metis.ext.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1nABCR-0006Kr-3p; Wed, 19 Jan 2022 14:40:31 +0100 From: Lucas Stach To: Shawn Guo , Rob Herring Cc: Pengutronix Kernel Team , NXP Linux Team , Fabio Estevam , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, patchwork-lst@pengutronix.de Subject: [PATCH 5/9] dt-bindings: soc: add binding for i.MX8MP HSIO blk-ctrl Date: Wed, 19 Jan 2022 14:40:23 +0100 Message-Id: <20220119134027.2931945-6-l.stach@pengutronix.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220119134027.2931945-1-l.stach@pengutronix.de> References: <20220119134027.2931945-1-l.stach@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:1101:1d::39 X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220119_054035_946086_ED4A8283 X-CRM114-Status: GOOD ( 14.30 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This adds the binding for the HSIO blk-ctrl on the i.MX8MP SoC. Signed-off-by: Lucas Stach --- .../soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml | 78 +++++++++++++++++++ 1 file changed, 78 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml new file mode 100644 index 000000000000..e9a9e1676142 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8MM DISP blk-ctrl + +maintainers: + - Lucas Stach + +description: + The i.MX8MP HSIO blk-ctrl is a top-level peripheral providing access to + the NoC and ensuring proper power sequencing of the high-speed IO + (USB an PCIe) peripherals located in the HSIO domain of the SoC. + +properties: + compatible: + items: + - const: fsl,imx8mp-hsio-blk-ctrl + - const: syscon + + reg: + maxItems: 1 + + '#power-domain-cells': + const: 1 + + power-domains: + minItems: 6 + maxItems: 6 + + power-domain-names: + items: + - const: bus + - const: usb + - const: usb-phy1 + - const: usb-phy2 + - const: pcie + - const: pcie-phy + + clocks: + minItems: 2 + maxItems: 2 + + clock-names: + items: + - const: usb + - const: pcie + +required: + - compatible + - reg + - power-domains + - power-domain-names + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + + hsio_blk_ctrl: blk-ctrl@32f10000 { + compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon"; + reg = <0x32f10000 0x24>; + clocks = <&clk IMX8MP_CLK_USB_ROOT>, + <&clk IMX8MP_CLK_PCIE_ROOT>; + clock-names = "usb", "pcie"; + power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>, + <&pgc_usb1_phy>, <&pgc_usb2_phy>, + <&pgc_hsiomix>, <&pgc_pcie_phy>; + power-domain-names = "bus", "usb", "usb-phy1", + "usb-phy2", "pcie", "pcie-phy"; + #power-domain-cells = <1>; + }; From patchwork Wed Jan 19 13:40:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Stach X-Patchwork-Id: 12717549 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E9BB4C433EF for ; Wed, 19 Jan 2022 13:44:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=SntwKh8mTaY7cuf+59NEh4la7877704kSAYnnb4yyeY=; b=lfxvuJ1X5i24p/ Aw8yV+WTbd6pe961y/0kFVDdrL1pYStfrb1wPTZAjACiudGl4F4HPT61NGkZmnh8EiMqKSNaCA5SM OUz4jdj7eRsFRQjyc6ELBvhfO4U9TnJDRecaIo/gkGQPPgUPxAf85qO3BXSjapboli9pyPDO70jhT eLoipb9pz1yjD08WWLQL6qPMtIMDgUR6AngcidcjqTYiPrh0aw4Eg/KIA1qdRwUyU7UmSCiGrxDZS d9E74iV9AzE3QD2TBF4dmhrfIb9kWsZqps22ijCZr/CzLh2UUeP9HlN8ZMVDxOMlQlElrirBIOUNs UQ8epT52wTmzblZ9xz3Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nABES-005gDr-LM; Wed, 19 Jan 2022 13:42:36 +0000 Received: from metis.ext.pengutronix.de ([2001:67c:670:201:290:27ff:fe1d:cc33]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nABCX-005fLH-SL for linux-arm-kernel@lists.infradead.org; Wed, 19 Jan 2022 13:40:41 +0000 Received: from dude03.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::39]) by metis.ext.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1nABCR-0006Kr-LC; Wed, 19 Jan 2022 14:40:31 +0100 From: Lucas Stach To: Shawn Guo , Rob Herring Cc: Pengutronix Kernel Team , NXP Linux Team , Fabio Estevam , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, patchwork-lst@pengutronix.de Subject: [PATCH 6/9] soc: imx: add i.MX8MP HSIO blk-ctrl Date: Wed, 19 Jan 2022 14:40:24 +0100 Message-Id: <20220119134027.2931945-7-l.stach@pengutronix.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220119134027.2931945-1-l.stach@pengutronix.de> References: <20220119134027.2931945-1-l.stach@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:1101:1d::39 X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220119_054038_364950_2833683F X-CRM114-Status: GOOD ( 30.16 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The i.MX8MP added some blk-ctrl peripherals that don't follow the regular structure of the blk-ctrls in the previous SoCs. Add a new file for those with currently only the HSIO blk-ctrl being supported. Others will be added later on. Signed-off-by: Lucas Stach --- drivers/soc/imx/Makefile | 1 + drivers/soc/imx/imx8mp-blk-ctrl.c | 444 ++++++++++++++++++++++++++++++ 2 files changed, 445 insertions(+) create mode 100644 drivers/soc/imx/imx8mp-blk-ctrl.c diff --git a/drivers/soc/imx/Makefile b/drivers/soc/imx/Makefile index 8a707077914c..63cd29f6d4d2 100644 --- a/drivers/soc/imx/Makefile +++ b/drivers/soc/imx/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o obj-$(CONFIG_IMX_GPCV2_PM_DOMAINS) += gpcv2.o obj-$(CONFIG_SOC_IMX8M) += soc-imx8m.o obj-$(CONFIG_SOC_IMX8M) += imx8m-blk-ctrl.o +obj-$(CONFIG_SOC_IMX8M) += imx8mp-blk-ctrl.o diff --git a/drivers/soc/imx/imx8mp-blk-ctrl.c b/drivers/soc/imx/imx8mp-blk-ctrl.c new file mode 100644 index 000000000000..7f4e1a151d2b --- /dev/null +++ b/drivers/soc/imx/imx8mp-blk-ctrl.c @@ -0,0 +1,444 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2022 Pengutronix, Lucas Stach + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define GPR_REG0 0x0 +#define PCIE_CLOCK_MODULE_EN BIT(0) +#define USB_CLOCK_MODULE_EN BIT(1) + +struct imx8mp_hsio_blk_ctrl_domain; + +struct imx8mp_hsio_blk_ctrl { + struct device *dev; + struct notifier_block power_nb; + struct device *bus_power_dev; + struct regmap *regmap; + struct imx8mp_hsio_blk_ctrl_domain *domains; + struct genpd_onecell_data onecell_data; +}; + +struct imx8mp_hsio_blk_ctrl_domain_data { + const char *name; + const char *clk_name; + const char *gpc_name; +}; + +struct imx8mp_hsio_blk_ctrl_domain { + struct generic_pm_domain genpd; + struct clk *clk; + struct device *power_dev; + struct imx8mp_hsio_blk_ctrl *bc; + int id; +}; + +static inline struct imx8mp_hsio_blk_ctrl_domain * +to_imx8mp_hsio_blk_ctrl_domain(struct generic_pm_domain *genpd) +{ + return container_of(genpd, struct imx8mp_hsio_blk_ctrl_domain, genpd); +} + +static int imx8mp_hsio_blk_ctrl_power_on(struct generic_pm_domain *genpd) +{ + struct imx8mp_hsio_blk_ctrl_domain *domain = + to_imx8mp_hsio_blk_ctrl_domain(genpd); + struct imx8mp_hsio_blk_ctrl *bc = domain->bc; + int ret; + + /* make sure bus domain is awake */ + ret = pm_runtime_get_sync(bc->bus_power_dev); + if (ret < 0) { + pm_runtime_put_noidle(bc->bus_power_dev); + dev_err(bc->dev, "failed to power up bus domain\n"); + return ret; + } + + /* enable upstream and blk-ctrl clocks */ + ret = clk_prepare_enable(domain->clk); + if (ret) { + dev_err(bc->dev, "failed to enable clocks\n"); + goto bus_put; + } + + switch (domain->id) { + case IMX8MP_HSIOBLK_PD_USB: + regmap_set_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN); + break; + case IMX8MP_HSIOBLK_PD_PCIE: + regmap_set_bits(bc->regmap, GPR_REG0, PCIE_CLOCK_MODULE_EN); + break; + default: + break; + } + + /* power up upstream GPC domain */ + ret = pm_runtime_get_sync(domain->power_dev); + if (ret < 0) { + dev_err(bc->dev, "failed to power up peripheral domain\n"); + goto clk_disable; + } + + return 0; + +clk_disable: + clk_disable_unprepare(domain->clk); +bus_put: + pm_runtime_put(bc->bus_power_dev); + + return ret; +} + +static int imx8mp_hsio_blk_ctrl_power_off(struct generic_pm_domain *genpd) +{ + struct imx8mp_hsio_blk_ctrl_domain *domain = + to_imx8mp_hsio_blk_ctrl_domain(genpd); + struct imx8mp_hsio_blk_ctrl *bc = domain->bc; + + /* disable clocks */ + switch (domain->id) { + case IMX8MP_HSIOBLK_PD_USB: + regmap_clear_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN); + break; + case IMX8MP_HSIOBLK_PD_PCIE: + regmap_clear_bits(bc->regmap, GPR_REG0, PCIE_CLOCK_MODULE_EN); + break; + default: + break; + } + + clk_disable_unprepare(domain->clk); + + /* power down upstream GPC domain */ + pm_runtime_put(domain->power_dev); + + /* allow bus domain to suspend */ + pm_runtime_put(bc->bus_power_dev); + + return 0; +} + +static struct generic_pm_domain * +imx8m_blk_ctrl_xlate(struct of_phandle_args *args, void *data) +{ + struct genpd_onecell_data *onecell_data = data; + unsigned int index = args->args[0]; + + if (args->args_count != 1 || + index >= onecell_data->num_domains) + return ERR_PTR(-EINVAL); + + return onecell_data->domains[index]; +} + +static struct lock_class_key blk_ctrl_genpd_lock_class; + +static const struct imx8mp_hsio_blk_ctrl_domain_data imx8mp_hsio_domain_data[] = { + [IMX8MP_HSIOBLK_PD_USB] = { + .name = "hsioblk-usb", + .clk_name = "usb", + .gpc_name = "usb", + }, + [IMX8MP_HSIOBLK_PD_USB_PHY1] = { + .name = "hsioblk-ubs-phy1", + .gpc_name = "usb-phy1", + }, + [IMX8MP_HSIOBLK_PD_USB_PHY2] = { + .name = "hsioblk-ubs-phy2", + .gpc_name = "usb-phy2", + }, + [IMX8MP_HSIOBLK_PD_PCIE] = { + .name = "hsioblk-pcie", + .clk_name = "pcie", + .gpc_name = "pcie", + }, + [IMX8MP_HSIOBLK_PD_PCIE_PHY] = { + .name = "hsioblk-pcie-phy", + .gpc_name = "pcie-phy", + }, +}; + +static int imx8mp_hsio_power_notifier(struct notifier_block *nb, + unsigned long action, void *data) +{ + struct imx8mp_hsio_blk_ctrl *bc = container_of(nb, struct imx8mp_hsio_blk_ctrl, + power_nb); + struct clk *usb_clk = bc->domains[IMX8MP_HSIOBLK_PD_USB].clk; + int ret; + + switch (action) { + case GENPD_NOTIFY_ON: + /* + * enable USB clock for a moment for the power-on ADB handshake + * to proceed + */ + ret = clk_prepare_enable(usb_clk); + if (ret) + return NOTIFY_BAD; + regmap_set_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN); + + udelay(5); + + regmap_clear_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN); + clk_disable_unprepare(usb_clk); + break; + case GENPD_NOTIFY_PRE_OFF: + /* enable USB clock for the power-down ADB handshake to work */ + ret = clk_prepare_enable(usb_clk); + if (ret) + return NOTIFY_BAD; + + regmap_set_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN); + break; + case GENPD_NOTIFY_OFF: + clk_disable_unprepare(usb_clk); + break; + default: + break; + } + + return NOTIFY_OK; +} + +static int imx8mp_hsio_blk_ctrl_probe(struct platform_device *pdev) +{ + int num_domains = ARRAY_SIZE(imx8mp_hsio_domain_data); + struct device *dev = &pdev->dev; + struct imx8mp_hsio_blk_ctrl *bc; + void __iomem *base; + int i, ret; + + struct regmap_config regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = 0x24, + }; + + bc = devm_kzalloc(dev, sizeof(*bc), GFP_KERNEL); + if (!bc) + return -ENOMEM; + + bc->dev = dev; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + bc->regmap = devm_regmap_init_mmio(dev, base, ®map_config); + if (IS_ERR(bc->regmap)) + return dev_err_probe(dev, PTR_ERR(bc->regmap), + "failed to init regmap\n"); + + bc->domains = devm_kcalloc(dev, num_domains, + sizeof(struct imx8mp_hsio_blk_ctrl_domain), + GFP_KERNEL); + if (!bc->domains) + return -ENOMEM; + + bc->onecell_data.num_domains = num_domains; + bc->onecell_data.xlate = imx8m_blk_ctrl_xlate; + bc->onecell_data.domains = + devm_kcalloc(dev, num_domains, + sizeof(struct generic_pm_domain *), GFP_KERNEL); + if (!bc->onecell_data.domains) + return -ENOMEM; + + bc->bus_power_dev = genpd_dev_pm_attach_by_name(dev, "bus"); + if (IS_ERR(bc->bus_power_dev)) + return dev_err_probe(dev, PTR_ERR(bc->bus_power_dev), + "failed to attach power domain\n"); + + for (i = 0; i < num_domains; i++) { + const struct imx8mp_hsio_blk_ctrl_domain_data *data = + &imx8mp_hsio_domain_data[i]; + struct imx8mp_hsio_blk_ctrl_domain *domain = &bc->domains[i]; + + if (data->clk_name) { + domain->clk = devm_clk_get(dev, data->clk_name); + if (IS_ERR(domain->clk)) { + ret = PTR_ERR(domain->clk); + dev_err_probe(dev, ret, "failed to get clock\n"); + goto cleanup_pds; + } + } + + domain->power_dev = + dev_pm_domain_attach_by_name(dev, data->gpc_name); + if (IS_ERR(domain->power_dev)) { + dev_err_probe(dev, PTR_ERR(domain->power_dev), + "failed to attach power domain\n"); + ret = PTR_ERR(domain->power_dev); + goto cleanup_pds; + } + + domain->genpd.name = data->name; + domain->genpd.power_on = imx8mp_hsio_blk_ctrl_power_on; + domain->genpd.power_off = imx8mp_hsio_blk_ctrl_power_off; + domain->bc = bc; + domain->id = i; + + ret = pm_genpd_init(&domain->genpd, NULL, true); + if (ret) { + dev_err_probe(dev, ret, "failed to init power domain\n"); + dev_pm_domain_detach(domain->power_dev, true); + goto cleanup_pds; + } + + /* + * We use runtime PM to trigger power on/off of the upstream GPC + * domain, as a strict hierarchical parent/child power domain + * setup doesn't allow us to meet the sequencing requirements. + * This means we have nested locking of genpd locks, without the + * nesting being visible at the genpd level, so we need a + * separate lock class to make lockdep aware of the fact that + * this are separate domain locks that can be nested without a + * self-deadlock. + */ + lockdep_set_class(&domain->genpd.mlock, + &blk_ctrl_genpd_lock_class); + + bc->onecell_data.domains[i] = &domain->genpd; + } + + ret = of_genpd_add_provider_onecell(dev->of_node, &bc->onecell_data); + if (ret) { + dev_err_probe(dev, ret, "failed to add power domain provider\n"); + goto cleanup_pds; + } + + bc->power_nb.notifier_call = imx8mp_hsio_power_notifier; + ret = dev_pm_genpd_add_notifier(bc->bus_power_dev, &bc->power_nb); + if (ret) { + dev_err_probe(dev, ret, "failed to add power notifier\n"); + goto cleanup_provider; + } + + dev_set_drvdata(dev, bc); + + return 0; + +cleanup_provider: + of_genpd_del_provider(dev->of_node); +cleanup_pds: + for (i--; i >= 0; i--) { + pm_genpd_remove(&bc->domains[i].genpd); + dev_pm_domain_detach(bc->domains[i].power_dev, true); + } + + dev_pm_domain_detach(bc->bus_power_dev, true); + + return ret; +} + +static int imx8mp_hsio_blk_ctrl_remove(struct platform_device *pdev) +{ + struct imx8mp_hsio_blk_ctrl *bc = dev_get_drvdata(&pdev->dev); + int i; + + of_genpd_del_provider(pdev->dev.of_node); + + for (i = 0; bc->onecell_data.num_domains; i++) { + struct imx8mp_hsio_blk_ctrl_domain *domain = &bc->domains[i]; + + pm_genpd_remove(&domain->genpd); + dev_pm_domain_detach(domain->power_dev, true); + } + + dev_pm_genpd_remove_notifier(bc->bus_power_dev); + + dev_pm_domain_detach(bc->bus_power_dev, true); + + return 0; +} + +#ifdef CONFIG_PM_SLEEP +static int imx8mp_hsio_blk_ctrl_suspend(struct device *dev) +{ + struct imx8mp_hsio_blk_ctrl *bc = dev_get_drvdata(dev); + int ret, i; + + /* + * This may look strange, but is done so the generic PM_SLEEP code + * can power down our domains and more importantly power them up again + * after resume, without tripping over our usage of runtime PM to + * control the upstream GPC domains. Things happen in the right order + * in the system suspend/resume paths due to the device parent/child + * hierarchy. + */ + ret = pm_runtime_get_sync(bc->bus_power_dev); + if (ret < 0) { + pm_runtime_put_noidle(bc->bus_power_dev); + return ret; + } + + for (i = 0; i < bc->onecell_data.num_domains; i++) { + struct imx8mp_hsio_blk_ctrl_domain *domain = &bc->domains[i]; + + ret = pm_runtime_get_sync(domain->power_dev); + if (ret < 0) { + pm_runtime_put_noidle(domain->power_dev); + goto out_fail; + } + } + + return 0; + +out_fail: + for (i--; i >= 0; i--) + pm_runtime_put(bc->domains[i].power_dev); + + pm_runtime_put(bc->bus_power_dev); + + return ret; +} + +static int imx8mp_hsio_blk_ctrl_resume(struct device *dev) +{ + struct imx8mp_hsio_blk_ctrl *bc = dev_get_drvdata(dev); + int i; + + for (i = 0; i < bc->onecell_data.num_domains; i++) + pm_runtime_put(bc->domains[i].power_dev); + + pm_runtime_put(bc->bus_power_dev); + + return 0; +} +#endif + +static const struct dev_pm_ops imx8mp_hsio_blk_ctrl_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(imx8mp_hsio_blk_ctrl_suspend, + imx8mp_hsio_blk_ctrl_resume) +}; + +static const struct of_device_id imx8mp_hsio_blk_ctrl_of_match[] = { + { + .compatible = "fsl,imx8mp-hsio-blk-ctrl", + }, { + /* Sentinel */ + } +}; +MODULE_DEVICE_TABLE(of, imx8m_blk_ctrl_of_match); + +static struct platform_driver imx8mp_hsio_blk_ctrl_driver = { + .probe = imx8mp_hsio_blk_ctrl_probe, + .remove = imx8mp_hsio_blk_ctrl_remove, + .driver = { + .name = "imx8mp-hsio-blk-ctrl", + .pm = &imx8mp_hsio_blk_ctrl_pm_ops, + .of_match_table = imx8mp_hsio_blk_ctrl_of_match, + }, +}; +module_platform_driver(imx8mp_hsio_blk_ctrl_driver); From patchwork Wed Jan 19 13:40:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Stach X-Patchwork-Id: 12717548 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B29E1C433EF for ; Wed, 19 Jan 2022 13:43:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=wC5dtgDa/zqW9qonYIPDyzWE1vXCNA5KsMOHD6kXeUk=; b=OLmb4LkZPsck65 vQJn2kIA48GrprqJjvVNBMKWERlZstw5VRZa/6EqGTsADHnlAlCWs7Iw+8/fw+tO6rqpYQ+tUmFxf +W2aYuO5J2I8z54o/xIEzpe3YmqCr+1deFdnCYcuEsZmufIkgPsG5AnlDfJxl0cKboZGQatG95rcp ZXQIAsiCZ+YeNb3KPpXjg4wM3QJXSaNBUQfc2kFcQVSc4emIC7fxUnp2X3uKLamCZahcAlnSDl+FG bhTFaiEqlmoK0Lpys8oucW1Eiy5mZocCqouNOfRveD2tQ+WgB0zsBMTGMvssWVxO8xzGEJMwzxe+x ttW6hGp5UqCJJ9kjqxZw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nABEB-005g34-49; Wed, 19 Jan 2022 13:42:19 +0000 Received: from metis.ext.pengutronix.de ([2001:67c:670:201:290:27ff:fe1d:cc33]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nABCY-005fLK-Cl for linux-arm-kernel@lists.infradead.org; Wed, 19 Jan 2022 13:40:40 +0000 Received: from dude03.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::39]) by metis.ext.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1nABCS-0006Kr-7F; Wed, 19 Jan 2022 14:40:32 +0100 From: Lucas Stach To: Shawn Guo , Rob Herring Cc: Pengutronix Kernel Team , NXP Linux Team , Fabio Estevam , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, patchwork-lst@pengutronix.de Subject: [PATCH 7/9] arm64: dts: imx8mp: add HSIO power-domains Date: Wed, 19 Jan 2022 14:40:25 +0100 Message-Id: <20220119134027.2931945-8-l.stach@pengutronix.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220119134027.2931945-1-l.stach@pengutronix.de> References: <20220119134027.2931945-1-l.stach@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:1101:1d::39 X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220119_054038_479631_46A76150 X-CRM114-Status: GOOD ( 12.43 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This adds the GPC and HSIO blk-ctrl nodes providing power control for the high-speed (USB and PCIe) IOs. Signed-off-by: Lucas Stach --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 63 ++++++++++++++++++++--- 1 file changed, 57 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 04d259de5667..b76af96b9b5c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -443,6 +444,44 @@ src: reset-controller@30390000 { interrupts = ; #reset-cells = <1>; }; + + gpc: gpc@303a0000 { + compatible = "fsl,imx8mp-gpc"; + reg = <0x303a0000 0x10000>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <3>; + + pgc { + #address-cells = <1>; + #size-cells = <0>; + + pgc_pcie_phy: power-domain@1 { + #power-domain-cells = <0>; + reg = ; + }; + + pgc_usb1_phy: power-domain@2 { + #power-domain-cells = <0>; + reg = ; + }; + + pgc_usb2_phy: power-domain@3 { + #power-domain-cells = <0>; + reg = ; + }; + + pgc_hsiomix: power-domains@17 { + #power-domain-cells = <0>; + reg = ; + clocks = <&clk IMX8MP_CLK_HSIO_AXI>, + <&clk IMX8MP_CLK_HSIO_ROOT>; + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; + assigned-clock-rates = <500000000>; + }; + }; + }; }; aips2: bus@30400000 { @@ -875,6 +914,20 @@ ddr-pmu@3d800000 { interrupts = ; }; + hsio_blk_ctrl: blk-ctrl@32f10000 { + compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon"; + reg = <0x32f10000 0x24>; + clocks = <&clk IMX8MP_CLK_USB_ROOT>, + <&clk IMX8MP_CLK_PCIE_ROOT>; + clock-names = "usb", "pcie"; + power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>, + <&pgc_usb1_phy>, <&pgc_usb2_phy>, + <&pgc_hsiomix>, <&pgc_pcie_phy>; + power-domain-names = "bus", "usb", "usb-phy1", + "usb-phy2", "pcie", "pcie-phy"; + #power-domain-cells = <1>; + }; + usb3_phy0: usb-phy@381f0040 { compatible = "fsl,imx8mp-usb-phy"; reg = <0x381f0040 0x40>; @@ -882,6 +935,7 @@ usb3_phy0: usb-phy@381f0040 { clock-names = "phy"; assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>; #phy-cells = <0>; status = "disabled"; }; @@ -893,6 +947,7 @@ usb3_0: usb@32f10100 { <&clk IMX8MP_CLK_USB_ROOT>; clock-names = "hsio", "suspend"; interrupts = ; + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; #address-cells = <1>; #size-cells = <1>; dma-ranges = <0x40000000 0x40000000 0xc0000000>; @@ -906,9 +961,6 @@ usb_dwc3_0: usb@38100000 { <&clk IMX8MP_CLK_USB_CORE_REF>, <&clk IMX8MP_CLK_USB_ROOT>; clock-names = "bus_early", "ref", "suspend"; - assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; - assigned-clock-rates = <500000000>; interrupts = ; phys = <&usb3_phy0>, <&usb3_phy0>; phy-names = "usb2-phy", "usb3-phy"; @@ -924,6 +976,7 @@ usb3_phy1: usb-phy@382f0040 { clock-names = "phy"; assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>; #phy-cells = <0>; }; @@ -934,6 +987,7 @@ usb3_1: usb@32f10108 { <&clk IMX8MP_CLK_USB_ROOT>; clock-names = "hsio", "suspend"; interrupts = ; + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; #address-cells = <1>; #size-cells = <1>; dma-ranges = <0x40000000 0x40000000 0xc0000000>; @@ -947,9 +1001,6 @@ usb_dwc3_1: usb@38200000 { <&clk IMX8MP_CLK_USB_CORE_REF>, <&clk IMX8MP_CLK_USB_ROOT>; clock-names = "bus_early", "ref", "suspend"; - assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; - assigned-clock-rates = <500000000>; interrupts = ; phys = <&usb3_phy1>, <&usb3_phy1>; phy-names = "usb2-phy", "usb3-phy"; From patchwork Wed Jan 19 13:40:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Stach X-Patchwork-Id: 12717546 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E3EF7C433EF for ; Wed, 19 Jan 2022 13:43:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=RcH7mJYmud0ShxoS6OD7UHFSitedvBiyYoF2Q0Lirv4=; b=aw4baHNTf/ECrX Qta0nNXvJbpq0rk6L9QBszmVA7HnN2fiNXBKApSnnDssAHswMsexkE55Rq4Yv3iJY5PlGnbsJwhw1 a+9kSuj3QkszJkFBVaknVnX9SBER2Q/HAGSjOojgIFUxtOMOAixKpU8fPBHgtNd8evtfBX4Xg2Mub hjnLqkn2YdYJhYkg3Myt7xkF0S/jUM9YwKxabBLwGklrSztTKetPQM6cGIt5hXs/3/CSISa9zwpfo u93x9YoAG2V0Ly/H7BpdVi2LefYPYC4PxyIqjM44WbH17xv+pFxuPIyrvc5kD6Zw/sQnYxB7OL7yb nkaq0Cfqf7I9syPheJkw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nABDu-005fsN-7l; Wed, 19 Jan 2022 13:42:02 +0000 Received: from metis.ext.pengutronix.de ([2001:67c:670:201:290:27ff:fe1d:cc33]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nABCY-005fLJ-5x for linux-arm-kernel@lists.infradead.org; Wed, 19 Jan 2022 13:40:40 +0000 Received: from dude03.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::39]) by metis.ext.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1nABCS-0006Kr-Og; Wed, 19 Jan 2022 14:40:32 +0100 From: Lucas Stach To: Shawn Guo , Rob Herring Cc: Pengutronix Kernel Team , NXP Linux Team , Fabio Estevam , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, patchwork-lst@pengutronix.de Subject: [PATCH 8/9] arm64: dts: imx8mp: add GPU power domains Date: Wed, 19 Jan 2022 14:40:26 +0100 Message-Id: <20220119134027.2931945-9-l.stach@pengutronix.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220119134027.2931945-1-l.stach@pengutronix.de> References: <20220119134027.2931945-1-l.stach@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:1101:1d::39 X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220119_054038_311081_2E99620C X-CRM114-Status: GOOD ( 10.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the power domains for the GPUs, which do not require any interaction with a blk-ctrl, but are simply two PU domains nested inside a MIX domain. Signed-off-by: Lucas Stach --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 24 +++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index b76af96b9b5c..fa9dca7acc94 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -471,6 +471,30 @@ pgc_usb2_phy: power-domain@3 { reg = ; }; + pgc_gpu2d: power-domain@6 { + #power-domain-cells = <0>; + reg = ; + power-domains = <&pgc_gpumix>; + }; + + pgc_gpumix: power-domain@7 { + #power-domain-cells = <0>; + reg = ; + clocks = <&clk IMX8MP_CLK_GPU_ROOT>, + <&clk IMX8MP_CLK_GPU_AHB>; + assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>, + <&clk IMX8MP_CLK_GPU_AHB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <800000000>, <400000000>; + }; + + pgc_gpu3d: power-domain@9 { + #power-domain-cells = <0>; + reg = ; + power-domains = <&pgc_gpumix>; + }; + pgc_hsiomix: power-domains@17 { #power-domain-cells = <0>; reg = ; From patchwork Wed Jan 19 13:40:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Stach X-Patchwork-Id: 12717545 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8B684C433F5 for ; Wed, 19 Jan 2022 13:43:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=pYtrUMx1iHjo/06y1qRGtFf8ViNmrOb/oz5swsH9HHI=; b=kF10+flZlT6t2i TaF6hq9jvZDyBD5H9pF1NdfYWBLUhrlf2O2WmH5G61Ql1Ili4djSPVvq54ZdMyDtaKDs86a6nbubG 0tgc62iUByiBWvR1yJh1Zzb1dv9dshyGUM41jmGs5ZNfwQ4U2LIPq7TfULlaGaMEzZABMNosp5Ypb 6YnhyvZA7cXxarOnLZhON0pHsZ17YlvFSu8h9y4J3wv1lO9hVAznnzcfpMXUyIJgv/jJyJcXCVGmw ZKpxzFr8gNQugL2Ns4Fjjj/9X9gS0ZsjkSMmLLw3VpSlbcGnGzfO944NS1U6LwMOE89xfsTCDByo5 Dpl8a0lu9u2n1ofNpB7A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nABDg-005fkr-VS; Wed, 19 Jan 2022 13:41:49 +0000 Received: from metis.ext.pengutronix.de ([2001:67c:670:201:290:27ff:fe1d:cc33]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nABCY-005fLI-1Z for linux-arm-kernel@lists.infradead.org; Wed, 19 Jan 2022 13:40:40 +0000 Received: from dude03.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::39]) by metis.ext.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1nABCT-0006Kr-9k; Wed, 19 Jan 2022 14:40:33 +0100 From: Lucas Stach To: Shawn Guo , Rob Herring Cc: Pengutronix Kernel Team , NXP Linux Team , Fabio Estevam , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, patchwork-lst@pengutronix.de Subject: [PATCH 9/9] arm64: dts: imx8mp: add GPU nodes Date: Wed, 19 Jan 2022 14:40:27 +0100 Message-Id: <20220119134027.2931945-10-l.stach@pengutronix.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220119134027.2931945-1-l.stach@pengutronix.de> References: <20220119134027.2931945-1-l.stach@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:1101:1d::39 X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220119_054038_174480_ABBB3BA5 X-CRM114-Status: GOOD ( 10.38 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the DT nodes for both the 3D and 2D GPU cores found on the i.MX8MP. etnaviv-gpu 38000000.gpu: model: GC7000, revision: 6204 etnaviv-gpu 38008000.gpu: model: GC520, revision: 5341 [drm] Initialized etnaviv 1.3.0 20151214 for etnaviv on minor 0 Signed-off-by: Lucas Stach --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 31 +++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index fa9dca7acc94..67cc837058d1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -922,6 +922,37 @@ eqos: ethernet@30bf0000 { }; }; + gpu3d: gpu@38000000 { + compatible = "vivante,gc"; + reg = <0x38000000 0x8000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_GPU3D_CORE>, + <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>, + <&clk IMX8MP_CLK_GPU_ROOT>, + <&clk IMX8MP_CLK_GPU_AHB>; + clock-names = "core", "shader", "bus", "reg"; + assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>, + <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <800000000>, <800000000>; + power-domains = <&pgc_gpu3d>; + }; + + gpu2d: gpu@38008000 { + compatible = "vivante,gc"; + reg = <0x38008000 0x8000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_GPU2D_CORE>, + <&clk IMX8MP_CLK_GPU_ROOT>, + <&clk IMX8MP_CLK_GPU_AHB>; + clock-names = "core", "bus", "reg"; + assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <800000000>; + power-domains = <&pgc_gpu2d>; + }; + gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>,