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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT017.mail.protection.outlook.com (10.13.172.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4909.7 via Frontend Transport; Wed, 19 Jan 2022 23:06:44 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.18; Wed, 19 Jan 2022 17:06:43 -0600 From: Terry Bowman To: , , , , , , , CC: , , , , , , , , Subject: [PATCH v3 1/9] kernel/resource: Introduce request_muxed_mem_region() Date: Wed, 19 Jan 2022 17:06:18 -0600 Message-ID: <20220119230626.31560-2-terry.bowman@amd.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220119230626.31560-1-terry.bowman@amd.com> References: <20220119230626.31560-1-terry.bowman@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a0ced1c5-f353-43cc-25a4-08d9dba05ca0 X-MS-TrafficTypeDiagnostic: DM6PR12MB2748:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8273; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2022 23:06:44.3947 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a0ced1c5-f353-43cc-25a4-08d9dba05ca0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT017.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB2748 Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org Support for requesting muxed memory region is implemented but not currently callable as a macro. Add the request muxed memory region macro. MMIO memory accesses can be synchronized using request_mem_region() which is already available. This call will return failure if the resource is busy. The 'muxed' version of this macro will handle a busy resource by using a wait queue to retry until the resource is available. Signed-off-by: Terry Bowman Reviewed-by: Andy Shevchenko --- include/linux/ioport.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/linux/ioport.h b/include/linux/ioport.h index 8359c50f9988..2a5567de318b 100644 --- a/include/linux/ioport.h +++ b/include/linux/ioport.h @@ -262,6 +262,8 @@ resource_union(struct resource *r1, struct resource *r2, struct resource *r) #define request_muxed_region(start,n,name) __request_region(&ioport_resource, (start), (n), (name), IORESOURCE_MUXED) #define __request_mem_region(start,n,name, excl) __request_region(&iomem_resource, (start), (n), (name), excl) #define request_mem_region(start,n,name) __request_region(&iomem_resource, (start), (n), (name), 0) +#define request_muxed_mem_region(start, n, name) \ + __request_region(&iomem_resource, (start), (n), (name), IORESOURCE_MUXED) #define request_mem_region_exclusive(start,n,name) \ __request_region(&iomem_resource, (start), (n), (name), IORESOURCE_EXCLUSIVE) #define rename_region(region, newname) do { (region)->name = (newname); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2022 23:06:55.5706 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9ceb3a3b-0a2a-49e5-731c-08d9dba06349 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT036.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2781 Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org Replace number constant with #define to improve readability and maintainability. Signed-off-by: Terry Bowman --- drivers/i2c/busses/i2c-piix4.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/i2c/busses/i2c-piix4.c b/drivers/i2c/busses/i2c-piix4.c index 8c1b31ed0c42..b88d990b013f 100644 --- a/drivers/i2c/busses/i2c-piix4.c +++ b/drivers/i2c/busses/i2c-piix4.c @@ -77,6 +77,7 @@ /* SB800 constants */ #define SB800_PIIX4_SMB_IDX 0xcd6 +#define SB800_PIIX4_SMB_MAP_SIZE 2 #define KERNCZ_IMC_IDX 0x3e #define KERNCZ_IMC_DATA 0x3f @@ -290,7 +291,9 @@ static int piix4_setup_sb800(struct pci_dev *PIIX4_dev, else smb_en = (aux) ? 0x28 : 0x2c; - if (!request_muxed_region(SB800_PIIX4_SMB_IDX, 2, "sb800_piix4_smb")) { + if (!request_muxed_region(SB800_PIIX4_SMB_IDX, + SB800_PIIX4_SMB_MAP_SIZE, + "sb800_piix4_smb")) { dev_err(&PIIX4_dev->dev, "SMB base address index region 0x%x already in use.\n", SB800_PIIX4_SMB_IDX); @@ -302,7 +305,7 @@ static int piix4_setup_sb800(struct pci_dev *PIIX4_dev, outb_p(smb_en + 1, SB800_PIIX4_SMB_IDX); smba_en_hi = inb_p(SB800_PIIX4_SMB_IDX + 1); - release_region(SB800_PIIX4_SMB_IDX, 2); + release_region(SB800_PIIX4_SMB_IDX, SB800_PIIX4_SMB_MAP_SIZE); if (!smb_en) { smb_en_status = smba_en_lo & 0x10; @@ -371,7 +374,8 @@ static int piix4_setup_sb800(struct pci_dev *PIIX4_dev, piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT; } } else { - if (!request_muxed_region(SB800_PIIX4_SMB_IDX, 2, + if (!request_muxed_region(SB800_PIIX4_SMB_IDX, + SB800_PIIX4_SMB_MAP_SIZE, "sb800_piix4_smb")) { release_region(piix4_smba, SMBIOSIZE); return -EBUSY; @@ -384,7 +388,7 @@ static int piix4_setup_sb800(struct pci_dev *PIIX4_dev, SB800_PIIX4_PORT_IDX; piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK; piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT; - release_region(SB800_PIIX4_SMB_IDX, 2); + release_region(SB800_PIIX4_SMB_IDX, SB800_PIIX4_SMB_MAP_SIZE); } dev_info(&PIIX4_dev->dev, @@ -682,7 +686,9 @@ static s32 piix4_access_sb800(struct i2c_adapter *adap, u16 addr, u8 port; int retval; - if (!request_muxed_region(SB800_PIIX4_SMB_IDX, 2, "sb800_piix4_smb")) + if (!request_muxed_region(SB800_PIIX4_SMB_IDX, + SB800_PIIX4_SMB_MAP_SIZE, + "sb800_piix4_smb")) return -EBUSY; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2022 23:07:06.6315 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ca766633-d22a-431e-d31c-08d9dba069de X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT012.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB3716 Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org Move duplicated region request and release code into a function. Move is in preparation for following MMIO changes. Signed-off-by: Terry Bowman --- drivers/i2c/busses/i2c-piix4.c | 43 +++++++++++++++++++++++----------- 1 file changed, 29 insertions(+), 14 deletions(-) diff --git a/drivers/i2c/busses/i2c-piix4.c b/drivers/i2c/busses/i2c-piix4.c index b88d990b013f..14324e03fe24 100644 --- a/drivers/i2c/busses/i2c-piix4.c +++ b/drivers/i2c/busses/i2c-piix4.c @@ -165,6 +165,26 @@ struct i2c_piix4_adapdata { u8 port; /* Port number, shifted */ }; +static int piix4_sb800_region_setup(struct device *dev) +{ + if (!request_muxed_region(SB800_PIIX4_SMB_IDX, + SB800_PIIX4_SMB_MAP_SIZE, + "sb800_piix4_smb")) { + dev_err(dev, + "SMB base address index region 0x%x already in use.\n", + SB800_PIIX4_SMB_IDX); + return -EBUSY; + } + + return 0; +} + +static void piix4_sb800_region_release(struct device *dev) +{ + release_region(SB800_PIIX4_SMB_IDX, + SB800_PIIX4_SMB_MAP_SIZE); +} + static int piix4_setup(struct pci_dev *PIIX4_dev, const struct pci_device_id *id) { @@ -270,6 +290,7 @@ static int piix4_setup_sb800(struct pci_dev *PIIX4_dev, unsigned short piix4_smba; u8 smba_en_lo, smba_en_hi, smb_en, smb_en_status, port_sel; u8 i2ccfg, i2ccfg_offset = 0x10; + int retval; /* SB800 and later SMBus does not support forcing address */ if (force || force_addr) { @@ -291,21 +312,16 @@ static int piix4_setup_sb800(struct pci_dev *PIIX4_dev, else smb_en = (aux) ? 0x28 : 0x2c; - if (!request_muxed_region(SB800_PIIX4_SMB_IDX, - SB800_PIIX4_SMB_MAP_SIZE, - "sb800_piix4_smb")) { - dev_err(&PIIX4_dev->dev, - "SMB base address index region 0x%x already in use.\n", - SB800_PIIX4_SMB_IDX); - return -EBUSY; - } + retval = piix4_sb800_region_setup(&PIIX4_dev->dev); + if (retval) + return retval; outb_p(smb_en, SB800_PIIX4_SMB_IDX); smba_en_lo = inb_p(SB800_PIIX4_SMB_IDX + 1); outb_p(smb_en + 1, SB800_PIIX4_SMB_IDX); smba_en_hi = inb_p(SB800_PIIX4_SMB_IDX + 1); - release_region(SB800_PIIX4_SMB_IDX, SB800_PIIX4_SMB_MAP_SIZE); + piix4_sb800_region_release(&PIIX4_dev->dev); if (!smb_en) { smb_en_status = smba_en_lo & 0x10; @@ -686,10 +702,9 @@ static s32 piix4_access_sb800(struct i2c_adapter *adap, u16 addr, u8 port; int retval; - if (!request_muxed_region(SB800_PIIX4_SMB_IDX, - SB800_PIIX4_SMB_MAP_SIZE, - "sb800_piix4_smb")) - return -EBUSY; + retval = piix4_sb800_region_setup(&adap->dev); + if (retval) + return retval; /* Request the SMBUS semaphore, avoid conflicts with the IMC */ smbslvcnt = inb_p(SMBSLVCNT); @@ -764,7 +779,7 @@ static s32 piix4_access_sb800(struct i2c_adapter *adap, u16 addr, piix4_imc_wakeup(); release: - release_region(SB800_PIIX4_SMB_IDX, SB800_PIIX4_SMB_MAP_SIZE); + piix4_sb800_region_release(&adap->dev); return retval; } From patchwork Wed Jan 19 23:06:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Bowman, Terry" X-Patchwork-Id: 12717856 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7601CC433FE for ; Wed, 19 Jan 2022 23:08:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344338AbiASXI4 (ORCPT ); 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Wed, 19 Jan 2022 17:07:16 -0600 From: Terry Bowman To: , , , , , , , CC: , , , , , , , , Subject: [PATCH v3 4/9] i2c: piix4: Move SMBus controller base address detect into function Date: Wed, 19 Jan 2022 17:06:21 -0600 Message-ID: <20220119230626.31560-5-terry.bowman@amd.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220119230626.31560-1-terry.bowman@amd.com> References: <20220119230626.31560-1-terry.bowman@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c962797b-ec67-4458-9205-08d9dba070c3 X-MS-TrafficTypeDiagnostic: BN9PR12MB5323:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2958; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: JbisiTx1AsowY9akX40zWqU8jC+Va/RHPq+eziMCd9QQR3/K9Gd0OeGzlgC0XyX9J78XOSdI0w1LIyxsmC8QeKkjRxr9XuImfV/m085EdF7sD5m4LGYRzP0lpOHMtg3oMCfZPL/vxjJOKDBsLLMoaZvfDJ30zJArqKioWwF7XVzKrGn7rRRnkZbgciAQFy/J+/4WakgEmGslC8NR6I0vxoia8S7LMFO2LdIWx62ZpkhEiRgURgi2bYe4KDgWbzVeh+i1hsmlekVUzixn8ZC0Si+NAIJO6m0h0AhIMUgImdbvc3yOYVg9pnArglk2uhclSSWJrsvVvUVGbWeWYkoHda6fMEdBH15TtWVF0X2r3luf2SSUdGlIl/tq0r5pvva7V8GbPLgnP5NFyLVbCzyjMq7kNYb1F5YYQjKma9lbPBQekAluD6pDxP7Xdu2xL8yjsxPnSIpTBBNvg0EroG6sC/ADNan8vOA4GHEGinyEc304Acaosm9NYLk8ufo7aHkgoZ3V3XxzFalmAE9b8yWo3eljIJnfIqtjJz8LocLKfI0Q/cN8DFyB95U8s4GTYqkS1Qu5GsOlx3GOo8v7+uIo/NrRQWg3o0+OF61QhmBMzfhXvd/jdrA5daBFjigxUcbLCZt54UbEsPcMW5+oO9aXMvQ/vgzFJF0YHBi6DZL03C8IqEqoOKBSOOtx1H1Q5Ak8EBu9xIWGmuWVTE+9IlmD0UzbhOk3EBgf3AfzelWb//MWtSvOg7Vuq99dffG4IrPEAQNIyI1PRBxin4ZtHgaynLSordMdR629G1bJ7hQIzzkCCxshCS5OVX+0iT3wFmVs X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(46966006)(40470700002)(36840700001)(40460700001)(82310400004)(110136005)(83380400001)(70586007)(7696005)(70206006)(2616005)(5660300002)(336012)(426003)(508600001)(316002)(86362001)(54906003)(8676002)(47076005)(1076003)(2906002)(36756003)(36860700001)(81166007)(16526019)(356005)(26005)(8936002)(44832011)(4326008)(186003)(6666004)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2022 23:07:18.1970 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c962797b-ec67-4458-9205-08d9dba070c3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT049.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR12MB5323 Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org Move SMBus controller base address detection into function. Refactor is in preparation for following MMIO changes. Signed-off-by: Terry Bowman --- drivers/i2c/busses/i2c-piix4.c | 68 +++++++++++++++++++++------------- 1 file changed, 43 insertions(+), 25 deletions(-) diff --git a/drivers/i2c/busses/i2c-piix4.c b/drivers/i2c/busses/i2c-piix4.c index 14324e03fe24..35fcb61f4750 100644 --- a/drivers/i2c/busses/i2c-piix4.c +++ b/drivers/i2c/busses/i2c-piix4.c @@ -284,11 +284,51 @@ static int piix4_setup(struct pci_dev *PIIX4_dev, return piix4_smba; } +static int piix4_setup_sb800_smba(struct pci_dev *PIIX4_dev, + u8 smb_en, + u8 aux, + u8 *smb_en_status, + unsigned short *piix4_smba) +{ + u8 smba_en_lo; + u8 smba_en_hi; + int retval; + + retval = piix4_sb800_region_setup(&PIIX4_dev->dev); + if (retval) + return retval; + + outb_p(smb_en, SB800_PIIX4_SMB_IDX); + smba_en_lo = inb_p(SB800_PIIX4_SMB_IDX + 1); + outb_p(smb_en + 1, SB800_PIIX4_SMB_IDX); + smba_en_hi = inb_p(SB800_PIIX4_SMB_IDX + 1); + + piix4_sb800_region_release(&PIIX4_dev->dev); + + if (!smb_en) { + *smb_en_status = smba_en_lo & 0x10; + *piix4_smba = smba_en_hi << 8; + if (aux) + *piix4_smba |= 0x20; + } else { + *smb_en_status = smba_en_lo & 0x01; + *piix4_smba = ((smba_en_hi << 8) | smba_en_lo) & 0xffe0; + } + + if (!*smb_en_status) { + dev_err(&PIIX4_dev->dev, + "SMBus Host Controller not enabled!\n"); + return -ENODEV; + } + + return retval; +} + static int piix4_setup_sb800(struct pci_dev *PIIX4_dev, const struct pci_device_id *id, u8 aux) { unsigned short piix4_smba; - u8 smba_en_lo, smba_en_hi, smb_en, smb_en_status, port_sel; + u8 smb_en, smb_en_status, port_sel; u8 i2ccfg, i2ccfg_offset = 0x10; int retval; @@ -312,33 +352,11 @@ static int piix4_setup_sb800(struct pci_dev *PIIX4_dev, else smb_en = (aux) ? 0x28 : 0x2c; - retval = piix4_sb800_region_setup(&PIIX4_dev->dev); + retval = piix4_setup_sb800_smba(PIIX4_dev, smb_en, + aux, &smb_en_status, &piix4_smba); if (retval) return retval; - outb_p(smb_en, SB800_PIIX4_SMB_IDX); - smba_en_lo = inb_p(SB800_PIIX4_SMB_IDX + 1); - outb_p(smb_en + 1, SB800_PIIX4_SMB_IDX); - smba_en_hi = inb_p(SB800_PIIX4_SMB_IDX + 1); - - piix4_sb800_region_release(&PIIX4_dev->dev); - - if (!smb_en) { - smb_en_status = smba_en_lo & 0x10; - piix4_smba = smba_en_hi << 8; - if (aux) - piix4_smba |= 0x20; - } else { - smb_en_status = smba_en_lo & 0x01; - piix4_smba = ((smba_en_hi << 8) | smba_en_lo) & 0xffe0; - } - - if (!smb_en_status) { - dev_err(&PIIX4_dev->dev, - "SMBus Host Controller not enabled!\n"); - return -ENODEV; - } - if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) return -ENODEV; From patchwork Wed Jan 19 23:06:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Bowman, Terry" X-Patchwork-Id: 12717857 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6CCBCC433F5 for ; Wed, 19 Jan 2022 23:09:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344264AbiASXI7 (ORCPT ); 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Wed, 19 Jan 2022 17:07:27 -0600 From: Terry Bowman To: , , , , , , , CC: , , , , , , , , Subject: [PATCH v3 5/9] i2c: piix4: Move SMBus port selection into function Date: Wed, 19 Jan 2022 17:06:22 -0600 Message-ID: <20220119230626.31560-6-terry.bowman@amd.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220119230626.31560-1-terry.bowman@amd.com> References: <20220119230626.31560-1-terry.bowman@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1c0e6590-a4eb-48f3-5f9e-08d9dba0771c X-MS-TrafficTypeDiagnostic: MWHPR12MB1663:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6108; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: NUTAl2bS2edLPdczGt4353mqH/hLRet53wnG9zp4TrejITlaFLX7Mvuk3sdMHBN9q1LEClu0nzII0/jk/cEgyI6reRyXAwFuImy2XCaJt21h3zRQR0XJxe0mEsi7ofFQtfrCChPs395CQZfZILpTjctazAe80R9OJ2g5OkhmVJtAvLTuMNo5zGqAWJAL1/XSGJWYxwXjsEJNOi0WoDC6aIT8WyPvMAXH98ij0jWDsamokMGVePXXvHGrU07mkbmPN0mDbHVIxjt7K+NoMviCYJMmsdL0epvoS9AwDrKREOiv8iTdBgHrun8AczjleBVZL8fBY/g2IAhZgygcYBt3PBSANuszzBtn+q28wQZcwSSBYlqwD3NszC/SDic7MW3CZfPaHYfOitaCtArBIjGHOj+6wO64iiUc4qRwVQ2mnrHmcW4/DaZERhDIkX4dV3+/Yg5d/vRJo9/iOsCWH13vKN8sSD+ceOt+aJc3Vi8k/X4Ssi6PVcbmavRjpJgC9r0huaqyQX8F26av2jpYA0D04VEBZoEHDu/rao9Vy0kILtQs7owBr88XBfku/JK/MRFSvfCuOCh5oVMivaeRxzXf4u6xoV/fDlNGq9FWbjhR8DWuFShZPkEXfbWWwqSWDmFVal7omkimlNxmgINrDK1sXo7eIYAPXYd7kQ0pYWS0hOeXuXXG+McNj1w2e1fqSk4icXb8NSiR1oB/wgu5j76low0meZIsiDdxlgjOWmE27L35iTupA8cbKmR+DKN0fZ/611ucQ8m0DHOUvQJfOYfJVqSc0iS8wBHRzlRGsdky5zjF1gyb9Kb9oi9Ny3wQNxgD X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(46966006)(40470700002)(36840700001)(336012)(16526019)(508600001)(110136005)(316002)(36860700001)(70586007)(70206006)(54906003)(8676002)(4326008)(186003)(1076003)(40460700001)(2906002)(6666004)(81166007)(82310400004)(8936002)(44832011)(86362001)(426003)(2616005)(5660300002)(83380400001)(356005)(36756003)(47076005)(7696005)(26005)(2101003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2022 23:07:28.7515 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1c0e6590-a4eb-48f3-5f9e-08d9dba0771c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT022.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1663 Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org Move port selection code into a separate function. Refactor is in preparation for following MMIO changes. Signed-off-by: Terry Bowman --- drivers/i2c/busses/i2c-piix4.c | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/drivers/i2c/busses/i2c-piix4.c b/drivers/i2c/busses/i2c-piix4.c index 35fcb61f4750..58b613b78c97 100644 --- a/drivers/i2c/busses/i2c-piix4.c +++ b/drivers/i2c/busses/i2c-piix4.c @@ -700,6 +700,19 @@ static void piix4_imc_wakeup(void) release_region(KERNCZ_IMC_IDX, 2); } +static int piix4_sb800_port_sel(u8 port) +{ + u8 smba_en_lo; + + outb_p(piix4_port_sel_sb800, SB800_PIIX4_SMB_IDX); + smba_en_lo = inb_p(SB800_PIIX4_SMB_IDX + 1); + + if ((smba_en_lo & piix4_port_mask_sb800) != port) + outb_p((smba_en_lo & ~piix4_port_mask_sb800) | port, + SB800_PIIX4_SMB_IDX + 1); + + return (smba_en_lo & piix4_port_mask_sb800); +} /* * Handles access to multiple SMBus ports on the SB800. * The port is selected by bits 2:1 of the smb_en register (0x2c). @@ -716,8 +729,7 @@ static s32 piix4_access_sb800(struct i2c_adapter *adap, u16 addr, unsigned short piix4_smba = adapdata->smba; int retries = MAX_TIMEOUT; int smbslvcnt; - u8 smba_en_lo; - u8 port; + u8 prev_port; int retval; retval = piix4_sb800_region_setup(&adap->dev); @@ -777,18 +789,12 @@ static s32 piix4_access_sb800(struct i2c_adapter *adap, u16 addr, } } - outb_p(piix4_port_sel_sb800, SB800_PIIX4_SMB_IDX); - smba_en_lo = inb_p(SB800_PIIX4_SMB_IDX + 1); - - port = adapdata->port; - if ((smba_en_lo & piix4_port_mask_sb800) != port) - outb_p((smba_en_lo & ~piix4_port_mask_sb800) | port, - SB800_PIIX4_SMB_IDX + 1); + prev_port = piix4_sb800_port_sel(adapdata->port); retval = piix4_access(adap, addr, flags, read_write, command, size, data); - outb_p(smba_en_lo, SB800_PIIX4_SMB_IDX + 1); + piix4_sb800_port_sel(prev_port); /* Release the semaphore */ outb_p(smbslvcnt | 0x20, SMBSLVCNT); From patchwork Wed Jan 19 23:06:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Bowman, Terry" X-Patchwork-Id: 12717858 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C7204C433FE for ; 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Wed, 19 Jan 2022 17:07:38 -0600 From: Terry Bowman To: , , , , , , , CC: , , , , , , , , Subject: [PATCH v3 6/9] i2c: piix4: Add EFCH MMIO support to region request and release Date: Wed, 19 Jan 2022 17:06:23 -0600 Message-ID: <20220119230626.31560-7-terry.bowman@amd.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220119230626.31560-1-terry.bowman@amd.com> References: <20220119230626.31560-1-terry.bowman@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 97c337fe-fadd-4f4c-1b39-08d9dba07db5 X-MS-TrafficTypeDiagnostic: MN2PR12MB4221:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7691; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: KhcUQWAC73f4cuUp2j8pyl/hbowzbL2OQTSL8RzAjl6Yofs1/lOyQq8O9NzIahP/y5q4UzmRd3dQjFDVvLhgSq/BqxyuwDDE0IV/C+9AiG5QVy2/xpBAr6IuuWRnwUUpvIG+6Snlsj2yBYDQk4iLUnzsfgTHBHhC/Wy6WrHeRk/IF6got4ZPFcXJWMFT5OHD2Bj50LMguN1CQheDKGTri+b4qu+h2DPQuhEQvOe5h2sgFawlP1bHh4mAIHzqIoi0/WRkwsqsndxm3Pv/jZbL/FWSGRtSQDUV9I/nI9AjvbICNYM23SX5tzkmVcO5GOgj8Mje1YIV4rMFUf44zjNVm3eWudUMlZ8msQ970gpWCoGOc0QCmnMS9Io2WBR2vB+499hIC8wC+w6du1z3nyWJwfnXp13SjBeT+VdlympMhfGqYQ1kElr0GleR/eSybxjYtxzEybjk7QDjzxAFpaqhxh5c0Hs7kOT9rE3aVKf9jx324dnh7rJr16kpnDXPWyepsYL/WMPG8xzQUsXEJ8t04LL6fDY2i2UrKpynyMuvi+Aze7fuqztFeglSBjN6CQPqhwbiEbZ1mDsPXiVBcvVMRRUg3orYphKkmKOn2CKG+bSqKJ0AZzXfT0iMLeH2G8j6F7vwbSjzY3dwMhV8392fb/6gUi2FDLzV1kSda7oyIVfouOtk6kLus+0Cvc/4GHI6SxZa9ijV565+RHcximyNVGiMICdu5ZWbED1X2sKNlf0PYdCsjF7chTxkAW6zgVKbtLHTzlx5HflWx1jA5ETfo1Vr3Sr3t/FP0/ahGChWr2mT877Kw6w25oOuNifvgQ2M X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(40470700002)(36840700001)(46966006)(426003)(6666004)(16526019)(4326008)(70586007)(81166007)(47076005)(82310400004)(110136005)(83380400001)(2906002)(26005)(86362001)(316002)(44832011)(8676002)(186003)(70206006)(1076003)(54906003)(336012)(36860700001)(8936002)(356005)(40460700001)(36756003)(508600001)(5660300002)(2616005)(7696005)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2022 23:07:39.9125 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 97c337fe-fadd-4f4c-1b39-08d9dba07db5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT013.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4221 Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org EFCH cd6h/cd7h port I/O may no longer be available on later AMD processors and it is recommended to use MMIO instead. Update the request and release functions to support MMIO. MMIO request/release and mmapping require details during cleanup. Add a MMIO configuration structure containing resource and vaddress details for mapping the region, accessing the region, and releasing the region. Signed-off-by: Terry Bowman --- drivers/i2c/busses/i2c-piix4.c | 76 +++++++++++++++++++++++++++------- 1 file changed, 61 insertions(+), 15 deletions(-) diff --git a/drivers/i2c/busses/i2c-piix4.c b/drivers/i2c/busses/i2c-piix4.c index 58b613b78c97..7aa6ceb27e4b 100644 --- a/drivers/i2c/busses/i2c-piix4.c +++ b/drivers/i2c/busses/i2c-piix4.c @@ -98,6 +98,9 @@ #define SB800_PIIX4_PORT_IDX_MASK_KERNCZ 0x18 #define SB800_PIIX4_PORT_IDX_SHIFT_KERNCZ 3 +#define SB800_PIIX4_FCH_PM_ADDR 0xFED80300 +#define SB800_PIIX4_FCH_PM_SIZE 8 + /* insmod parameters */ /* If force is set to anything different from 0, we forcibly enable the @@ -156,6 +159,12 @@ static const char *piix4_main_port_names_sb800[PIIX4_MAX_ADAPTERS] = { }; static const char *piix4_aux_port_name_sb800 = " port 1"; +struct sb800_mmio_cfg { + void __iomem *addr; + struct resource *res; + bool use_mmio; +}; + struct i2c_piix4_adapdata { unsigned short smba; @@ -163,26 +172,60 @@ struct i2c_piix4_adapdata { bool sb800_main; bool notify_imc; u8 port; /* Port number, shifted */ + struct sb800_mmio_cfg mmio_cfg; }; -static int piix4_sb800_region_setup(struct device *dev) +static int piix4_sb800_region_setup(struct device *dev, + struct sb800_mmio_cfg *mmio_cfg) { - if (!request_muxed_region(SB800_PIIX4_SMB_IDX, - SB800_PIIX4_SMB_MAP_SIZE, - "sb800_piix4_smb")) { - dev_err(dev, - "SMB base address index region 0x%x already in use.\n", - SB800_PIIX4_SMB_IDX); - return -EBUSY; + if (mmio_cfg->use_mmio) { + struct resource *res; + void __iomem *addr; + + res = request_muxed_mem_region(SB800_PIIX4_FCH_PM_ADDR, + SB800_PIIX4_FCH_PM_SIZE, + "sb800_piix4_smb"); + if (!res) { + dev_err(dev, + "SMBus base address memory region 0x%x already in use.\n", + SB800_PIIX4_FCH_PM_ADDR); + return -EBUSY; + } + + addr = ioremap(SB800_PIIX4_FCH_PM_ADDR, + SB800_PIIX4_FCH_PM_SIZE); + if (!addr) { + release_resource(res); + dev_err(dev, "SMBus base address mapping failed.\n"); + return -ENOMEM; + } + + mmio_cfg->res = res; + mmio_cfg->addr = addr; + } else { + if (!request_muxed_region(SB800_PIIX4_SMB_IDX, + SB800_PIIX4_SMB_MAP_SIZE, + "sb800_piix4_smb")) { + dev_err(dev, + "SMBus base address index region 0x%x already in use.\n", + SB800_PIIX4_SMB_IDX); + return -EBUSY; + } } return 0; } -static void piix4_sb800_region_release(struct device *dev) +static void piix4_sb800_region_release(struct device *dev, + struct sb800_mmio_cfg *mmio_cfg) { - release_region(SB800_PIIX4_SMB_IDX, - SB800_PIIX4_SMB_MAP_SIZE); + if (mmio_cfg->use_mmio) { + iounmap(mmio_cfg->addr); + release_resource(mmio_cfg->res); + } else { + release_region(SB800_PIIX4_SMB_IDX, + SB800_PIIX4_SMB_MAP_SIZE); + } } static int piix4_setup(struct pci_dev *PIIX4_dev, @@ -290,11 +333,14 @@ static int piix4_setup_sb800_smba(struct pci_dev *PIIX4_dev, u8 *smb_en_status, unsigned short *piix4_smba) { + struct sb800_mmio_cfg mmio_cfg; u8 smba_en_lo; u8 smba_en_hi; int retval; - retval = piix4_sb800_region_setup(&PIIX4_dev->dev); + mmio_cfg.use_mmio = 0; + + retval = piix4_sb800_region_setup(&PIIX4_dev->dev, &mmio_cfg); if (retval) return retval; @@ -303,7 +349,7 @@ static int piix4_setup_sb800_smba(struct pci_dev *PIIX4_dev, outb_p(smb_en + 1, SB800_PIIX4_SMB_IDX); smba_en_hi = inb_p(SB800_PIIX4_SMB_IDX + 1); - piix4_sb800_region_release(&PIIX4_dev->dev); + piix4_sb800_region_release(&PIIX4_dev->dev, &mmio_cfg); if (!smb_en) { *smb_en_status = smba_en_lo & 0x10; @@ -732,7 +778,7 @@ static s32 piix4_access_sb800(struct i2c_adapter *adap, u16 addr, u8 prev_port; int retval; - retval = piix4_sb800_region_setup(&adap->dev); + retval = piix4_sb800_region_setup(&adap->dev, &adapdata->mmio_cfg); if (retval) return retval; @@ -803,7 +849,7 @@ static s32 piix4_access_sb800(struct i2c_adapter *adap, u16 addr, piix4_imc_wakeup(); release: - piix4_sb800_region_release(&adap->dev); + piix4_sb800_region_release(&adap->dev, &adapdata->mmio_cfg); return retval; } From patchwork Wed Jan 19 23:06:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Bowman, Terry" X-Patchwork-Id: 12717859 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4F1D5C43217 for ; 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Wed, 19 Jan 2022 17:07:49 -0600 From: Terry Bowman To: , , , , , , , CC: , , , , , , , , Subject: [PATCH v3 7/9] i2c: piix4: Add EFCH MMIO support to SMBus base address detect Date: Wed, 19 Jan 2022 17:06:24 -0600 Message-ID: <20220119230626.31560-8-terry.bowman@amd.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220119230626.31560-1-terry.bowman@amd.com> References: <20220119230626.31560-1-terry.bowman@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b2403b0e-2a30-4f20-13a4-08d9dba0844b X-MS-TrafficTypeDiagnostic: BYAPR12MB3302:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3173; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 0TM0rcIcTzUj5aa9Il8nsH10ZKTrAoj/WTWWags63X5pwFR66lQy3Gx1syipIIi/uLye3VG+Bi0vRSwiB5saxVTYTcFqwyxiZoaB03XanDg1V39mo/rNpgOxeh4kahzb5C+b1fzSjPUhleJ/CKmm8dGYgrSwXqZ2i6AWYwaZh52csoLGfu1g0YHdTZEaTT8VDOp+HROeKjH3KrvRdwyL88cdRSH9q7S3mTAYREDBTqTTFmgdhNbOrz/ia5rLRKzA6p1FHniO3C5luGjFUl/sooMYkIJWWLZZGtpTHTfgesTi09314i3uEUbkoo+W2cNBKofrwid8z0b/bNB4SRF/ozkmRqlXzm6xLU4aPoOIUJ5eqLZFC25DgSZttAbQH4r2ZsTkIs/Dyq/hJwwQym7o/y/wEvMKijXaluPXLjQ4qdhjXXrOZbizspUyH62eKT0WZMKSR7yTloTO6V0ynXCGFb5fYhL0/sLC6VI0SVASxrpYeNjAiLXhUVwsIyeaLTg8PMqtDHT/1Qf/r73qfiUVEL5zPjdkXmIAKXjlCOG0Dqyq3V5YmmLIwsB84cKmh4BzKy/bkDVvVCpZ2aVf2SjK2fKmTsvY1qBiWTRsqvWSHisRfyqvKZ/0Glin/4xRx1R0t+NZe1ybnz5YtDyk0fvgARTT5ZVk1olrnETsSN3d3kumCDiBt+gja3NE9JAEsY3zilvafvQNloKhoFYFqoWx2z+I3GCrvLiTNcUBVO5tAsojtaB8S/r0y4ITvGVNM/VfSLF81XKaYYEr0CQDsVmx7ixj+9wgmDqGaJHjQVvqJxhaE2auPZOA+BakjoRar8Ip X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(40470700002)(36840700001)(46966006)(356005)(8676002)(508600001)(5660300002)(70586007)(82310400004)(70206006)(336012)(426003)(2616005)(186003)(26005)(16526019)(83380400001)(7696005)(86362001)(40460700001)(1076003)(36860700001)(81166007)(8936002)(36756003)(4326008)(44832011)(54906003)(110136005)(2906002)(316002)(6666004)(47076005)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2022 23:07:50.9617 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b2403b0e-2a30-4f20-13a4-08d9dba0844b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT056.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB3302 Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org The EFCH SMBus controller's base address is determined using details in FCH::PM::DECODEEN[smbusasfiobase] and FCH::PM::DECODEEN[smbusasfioen]. This code also writes to FCH::PM::ISACONTROL[mmioen] to enable MMIO decoding. These register fields were accessed using cd6h/cd7h port I/O. cd6h/cd7h port I/O is no longer available in later AMD processors. Change base address detection to use MMIO instead of port I/O cd6h/cd7h. Signed-off-by: Terry Bowman --- drivers/i2c/busses/i2c-piix4.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/i2c/busses/i2c-piix4.c b/drivers/i2c/busses/i2c-piix4.c index 7aa6ceb27e4b..b85f926451b8 100644 --- a/drivers/i2c/busses/i2c-piix4.c +++ b/drivers/i2c/busses/i2c-piix4.c @@ -98,6 +98,7 @@ #define SB800_PIIX4_PORT_IDX_MASK_KERNCZ 0x18 #define SB800_PIIX4_PORT_IDX_SHIFT_KERNCZ 3 +#define SB800_PIIX4_FCH_PM_DECODEEN_MMIO BIT(1) #define SB800_PIIX4_FCH_PM_ADDR 0xFED80300 #define SB800_PIIX4_FCH_PM_SIZE 8 @@ -344,10 +345,18 @@ static int piix4_setup_sb800_smba(struct pci_dev *PIIX4_dev, if (retval) return retval; - outb_p(smb_en, SB800_PIIX4_SMB_IDX); - smba_en_lo = inb_p(SB800_PIIX4_SMB_IDX + 1); - outb_p(smb_en + 1, SB800_PIIX4_SMB_IDX); - smba_en_hi = inb_p(SB800_PIIX4_SMB_IDX + 1); + if (mmio_cfg.use_mmio) { + iowrite32(ioread32(mmio_cfg.addr + 4) | SB800_PIIX4_FCH_PM_DECODEEN_MMIO, + mmio_cfg.addr + 4); + + smba_en_lo = ioread8(mmio_cfg.addr); + smba_en_hi = ioread8(mmio_cfg.addr + 1); + } else { + outb_p(smb_en, SB800_PIIX4_SMB_IDX); + smba_en_lo = inb_p(SB800_PIIX4_SMB_IDX + 1); + outb_p(smb_en + 1, SB800_PIIX4_SMB_IDX); + smba_en_hi = inb_p(SB800_PIIX4_SMB_IDX + 1); + } piix4_sb800_region_release(&PIIX4_dev->dev, &mmio_cfg); From patchwork Wed Jan 19 23:06:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Bowman, Terry" X-Patchwork-Id: 12717861 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C825EC433F5 for ; Wed, 19 Jan 2022 23:09:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1357753AbiASXJP (ORCPT ); Wed, 19 Jan 2022 18:09:15 -0500 Received: from mail-co1nam11on2041.outbound.protection.outlook.com ([40.107.220.41]:47396 "EHLO NAM11-CO1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1344307AbiASXIE (ORCPT ); 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Wed, 19 Jan 2022 23:08:02 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT009.mail.protection.outlook.com (10.13.173.20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4909.7 via Frontend Transport; Wed, 19 Jan 2022 23:08:02 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.18; Wed, 19 Jan 2022 17:08:00 -0600 From: Terry Bowman To: , , , , , , , CC: , , , , , , , , Subject: [PATCH v3 8/9] i2c: piix4: Add EFCH MMIO support for SMBus port select Date: Wed, 19 Jan 2022 17:06:25 -0600 Message-ID: <20220119230626.31560-9-terry.bowman@amd.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220119230626.31560-1-terry.bowman@amd.com> References: <20220119230626.31560-1-terry.bowman@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 20cc6cd2-4673-4f4e-ea83-08d9dba08aea X-MS-TrafficTypeDiagnostic: BY5PR12MB4147:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3513; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2022 23:08:02.0599 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 20cc6cd2-4673-4f4e-ea83-08d9dba08aea X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT009.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4147 Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org AMD processors include registers capable of selecting between 2 SMBus ports. Port selection is made during each user access by writing to FCH::PM::DECODEEN[smbus0sel]. Change the driver to use MMIO during SMBus port selection because cd6h/cd7h port I/O is not available on later AMD processors. Signed-off-by: Terry Bowman --- drivers/i2c/busses/i2c-piix4.c | 25 +++++++++++++++++-------- 1 file changed, 17 insertions(+), 8 deletions(-) diff --git a/drivers/i2c/busses/i2c-piix4.c b/drivers/i2c/busses/i2c-piix4.c index b85f926451b8..1811bdc96363 100644 --- a/drivers/i2c/busses/i2c-piix4.c +++ b/drivers/i2c/busses/i2c-piix4.c @@ -755,19 +755,28 @@ static void piix4_imc_wakeup(void) release_region(KERNCZ_IMC_IDX, 2); } -static int piix4_sb800_port_sel(u8 port) +static int piix4_sb800_port_sel(u8 port, struct sb800_mmio_cfg *mmio_cfg) { u8 smba_en_lo; - outb_p(piix4_port_sel_sb800, SB800_PIIX4_SMB_IDX); - smba_en_lo = inb_p(SB800_PIIX4_SMB_IDX + 1); + if (mmio_cfg->use_mmio) { + smba_en_lo = ioread8(mmio_cfg->addr + piix4_port_sel_sb800); + + if ((smba_en_lo & piix4_port_mask_sb800) != port) + iowrite8((smba_en_lo & ~piix4_port_mask_sb800) | port, + mmio_cfg->addr + piix4_port_sel_sb800); + } else { + outb_p(piix4_port_sel_sb800, SB800_PIIX4_SMB_IDX); + smba_en_lo = inb_p(SB800_PIIX4_SMB_IDX + 1); - if ((smba_en_lo & piix4_port_mask_sb800) != port) - outb_p((smba_en_lo & ~piix4_port_mask_sb800) | port, - SB800_PIIX4_SMB_IDX + 1); + if ((smba_en_lo & piix4_port_mask_sb800) != port) + outb_p((smba_en_lo & ~piix4_port_mask_sb800) | port, + SB800_PIIX4_SMB_IDX + 1); + } return (smba_en_lo & piix4_port_mask_sb800); } + /* * Handles access to multiple SMBus ports on the SB800. * The port is selected by bits 2:1 of the smb_en register (0x2c). @@ -844,12 +853,12 @@ static s32 piix4_access_sb800(struct i2c_adapter *adap, u16 addr, } } - prev_port = piix4_sb800_port_sel(adapdata->port); + prev_port = piix4_sb800_port_sel(adapdata->port, &adapdata->mmio_cfg); retval = piix4_access(adap, addr, flags, read_write, command, size, data); - piix4_sb800_port_sel(prev_port); + piix4_sb800_port_sel(prev_port, &adapdata->mmio_cfg); /* Release the semaphore */ outb_p(smbslvcnt | 0x20, SMBSLVCNT); From patchwork Wed Jan 19 23:06:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Bowman, Terry" X-Patchwork-Id: 12717860 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 27262C433EF for ; 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Wed, 19 Jan 2022 17:08:11 -0600 From: Terry Bowman To: , , , , , , , CC: , , , , , , , , Subject: [PATCH v3 9/9] i2c: piix4: Enable EFCH MMIO for Family 17h+ Date: Wed, 19 Jan 2022 17:06:26 -0600 Message-ID: <20220119230626.31560-10-terry.bowman@amd.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220119230626.31560-1-terry.bowman@amd.com> References: <20220119230626.31560-1-terry.bowman@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 63a6f346-4a5c-4c09-c96f-08d9dba09194 X-MS-TrafficTypeDiagnostic: BL1PR12MB5304:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5797; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: RD6xB0seqVqrq7oZQ5C9215nlw8Gkg6iSR71Ku+rC/iS/YsgWhyY4X/SMnzWHlx63fxxNINchyJKR+tBtkt0GvF7f8XXkg4UO/WqWURw1tcoW77uqx/fC3o4kSLZ/ggetbG8pVJISwhED5bFES8M/SUs2jIePNVCLRHeTma77vID4tZnd0e64LA/zJOzlq2maRv46tMzNfBRA2rKxklp6r+5XTyBba3MMJklzUfe2Dk+2JkM1G8s8hldHORM/U9MD3e9H2LwLDSue2DTVKSFfREACwW2YKGbOg6hMejJZ7l66TDQ2hRcQ5Kx46gx22OBMNnP8VOEOEd/YMrdrWxNdw/96sVXA5d3GefoAF8UGKnco61JSRxXMFtrGxWX0iBWK77qpJhRpakv5sssLT0JyLSOMoWCnWQEQy6vVonrOF5ZTB3yZjFtohA9DKVOcARkUjutmHNaphU0/D67bRHuwPNGnv5I2rBZ6xLDBYyBmOqe95RVViDNYETS18nxXZZh6gWmyYjrqx83h7CBWTMp89R0ShrE8/c2bOU6wCppznb5D1BPCg2koPUpZFzPjEimdJd47LOkmJt3MOXJAr5Q+rlTv7mdFb4vEcp2Q8qd5uklftty1vx51fGLsASuxaSLFhaRy8xBLoKBNcGfAfJObXEtqP6ogPqIPdLa/4x2xN0D1baaI2dMqpeAwfxeR0utaxM3FrQFtYyYaNUT0WNKQAfR6lMPU52km0p5lUFcDWPIDM4VuNgPWPRtnaaiblSgHP6ZQgFvIw8i6qJQx7rhXvH/pKAT1csdYi5m81yPVqa0HYBKqgPEA5OiBq7tazc4 X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(40470700002)(46966006)(316002)(356005)(47076005)(5660300002)(2616005)(36756003)(83380400001)(81166007)(426003)(54906003)(36860700001)(110136005)(508600001)(44832011)(186003)(16526019)(2906002)(1076003)(336012)(4326008)(86362001)(7696005)(8676002)(40460700001)(82310400004)(70206006)(70586007)(26005)(8936002)(6666004)(2101003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2022 23:08:13.2552 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 63a6f346-4a5c-4c09-c96f-08d9dba09194 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT059.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5304 Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org Enable EFCH MMIO using check for SMBus PCI revision ID value 0x51 or greater. SMBus PCI revision ID 0x51 is first used by family 17h. This PCI revision ID check will also enable future AMD processors with the same EFCH SMBus controller HW. Signed-off-by: Terry Bowman --- drivers/i2c/busses/i2c-piix4.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-piix4.c b/drivers/i2c/busses/i2c-piix4.c index 1811bdc96363..1e8061c46a89 100644 --- a/drivers/i2c/busses/i2c-piix4.c +++ b/drivers/i2c/busses/i2c-piix4.c @@ -102,6 +102,8 @@ #define SB800_PIIX4_FCH_PM_ADDR 0xFED80300 #define SB800_PIIX4_FCH_PM_SIZE 8 +#define AMD_PCI_SMBUS_REVISION_MMIO 0x51 + /* insmod parameters */ /* If force is set to anything different from 0, we forcibly enable the @@ -229,6 +231,13 @@ static void piix4_sb800_region_release(struct device *dev, } } +static bool piix4_sb800_use_mmio(struct pci_dev *PIIX4_dev) +{ + return (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD && + PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS && + PIIX4_dev->revision >= AMD_PCI_SMBUS_REVISION_MMIO); +} + static int piix4_setup(struct pci_dev *PIIX4_dev, const struct pci_device_id *id) { @@ -339,7 +348,7 @@ static int piix4_setup_sb800_smba(struct pci_dev *PIIX4_dev, u8 smba_en_hi; int retval; - mmio_cfg.use_mmio = 0; + mmio_cfg.use_mmio = piix4_sb800_use_mmio(PIIX4_dev); retval = piix4_sb800_region_setup(&PIIX4_dev->dev, &mmio_cfg); if (retval)