From patchwork Thu Jan 20 20:07:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 12719180 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2623AC433EF for ; Fri, 21 Jan 2022 00:14:49 +0000 (UTC) Received: from localhost ([::1]:46214 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nAhZk-0004V0-VA for qemu-devel@archiver.kernel.org; Thu, 20 Jan 2022 19:14:47 -0500 Received: from eggs.gnu.org ([209.51.188.92]:44466) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAdj5-0002jO-Vn for qemu-devel@nongnu.org; Thu, 20 Jan 2022 15:08:08 -0500 Received: from [2607:f8b0:4864:20::72f] (port=33344 helo=mail-qk1-x72f.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nAdj4-0006bX-DB for qemu-devel@nongnu.org; Thu, 20 Jan 2022 15:08:07 -0500 Received: by mail-qk1-x72f.google.com with SMTP id a21so7529863qkn.0 for ; Thu, 20 Jan 2022 12:08:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BBmkG1+ALI+HGh7UCtwJ4kgr5/kyVhEtbj+USaz0SuM=; b=l2yk5rbaD9JSrEDGdLMYoLtVQqcwvWs7mz6vdJQxNdb9rtS2gYZ2Y260zzsaaxbcmT 04jrAOybW+0YOmi98LveaNz6rWy3wt63Fw+Q+JfF3S8WS0/PGj+CeZhqMvPSu3vD5FCr JeKjUgZ8hnHLUMrSQ+XzNUWel42tqtc6KVAti7hS6fKUin+P/devlHLR38D9jQeuCKx0 dPVKPlNiHI9ViwCOrxbS2pEslo/Pss6123u4uFIndCNM5ZL0ucntbAmzvRDIhc0qlbIy 7Rjm6bc5u2jx03zP3nHrIkDSE9XaBQ89yN02QMr9c6lnIiz+UXPs0UR6gqiuXNJk2E1P QJtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BBmkG1+ALI+HGh7UCtwJ4kgr5/kyVhEtbj+USaz0SuM=; b=cILokn7J2KkDLQY7GunF6sgRtxPvZs1b9zv16x7Fn9Fa6kmPa2Y4W8Tq3vIZUgXZme tYUQEOLjbuTe9EPLwGmDEzTzsUQbTm0zKxFHDK3tGBYqXvE0CpeJ3fhSa1td0uq/XFbm j0dlWNccxMWwFZl7ko3CqJfCLZyWyqGCxRFkas7tNEPMG1tV+AUv9LyFlOSaAVUip9sy TNzaC5NxMkB7gjZ3B5MSvbCK1P+Y3Vp9+z/I+gdioSS5atDLxZiYC2cfosRKQ9iq18nq vbFGXogIFB1uKrtO9rAksPyiwAfy3kmGWjHKgu6BYLxLfIy4NVhryaC7kVowkvGrH4D2 yR+Q== X-Gm-Message-State: AOAM532a8DilBABNZg4N2YkDHpFsBCoG5S5YvMIbPpywduuV5+uVbXLa do1LOc3yPsCMReJafmJLl1nP3zdxFlfYJQ== X-Google-Smtp-Source: ABdhPJx8d+qSmPitzqOpMpA6QVvX0HrRMabC+MCDOTlgnQvaQ1b6gC5YowJTlKeENKZLBMMhRB18oA== X-Received: by 2002:a05:620a:458e:: with SMTP id bp14mr437581qkb.130.1642709285329; Thu, 20 Jan 2022 12:08:05 -0800 (PST) Received: from rivos-atish.. (adsl-70-228-75-190.dsl.akrnoh.ameritech.net. [70.228.75.190]) by smtp.gmail.com with ESMTPSA id a136sm1834160qkc.56.2022.01.20.12.08.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Jan 2022 12:08:04 -0800 (PST) From: Atish Patra To: qemu-devel@nongnu.org Subject: [RFC 1/5] target/riscv: Add the privileged spec version 1.12.0 Date: Thu, 20 Jan 2022 12:07:31 -0800 Message-Id: <20220120200735.2739543-2-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220120200735.2739543-1-atishp@rivosinc.com> References: <20220120200735.2739543-1-atishp@rivosinc.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::72f (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::72f; envelope-from=atishp@rivosinc.com; helo=mail-qk1-x72f.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Anup Patel , Bin Meng , Atish Patra , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Add the definition for ratified privileged specification version v1.12 Signed-off-by: Atish Patra --- target/riscv/cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 4d630867650a..671f65100b1a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -82,6 +82,7 @@ enum { #define PRIV_VERSION_1_10_0 0x00011000 #define PRIV_VERSION_1_11_0 0x00011100 +#define PRIV_VERSION_1_12_0 0x00011200 #define VEXT_VERSION_1_00_0 0x00010000 From patchwork Thu Jan 20 20:07:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 12719105 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7862FC433EF for ; Thu, 20 Jan 2022 22:17:51 +0000 (UTC) Received: from localhost ([::1]:33302 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nAfkc-0007ZF-3q for qemu-devel@archiver.kernel.org; Thu, 20 Jan 2022 17:17:50 -0500 Received: from eggs.gnu.org ([209.51.188.92]:44528) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAdj8-0002qE-2o for qemu-devel@nongnu.org; Thu, 20 Jan 2022 15:08:10 -0500 Received: from [2607:f8b0:4864:20::834] (port=45633 helo=mail-qt1-x834.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nAdj6-0006ib-2H for qemu-devel@nongnu.org; Thu, 20 Jan 2022 15:08:09 -0500 Received: by mail-qt1-x834.google.com with SMTP id x8so7557543qta.12 for ; Thu, 20 Jan 2022 12:08:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=D+ihxa1Ld5LxT20StF+81LT6lsXU3VYkkQbIBKYyb9w=; b=EbqYbbOu9agKYYpJipy722ZUTzDgTp25eZ+Y7AlBKndmwkenu4yJ1+S7UjS1nzWO0e 2/s4LyUypr1TncQoulW2uk60+MIiw+sPvgn7htpwTW9TJ5uSRD8BHlj0BK5cJhufKq7b Vm3ryvYwK4goxLQxHDSaslVhS+XCsuEKgeb8V+9v8Ur02SGDpE2Jk0g7yn6NK40QngEr u8E9nTR2lJ4sdYxtjff/LsDQ+Ho3CR0jliEFwJvrR+bWjMCbxlG8nEExTgsgwoetIm98 t6qwThhw7eAlv6K3ohA4OY2iSPYvjhOvl26yJH4nxh9Ng2nTrCn6zg0COl8fftE20Scc xdyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=D+ihxa1Ld5LxT20StF+81LT6lsXU3VYkkQbIBKYyb9w=; b=YorJtkB/QTJm2m5dVfjFSjBSX2yKt1L+2IJlYHrviomZzDhlesdv5v3aC1GN8iNnxh cjAXTftvKNBYhdrd17dkPFLiFe5vLkGbQAlAEjxdKuI+XaiXC2kZ2toJlX9HqmvnIIip HbHySaMRYO93ge5DYEPsRXFZ7nPrrM92Pbo2UhA+e63Hp29ElYW1qaqfyXGZMtzVIfQ4 Bhq3z346sqjTKtniFT6RQR9NBO4XMJNtE5C7hQmMsTBBSOqlclbUd6zKYMwusbMcbTF8 BF3DxrJL5b9idKoHhTNgC7tZ3ScUEUfMAYUuCzPdny1ekxiTreEF5mUKLRJ5bBPU8D6p VwoA== X-Gm-Message-State: AOAM531vZTpadGllQq921lDfr85rfjbefa/q7OnFsc5LXr2l/W8GBSMd DJB63vksmEDfkf2w3c6FYxTVYEgEppkS9A== X-Google-Smtp-Source: ABdhPJw+Vp5wD9222Ynvu/EQCjpP8cSEINE6XOkd9qh8kq+l86VQk+Rouu0C7OqVicbMVLR7YIj4nQ== X-Received: by 2002:a05:622a:512:: with SMTP id l18mr641866qtx.120.1642709286765; Thu, 20 Jan 2022 12:08:06 -0800 (PST) Received: from rivos-atish.. (adsl-70-228-75-190.dsl.akrnoh.ameritech.net. [70.228.75.190]) by smtp.gmail.com with ESMTPSA id a136sm1834160qkc.56.2022.01.20.12.08.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Jan 2022 12:08:06 -0800 (PST) From: Atish Patra To: qemu-devel@nongnu.org Subject: [RFC 2/5] target/riscv: Introduce privilege version field in the CSR ops. Date: Thu, 20 Jan 2022 12:07:32 -0800 Message-Id: <20220120200735.2739543-3-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220120200735.2739543-1-atishp@rivosinc.com> References: <20220120200735.2739543-1-atishp@rivosinc.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::834 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::834; envelope-from=atishp@rivosinc.com; helo=mail-qt1-x834.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Anup Patel , Bin Meng , Atish Patra , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" To allow/disallow the CSR access based on the privilege spec, a new field in the csr_ops is introduced. It also adds the privileged specification version (v1.12) for the CSRs introduced in the v1.12. This includes the new ratified extensions such as Vector, Hypervisor and secconfig CSR. Signed-off-by: Atish Patra --- target/riscv/cpu.h | 1 + target/riscv/csr.c | 103 ++++++++++++++++++++++++++++++--------------- 2 files changed, 69 insertions(+), 35 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 671f65100b1a..7f87917204c5 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -521,6 +521,7 @@ typedef struct { riscv_csr_op_fn op; riscv_csr_read128_fn read128; riscv_csr_write128_fn write128; + uint32_t min_priv_ver; } riscv_csr_operations; /* CSR function table constants */ diff --git a/target/riscv/csr.c b/target/riscv/csr.c index adb3d4381d1f..762d3269b4a4 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1991,13 +1991,20 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_FRM] = { "frm", fs, read_frm, write_frm }, [CSR_FCSR] = { "fcsr", fs, read_fcsr, write_fcsr }, /* Vector CSRs */ - [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart }, - [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat }, - [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm }, - [CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr }, - [CSR_VL] = { "vl", vs, read_vl }, - [CSR_VTYPE] = { "vtype", vs, read_vtype }, - [CSR_VLENB] = { "vlenb", vs, read_vlenb }, + [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart, NULL, + NULL, NULL, PRIV_VERSION_1_12_0 }, + [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat, NULL, + NULL, NULL, PRIV_VERSION_1_12_0 }, + [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm, NULL, + NULL, NULL, PRIV_VERSION_1_12_0 }, + [CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr, NULL, + NULL, NULL, PRIV_VERSION_1_12_0 }, + [CSR_VL] = { "vl", vs, read_vl, NULL, NULL, NULL, NULL, + PRIV_VERSION_1_12_0 }, + [CSR_VTYPE] = { "vtype", vs, read_vtype, NULL, NULL, NULL, NULL, + PRIV_VERSION_1_12_0 }, + [CSR_VLENB] = { "vlenb", vs, read_vlenb, NULL, NULL, NULL, NULL, + PRIV_VERSION_1_12_0 }, /* User Timers and Counters */ [CSR_CYCLE] = { "cycle", ctr, read_instret }, [CSR_INSTRET] = { "instret", ctr, read_instret }, @@ -2063,36 +2070,62 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { /* Supervisor Protection and Translation */ [CSR_SATP] = { "satp", smode, read_satp, write_satp }, - [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus }, - [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg }, - [CSR_HIDELEG] = { "hideleg", hmode, read_hideleg, write_hideleg }, - [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip }, - [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip }, - [CSR_HIE] = { "hie", hmode, read_hie, write_hie }, - [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, write_hcounteren }, - [CSR_HGEIE] = { "hgeie", hmode, read_zero, write_hgeie }, - [CSR_HTVAL] = { "htval", hmode, read_htval, write_htval }, - [CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst }, - [CSR_HGEIP] = { "hgeip", hmode, read_zero, write_hgeip }, - [CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp }, - [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, write_htimedelta }, - [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah }, - - [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, write_vsstatus }, - [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip }, - [CSR_VSIE] = { "vsie", hmode, read_vsie, write_vsie }, - [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec }, - [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, write_vsscratch }, - [CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc }, - [CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause }, - [CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval }, - [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp }, - - [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2 }, - [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst }, + [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus, + NULL, NULL, NULL, PRIV_VERSION_1_12_0 }, + [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg, + NULL, NULL, NULL, PRIV_VERSION_1_12_0 }, + [CSR_HIDELEG] = { "hideleg", hmode, read_hideleg, write_hideleg, + NULL, NULL, NULL, PRIV_VERSION_1_12_0 }, + [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip, + NULL, NULL, PRIV_VERSION_1_12_0 }, + [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip, + NULL, NULL, PRIV_VERSION_1_12_0 }, + [CSR_HIE] = { "hie", hmode, read_hie, write_hie, + NULL, NULL, NULL, PRIV_VERSION_1_12_0 }, + [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, write_hcounteren, + NULL, NULL, NULL, PRIV_VERSION_1_12_0 }, + [CSR_HGEIE] = { "hgeie", hmode, read_zero, write_hgeie, + NULL, NULL, NULL, PRIV_VERSION_1_12_0 }, + [CSR_HTVAL] = { "htval", hmode, read_htval, write_htval, + NULL, NULL, NULL, PRIV_VERSION_1_12_0 }, + [CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst, + NULL, NULL, NULL, PRIV_VERSION_1_12_0 }, + [CSR_HGEIP] = { "hgeip", hmode, read_zero, write_hgeip, + NULL, NULL, NULL, PRIV_VERSION_1_12_0 }, + [CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp, + NULL, NULL, NULL, PRIV_VERSION_1_12_0 }, + [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, write_htimedelta, + NULL, NULL, NULL, PRIV_VERSION_1_12_0 }, + [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah, + NULL, NULL, NULL, PRIV_VERSION_1_12_0 }, + + [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, write_vsstatus, + NULL, NULL, NULL, PRIV_VERSION_1_12_0 }, + [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip, + NULL, NULL, PRIV_VERSION_1_12_0 }, + [CSR_VSIE] = { "vsie", hmode, read_vsie, write_vsie, + NULL, NULL, NULL, PRIV_VERSION_1_12_0 }, + [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec, + NULL, NULL, NULL, PRIV_VERSION_1_12_0 }, + [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, write_vsscratch, + NULL, NULL, NULL, PRIV_VERSION_1_12_0 }, + [CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc, + NULL, NULL, NULL, PRIV_VERSION_1_12_0 }, + [CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause, + NULL, NULL, NULL, PRIV_VERSION_1_12_0 }, + [CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval, + NULL, NULL, NULL, PRIV_VERSION_1_12_0 }, + [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp, + NULL, NULL, NULL, PRIV_VERSION_1_12_0 }, + + [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2, + NULL, NULL, NULL, PRIV_VERSION_1_12_0 }, + [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst, + NULL, NULL, NULL, PRIV_VERSION_1_12_0 }, /* Physical Memory Protection */ - [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg }, + [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg, + NULL, NULL, NULL, PRIV_VERSION_1_12_0 }, [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg }, [CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg }, [CSR_PMPCFG2] = { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg }, From patchwork Thu Jan 20 20:07:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 12719165 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9189DC433EF for ; Thu, 20 Jan 2022 23:37:09 +0000 (UTC) Received: from localhost ([::1]:38690 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nAgzM-00044P-Gg for qemu-devel@archiver.kernel.org; Thu, 20 Jan 2022 18:37:08 -0500 Received: from eggs.gnu.org ([209.51.188.92]:44570) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAdj9-0002u8-7r for qemu-devel@nongnu.org; Thu, 20 Jan 2022 15:08:11 -0500 Received: from [2607:f8b0:4864:20::82a] (port=37875 helo=mail-qt1-x82a.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nAdj7-0006jd-6v for qemu-devel@nongnu.org; Thu, 20 Jan 2022 15:08:10 -0500 Received: by mail-qt1-x82a.google.com with SMTP id w6so7626936qtk.4 for ; Thu, 20 Jan 2022 12:08:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gcyvwy60lDI4mRKvvhxRvuWkmlILSey6pXpoZi3U/Ok=; b=BI7GWHHBZHT5mTxauRM9DklNp0DI72XFoRqJ52e0+rStA8+ZVJPpBZ1bxr+/iqKMnw Qw0KS/kMo0WgrGTbhNCrn+MQtSv39Txbnh4/0k4Q1uczXB5KDxgDpMymsoNgSevx84QP 40XGtafwWnYMt0SZecq2KhIMZcuGsk8vZ+a86ILI8h+ttRR78D8PMs6tJhl3ed2A4Vyv GJ/AHmtFNcVweNs3BidhUsGqeV0CBeN0NL1tgamOFSmByoaLiwx26DfbB4kH3yVMxmc2 iPJxHG/6cgrWem++FY8RoHa9DXWBIVtEDHNDXhYsGJX3K7vq3qT32Gu9D7v+h63DdTXX RoJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gcyvwy60lDI4mRKvvhxRvuWkmlILSey6pXpoZi3U/Ok=; b=MRGn5ekoMp6bNnNUF+boImYdirI2qc/aa7+wEbgGZ0/5XY/9aNSALnLuOSc/RRmxc8 jSBYtY9EVoMZs/rOlxFVPca6vfTPg2040awXE3Ja/l9qsVnbmhtR6KgqXVOPK16xwkmh LOpHoxK/2xXITQyl2PZSkO1/AnryhD2sOeiYXoDTPhAnStBhQqlnyFQ262H/4jKP5jAD 3j9neVcuHKRQa9BJZnHP94uA90xN3rGHsmShH7BK9KkBTzsG83LUvYRdSM4fjGiWSdkM IHzM4Lv1mHeTnmPCi4paouobKDba8nnaC55VlYr7mDPBbdR8+sv2IbnXJ7heM40luZ0l QzXw== X-Gm-Message-State: AOAM532KYlr45EK/gxSWjadDV6WavD9d4+76jrpPTdg1Qhkq6Q/Z+F2L 5+QEs1TmMteoEsfdDqeVWSZm/RzREO/qjQ== X-Google-Smtp-Source: ABdhPJyliGdFSMV2Im1Kn2Aib9rWlpdIlloIh0IDS3vQTmPpXV/3yL1+xg2XUOW1bXUbeyiWDawT4g== X-Received: by 2002:ac8:7e89:: with SMTP id w9mr639009qtj.328.1642709288126; Thu, 20 Jan 2022 12:08:08 -0800 (PST) Received: from rivos-atish.. (adsl-70-228-75-190.dsl.akrnoh.ameritech.net. [70.228.75.190]) by smtp.gmail.com with ESMTPSA id a136sm1834160qkc.56.2022.01.20.12.08.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Jan 2022 12:08:07 -0800 (PST) From: Atish Patra To: qemu-devel@nongnu.org Subject: [RFC 3/5] target/riscv: Add support for mconfigptr Date: Thu, 20 Jan 2022 12:07:33 -0800 Message-Id: <20220120200735.2739543-4-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220120200735.2739543-1-atishp@rivosinc.com> References: <20220120200735.2739543-1-atishp@rivosinc.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::82a (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::82a; envelope-from=atishp@rivosinc.com; helo=mail-qt1-x82a.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Anup Patel , Bin Meng , Atish Patra , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" RISC-V privileged specification v1.12 introduced a mconfigptr which will hold the physical address of a configuration data structure. As Qemu doesn't have a configuration data structure, is read as zero which is valid as per the priv spec. Signed-off-by: Atish Patra --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 5a6d49aa64cc..f6f90b5cbd52 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -148,6 +148,7 @@ #define CSR_MARCHID 0xf12 #define CSR_MIMPID 0xf13 #define CSR_MHARTID 0xf14 +#define CSR_MCONFIGPTR 0xf15 /* Machine Trap Setup */ #define CSR_MSTATUS 0x300 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 762d3269b4a4..e66bf2201857 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -2030,6 +2030,8 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_MARCHID] = { "marchid", any, read_zero }, [CSR_MIMPID] = { "mimpid", any, read_zero }, [CSR_MHARTID] = { "mhartid", any, read_mhartid }, + [CSR_MCONFIGPTR] = { "mconfigptr", any, read_zero, NULL, NULL, NULL, NULL, + PRIV_VERSION_1_12_0}, /* Machine Trap Setup */ [CSR_MSTATUS] = { "mstatus", any, read_mstatus, write_mstatus, NULL, From patchwork Thu Jan 20 20:07:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 12719122 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E08ECC433EF for ; Thu, 20 Jan 2022 23:14:42 +0000 (UTC) Received: from localhost ([::1]:37130 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nAgdd-00084z-4V for qemu-devel@archiver.kernel.org; Thu, 20 Jan 2022 18:14:41 -0500 Received: from eggs.gnu.org ([209.51.188.92]:44610) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAdjA-00030d-Tw for qemu-devel@nongnu.org; Thu, 20 Jan 2022 15:08:12 -0500 Received: from [2607:f8b0:4864:20::f2f] (port=34704 helo=mail-qv1-xf2f.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nAdj8-0006kD-TA for qemu-devel@nongnu.org; Thu, 20 Jan 2022 15:08:12 -0500 Received: by mail-qv1-xf2f.google.com with SMTP id a7so8030168qvl.1 for ; Thu, 20 Jan 2022 12:08:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Nj3WhyNP+S00BDAxW6pcamIiXSThg7IDMnlWfmpaY40=; b=y96BYY53dBdQRUpCo8YwTGjwEiPm5R9t0F2mEI61W7XzNgMm4ifQXQDc79+z8gTb28 OHABvV0U9dPcefonpC7BD17hpQTJzEpITdtIl6ELyCrIrhUAcbfr/TBJBTPFiseRjB8N Jq4opnwudcOkRzzOdprLGx5fdcvJk8oyZKloKOoZTXZe+CJrxPak/zxvhMBYjdcbfcj9 RW9laG3z541VkKHuq2UhXiP/4AtyhYbIGaaawc7dlXNtlBZAqgqozPyGz+3vAtIihm+b rrrQ2dLltTEk6tvf7IHypz6UDF1Qs8L23OGZwmq0wnkwWbM2NiyagAeK3Ce8l38KYfLJ p0FQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Nj3WhyNP+S00BDAxW6pcamIiXSThg7IDMnlWfmpaY40=; b=DBA1aJjHWZOv39eWXW87bOOqb7WkAqy4VlO4lNmU9hYIlvVC7h96rQVrB6m6JVMkNI DspG9YIwODg7iWVL9lkKBqXbRQNw33iEDwEhEVuhjkK8/8tyO3ta0m6r+GAMvvAn+BEz fb+Cb9MQ3JnniQau/HeQJz42C8Kv/PbQ4qEYOYU8guEgG8gnfUKPGWXuM6w9JoAoerN4 PTZQwbNL55BtaYCXorpJSnbfYug/9whyp8l+J0+wwwYxRbKcOERujizN38bLjHNsC/3k 8y93oHLwaQgkLYOYzFl42jviRJZBnT9991HAq5ZIVGsIYjaSmYJAci/ZeHRvHI57g7U8 iWIQ== X-Gm-Message-State: AOAM532vooLcjZkN+SJpZfvUNSdmu4cLoFkzJHCjzDDENB9MhFAIpzNL yAmav0NTEIge/69kYlWlYFVSPtpSMS+ydA== X-Google-Smtp-Source: ABdhPJy7c+hgD4+rE/KHuvcdYqDNArNJOu7WNoqW5k4khnJlQZ8bjenW4fZo5D0Od7KKUTBeP5w/cg== X-Received: by 2002:ad4:4c50:: with SMTP id cs16mr493477qvb.74.1642709289676; Thu, 20 Jan 2022 12:08:09 -0800 (PST) Received: from rivos-atish.. (adsl-70-228-75-190.dsl.akrnoh.ameritech.net. [70.228.75.190]) by smtp.gmail.com with ESMTPSA id a136sm1834160qkc.56.2022.01.20.12.08.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Jan 2022 12:08:09 -0800 (PST) From: Atish Patra To: qemu-devel@nongnu.org Subject: [RFC 4/5] target/riscv: Add *envcfg* CSRs support Date: Thu, 20 Jan 2022 12:07:34 -0800 Message-Id: <20220120200735.2739543-5-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220120200735.2739543-1-atishp@rivosinc.com> References: <20220120200735.2739543-1-atishp@rivosinc.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::f2f (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::f2f; envelope-from=atishp@rivosinc.com; helo=mail-qv1-xf2f.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Anup Patel , Bin Meng , Atish Patra , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The RISC-V privileged specification v1.12 defines few execution environment configuration CSRs that can be used enable/disable extensions per privilege levels. Add the basic support for these CSRs. Signed-off-by: Atish Patra --- target/riscv/cpu.h | 8 ++++ target/riscv/cpu_bits.h | 31 +++++++++++++++ target/riscv/csr.c | 84 +++++++++++++++++++++++++++++++++++++++++ target/riscv/machine.c | 26 +++++++++++++ 4 files changed, 149 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7f87917204c5..b9462300a472 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -264,6 +264,14 @@ struct CPURISCVState { target_ulong spmbase; target_ulong upmmask; target_ulong upmbase; + + /* CSRs for execution enviornment configuration */ + + target_ulong menvcfg; + target_ulong menvcfgh; + target_ulong senvcfg; + target_ulong henvcfg; + target_ulong henvcfgh; #endif float_status fp_status; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index f6f90b5cbd52..afb237c2313b 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -177,6 +177,9 @@ #define CSR_STVEC 0x105 #define CSR_SCOUNTEREN 0x106 +/* Supervisor Configuration CSRs */ +#define CSR_SENVCFG 0x10A + /* Supervisor Trap Handling */ #define CSR_SSCRATCH 0x140 #define CSR_SEPC 0x141 @@ -204,6 +207,10 @@ #define CSR_HTIMEDELTA 0x605 #define CSR_HTIMEDELTAH 0x615 +/* Hypervisor Configuration CSRs */ +#define CSR_HENVCFG 0x60A +#define CSR_HENVCFGH 0x61A + /* Virtual CSRs */ #define CSR_VSSTATUS 0x200 #define CSR_VSIE 0x204 @@ -218,6 +225,10 @@ #define CSR_MTINST 0x34a #define CSR_MTVAL2 0x34b +/* Machine Configuration CSRs */ +#define CSR_MENVCFG 0x30A +#define CSR_MENVCFGH 0x31A + /* Enhanced Physical Memory Protection (ePMP) */ #define CSR_MSECCFG 0x747 #define CSR_MSECCFGH 0x757 @@ -578,6 +589,26 @@ typedef enum RISCVException { #define PM_EXT_CLEAN 0x00000002ULL #define PM_EXT_DIRTY 0x00000003ULL +/* Execution enviornment configuration bits */ +#define MENVCFG_FIOM (1 << 0) +#define MENVCFG_CBE 0x30000ULL +#define MENVCFG_CBCFE (1 << 6) +#define MENVCFG_CBZE (1 << 7) +#define MENVCFG_PBMTE (1 << 62) +#define MENVCFG_STCE (1 << 63) + +#define SENVCFG_FIOM MENVCFG_FIOM +#define SENVCFG_CBE MENVCFG_CBE +#define SENVCFG_CBCFE MENVCFG_CBCFE +#define SENVCFG_CBZE MENVCFG_CBZE + +#define HENVCFG_FIOM MENVCFG_FIOM +#define HENVCFG_CBE MENVCFG_CBE +#define HENVCFG_CBCFE MENVCFG_CBCFE +#define HENVCFG_CBZE MENVCFG_CBZE +#define HENVCFG_PBMTE MENVCFG_PBMTE +#define HENVCFG_STCE MENVCFG_STCE + /* Offsets for every pair of control bits per each priv level */ #define XS_OFFSET 0ULL #define U_OFFSET 2ULL diff --git a/target/riscv/csr.c b/target/riscv/csr.c index e66bf2201857..a4bbae7a1bbd 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -853,6 +853,77 @@ static RISCVException write_mtval(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } +/* Execution environment configuration setup */ +static RISCVException read_menvcfg(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val = env->menvcfg; + return RISCV_EXCP_NONE; +} + +static RISCVException write_menvcfg(CPURISCVState *env, int csrno, + target_ulong val) +{ + env->menvcfg = val; + return RISCV_EXCP_NONE; +} + +static RISCVException read_menvcfgh(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val = env->menvcfgh; + return RISCV_EXCP_NONE; +} + +static RISCVException write_menvcfgh(CPURISCVState *env, int csrno, + target_ulong val) +{ + env->menvcfgh = val; + return RISCV_EXCP_NONE; +} + +static RISCVException read_senvcfg(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val = env->senvcfg; + return RISCV_EXCP_NONE; +} + +static RISCVException write_senvcfg(CPURISCVState *env, int csrno, + target_ulong val) +{ + env->senvcfg = val; + return RISCV_EXCP_NONE; +} + +static RISCVException read_henvcfg(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val = env->henvcfg; + return RISCV_EXCP_NONE; +} + +static RISCVException write_henvcfg(CPURISCVState *env, int csrno, + target_ulong val) +{ + env->henvcfg = val; + return RISCV_EXCP_NONE; +} + +static RISCVException read_henvcfgh(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val = env->henvcfgh; + return RISCV_EXCP_NONE; +} + +static RISCVException write_henvcfgh(CPURISCVState *env, int csrno, + target_ulong val) +{ + env->henvcfgh = val; + return RISCV_EXCP_NONE; +} + static RISCVException rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value, target_ulong new_value, target_ulong write_mask) @@ -2054,6 +2125,19 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_MTVAL] = { "mtval", any, read_mtval, write_mtval }, [CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip }, + /* Execution environment configuration */ + [CSR_MENVCFG] = { "menvcfg", any, read_menvcfg, write_menvcfg, NULL, + NULL, NULL, PRIV_VERSION_1_12_0}, + [CSR_MENVCFGH] = { "menvcfgh", any32, read_menvcfgh, write_menvcfgh, NULL, + NULL, NULL, PRIV_VERSION_1_12_0}, + [CSR_SENVCFG] = { "senvcfg", smode, read_senvcfg, write_senvcfg, NULL, + NULL, NULL, PRIV_VERSION_1_12_0}, + [CSR_HENVCFG] = { "henvcfg", hmode, read_henvcfg, write_henvcfg, NULL, + NULL, NULL, PRIV_VERSION_1_12_0}, + [CSR_HENVCFGH] = { "henvcfgh", hmode32, read_henvcfgh, write_henvcfgh, NULL, + NULL, NULL, PRIV_VERSION_1_12_0}, + + /* Supervisor Trap Setup */ [CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus, NULL, read_sstatus_i128 }, diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 13b9ab375b95..59479a999b87 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -185,6 +185,31 @@ static const VMStateDescription vmstate_rv128 = { } }; +/* TODO: henvcfg need both hyper_needed & envcfg_needed */ +static bool envcfg_needed(void *opaque) +{ + RISCVCPU *cpu = opaque; + CPURISCVState *env = &cpu->env; + + return (env->priv_ver >= PRIV_VERSION_1_12_0 ? 1 : 0); +} + +static const VMStateDescription vmstate_envcfg = { + .name = "cpu/envcfg", + .version_id = 1, + .minimum_version_id = 1, + .needed = envcfg_needed, + .fields = (VMStateField[]) { + VMSTATE_UINTTL(env.menvcfg, RISCVCPU), + VMSTATE_UINTTL(env.menvcfgh, RISCVCPU), + VMSTATE_UINTTL(env.senvcfg, RISCVCPU), + VMSTATE_UINTTL(env.henvcfg, RISCVCPU), + VMSTATE_UINTTL(env.henvcfgh, RISCVCPU), + + VMSTATE_END_OF_LIST() + } +}; + const VMStateDescription vmstate_riscv_cpu = { .name = "cpu", .version_id = 3, @@ -240,6 +265,7 @@ const VMStateDescription vmstate_riscv_cpu = { &vmstate_vector, &vmstate_pointermasking, &vmstate_rv128, + &vmstate_envcfg, NULL } }; From patchwork Thu Jan 20 20:07:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 12719168 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 74F4DC433EF for ; Thu, 20 Jan 2022 23:44:11 +0000 (UTC) Received: from localhost ([::1]:46128 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nAh6A-0001CN-8k for qemu-devel@archiver.kernel.org; Thu, 20 Jan 2022 18:44:10 -0500 Received: from eggs.gnu.org ([209.51.188.92]:44638) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nAdjC-00035j-3T for qemu-devel@nongnu.org; Thu, 20 Jan 2022 15:08:14 -0500 Received: from [2607:f8b0:4864:20::732] (port=35470 helo=mail-qk1-x732.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nAdjA-0006kl-Cv for qemu-devel@nongnu.org; Thu, 20 Jan 2022 15:08:13 -0500 Received: by mail-qk1-x732.google.com with SMTP id j85so7490059qke.2 for ; Thu, 20 Jan 2022 12:08:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pkyENVGUMb3mufj6ENQMxHRLGDlkjMu9ZYeHJiUyAZs=; b=WoN9cxO3iSz5z68avTv/5yxHCGJo8B5cFJhG9ZCt1ymLj071kfPjd09o1NaO+igV39 3P6UR+XGyqWaaL9+Cocqww9QfS8+JdjG9oZ56ywS3KTpG/g7aWOXhN+ZSTPm+4IloC+X raQUb/Dbn0RP4g1Jteog/C2rMSITUyVNIXWhZSiHBBHG2Y3rJYcJdtvF/gJHY9xsMseM 7Z86Pj8QW+BlaZ8WFRr2IPSBgX/xlX0KDGITT3fudBLDV4Ele4BAv2g3Qgx3SoY/8UOW wytpLTRDJjW3uREgXLXFBnrqNpzh1HY8tRhY6tE6N78So1I+nICJIGsrs8N1Z1cqLIT6 3ggA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pkyENVGUMb3mufj6ENQMxHRLGDlkjMu9ZYeHJiUyAZs=; b=pljmoyA30DUOYfZuDcynwxtMMymio9hLGyfvc+GGniRZ4fdaWnqbknqu+uDOXQY4ZH u1e5+O6LtNBxAnii+i1H8kmmpwsWRZ4/WE1yayluA5qUpUVBvlSMdlSz9f+eiSKuOfKg VabkDnF+s8Jo/LQzVPECJcFmzK689ImmPTJhKVIMcE3lTqz/ecyImLmOxJGI55/FEh6T uwczjQhKz5VAFUKPzfmM9SFa5dDccK6vcYuVrcQ61F+jFZdGsoSiz9bhuasJRZHYMhVk F89ojf2njOWDbV20D/36QoOM+kVyW48+UDe0nO9XKlkGIHaRcEgCWj6PSkcr1UCtuIaC rq4A== X-Gm-Message-State: AOAM532yAZqgwuSzHdu78Xmx0V10OWp6xwXBdJbe4HVkvqVhNXk4+5xb 9mfZJk7c/oCbq6GeqZb9O9iu4Py+1WXKqQ== X-Google-Smtp-Source: ABdhPJw/4BL1RqNPQce4YIreliiKBZOMcvv5VwmC9Azki9+QnOUycetcu82J0pWJtCnojsT9Mxqsjw== X-Received: by 2002:a05:620a:2684:: with SMTP id c4mr440358qkp.24.1642709291245; Thu, 20 Jan 2022 12:08:11 -0800 (PST) Received: from rivos-atish.. (adsl-70-228-75-190.dsl.akrnoh.ameritech.net. [70.228.75.190]) by smtp.gmail.com with ESMTPSA id a136sm1834160qkc.56.2022.01.20.12.08.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Jan 2022 12:08:10 -0800 (PST) From: Atish Patra To: qemu-devel@nongnu.org Subject: [RFC 5/5] target/riscv: Enable privileged spec version 1.12 Date: Thu, 20 Jan 2022 12:07:35 -0800 Message-Id: <20220120200735.2739543-6-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220120200735.2739543-1-atishp@rivosinc.com> References: <20220120200735.2739543-1-atishp@rivosinc.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::732 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::732; envelope-from=atishp@rivosinc.com; helo=mail-qk1-x732.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Anup Patel , Bin Meng , Atish Patra , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Virt machine uses privileged specification version 1.12 now. All other machine continue to use the default one defined for that machine unless changed to 1.12 by the user explicitly. Signed-off-by: Atish Patra --- target/riscv/cpu.c | 8 +++++--- target/riscv/csr.c | 10 ++++++++++ 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9bc25d3055d4..cec5791151e7 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -153,7 +153,7 @@ static void riscv_any_cpu_init(Object *obj) #elif defined(TARGET_RISCV64) set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); #endif - set_priv_version(env, PRIV_VERSION_1_11_0); + set_priv_version(env, PRIV_VERSION_1_12_0); } #if defined(TARGET_RISCV64) @@ -439,7 +439,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } if (cpu->cfg.priv_spec) { - if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { + if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { + priv_version = PRIV_VERSION_1_12_0; + } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { priv_version = PRIV_VERSION_1_11_0; } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { priv_version = PRIV_VERSION_1_10_0; @@ -454,7 +456,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) if (priv_version) { set_priv_version(env, priv_version); } else if (!env->priv_ver) { - set_priv_version(env, PRIV_VERSION_1_11_0); + set_priv_version(env, PRIV_VERSION_1_12_0); } if (cpu->cfg.mmu) { diff --git a/target/riscv/csr.c b/target/riscv/csr.c index a4bbae7a1bbd..62d429cc3f17 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1874,6 +1874,12 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env, int read_only = get_field(csrno, 0xC00) == 3; #if !defined(CONFIG_USER_ONLY) int effective_priv = env->priv; + int csr_min_priv = csr_ops[csrno].min_priv_ver; + + /* The default privilege specification version supported is 1.10 */ + if (!csr_min_priv) { + csr_min_priv = PRIV_VERSION_1_10_0; + } if (riscv_has_ext(env, RVH) && env->priv == PRV_S && @@ -1904,6 +1910,10 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env, return RISCV_EXCP_ILLEGAL_INST; } + if (env->priv_ver < csr_min_priv) { + return RISCV_EXCP_ILLEGAL_INST; + } + return csr_ops[csrno].predicate(env, csrno); }