From patchwork Thu Jan 20 23:20:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12719134 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58D2DC4332F for ; Thu, 20 Jan 2022 23:20:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378184AbiATXUo (ORCPT ); Thu, 20 Jan 2022 18:20:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39590 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378156AbiATXUf (ORCPT ); Thu, 20 Jan 2022 18:20:35 -0500 Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [IPv6:2a00:1450:4864:20::32d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0B53AC061574; Thu, 20 Jan 2022 15:20:35 -0800 (PST) Received: by mail-wm1-x32d.google.com with SMTP id q141-20020a1ca793000000b00347b48dfb53so17814279wme.0; Thu, 20 Jan 2022 15:20:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=yLgKzWlNB46h4cCxcd6MlOdDX7NDwn6Xp4ylh5jriKo=; b=co4Wq1cm6z6LLDXS4ecPwr0XrQn6k407E/wnERm/vD4/3oIq4EChBGSf4IRoUNVqij YQgz4CBXnVj8Cv6iqEa60N8Ts6AXtqL2wjEpgAm+WGVkOyMLs01HGrJz+hGWCSoqyWir dpBV/vivTwC97ti0m5fCYw492bi4lBd7ZKE3Pa95rrvtpzPL4H6JG8p+ISZmVfjtFgEy jUdBIkCOtxtM3lUQ6KCOuyCJrJZ+4RjfJwzlX+XswTf9ItAeX4RytNaCnUjUOj2hyNlB KByEGyvoptcXIcGhld509EIjKi9AoRLoraxagqBKJfKhI2quog47x8jYAoPzkge0Y0eH xsvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yLgKzWlNB46h4cCxcd6MlOdDX7NDwn6Xp4ylh5jriKo=; b=WDsbjdrhqR9CH2oUgmmDFNCoE7JNNKRNxTg9wLmZrTG896iTk0YvMlHz3y9PEWQ+ed 3DEgA+EPyEPcr5tRSOBtqHhlcDFOwbBe6cks0zMryDq4S0H1MpY0S+ZrbcpqNZcZ69RP b0uS3/fzdXn+5DEB0V8DRhLNS/sAJuL1Ckdb688AxSZgWMf5i5aatWVed0LyBCpeYILa ijrjNc2ga8nJhSL/TYcUdxdjI0ycDNlmtgI1o8PwDXXcnjjE7ZyAizweHYdB/cjrfHse y5Nx85sJ+W7kb7FZK2w0P4NRlTCqd6AlJkb2BG5icLBpFdt4q4rN7MxVjAKQ/7Drtur6 /6qQ== X-Gm-Message-State: AOAM531a6Xew7jITnIhj221xez8re8OyayUJJFjl+R/YQbyZOgshQ7Vo XGi6Nf9mVybjs8Ar0xEHB14= X-Google-Smtp-Source: ABdhPJxw5KjBYGVH5hjG7osX6x9iTgxr3OjDNdhzsuvWuP5sl1NgcaP0/bxika7l56StnCbRtcAMmQ== X-Received: by 2002:a5d:488a:: with SMTP id g10mr1175857wrq.653.1642720833423; Thu, 20 Jan 2022 15:20:33 -0800 (PST) Received: from localhost.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id a9sm3939283wmm.32.2022.01.20.15.20.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Jan 2022 15:20:33 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Taniya Das , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 01/15] dt-bindings: clock: permit additionalProprieties to qcom,gcc Date: Fri, 21 Jan 2022 00:20:14 +0100 Message-Id: <20220120232028.6738-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220120232028.6738-1-ansuelsmth@gmail.com> References: <20220120232028.6738-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org To permit the use of qcom,gcc as a template for other Documentation, set additionalProprieties to true. While at it add the missing syscon for qcom,ipq8064 that is mandatory for the correct function of the tsens driver. Signed-off-by: Ansuel Smith --- .../devicetree/bindings/clock/qcom,gcc.yaml | 41 ++++++++++--------- 1 file changed, 22 insertions(+), 19 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml index f66d703bd913..3fd03687a6f7 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml @@ -36,24 +36,27 @@ description: | properties: compatible: - enum: - - qcom,gcc-apq8084 - - qcom,gcc-ipq4019 - - qcom,gcc-ipq6018 - - qcom,gcc-ipq8064 - - qcom,gcc-mdm9607 - - qcom,gcc-msm8226 - - qcom,gcc-msm8660 - - qcom,gcc-msm8916 - - qcom,gcc-msm8939 - - qcom,gcc-msm8953 - - qcom,gcc-msm8960 - - qcom,gcc-msm8974 - - qcom,gcc-msm8974pro - - qcom,gcc-msm8974pro-ac - - qcom,gcc-mdm9615 - - qcom,gcc-sdm630 - - qcom,gcc-sdm660 + oneOf: + - enum: + - qcom,gcc-apq8084 + - qcom,gcc-ipq4019 + - qcom,gcc-ipq6018 + - qcom,gcc-mdm9607 + - qcom,gcc-msm8226 + - qcom,gcc-msm8660 + - qcom,gcc-msm8916 + - qcom,gcc-msm8939 + - qcom,gcc-msm8953 + - qcom,gcc-msm8960 + - qcom,gcc-msm8974 + - qcom,gcc-msm8974pro + - qcom,gcc-msm8974pro-ac + - qcom,gcc-mdm9615 + - qcom,gcc-sdm630 + - qcom,gcc-sdm660 + - items: + - const: qcom,gcc-ipq8064 + - const: syscon '#clock-cells': const: 1 @@ -78,7 +81,7 @@ required: - '#reset-cells' - '#power-domain-cells' -additionalProperties: false +additionalProperties: true examples: # Example for GCC for MSM8960: From patchwork Thu Jan 20 23:20:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12719133 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 186D7C433EF for ; Thu, 20 Jan 2022 23:20:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378172AbiATXUm (ORCPT ); Thu, 20 Jan 2022 18:20:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39594 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378158AbiATXUg (ORCPT ); Thu, 20 Jan 2022 18:20:36 -0500 Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [IPv6:2a00:1450:4864:20::330]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1A921C06173F; Thu, 20 Jan 2022 15:20:36 -0800 (PST) Received: by mail-wm1-x330.google.com with SMTP id j5-20020a05600c1c0500b0034d2e956aadso17640157wms.4; Thu, 20 Jan 2022 15:20:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=+A0y4CdRvgUX+GrCK344T8r/tQN4874ehIU8J3A6Bjo=; b=cM2seonXSM/uOv5mpKdenKOcBAiT5HDQ6IMdrmr22+BzojXZWv+FMQ9mt5SZXVODq1 YQbHDXy8foy3GSt0m+zWsAOm10LDPLSTU/at3epvKDp4GaJteuNmESO5duviY42duQvJ 2s+Ol76rqFpBzLWVKtayrqdvg+uj7oeRovOGCCQDHiHTjA88+Tg0F63w79Q0X9KByyp/ X4AkKV2Ykg13PxQwXq6VMrjjzF9fBfh/qPZrO1gaEXrzrPbG+Hv+23PLoDtIvehvzuRg haJI+1mUnGkoPILtKJrhWhiuv5bflGpazHeYRJ39p2mifbbBKEck6eLO6WY0WPo5J8D2 hshg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+A0y4CdRvgUX+GrCK344T8r/tQN4874ehIU8J3A6Bjo=; b=dOZQ/b+PW6tIZZvWG2KM784e9X/J4VdgIygBq+g33fKMj8ss6Iu7V9U9P+2SJUGo8e E9my8HJZAeDOa2Ak6c/Qi9B8Rz/ynMGockHlF17Su52XJPjaLPOFT1j3rnOWDjhb7MhB 70NGnrhcYnsYf4DAbEjGG8pdF2L03nj0bsriiV3ejHWKmdDvggtWWiyHz0FXGrpdHieQ dIumKSfA1pKdOswjL4jz28v3iS6izxoDiVtI4tjqZVRUoCnS0JnmGym4mMK1b+YtHWWS e4izwgBMO1KMwIZXXnu99F4NDAGx5JvO0Rtx1/pg1J9toNY+OWwD5HEmz9C2Fa+Mztok 0Dvw== X-Gm-Message-State: AOAM532WOccSDZuCVsyYbzxRgQnAtyreZJY+RPHuLtu6K2y1qhL8R8iU zCvX0bM5xaEBIAyyeaVN0ck= X-Google-Smtp-Source: ABdhPJyfT4FvBvOtlgUA25/6rhE+tF2ZpQFbPoXIg1yLWTU0828YNECy33l6fnzQ8+wsS5JY8ExquQ== X-Received: by 2002:adf:e48c:: with SMTP id i12mr1199753wrm.43.1642720834530; Thu, 20 Jan 2022 15:20:34 -0800 (PST) Received: from localhost.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id a9sm3939283wmm.32.2022.01.20.15.20.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Jan 2022 15:20:34 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Taniya Das , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 02/15] dt-bindings: clock: simplify qcom,gcc-apq8064 Documentation Date: Fri, 21 Jan 2022 00:20:15 +0100 Message-Id: <20220120232028.6738-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220120232028.6738-1-ansuelsmth@gmail.com> References: <20220120232028.6738-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Simplify qcon,gcc-apq8064 Documentation by using qcom,gcc.yaml as a template. Signed-off-by: Ansuel Smith --- .../bindings/clock/qcom,gcc-apq8064.yaml | 27 +++---------------- 1 file changed, 3 insertions(+), 24 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml index 8e2eac6cbfb9..d65b3fc5bfa1 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml @@ -6,6 +6,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Global Clock & Reset Controller Binding for APQ8064 +allOf: + - $ref: qcom,gcc.yaml# + maintainers: - Stephen Boyd - Taniya Das @@ -19,21 +22,6 @@ description: | - dt-bindings/reset/qcom,gcc-msm8960.h properties: - compatible: - const: qcom,gcc-apq8064 - - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - nvmem-cells: minItems: 1 maxItems: 2 @@ -53,16 +41,7 @@ properties: '#thermal-sensor-cells': const: 1 - protected-clocks: - description: - Protected clock specifier list as per common clock binding. - required: - - compatible - - reg - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' - nvmem-cells - nvmem-cell-names - '#thermal-sensor-cells' From patchwork Thu Jan 20 23:20:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12719132 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4EF81C4321E for ; Thu, 20 Jan 2022 23:20:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378165AbiATXUj (ORCPT ); Thu, 20 Jan 2022 18:20:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39602 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378159AbiATXUh (ORCPT ); Thu, 20 Jan 2022 18:20:37 -0500 Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 263ABC061574; Thu, 20 Jan 2022 15:20:37 -0800 (PST) Received: by mail-wm1-x335.google.com with SMTP id l35-20020a05600c1d2300b0034d477271c1so17649823wms.3; Thu, 20 Jan 2022 15:20:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=NqCTa9NPeJIZj8OJYmPeW7U5uohmgzf9QA184JG+m+o=; b=T7QgcwUm37r+BBCTIeRiF/awvjrCNxtIFhO6n6kcA2xo1onnJpTrWswW5v3Z+d3nvH rlCHwVkBZXQuRJKJRpzt+4y2dXsbaljqtC8GxxevPb+4lo0VE7rrHVOaCLwSF4ljpQE9 EdbUlLwWkxAAKPymhiVd89cTZ3T7KTRJ0844hbHCUxQeRVTLVnD6qcqdgPijluVXi10Z N9IhBgMI+4BfAcuP6w/67mhKEtQ4bl5dXRzEBi8jBAhqWRRHYS6UuxhZ+ZKuTS4Ca+qA NSBeDnj2r8UW4RU4FGtW8SSZRWw+S3I0AHSJ0deX/SjcApne1daU3WQxCDu6Qx8t57YB Y43Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NqCTa9NPeJIZj8OJYmPeW7U5uohmgzf9QA184JG+m+o=; b=16SuuxQMm7I6Zn9Qz1MSNQbANdtfw3NOru0IYm3hk+70qKEeP83Paz6lLrTpVoNp7p KQmKuztWKR9NakhCV0lZxQ3axzgV4fyot7hzgHofLQpzcsHFrUm3jPswPvz+mzOrjRo0 iH001RQukNXLr/kyD0/V9nYgiwpPpb5nEKn5r+jTMFo4BZi7L74ILFk3s0YvFc1XYecd tPvZUpOjdidN1bY+0kBu/3DUlVfJ3RiLh16GpsU39v63JfR6YLujo7FOQrHU2nrxSKNS 5XLsRXT2A8H/mQmWilIQvkHfMM+x1borEzihomDMy+Xlm/ym4lDXRlpV+3gZkBSKaPHc 03qg== X-Gm-Message-State: AOAM530fze6cA2upJbfqhkAtEtRurVzZu8/9Dt9XFMDiCKuLnp8HTmzW LKrRha8Oks3h+yFvctTU9bo= X-Google-Smtp-Source: ABdhPJy31IV3HCJP3tN1S1eF6mObbX7TSSd8e9QxOK89J11YROL/Jt1/8KYCtTOerGEo5V0cc5pJpA== X-Received: by 2002:a5d:4742:: with SMTP id o2mr1244653wrs.346.1642720835621; Thu, 20 Jan 2022 15:20:35 -0800 (PST) Received: from localhost.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id a9sm3939283wmm.32.2022.01.20.15.20.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Jan 2022 15:20:35 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Taniya Das , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 03/15] dt-bindings: clock: Document qcom,gcc-ipq8064 binding Date: Fri, 21 Jan 2022 00:20:16 +0100 Message-Id: <20220120232028.6738-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220120232028.6738-1-ansuelsmth@gmail.com> References: <20220120232028.6738-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Document qcom,gcc-ipq8064 binding needed to declare pxo and cxo source clocks. The gcc node is also used by the tsens driver, already documented, to get the calib nvmem cells and the base reg from gcc. Signed-off-by: Ansuel Smith --- .../bindings/clock/qcom,gcc-ipq8064.yaml | 70 +++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml new file mode 100644 index 000000000000..abc76a46b2ca --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq8064.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller Binding for IPQ8064 + +allOf: + - $ref: qcom,gcc.yaml# + +maintainers: + - Ansuel Smith + +description: | + Qualcomm global clock control module which supports the clocks, resets and + power domains on IPQ8064. + + See also: + - dt-bindings/clock/qcom,gcc-ipq806x.h + - dt-bindings/reset/qcom,gcc-ipq806x.h + +properties: + clocks: + items: + - description: PXO source + - description: CXO source + + clock-names: + items: + - const: pxo + - const: cxo + + thermal-sensor: + type: object + + allOf: + - $ref: /schemas/thermal/qcom-tsens.yaml# + +required: + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + + gcc: clock-controller@900000 { + compatible = "qcom,gcc-ipq8064", "syscon"; + reg = <0x00900000 0x4000>; + clocks = <&pxo_board>, <&cxo_board>; + clock-names = "pxo", "cxo"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + + tsens: thermal-sensor { + compatible = "qcom,ipq8064-tsens"; + + nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>; + nvmem-cell-names = "calib", "calib_backup"; + interrupts = ; + interrupt-names = "uplow"; + + #qcom,sensors = <11>; + #thermal-sensor-cells = <1>; + }; + }; From patchwork Thu Jan 20 23:20:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12719135 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CCBC4C43219 for ; Thu, 20 Jan 2022 23:20:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378190AbiATXUp (ORCPT ); Thu, 20 Jan 2022 18:20:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39604 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378164AbiATXUi (ORCPT ); Thu, 20 Jan 2022 18:20:38 -0500 Received: from mail-wm1-x336.google.com (mail-wm1-x336.google.com [IPv6:2a00:1450:4864:20::336]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 37F37C061574; Thu, 20 Jan 2022 15:20:38 -0800 (PST) Received: by mail-wm1-x336.google.com with SMTP id q9-20020a7bce89000000b00349e697f2fbso25364609wmj.0; Thu, 20 Jan 2022 15:20:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=wlPGztyCglYvRuLUlqRz5tHJBkS2fLA0AOcHKOEzeZA=; b=qylYzNHkxPlUCZCh/UUba7zSFTg0tlnPOJO65g/dz0P9jajbHoWX6w43gJsE281asm SHlhca2p6DJHrWk5By8jkDun3xAtZitvSzkjwBjzF8Fg5IDKmdTPsYb/Ed1j5uYweeIT 0dEKGaYUIEYxM4aYVMtFev9HGLNlKFNMoRZWMV7Xjj8CrsC9zATVqBUeSjhb3/g9oGT1 CXeSK6kBVxuZPbKn0Q7WPViSN0HcehWNihpbqOW5BNW+JRTOgEkzMq2nnSRTIpyZMK+M DWuKC51RuWaKApdLvhCtNeqcCBWjrm0gc7jwXDRzEPCzC2oweLv3dv5DGGdlmpS3eGvX kWLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wlPGztyCglYvRuLUlqRz5tHJBkS2fLA0AOcHKOEzeZA=; b=eMPZnc5erEsIPT8uzfI3VdN8vra/EAD5C/8lu1GmlnR7waOqL00KQJRMoPhKwM/7XA KJtXeQULgnM15yE3z461nc+F+H4tHlvpGWxPVBZG3plp5P5JCw6TIw6ys4lQj5W/3U1e SqTmvJLpCLmEX38Qplsyyjuu4r6FctpNRe0b8ydy9dTtm8Cc8Rz6RK+OB5pnwDPMYtQD M1opLfgkSUm8R1R+s+AUmjwZfLThuaj8mFdQOfv/CgOLl9dgHY6PdJXeAqhoZX1cFw5W /n67v4OY9lFhnY8C9ppU1aZDh88EGf75H0faAmA3TVQZr4S/b01jzOc4DdDz3iiu8vHQ njuQ== X-Gm-Message-State: AOAM531Hpd5UhO6yKzhQzNCgl9RA54rCPvUx8HvePjBPmEsQwcFcZ9E6 9Y23ZXy7SF/rupNWfMd0bYQ= X-Google-Smtp-Source: ABdhPJzRuoORYNNlpShJIX2//ljGG71KRPAB1iT6P6gM0Zw8uH63ph/DkBXUN6hwrO7tBtqokSx00A== X-Received: by 2002:a05:600c:1e19:: with SMTP id ay25mr11141981wmb.131.1642720836631; Thu, 20 Jan 2022 15:20:36 -0800 (PST) Received: from localhost.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id a9sm3939283wmm.32.2022.01.20.15.20.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Jan 2022 15:20:36 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Taniya Das , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 04/15] drivers: clk: qcom: gcc-ipq806x: fix wrong naming for gcc_pxo_pll8_pll0 Date: Fri, 21 Jan 2022 00:20:17 +0100 Message-Id: <20220120232028.6738-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220120232028.6738-1-ansuelsmth@gmail.com> References: <20220120232028.6738-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Parent gcc_pxo_pll8_pll0 had the parent definition and parent map swapped. Fix this naming error. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/gcc-ipq806x.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index d6b7adb4be38..34cddf461dba 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -291,13 +291,13 @@ static const char * const gcc_pxo_pll3[] = { "pll3", }; -static const struct parent_map gcc_pxo_pll8_pll0[] = { +static const struct parent_map gcc_pxo_pll8_pll0_map[] = { { P_PXO, 0 }, { P_PLL8, 3 }, { P_PLL0, 2 } }; -static const char * const gcc_pxo_pll8_pll0_map[] = { +static const char * const gcc_pxo_pll8_pll0[] = { "pxo", "pll8_vote", "pll0_vote", @@ -1993,7 +1993,7 @@ static struct clk_rcg usb30_master_clk_src = { }, .s = { .src_sel_shift = 0, - .parent_map = gcc_pxo_pll8_pll0, + .parent_map = gcc_pxo_pll8_pll0_map, }, .freq_tbl = clk_tbl_usb30_master, .clkr = { @@ -2001,7 +2001,7 @@ static struct clk_rcg usb30_master_clk_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb30_master_ref_src", - .parent_names = gcc_pxo_pll8_pll0_map, + .parent_names = gcc_pxo_pll8_pll0, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -2063,7 +2063,7 @@ static struct clk_rcg usb30_utmi_clk = { }, .s = { .src_sel_shift = 0, - .parent_map = gcc_pxo_pll8_pll0, + .parent_map = gcc_pxo_pll8_pll0_map, }, .freq_tbl = clk_tbl_usb30_utmi, .clkr = { @@ -2071,7 +2071,7 @@ static struct clk_rcg usb30_utmi_clk = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb30_utmi_clk", - .parent_names = gcc_pxo_pll8_pll0_map, + .parent_names = gcc_pxo_pll8_pll0, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -2133,7 +2133,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_src = { }, .s = { .src_sel_shift = 0, - .parent_map = gcc_pxo_pll8_pll0, + .parent_map = gcc_pxo_pll8_pll0_map, }, .freq_tbl = clk_tbl_usb, .clkr = { @@ -2141,7 +2141,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb_hs1_xcvr_src", - .parent_names = gcc_pxo_pll8_pll0_map, + .parent_names = gcc_pxo_pll8_pll0, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -2197,7 +2197,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_src = { }, .s = { .src_sel_shift = 0, - .parent_map = gcc_pxo_pll8_pll0, + .parent_map = gcc_pxo_pll8_pll0_map, }, .freq_tbl = clk_tbl_usb, .clkr = { @@ -2205,7 +2205,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb_fs1_xcvr_src", - .parent_names = gcc_pxo_pll8_pll0_map, + .parent_names = gcc_pxo_pll8_pll0, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, From patchwork Thu Jan 20 23:20:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12719136 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3285AC28CF5 for ; Thu, 20 Jan 2022 23:20:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378195AbiATXUp (ORCPT ); Thu, 20 Jan 2022 18:20:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39612 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378168AbiATXUj (ORCPT ); Thu, 20 Jan 2022 18:20:39 -0500 Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 68604C06173F; Thu, 20 Jan 2022 15:20:39 -0800 (PST) Received: by mail-wm1-x335.google.com with SMTP id n8so14867557wmk.3; Thu, 20 Jan 2022 15:20:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=WerBO9FmBNHoC1xzdy+NyC6mMRm8VImp6T8cuwrzvc0=; b=ioogJNQlHexWWcxtdfe3Zf7mrtEWzG3e/K2semSHbGdWDzMbkd90+MvAt8xBzbtsHx kkz7babdELRIF1WTte+rb4PQC0QzP2JK1lGm+DzzAm8m/pScqcH1VPWy46NRpwV1h6cq wGQwzMlMYc0AGieLmDDL5wSrA0aSiHrRuaXMuf04qONuuIaM21sStEfLzk+wF44Uecwn 8e18CHTt0dY7M9f6UX5n084+QZzoe1fZrVHjL1pGeYXZTUb3Vv72dvef8FBiOEWBgc65 ikVIEPPytM3E/I2sf5INI6JiELWml5jrUV/yqeakQX6gDuXjRXm8Rzd0RiWcX4SH80RO BrwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WerBO9FmBNHoC1xzdy+NyC6mMRm8VImp6T8cuwrzvc0=; b=B/keiRiB/z0E5jfTzd7Q4JYx4P5ZS2lWGXVWLTCGNzmpAAz7w2mEUYN7sBgBshqyBN aLn87ZRrPapENnpiXNNEcs3YjrN/QapolNDoFY04r3S6GVU8c+pmphRg4N9vwE5bwm6g 0RTfX9Hcy/UlMXskM1KHyfEKgLlDIR2D2IHGu5IOkZLylns8iwm17fZ5mR4GQpIJsV3u McOo9kCjDCXlH3SKbgNyHowU7yYTLQwTqh/ORRl4LI5QnUK48fstGZHuAKizLf3MMAeS GgIRpZpGqd3fNKU1daLLpIM2QtbnXawJkMKScAZjlsNh4yI987V0zK3H1uFNh95rKlDX D8RA== X-Gm-Message-State: AOAM530ZuqasvwRoIUQWKc2p6BQFxJy/PclgDm4juypiAa65rryGMPKb cmxro7WeiAu44dE6ZBe4tzg= X-Google-Smtp-Source: ABdhPJwN6C/jc/uSgBc3ZB6U+7VFKOxI4JIunL700mhNqKUnH74xu2l91qIIiGZ9Sv5R6zm6zgHUCg== X-Received: by 2002:adf:b601:: with SMTP id f1mr1214950wre.271.1642720837746; Thu, 20 Jan 2022 15:20:37 -0800 (PST) Received: from localhost.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id a9sm3939283wmm.32.2022.01.20.15.20.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Jan 2022 15:20:37 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Taniya Das , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 05/15] drivers: clk: qcom: gcc-ipq806x: convert parent_names to parent_data Date: Fri, 21 Jan 2022 00:20:18 +0100 Message-Id: <20220120232028.6738-6-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220120232028.6738-1-ansuelsmth@gmail.com> References: <20220120232028.6738-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Convert parent_names to parent_data to modernize the driver. Where possible use parent_hws directly. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/gcc-ipq806x.c | 286 ++++++++++++++++++++------------- 1 file changed, 173 insertions(+), 113 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index 34cddf461dba..828383c30322 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -25,6 +25,10 @@ #include "clk-hfpll.h" #include "reset.h" +static const struct clk_parent_data gcc_pxo[] = { + { .fw_name = "pxo" }, +}; + static struct clk_pll pll0 = { .l_reg = 0x30c4, .m_reg = 0x30c8, @@ -35,7 +39,7 @@ static struct clk_pll pll0 = { .status_bit = 16, .clkr.hw.init = &(struct clk_init_data){ .name = "pll0", - .parent_names = (const char *[]){ "pxo" }, + .parent_data = gcc_pxo, .num_parents = 1, .ops = &clk_pll_ops, }, @@ -46,7 +50,9 @@ static struct clk_regmap pll0_vote = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "pll0_vote", - .parent_names = (const char *[]){ "pll0" }, + .parent_hws = (const struct clk_hw*[]){ + &pll0.clkr.hw, + }, .num_parents = 1, .ops = &clk_pll_vote_ops, }, @@ -62,7 +68,7 @@ static struct clk_pll pll3 = { .status_bit = 16, .clkr.hw.init = &(struct clk_init_data){ .name = "pll3", - .parent_names = (const char *[]){ "pxo" }, + .parent_data = gcc_pxo, .num_parents = 1, .ops = &clk_pll_ops, }, @@ -89,7 +95,7 @@ static struct clk_pll pll8 = { .status_bit = 16, .clkr.hw.init = &(struct clk_init_data){ .name = "pll8", - .parent_names = (const char *[]){ "pxo" }, + .parent_data = gcc_pxo, .num_parents = 1, .ops = &clk_pll_ops, }, @@ -100,7 +106,9 @@ static struct clk_regmap pll8_vote = { .enable_mask = BIT(8), .hw.init = &(struct clk_init_data){ .name = "pll8_vote", - .parent_names = (const char *[]){ "pll8" }, + .parent_hws = (const struct clk_hw*[]){ + &pll8.clkr.hw, + }, .num_parents = 1, .ops = &clk_pll_vote_ops, }, @@ -123,7 +131,7 @@ static struct hfpll_data hfpll0_data = { static struct clk_hfpll hfpll0 = { .d = &hfpll0_data, .clkr.hw.init = &(struct clk_init_data){ - .parent_names = (const char *[]){ "pxo" }, + .parent_data = gcc_pxo, .num_parents = 1, .name = "hfpll0", .ops = &clk_ops_hfpll, @@ -149,7 +157,7 @@ static struct hfpll_data hfpll1_data = { static struct clk_hfpll hfpll1 = { .d = &hfpll1_data, .clkr.hw.init = &(struct clk_init_data){ - .parent_names = (const char *[]){ "pxo" }, + .parent_data = gcc_pxo, .num_parents = 1, .name = "hfpll1", .ops = &clk_ops_hfpll, @@ -175,7 +183,7 @@ static struct hfpll_data hfpll_l2_data = { static struct clk_hfpll hfpll_l2 = { .d = &hfpll_l2_data, .clkr.hw.init = &(struct clk_init_data){ - .parent_names = (const char *[]){ "pxo" }, + .parent_data = gcc_pxo, .num_parents = 1, .name = "hfpll_l2", .ops = &clk_ops_hfpll, @@ -194,7 +202,7 @@ static struct clk_pll pll14 = { .status_bit = 16, .clkr.hw.init = &(struct clk_init_data){ .name = "pll14", - .parent_names = (const char *[]){ "pxo" }, + .parent_data = gcc_pxo, .num_parents = 1, .ops = &clk_pll_ops, }, @@ -205,7 +213,9 @@ static struct clk_regmap pll14_vote = { .enable_mask = BIT(14), .hw.init = &(struct clk_init_data){ .name = "pll14_vote", - .parent_names = (const char *[]){ "pll14" }, + .parent_hws = (const struct clk_hw*[]){ + &pll14.clkr.hw, + }, .num_parents = 1, .ops = &clk_pll_vote_ops, }, @@ -238,7 +248,7 @@ static struct clk_pll pll18 = { .freq_tbl = pll18_freq_tbl, .clkr.hw.init = &(struct clk_init_data){ .name = "pll18", - .parent_names = (const char *[]){ "pxo" }, + .parent_data = gcc_pxo, .num_parents = 1, .ops = &clk_pll_ops, }, @@ -259,9 +269,9 @@ static const struct parent_map gcc_pxo_pll8_map[] = { { P_PLL8, 3 } }; -static const char * const gcc_pxo_pll8[] = { - "pxo", - "pll8_vote", +static const struct clk_parent_data gcc_pxo_pll8[] = { + { .fw_name = "pxo" }, + { .hw = &pll8_vote.hw }, }; static const struct parent_map gcc_pxo_pll8_cxo_map[] = { @@ -270,10 +280,10 @@ static const struct parent_map gcc_pxo_pll8_cxo_map[] = { { P_CXO, 5 } }; -static const char * const gcc_pxo_pll8_cxo[] = { - "pxo", - "pll8_vote", - "cxo", +static const struct clk_parent_data gcc_pxo_pll8_cxo[] = { + { .fw_name = "pxo" }, + { .hw = &pll8_vote.hw }, + { .fw_name = "cxo" }, }; static const struct parent_map gcc_pxo_pll3_map[] = { @@ -286,9 +296,9 @@ static const struct parent_map gcc_pxo_pll3_sata_map[] = { { P_PLL3, 6 } }; -static const char * const gcc_pxo_pll3[] = { - "pxo", - "pll3", +static const struct clk_parent_data gcc_pxo_pll3[] = { + { .fw_name = "pxo" }, + { .hw = &pll3.clkr.hw }, }; static const struct parent_map gcc_pxo_pll8_pll0_map[] = { @@ -297,10 +307,10 @@ static const struct parent_map gcc_pxo_pll8_pll0_map[] = { { P_PLL0, 2 } }; -static const char * const gcc_pxo_pll8_pll0[] = { - "pxo", - "pll8_vote", - "pll0_vote", +static const struct clk_parent_data gcc_pxo_pll8_pll0[] = { + { .fw_name = "pxo" }, + { .hw = &pll8_vote.hw }, + { .hw = &pll0_vote.hw }, }; static const struct parent_map gcc_pxo_pll8_pll14_pll18_pll0_map[] = { @@ -311,12 +321,12 @@ static const struct parent_map gcc_pxo_pll8_pll14_pll18_pll0_map[] = { { P_PLL18, 1 } }; -static const char * const gcc_pxo_pll8_pll14_pll18_pll0[] = { - "pxo", - "pll8_vote", - "pll0_vote", - "pll14", - "pll18", +static const struct clk_parent_data gcc_pxo_pll8_pll14_pll18_pll0[] = { + { .fw_name = "pxo" }, + { .hw = &pll8_vote.hw }, + { .hw = &pll0_vote.hw }, + { .hw = &pll14.clkr.hw }, + { .hw = &pll18.clkr.hw }, }; static struct freq_tbl clk_tbl_gsbi_uart[] = { @@ -362,7 +372,7 @@ static struct clk_rcg gsbi1_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi1_uart_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -378,8 +388,8 @@ static struct clk_branch gsbi1_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi1_uart_clk", - .parent_names = (const char *[]){ - "gsbi1_uart_src", + .parent_hws = (const struct clk_hw*[]){ + &gsbi1_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -413,7 +423,7 @@ static struct clk_rcg gsbi2_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi2_uart_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -429,8 +439,8 @@ static struct clk_branch gsbi2_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi2_uart_clk", - .parent_names = (const char *[]){ - "gsbi2_uart_src", + .parent_hws = (const struct clk_hw*[]){ + &gsbi2_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -464,7 +474,7 @@ static struct clk_rcg gsbi4_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi4_uart_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -480,8 +490,8 @@ static struct clk_branch gsbi4_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi4_uart_clk", - .parent_names = (const char *[]){ - "gsbi4_uart_src", + .parent_hws = (const struct clk_hw*[]){ + &gsbi4_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -515,7 +525,7 @@ static struct clk_rcg gsbi5_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi5_uart_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -531,8 +541,8 @@ static struct clk_branch gsbi5_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi5_uart_clk", - .parent_names = (const char *[]){ - "gsbi5_uart_src", + .parent_hws = (const struct clk_hw*[]){ + &gsbi5_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -566,7 +576,7 @@ static struct clk_rcg gsbi6_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi6_uart_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -582,8 +592,8 @@ static struct clk_branch gsbi6_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi6_uart_clk", - .parent_names = (const char *[]){ - "gsbi6_uart_src", + .parent_hws = (const struct clk_hw*[]){ + &gsbi6_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -617,7 +627,7 @@ static struct clk_rcg gsbi7_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi7_uart_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -633,8 +643,8 @@ static struct clk_branch gsbi7_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi7_uart_clk", - .parent_names = (const char *[]){ - "gsbi7_uart_src", + .parent_hws = (const struct clk_hw*[]){ + &gsbi7_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -681,7 +691,7 @@ static struct clk_rcg gsbi1_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi1_qup_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -697,7 +707,9 @@ static struct clk_branch gsbi1_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi1_qup_clk", - .parent_names = (const char *[]){ "gsbi1_qup_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gsbi1_qup_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -730,7 +742,7 @@ static struct clk_rcg gsbi2_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi2_qup_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -746,7 +758,9 @@ static struct clk_branch gsbi2_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi2_qup_clk", - .parent_names = (const char *[]){ "gsbi2_qup_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gsbi2_qup_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -779,7 +793,7 @@ static struct clk_rcg gsbi4_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi4_qup_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -795,7 +809,9 @@ static struct clk_branch gsbi4_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi4_qup_clk", - .parent_names = (const char *[]){ "gsbi4_qup_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gsbi4_qup_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -828,7 +844,7 @@ static struct clk_rcg gsbi5_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi5_qup_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -844,7 +860,9 @@ static struct clk_branch gsbi5_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi5_qup_clk", - .parent_names = (const char *[]){ "gsbi5_qup_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gsbi5_qup_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -877,7 +895,7 @@ static struct clk_rcg gsbi6_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi6_qup_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -893,7 +911,9 @@ static struct clk_branch gsbi6_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi6_qup_clk", - .parent_names = (const char *[]){ "gsbi6_qup_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gsbi6_qup_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -926,7 +946,7 @@ static struct clk_rcg gsbi7_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi7_qup_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -942,7 +962,9 @@ static struct clk_branch gsbi7_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi7_qup_clk", - .parent_names = (const char *[]){ "gsbi7_qup_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gsbi7_qup_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1076,7 +1098,7 @@ static struct clk_rcg gp0_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gp0_src", - .parent_names = gcc_pxo_pll8_cxo, + .parent_data = gcc_pxo_pll8_cxo, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -1092,7 +1114,9 @@ static struct clk_branch gp0_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gp0_clk", - .parent_names = (const char *[]){ "gp0_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gp0_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1125,7 +1149,7 @@ static struct clk_rcg gp1_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gp1_src", - .parent_names = gcc_pxo_pll8_cxo, + .parent_data = gcc_pxo_pll8_cxo, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -1141,7 +1165,9 @@ static struct clk_branch gp1_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gp1_clk", - .parent_names = (const char *[]){ "gp1_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gp1_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1174,7 +1200,7 @@ static struct clk_rcg gp2_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gp2_src", - .parent_names = gcc_pxo_pll8_cxo, + .parent_data = gcc_pxo_pll8_cxo, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -1190,7 +1216,9 @@ static struct clk_branch gp2_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gp2_clk", - .parent_names = (const char *[]){ "gp2_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gp2_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1228,7 +1256,7 @@ static struct clk_rcg prng_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "prng_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, }, @@ -1244,7 +1272,9 @@ static struct clk_branch prng_clk = { .enable_mask = BIT(10), .hw.init = &(struct clk_init_data){ .name = "prng_clk", - .parent_names = (const char *[]){ "prng_src" }, + .parent_hws = (const struct clk_hw*[]){ + &prng_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, }, @@ -1290,7 +1320,7 @@ static struct clk_rcg sdc1_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "sdc1_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, }, @@ -1305,7 +1335,9 @@ static struct clk_branch sdc1_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "sdc1_clk", - .parent_names = (const char *[]){ "sdc1_src" }, + .parent_hws = (const struct clk_hw*[]){ + &sdc1_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1338,7 +1370,7 @@ static struct clk_rcg sdc3_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "sdc3_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, }, @@ -1353,7 +1385,9 @@ static struct clk_branch sdc3_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "sdc3_clk", - .parent_names = (const char *[]){ "sdc3_src" }, + .parent_hws = (const struct clk_hw*[]){ + &sdc3_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1421,7 +1455,7 @@ static struct clk_rcg tsif_ref_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "tsif_ref_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, }, @@ -1436,7 +1470,9 @@ static struct clk_branch tsif_ref_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "tsif_ref_clk", - .parent_names = (const char *[]){ "tsif_ref_src" }, + .parent_hws = (const struct clk_hw*[]){ + &tsif_ref_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1583,7 +1619,7 @@ static struct clk_rcg pcie_ref_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "pcie_ref_src", - .parent_names = gcc_pxo_pll3, + .parent_data = gcc_pxo_pll3, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -1599,7 +1635,9 @@ static struct clk_branch pcie_ref_src_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "pcie_ref_src_clk", - .parent_names = (const char *[]){ "pcie_ref_src" }, + .parent_hws = (const struct clk_hw*[]){ + &pcie_ref_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1675,7 +1713,7 @@ static struct clk_rcg pcie1_ref_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "pcie1_ref_src", - .parent_names = gcc_pxo_pll3, + .parent_data = gcc_pxo_pll3, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -1691,7 +1729,9 @@ static struct clk_branch pcie1_ref_src_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "pcie1_ref_src_clk", - .parent_names = (const char *[]){ "pcie1_ref_src" }, + .parent_hws = (const struct clk_hw*[]){ + &pcie1_ref_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1767,7 +1807,7 @@ static struct clk_rcg pcie2_ref_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "pcie2_ref_src", - .parent_names = gcc_pxo_pll3, + .parent_data = gcc_pxo_pll3, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -1783,7 +1823,9 @@ static struct clk_branch pcie2_ref_src_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "pcie2_ref_src_clk", - .parent_names = (const char *[]){ "pcie2_ref_src" }, + .parent_hws = (const struct clk_hw*[]){ + &pcie2_ref_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1864,7 +1906,7 @@ static struct clk_rcg sata_ref_src = { .enable_mask = BIT(7), .hw.init = &(struct clk_init_data){ .name = "sata_ref_src", - .parent_names = gcc_pxo_pll3, + .parent_data = gcc_pxo_pll3, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -1880,7 +1922,9 @@ static struct clk_branch sata_rxoob_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "sata_rxoob_clk", - .parent_names = (const char *[]){ "sata_ref_src" }, + .parent_hws = (const struct clk_hw*[]){ + &sata_ref_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1896,7 +1940,9 @@ static struct clk_branch sata_pmalive_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "sata_pmalive_clk", - .parent_names = (const char *[]){ "sata_ref_src" }, + .parent_hws = (const struct clk_hw*[]){ + &sata_ref_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1912,7 +1958,7 @@ static struct clk_branch sata_phy_ref_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "sata_phy_ref_clk", - .parent_names = (const char *[]){ "pxo" }, + .parent_data = gcc_pxo, .num_parents = 1, .ops = &clk_branch_ops, }, @@ -2001,7 +2047,7 @@ static struct clk_rcg usb30_master_clk_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb30_master_ref_src", - .parent_names = gcc_pxo_pll8_pll0, + .parent_data = gcc_pxo_pll8_pll0, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -2017,7 +2063,9 @@ static struct clk_branch usb30_0_branch_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "usb30_0_branch_clk", - .parent_names = (const char *[]){ "usb30_master_ref_src", }, + .parent_hws = (const struct clk_hw*[]){ + &usb30_master_clk_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -2033,7 +2081,9 @@ static struct clk_branch usb30_1_branch_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "usb30_1_branch_clk", - .parent_names = (const char *[]){ "usb30_master_ref_src", }, + .parent_hws = (const struct clk_hw*[]){ + &usb30_master_clk_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -2071,7 +2121,7 @@ static struct clk_rcg usb30_utmi_clk = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb30_utmi_clk", - .parent_names = gcc_pxo_pll8_pll0, + .parent_data = gcc_pxo_pll8_pll0, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -2087,7 +2137,9 @@ static struct clk_branch usb30_0_utmi_clk_ctl = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "usb30_0_utmi_clk_ctl", - .parent_names = (const char *[]){ "usb30_utmi_clk", }, + .parent_hws = (const struct clk_hw*[]){ + &usb30_utmi_clk.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -2103,7 +2155,9 @@ static struct clk_branch usb30_1_utmi_clk_ctl = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "usb30_1_utmi_clk_ctl", - .parent_names = (const char *[]){ "usb30_utmi_clk", }, + .parent_hws = (const struct clk_hw*[]){ + &usb30_utmi_clk.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -2141,7 +2195,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb_hs1_xcvr_src", - .parent_names = gcc_pxo_pll8_pll0, + .parent_data = gcc_pxo_pll8_pll0, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -2157,7 +2211,9 @@ static struct clk_branch usb_hs1_xcvr_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "usb_hs1_xcvr_clk", - .parent_names = (const char *[]){ "usb_hs1_xcvr_src" }, + .parent_hws = (const struct clk_hw*[]){ + &usb_hs1_xcvr_clk_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -2205,7 +2261,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb_fs1_xcvr_src", - .parent_names = gcc_pxo_pll8_pll0, + .parent_data = gcc_pxo_pll8_pll0, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -2221,7 +2277,9 @@ static struct clk_branch usb_fs1_xcvr_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "usb_fs1_xcvr_clk", - .parent_names = (const char *[]){ "usb_fs1_xcvr_src", }, + .parent_hws = (const struct clk_hw*[]){ + &usb_fs1_xcvr_clk_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -2237,7 +2295,9 @@ static struct clk_branch usb_fs1_sys_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "usb_fs1_sys_clk", - .parent_names = (const char *[]){ "usb_fs1_xcvr_src", }, + .parent_hws = (const struct clk_hw*[]){ + &usb_fs1_xcvr_clk_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -2337,7 +2397,7 @@ static struct clk_dyn_rcg gmac_core1_src = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "gmac_core1_src", - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, .num_parents = 5, .ops = &clk_dyn_rcg_ops, }, @@ -2354,8 +2414,8 @@ static struct clk_branch gmac_core1_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "gmac_core1_clk", - .parent_names = (const char *[]){ - "gmac_core1_src", + .parent_hws = (const struct clk_hw*[]){ + &gmac_core1_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -2409,7 +2469,7 @@ static struct clk_dyn_rcg gmac_core2_src = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "gmac_core2_src", - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, .num_parents = 5, .ops = &clk_dyn_rcg_ops, }, @@ -2426,8 +2486,8 @@ static struct clk_branch gmac_core2_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "gmac_core2_clk", - .parent_names = (const char *[]){ - "gmac_core2_src", + .parent_hws = (const struct clk_hw*[]){ + &gmac_core2_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -2481,7 +2541,7 @@ static struct clk_dyn_rcg gmac_core3_src = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "gmac_core3_src", - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, .num_parents = 5, .ops = &clk_dyn_rcg_ops, }, @@ -2498,8 +2558,8 @@ static struct clk_branch gmac_core3_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "gmac_core3_clk", - .parent_names = (const char *[]){ - "gmac_core3_src", + .parent_hws = (const struct clk_hw*[]){ + &gmac_core3_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -2553,7 +2613,7 @@ static struct clk_dyn_rcg gmac_core4_src = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "gmac_core4_src", - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, .num_parents = 5, .ops = &clk_dyn_rcg_ops, }, @@ -2570,8 +2630,8 @@ static struct clk_branch gmac_core4_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "gmac_core4_clk", - .parent_names = (const char *[]){ - "gmac_core4_src", + .parent_hws = (const struct clk_hw*[]){ + &gmac_core4_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -2613,7 +2673,7 @@ static struct clk_dyn_rcg nss_tcm_src = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "nss_tcm_src", - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, .num_parents = 5, .ops = &clk_dyn_rcg_ops, }, @@ -2628,8 +2688,8 @@ static struct clk_branch nss_tcm_clk = { .enable_mask = BIT(6) | BIT(4), .hw.init = &(struct clk_init_data){ .name = "nss_tcm_clk", - .parent_names = (const char *[]){ - "nss_tcm_src", + .parent_hws = (const struct clk_hw*[]){ + &nss_tcm_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -2691,7 +2751,7 @@ static struct clk_dyn_rcg ubi32_core1_src_clk = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "ubi32_core1_src_clk", - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, .num_parents = 5, .ops = &clk_dyn_rcg_ops, .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, @@ -2744,7 +2804,7 @@ static struct clk_dyn_rcg ubi32_core2_src_clk = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "ubi32_core2_src_clk", - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, .num_parents = 5, .ops = &clk_dyn_rcg_ops, .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, From patchwork Thu Jan 20 23:20:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12719145 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F476C433EF for ; Thu, 20 Jan 2022 23:21:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378210AbiATXUq (ORCPT ); Thu, 20 Jan 2022 18:20:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39616 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378169AbiATXUk (ORCPT ); Thu, 20 Jan 2022 18:20:40 -0500 Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [IPv6:2a00:1450:4864:20::332]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 68F08C061574; Thu, 20 Jan 2022 15:20:40 -0800 (PST) Received: by mail-wm1-x332.google.com with SMTP id v123so14913297wme.2; Thu, 20 Jan 2022 15:20:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=uhs8yO3Tw+6wvqO+3KXCFZjOTAYX1wXl4HfqPcifPzU=; b=CM6wh34zPpdPYKwnxRRmcdM+NEftIriBZKtAji8rZLzuMsUxvZgEx3/PMsPBAPXkew rqF1BYntNcmtvaY/Kxt1wxo626+4enA+wRBixfBykM7DIf2qK7YWWqj/qFChj1Wl6hGJ NxOFl7ODRBrF4HAJToLvXwf/MvvxBM9bzgsPevyQ+xs/k1OHSbHfs9rn2qoMzLW8HQJK 4CblLT04pEUPLCal+fqOq8L3fSg6uPkRQxDgf8wpyIIoQum8T1FpYUvc/CD+H6uToo9Q n9zysv0JfUmooRvSJAMS1oJIW4/JLzEidpl49mJUZ4iwKoj2ISqnKCtWjOZZCwczE6Ss ab2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uhs8yO3Tw+6wvqO+3KXCFZjOTAYX1wXl4HfqPcifPzU=; b=texPi3dXgu8X5ZQMheDjkswcUuSEPuEiEheU13t3txKqG7rs0PqQnb/B4Zl9q6rk6f /tLIMZ6Ov/WyoUV/MZItMmn3zKHRqvwPOg/y2VDRSISc1AbWK9bKiXvVoa9xCmTenPhq Iexve4P8bT++t1ceGfacYNJRV9/P3sUQwkJmRrT21uMCczBjFziDQWxBcsC1KDzeVqvd xJEN8rSZHWdF6sausgg7kPUEjez5gAaE1oHVWdwYELoYqjQQGKylfWIHsqlBmdOiSQnI UV+FuSKxvYCnHiW6cYMBNwrtolQ1rfQ6Vszrxrb0N1endeIFc8rGqsj7+FWeIpFmF2Ma V3Sg== X-Gm-Message-State: AOAM5314v7CGOBqjbtRw4/Ok0pumfcMgr5rqtaLAcR8EgBzBVlVGrfoB +bLELzLLPx2ZfKkLtZuTD60= X-Google-Smtp-Source: ABdhPJw2gZbmybGx74zX8kNg2CJf/wovRVJezZ6yE/i0XqN1fs9d4EmeDtIB6oL28VA2kFUes2n0pA== X-Received: by 2002:a05:600c:3847:: with SMTP id s7mr11497357wmr.101.1642720838861; Thu, 20 Jan 2022 15:20:38 -0800 (PST) Received: from localhost.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id a9sm3939283wmm.32.2022.01.20.15.20.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Jan 2022 15:20:38 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Taniya Das , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 06/15] drivers: clk: qcom: gcc-ipq806x: use ARRAY_SIZE for num_parents Date: Fri, 21 Jan 2022 00:20:19 +0100 Message-Id: <20220120232028.6738-7-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220120232028.6738-1-ansuelsmth@gmail.com> References: <20220120232028.6738-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Use ARRAY_SIZE for num_parents instead of hardcoding the value. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/gcc-ipq806x.c | 68 +++++++++++++++++----------------- 1 file changed, 34 insertions(+), 34 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index 828383c30322..f6db7247835e 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -373,7 +373,7 @@ static struct clk_rcg gsbi1_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi1_uart_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -424,7 +424,7 @@ static struct clk_rcg gsbi2_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi2_uart_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -475,7 +475,7 @@ static struct clk_rcg gsbi4_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi4_uart_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -526,7 +526,7 @@ static struct clk_rcg gsbi5_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi5_uart_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -577,7 +577,7 @@ static struct clk_rcg gsbi6_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi6_uart_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -628,7 +628,7 @@ static struct clk_rcg gsbi7_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi7_uart_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -692,7 +692,7 @@ static struct clk_rcg gsbi1_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi1_qup_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -743,7 +743,7 @@ static struct clk_rcg gsbi2_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi2_qup_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -794,7 +794,7 @@ static struct clk_rcg gsbi4_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi4_qup_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -845,7 +845,7 @@ static struct clk_rcg gsbi5_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi5_qup_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -896,7 +896,7 @@ static struct clk_rcg gsbi6_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi6_qup_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -947,7 +947,7 @@ static struct clk_rcg gsbi7_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi7_qup_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -1099,7 +1099,7 @@ static struct clk_rcg gp0_src = { .hw.init = &(struct clk_init_data){ .name = "gp0_src", .parent_data = gcc_pxo_pll8_cxo, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -1150,7 +1150,7 @@ static struct clk_rcg gp1_src = { .hw.init = &(struct clk_init_data){ .name = "gp1_src", .parent_data = gcc_pxo_pll8_cxo, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -1201,7 +1201,7 @@ static struct clk_rcg gp2_src = { .hw.init = &(struct clk_init_data){ .name = "gp2_src", .parent_data = gcc_pxo_pll8_cxo, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -1257,7 +1257,7 @@ static struct clk_rcg prng_src = { .hw.init = &(struct clk_init_data){ .name = "prng_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, }, }, @@ -1321,7 +1321,7 @@ static struct clk_rcg sdc1_src = { .hw.init = &(struct clk_init_data){ .name = "sdc1_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, }, } @@ -1371,7 +1371,7 @@ static struct clk_rcg sdc3_src = { .hw.init = &(struct clk_init_data){ .name = "sdc3_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, }, } @@ -1456,7 +1456,7 @@ static struct clk_rcg tsif_ref_src = { .hw.init = &(struct clk_init_data){ .name = "tsif_ref_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, }, } @@ -1620,7 +1620,7 @@ static struct clk_rcg pcie_ref_src = { .hw.init = &(struct clk_init_data){ .name = "pcie_ref_src", .parent_data = gcc_pxo_pll3, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll3), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -1714,7 +1714,7 @@ static struct clk_rcg pcie1_ref_src = { .hw.init = &(struct clk_init_data){ .name = "pcie1_ref_src", .parent_data = gcc_pxo_pll3, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll3), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -1808,7 +1808,7 @@ static struct clk_rcg pcie2_ref_src = { .hw.init = &(struct clk_init_data){ .name = "pcie2_ref_src", .parent_data = gcc_pxo_pll3, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll3), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -1907,7 +1907,7 @@ static struct clk_rcg sata_ref_src = { .hw.init = &(struct clk_init_data){ .name = "sata_ref_src", .parent_data = gcc_pxo_pll3, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll3), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -2048,7 +2048,7 @@ static struct clk_rcg usb30_master_clk_src = { .hw.init = &(struct clk_init_data){ .name = "usb30_master_ref_src", .parent_data = gcc_pxo_pll8_pll0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -2122,7 +2122,7 @@ static struct clk_rcg usb30_utmi_clk = { .hw.init = &(struct clk_init_data){ .name = "usb30_utmi_clk", .parent_data = gcc_pxo_pll8_pll0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -2196,7 +2196,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_src = { .hw.init = &(struct clk_init_data){ .name = "usb_hs1_xcvr_src", .parent_data = gcc_pxo_pll8_pll0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -2262,7 +2262,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_src = { .hw.init = &(struct clk_init_data){ .name = "usb_fs1_xcvr_src", .parent_data = gcc_pxo_pll8_pll0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -2398,7 +2398,7 @@ static struct clk_dyn_rcg gmac_core1_src = { .hw.init = &(struct clk_init_data){ .name = "gmac_core1_src", .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), .ops = &clk_dyn_rcg_ops, }, }, @@ -2470,7 +2470,7 @@ static struct clk_dyn_rcg gmac_core2_src = { .hw.init = &(struct clk_init_data){ .name = "gmac_core2_src", .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), .ops = &clk_dyn_rcg_ops, }, }, @@ -2542,7 +2542,7 @@ static struct clk_dyn_rcg gmac_core3_src = { .hw.init = &(struct clk_init_data){ .name = "gmac_core3_src", .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), .ops = &clk_dyn_rcg_ops, }, }, @@ -2614,7 +2614,7 @@ static struct clk_dyn_rcg gmac_core4_src = { .hw.init = &(struct clk_init_data){ .name = "gmac_core4_src", .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), .ops = &clk_dyn_rcg_ops, }, }, @@ -2674,7 +2674,7 @@ static struct clk_dyn_rcg nss_tcm_src = { .hw.init = &(struct clk_init_data){ .name = "nss_tcm_src", .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), .ops = &clk_dyn_rcg_ops, }, }, @@ -2752,7 +2752,7 @@ static struct clk_dyn_rcg ubi32_core1_src_clk = { .hw.init = &(struct clk_init_data){ .name = "ubi32_core1_src_clk", .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), .ops = &clk_dyn_rcg_ops, .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, }, @@ -2805,7 +2805,7 @@ static struct clk_dyn_rcg ubi32_core2_src_clk = { .hw.init = &(struct clk_init_data){ .name = "ubi32_core2_src_clk", .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), .ops = &clk_dyn_rcg_ops, .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, }, From patchwork Thu Jan 20 23:20:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12719137 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B74DAC433EF for ; Thu, 20 Jan 2022 23:20:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378224AbiATXUs (ORCPT ); Thu, 20 Jan 2022 18:20:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39624 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378170AbiATXUl (ORCPT ); Thu, 20 Jan 2022 18:20:41 -0500 Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [IPv6:2a00:1450:4864:20::329]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 62B24C061574; Thu, 20 Jan 2022 15:20:41 -0800 (PST) Received: by mail-wm1-x329.google.com with SMTP id p18so14857715wmg.4; Thu, 20 Jan 2022 15:20:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=RtUb0uNm8GCwaxKxVgq9cIPVLkXV4oSCeOPZFznLHNM=; b=oTuNnF35NC7w8bS04lrj9HtubZs9Sr2TqHrBkbDLNnJ95VCmFn9b+gvlWdv0pLkKwC HIZNl4g0ZOdlrQ/w0WjAYYm902HtrWQMxhDUii0EkVXCzBrgTAcA+8khRY2HasZn09Ve zm8Mp2n+gMpDPw1LRGDXlSAuH6UQeX9m8bwpJkPraeIRO5uTjCiDEZkS0QNjGZmUvC1U ZPoTOiBnCJW8K+zC1aLCarQcVELMnbXAxveggtn4NPg2njSBYnSgDXyl9UMB7BBTtxqA i2do9JWT6YPI8z9WF5+XO9dRF5mJIaq+DIMTUlaqo1SBSTOl3U8lOoH8iCAVj9W8Iy1h vpVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RtUb0uNm8GCwaxKxVgq9cIPVLkXV4oSCeOPZFznLHNM=; b=KsUlYxKxZR1oCV9Z4fppyvLKq8QtsFldlpWz1cgJT8WSf7kHVdohPIWaClPfiDwTPM tmH/QbkVxrZ7Kba06U63cScHz1EgCj/lZFtBIsHSAZ3B9CYCMU8AWxXxzoE9Nvgv/DGR Urq3nAZA1A2tZ3bDRk4lb0/chdxFXcwBhAJ20Nn5NoA+9p0mGxXSASOgGfaTDvJC/Vqb JewE9nuaj508CfDqBVJy10p2XeTsjRgQnmHj8uIIXzr5mHNpBm2GDYpOIJTB3wOVDbM7 W9sMGIjhPAg/nTHElgg8D8Aq7ZxYqvz9aGMS67dlKQl6lckfE/zIsGl4KBRRJzM3pEaG ay5Q== X-Gm-Message-State: AOAM533EZFL2HboateYCjZn6jvk2ufVl9tassna33XwBHRWBIS1ChxN5 esD2pVgwmU5NFHvlj3RvoiY= X-Google-Smtp-Source: ABdhPJwM6eXaNMTCDWTfwzTVXUSynuaytKF80a9i9i3UVlmeaBLBp1X4GnorHb5xvR5ZNpibnLyvyA== X-Received: by 2002:a5d:658a:: with SMTP id q10mr1237736wru.703.1642720839858; Thu, 20 Jan 2022 15:20:39 -0800 (PST) Received: from localhost.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id a9sm3939283wmm.32.2022.01.20.15.20.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Jan 2022 15:20:39 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Taniya Das , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 07/15] drivers: clk: qcom: gcc-ipq806x: drop hardcoded pxo and cxo source clk Date: Fri, 21 Jan 2022 00:20:20 +0100 Message-Id: <20220120232028.6738-8-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220120232028.6738-1-ansuelsmth@gmail.com> References: <20220120232028.6738-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org We now define these clk in dts. Drop pxo and cxo hardcoded in the gcc probe function. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/gcc-ipq806x.c | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index f6db7247835e..a4bf78fe8678 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -3119,23 +3119,14 @@ MODULE_DEVICE_TABLE(of, gcc_ipq806x_match_table); static int gcc_ipq806x_probe(struct platform_device *pdev) { - struct device *dev = &pdev->dev; struct regmap *regmap; int ret; - ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 25000000); - if (ret) - return ret; - - ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 25000000); - if (ret) - return ret; - ret = qcom_cc_probe(pdev, &gcc_ipq806x_desc); if (ret) return ret; - regmap = dev_get_regmap(dev, NULL); + regmap = dev_get_regmap(&pdev->dev, NULL); if (!regmap) return -ENODEV; From patchwork Thu Jan 20 23:20:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12719138 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B8AD3C433F5 for ; Thu, 20 Jan 2022 23:20:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378233AbiATXUu (ORCPT ); Thu, 20 Jan 2022 18:20:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39626 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378174AbiATXUm (ORCPT ); Thu, 20 Jan 2022 18:20:42 -0500 Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [IPv6:2a00:1450:4864:20::329]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6CCC2C061574; Thu, 20 Jan 2022 15:20:42 -0800 (PST) Received: by mail-wm1-x329.google.com with SMTP id az27-20020a05600c601b00b0034d2956eb04so17624765wmb.5; Thu, 20 Jan 2022 15:20:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=cBE+j0nomJ1s8ZdluzXzBh2EPO3NhAaZtGzkoFt0ias=; b=Whyb03my8IFhPEptRVlGr4URhZBE38JrzGRa6OZPM1l9NvAhz6dnlhFLm7ZcTBVkTI qp14N9itW0nIw/izG1Ymngd9AiAgtQdLVM0B35iBktN3y3Euln6wAgqlsuH2O34uJhMk HcQ3xYSfqJWT4u39UDGiXAD8mrByL9scx7ALgayE1UELY8tPzvkqi2iHFKBNVLIQyI5q GLlZ0eIjt1PnBbI6DSt2L2FYe12L2rZXtl6tSohsAFbzzEY/D1Kho9GGg9BSnP40F5Ve FImm3pUQzJG6WuXJBo61NUUW/o4C7yZZwHz1DpNn85D/wo+iGQuqJORhPKgvxfaQ0D8U o0EA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cBE+j0nomJ1s8ZdluzXzBh2EPO3NhAaZtGzkoFt0ias=; b=f66Uk1aBJ/MJfhqYGuBGcaMTVWbwCxS+vjhKHsDr2P1qMhOcSidV03q4yqhdIBwVUD zOmY7lRK6p2j2uCzva3PpN56B8z7mMfHBbMr3aKFFJi5yCq6vH+p6h+8uggj+lhpzaoc 4xKdSuKos9Ul0TsHoj2+u1KUYoDO54vH+LEjGR3vOWMK9Tr6dNSqeGpRgI8k6xWsYPiO dZ41s9Jvm37+8kNRlF4bBKLnzc9FHKMst/ihUgkAW97cCOajl+jVnZWL3vhLiEcrMUs3 +UwNIeHJ3Ze2F/mP0qr3diyFtmX22aWkm+hFZdg0Im07ETFIPJzfQ2NqdlGJvjI4tMxM LGxw== X-Gm-Message-State: AOAM532jJ+xzLPtf8pas4plNgE16cBeqGMsu9AGNPZgUWJXIk16k3Ipr xGGXDkTJmZcBQ7uBfbozaKc= X-Google-Smtp-Source: ABdhPJx9wHd3mKhqjNGyUqybkNbuUoivja0ogM0Tz2QwlOoqewFC0ZktNmyjY0JjN5aavyUw6LVfOA== X-Received: by 2002:adf:fb4f:: with SMTP id c15mr1145070wrs.509.1642720840908; Thu, 20 Jan 2022 15:20:40 -0800 (PST) Received: from localhost.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id a9sm3939283wmm.32.2022.01.20.15.20.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Jan 2022 15:20:40 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Taniya Das , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 08/15] drivers: clk: qcom: gcc-ipq806x: add additional freq nss cores Date: Fri, 21 Jan 2022 00:20:21 +0100 Message-Id: <20220120232028.6738-9-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220120232028.6738-1-ansuelsmth@gmail.com> References: <20220120232028.6738-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Ipq8065 SoC (an evolution of ipq8064 SoC) contains nss cores that can be clocked to 800MHz. Add these missing freq to the gcc driver. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/gcc-ipq806x.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index a4bf78fe8678..53a61860063d 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -232,7 +232,9 @@ static struct clk_regmap pll14_vote = { static struct pll_freq_tbl pll18_freq_tbl[] = { NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625), + NSS_PLL_RATE(600000000, 48, 0, 1, 0x01495625), NSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625), + NSS_PLL_RATE(800000000, 64, 0, 1, 0x01495625), }; static struct clk_pll pll18 = { @@ -2702,7 +2704,9 @@ static const struct freq_tbl clk_tbl_nss[] = { { 110000000, P_PLL18, 1, 1, 5 }, { 275000000, P_PLL18, 2, 0, 0 }, { 550000000, P_PLL18, 1, 0, 0 }, + { 600000000, P_PLL18, 1, 0, 0 }, { 733000000, P_PLL18, 1, 0, 0 }, + { 800000000, P_PLL18, 1, 0, 0 }, { } }; From patchwork Thu Jan 20 23:20:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12719139 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD04DC433F5 for ; Thu, 20 Jan 2022 23:21:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378240AbiATXU4 (ORCPT ); Thu, 20 Jan 2022 18:20:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39638 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378181AbiATXUn (ORCPT ); Thu, 20 Jan 2022 18:20:43 -0500 Received: from mail-wm1-x32b.google.com (mail-wm1-x32b.google.com [IPv6:2a00:1450:4864:20::32b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7D6F5C061746; Thu, 20 Jan 2022 15:20:43 -0800 (PST) Received: by mail-wm1-x32b.google.com with SMTP id bg19-20020a05600c3c9300b0034565e837b6so8027519wmb.1; Thu, 20 Jan 2022 15:20:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=clnqaNqyzpxcBB6mJhgn58xxBFPn79gkEl2JvXBz70c=; b=NGpxLUYhGZRwkdTAA14yVKPz9M2xEFxsfxWEDicVhK/Lodv7MaCKU6PE4alcwBwPZk jjDd+MqOLx+IdT089YxnpRKa5yjd8R1op9q8cuPwDgMyvOMeYCRmk8aaIPu1pfXUwtWo /qiYXTEQ/zED0kV4nuBV4UA7dSQcrcnPQqoGtin8/1TcPFE8wPOrim7q6m5ZccRqXn2G UaLBU/dUM3GvfRNYhb5rUU3cnozD32CMRacnMFdpAOY5hZ3m6olJr4psgxUpcA+2o7Gf C7YKbiEbHvDnxdV1O+H206uPUBsdmPJUioltt6Sfjnuep9ozFcZSvCM+SzKE3GKz/pgI hb0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=clnqaNqyzpxcBB6mJhgn58xxBFPn79gkEl2JvXBz70c=; b=NB9nO3p6CqbVonIKgJjTD5NGD1Vw3SXdog5jJLKiLAye8ODLnMwDgxMYYU97FnZXZX YqTidzojl1eSG+Z6ISaYVBH7sUtyOYpiw1618n8vXKrSJNRXDHToxwLX5gwe73Hrx4Jw 96OJ0lyktfodr2lmnAb6MGEKCmLp/axnov1OHxPpkMql5d9QR0oZYxrfPIlGZj+KEwjL 6Zd5EWiCNkcZDoEVhhgYwHsAYAosw4+Cz1oemgTtIV+4JIraNIkNKaK6Xi0yBRy8qB6k 68pQVLQ5g5P1w1jGIPJy8f+pQjnbYBei4YZd3MYj4wuRfvAoR0oE0QCH1TWTORO3uwGd 5Rog== X-Gm-Message-State: AOAM531Nru5EsP0xLyK9S1eyl6G4564JZyF2riakfgN1BGXKAqPr/vXb D39P8rhsyKttHe7+7gvpVQA= X-Google-Smtp-Source: ABdhPJysxGudcpVSLa5mWnl2o8dgYwXuaz9Jla/fRyikTcQJIMVLZEPM5/il8c0u5EzYY7t7x8nfYw== X-Received: by 2002:a05:600c:3d12:: with SMTP id bh18mr1120431wmb.4.1642720842004; Thu, 20 Jan 2022 15:20:42 -0800 (PST) Received: from localhost.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id a9sm3939283wmm.32.2022.01.20.15.20.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Jan 2022 15:20:41 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Taniya Das , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 09/15] drivers: clk: qcom: gcc-ipq806x: add unusued flag for critical clock Date: Fri, 21 Jan 2022 00:20:22 +0100 Message-Id: <20220120232028.6738-10-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220120232028.6738-1-ansuelsmth@gmail.com> References: <20220120232028.6738-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Some clocks are used by other devices present on the SoC. For example the gsbi4_h_clk is used by RPM and is if disabled cause the RPM to reject any regulator change command. These clock should never be disabled. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/gcc-ipq806x.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index 53a61860063d..77bc3d94f580 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -798,7 +798,7 @@ static struct clk_rcg gsbi4_qup_src = { .parent_data = gcc_pxo_pll8, .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, + .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED, }, }, }; @@ -816,7 +816,7 @@ static struct clk_branch gsbi4_qup_clk = { }, .num_parents = 1, .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, }, }, }; @@ -900,7 +900,7 @@ static struct clk_rcg gsbi6_qup_src = { .parent_data = gcc_pxo_pll8, .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, + .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED, }, }, }; @@ -969,7 +969,7 @@ static struct clk_branch gsbi7_qup_clk = { }, .num_parents = 1, .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, }, }, }; @@ -1015,6 +1015,7 @@ static struct clk_branch gsbi4_h_clk = { .hw.init = &(struct clk_init_data){ .name = "gsbi4_h_clk", .ops = &clk_branch_ops, + .flags = CLK_IGNORE_UNUSED, }, }, }; From patchwork Thu Jan 20 23:20:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12719146 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4DF6DC433EF for ; Thu, 20 Jan 2022 23:21:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378290AbiATXVW (ORCPT ); Thu, 20 Jan 2022 18:21:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39644 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378187AbiATXUp (ORCPT ); Thu, 20 Jan 2022 18:20:45 -0500 Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [IPv6:2a00:1450:4864:20::329]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9D631C061748; Thu, 20 Jan 2022 15:20:44 -0800 (PST) Received: by mail-wm1-x329.google.com with SMTP id o7-20020a05600c510700b00347e10f66d1so8046630wms.0; Thu, 20 Jan 2022 15:20:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=EXW/q6yX9wxCGxkY1EpqijRPyr0+7BNt2tp7DEwa3FY=; b=CLcuoxP7b2nyCEsoGcgJWSzkusmI6fi81voE1CX+UPLwCpqi5JWmVP1EN/HbrCfJah nrEOTgfUf0VutgmSUPMDek+PoTsnuIU0y4awxxHslUeOrG3bSrhjxtS1HlT69p0ZlMb2 b3YQhKcYg25PHFhTrOSq8eoTtuy2cpNUgTUxsDW3wp216GAj5a/zW6E21Umo5UZVATTy ipSfjQlwP2kDJCx82oB4SbWZFlWNpPHTGuFo+kYsf/zz8D7iH2Ehiif1TEpfvi4X0RHL vysCd+E6G2CNi+f6nUqq930dP8fpEvbkuQJGRcl5v3ABCy4cuEgsBDIRHMQ0g7uO10WH 330Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EXW/q6yX9wxCGxkY1EpqijRPyr0+7BNt2tp7DEwa3FY=; b=fKrHPF/+kKheSvhuIHoHLpiWj222GV/6FOrFFJLTV3qteFFA5iQeGCAetLQRUR1gGO L+wTImK62M9y7pVDuOUftdOTc1fAZveNMIw9VBTiktPd5NA5JJcdFSLiiYLIKTx9EoBi Ux9or6WsHzH0BxAY8vhCSQ2RF/V/ivPHOYADasxrXsPsZ60xNcHDCMgQg2G9CgQOBC1S INKga4meDxMUmz38lplnTr5UiTxTMBB1SQ45pmpbgP1HECqSTjXyftz0t//2kGUG9quc YcoGUPfBM/1pGKMmBOqGWDOSO2p+3AofvgQoXJD/8M6gq3HPwEDHzDXb2VciYDcboQXj NAXQ== X-Gm-Message-State: AOAM531Ta6svEjnpH0aWz7csknXh+KZyyue6W0r0OGtmmbWqeVffj1KL U4FAcgJAKHCXtsWDZpOi8EE= X-Google-Smtp-Source: ABdhPJyuS982P3dJ+9/hHjPwlCWgs1xqXBuft+Q47eoy8lSRRAPlhuDfLZ82NRh9r1IW7XzYUW6wYA== X-Received: by 2002:a05:6000:1184:: with SMTP id g4mr1285241wrx.278.1642720843117; Thu, 20 Jan 2022 15:20:43 -0800 (PST) Received: from localhost.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id a9sm3939283wmm.32.2022.01.20.15.20.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Jan 2022 15:20:42 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Taniya Das , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 10/15] drivers: clk: qcom: gcc-ipq806x: add additional freq for sdc table Date: Fri, 21 Jan 2022 00:20:23 +0100 Message-Id: <20220120232028.6738-11-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220120232028.6738-1-ansuelsmth@gmail.com> References: <20220120232028.6738-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add additional freq supported for the sdc table. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/gcc-ipq806x.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index 77bc3d94f580..dbd61e4844b0 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -1292,6 +1292,7 @@ static const struct freq_tbl clk_tbl_sdc[] = { { 20210000, P_PLL8, 1, 1, 19 }, { 24000000, P_PLL8, 4, 1, 4 }, { 48000000, P_PLL8, 4, 1, 2 }, + { 52000000, P_PLL8, 1, 2, 15 }, /* 51.2 Mhz */ { 64000000, P_PLL8, 3, 1, 2 }, { 96000000, P_PLL8, 4, 0, 0 }, { 192000000, P_PLL8, 2, 0, 0 }, From patchwork Thu Jan 20 23:20:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12719140 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6B72C43219 for ; Thu, 20 Jan 2022 23:21:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378252AbiATXU7 (ORCPT ); Thu, 20 Jan 2022 18:20:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39656 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378198AbiATXUq (ORCPT ); Thu, 20 Jan 2022 18:20:46 -0500 Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B1845C06173F; Thu, 20 Jan 2022 15:20:45 -0800 (PST) Received: by mail-wm1-x32c.google.com with SMTP id j5-20020a05600c1c0500b0034d2e956aadso17640900wms.4; Thu, 20 Jan 2022 15:20:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=CXVZRlEKPP4hcCweUpH3JuNpFEE+gl2M3UXNpQ3IHj0=; b=Ya5ahECiik+EI90hXBMoD7x/gKR47I4qsNXYBdexkEEz4ccDAaQeJWJ5I3atnWdfpR VTzk8YGre+HvRsg4wgryGuk1SIHPiOKTbbO4HXlj6wRPJ6vsb1v9NB7GALotfKraRY0G 1c4xNy4cXe2VR3q9T/QWT1kcUNsAc7hOCyEijIGsQYBybiObrq9Gru9nP446tbE3J5dQ Vl4AFrwdTNckMLtSEGxaNn5NB62YQsqT2k94h2VdPjius178XKnD/rz6iw2tNk0l5eym AbvJ328+voz1OW2XPk5zLPbtXza8nLMJgu/eSD/kYTcVa0JktL9qzQlgyJCDwoQBL7JF S28w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CXVZRlEKPP4hcCweUpH3JuNpFEE+gl2M3UXNpQ3IHj0=; b=W+PzKCiWI6mYcnOzvXkjcVYVJMbLTavtlrsN1j7Y9HxTfgwUkUis66XUMikwD8Vi6R vjKCFz0gVNVeKG1zBxybBWxLzfb1vEPBG2zkpK3GcCu0OcflAtgQ9/98HiR/IqY7HBGl Dl09DuLvoEPcJTGp7GOm0UYUMdHsjqdiZNoH0HvB1NwwT7piZOrrZIMShXskviu+C4++ A9Ny/K5tlz/sIsc+uWiXBizwKjhnDtAbgwokXCq9D5zfW/ThMcRtEQbHHhVAWv7cIgXb Vyq6csPdZV6cB1vJXSDh8UOhQKBWmT+hPIPqRBaFWH/u+EldcgD3cCd166XTujzD2Fux xydQ== X-Gm-Message-State: AOAM533YMekalI2USYaBhDhPVFS3R2n0/sbCCQ8pDpnN+QHcUfsiViB4 HLI28xGt82Ot/lDazGP+KX0= X-Google-Smtp-Source: ABdhPJzBimoN+aIvqoMDnCkV82jqCOR++0dBAy2a4x+wuwmUQhWXGr6NdM3kyrdR4e4DaSour1+W4A== X-Received: by 2002:a5d:6042:: with SMTP id j2mr1275472wrt.105.1642720844158; Thu, 20 Jan 2022 15:20:44 -0800 (PST) Received: from localhost.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id a9sm3939283wmm.32.2022.01.20.15.20.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Jan 2022 15:20:43 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Taniya Das , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 11/15] dt-bindings: clock: add ipq8064 ce5 clk define Date: Fri, 21 Jan 2022 00:20:24 +0100 Message-Id: <20220120232028.6738-12-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220120232028.6738-1-ansuelsmth@gmail.com> References: <20220120232028.6738-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add ipq8064 ce5 clk define needed for CryptoEngine in gcc driver. Signed-off-by: Ansuel Smith --- include/dt-bindings/clock/qcom,gcc-ipq806x.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/qcom,gcc-ipq806x.h b/include/dt-bindings/clock/qcom,gcc-ipq806x.h index 7deec14a6dee..02262d2ac899 100644 --- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h +++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h @@ -240,7 +240,7 @@ #define PLL14 232 #define PLL14_VOTE 233 #define PLL18 234 -#define CE5_SRC 235 +#define CE5_A_CLK 235 #define CE5_H_CLK 236 #define CE5_CORE_CLK 237 #define CE3_SLEEP_CLK 238 @@ -283,5 +283,8 @@ #define EBI2_AON_CLK 281 #define NSSTCM_CLK_SRC 282 #define NSSTCM_CLK 283 +#define CE5_A_CLK_SRC 285 +#define CE5_H_CLK_SRC 286 +#define CE5_CORE_CLK_SRC 287 #endif From patchwork Thu Jan 20 23:20:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12719144 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED79CC433FE for ; Thu, 20 Jan 2022 23:21:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378256AbiATXVL (ORCPT ); Thu, 20 Jan 2022 18:21:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39664 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378220AbiATXUr (ORCPT ); Thu, 20 Jan 2022 18:20:47 -0500 Received: from mail-wm1-x333.google.com (mail-wm1-x333.google.com [IPv6:2a00:1450:4864:20::333]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C27F1C061574; Thu, 20 Jan 2022 15:20:46 -0800 (PST) Received: by mail-wm1-x333.google.com with SMTP id l12-20020a7bc34c000000b003467c58cbdfso25311700wmj.2; Thu, 20 Jan 2022 15:20:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=vaOb6lzR+ohDnwzAKg4t+EygQuxBAzQ4LziIApjliUg=; b=hVo8QgLIr0GUAFf5yfHgbNNXb0waZUSjtFtYr85H6g9uTqfAl6o8AeXfggT/dSBSvy UuzG/mXnCCGpKALHZUsTai72QfX2afpBAvm7pxXK7/56SexDqGgZQMiBbd2h71aHbP7y JeN7wIGq63tX0RxV/3WGGM/OxUeI4xK+nRWG4RMBxkXc0EzxPL6N53jb3AQF8ZjqJ/lu TB9KGUoPXd7mk8913+CjiwNQ0Nw0YsQoDXU/ZLsGAsaLec+X5E9SUII3vug0zw57KF2L QpoJzYGh+9IdzXdhq8UG0wiax91HT4HF0fDHAyv/PP2eBlurLmAa14Wm1+5NfPJl5h6W DJ9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vaOb6lzR+ohDnwzAKg4t+EygQuxBAzQ4LziIApjliUg=; b=Bbrsj/zzrJ7U7Gk1AuPiD3qNkYxgCXysT7EG3bHu7SyanWIqP4hEK6ymRAry5lx3cX hVBoTf6XFEOtl5Skr8qWsKZN7aGhMQY33TEu7Wf9iZMp4hs+nJV4UB6pl+VsT96i4ckO Nj4SblKXuNAakL0OIpQmadFgT4qVrQsVlUxegSfY9thfUfmxO3ubXYrWp7NNZ/Ig7aiB SfH+Rgm4yW6EMUgsstuFEV7uT5AaZMhRWnKh/gGCxsiWwX8Uq0w3txlskFQTrMXioPw1 s0W87Rlpimxw7eS8dmjNHhbR3fZujTZ2Gaqvurx980KwJcvoG1iP7DN0cEu88eu6wBIg PBfw== X-Gm-Message-State: AOAM530fyG8h3ZAgHo4A+YuqtUBO4HdOxpdNLo4QO1WuG681QM9n65m+ nYjdwZbjzVMB+OCxdkqDEROxXaHMurU= X-Google-Smtp-Source: ABdhPJx7tj2wIsfBqlflD054IGOMw0pCyVCzxjHk2d8t1MK3mhogBAyj5t9dVFdAjovn3DyPl7MhVw== X-Received: by 2002:a1c:7316:: with SMTP id d22mr11186776wmb.5.1642720845235; Thu, 20 Jan 2022 15:20:45 -0800 (PST) Received: from localhost.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id a9sm3939283wmm.32.2022.01.20.15.20.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Jan 2022 15:20:44 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Taniya Das , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 12/15] drivers: clk: qcom: gcc-ipq806x: add CryptoEngine clocks Date: Fri, 21 Jan 2022 00:20:25 +0100 Message-Id: <20220120232028.6738-13-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220120232028.6738-1-ansuelsmth@gmail.com> References: <20220120232028.6738-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add missing CryptoEngine clocks and pll11 required clock. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/gcc-ipq806x.c | 244 +++++++++++++++++++++++++++++++++ 1 file changed, 244 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index dbd61e4844b0..a86d1504a149 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -256,6 +256,24 @@ static struct clk_pll pll18 = { }, }; +static struct clk_pll pll11 = { + .l_reg = 0x3184, + .m_reg = 0x3188, + .n_reg = 0x318c, + .config_reg = 0x3194, + .mode_reg = 0x3180, + .status_reg = 0x3198, + .status_bit = 16, + .clkr.hw.init = &(struct clk_init_data){ + .name = "pll11", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "pxo", + }, + .num_parents = 1, + .ops = &clk_pll_ops, + }, +}; + enum { P_PXO, P_PLL8, @@ -264,6 +282,7 @@ enum { P_CXO, P_PLL14, P_PLL18, + P_PLL11, }; static const struct parent_map gcc_pxo_pll8_map[] = { @@ -331,6 +350,44 @@ static const struct clk_parent_data gcc_pxo_pll8_pll14_pll18_pll0[] = { { .hw = &pll18.clkr.hw }, }; +static const struct parent_map gcc_pxo_pll8_pll0_pll14_pll18_pll11_map[] = { + { P_PXO, 0 }, + { P_PLL8, 4 }, + { P_PLL0, 2 }, + { P_PLL14, 5 }, + { P_PLL18, 1 }, + { P_PLL11, 3 }, +}; + +static const struct clk_parent_data gcc_pxo_pll8_pll0_pll14_pll18_pll11[] = { + { .fw_name = "pxo" }, + { .hw = &pll8_vote.hw }, + { .hw = &pll0_vote.hw }, + { .hw = &pll14.clkr.hw }, + { .hw = &pll18.clkr.hw }, + { .hw = &pll11.clkr.hw }, + +}; + +static const struct parent_map gcc_pxo_pll3_pll0_pll14_pll18_pll11_map[] = { + { P_PXO, 0 }, + { P_PLL3, 6 }, + { P_PLL0, 2 }, + { P_PLL14, 5 }, + { P_PLL18, 1 }, + { P_PLL11, 3 }, +}; + +static const struct clk_parent_data gcc_pxo_pll3_pll0_pll14_pll18_pll11[] = { + { .fw_name = "pxo" }, + { .hw = &pll3.clkr.hw }, + { .hw = &pll0_vote.hw }, + { .hw = &pll14.clkr.hw }, + { .hw = &pll18.clkr.hw }, + { .hw = &pll11.clkr.hw }, + +}; + static struct freq_tbl clk_tbl_gsbi_uart[] = { { 1843200, P_PLL8, 2, 6, 625 }, { 3686400, P_PLL8, 2, 12, 625 }, @@ -2818,6 +2875,186 @@ static struct clk_dyn_rcg ubi32_core2_src_clk = { }, }; +static const struct freq_tbl clk_tbl_ce5_core[] = { + { 150000000, P_PLL3, 8, 1, 1 }, + { 213200000, P_PLL11, 5, 1, 1 }, + { } +}; + +static struct clk_dyn_rcg ce5_core_src = { + .ns_reg[0] = 0x36C4, + .ns_reg[1] = 0x36C8, + .bank_reg = 0x36C0, + .s[0] = { + .src_sel_shift = 0, + .parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map, + }, + .s[1] = { + .src_sel_shift = 0, + .parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map, + }, + .p[0] = { + .pre_div_shift = 3, + .pre_div_width = 4, + }, + .p[1] = { + .pre_div_shift = 3, + .pre_div_width = 4, + }, + .mux_sel_bit = 0, + .freq_tbl = clk_tbl_ce5_core, + .clkr = { + .enable_reg = 0x36C0, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "ce5_core_src", + .parent_data = gcc_pxo_pll3_pll0_pll14_pll18_pll11, + .num_parents = ARRAY_SIZE(gcc_pxo_pll3_pll0_pll14_pll18_pll11), + .ops = &clk_dyn_rcg_ops, + }, + }, +}; + +static struct clk_branch ce5_core_clk = { + .halt_reg = 0x2FDC, + .halt_bit = 5, + .hwcg_reg = 0x36CC, + .hwcg_bit = 6, + .clkr = { + .enable_reg = 0x36CC, + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "ce5_core_clk", + .parent_hws = (const struct clk_hw*[]){ + &ce5_core_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + +static const struct freq_tbl clk_tbl_ce5_a_clk[] = { + { 160000000, P_PLL0, 5, 1, 1 }, + { 213200000, P_PLL11, 5, 1, 1 }, + { } +}; + +static struct clk_dyn_rcg ce5_a_clk_src = { + .ns_reg[0] = 0x3d84, + .ns_reg[1] = 0x3d88, + .bank_reg = 0x3d80, + .s[0] = { + .src_sel_shift = 0, + .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map, + }, + .s[1] = { + .src_sel_shift = 0, + .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map, + }, + .p[0] = { + .pre_div_shift = 3, + .pre_div_width = 4, + }, + .p[1] = { + .pre_div_shift = 3, + .pre_div_width = 4, + }, + .mux_sel_bit = 0, + .freq_tbl = clk_tbl_ce5_a_clk, + .clkr = { + .enable_reg = 0x3d80, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "ce5_a_clk_src", + .parent_data = gcc_pxo_pll8_pll0_pll14_pll18_pll11, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0_pll14_pll18_pll11), + .ops = &clk_dyn_rcg_ops, + }, + }, +}; + +static struct clk_branch ce5_a_clk = { + .halt_reg = 0x3c20, + .halt_bit = 12, + .hwcg_reg = 0x3d8c, + .hwcg_bit = 6, + .clkr = { + .enable_reg = 0x3d8c, + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "ce5_a_clk", + .parent_hws = (const struct clk_hw*[]){ + &ce5_a_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + +static const struct freq_tbl clk_tbl_ce5_h_clk[] = { + { 160000000, P_PLL0, 5, 1, 1 }, + { 213200000, P_PLL11, 5, 1, 1 }, + { } +}; + +static struct clk_dyn_rcg ce5_h_clk_src = { + .ns_reg[0] = 0x3c64, + .ns_reg[1] = 0x3c68, + .bank_reg = 0x3c60, + .s[0] = { + .src_sel_shift = 0, + .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map, + }, + .s[1] = { + .src_sel_shift = 0, + .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map, + }, + .p[0] = { + .pre_div_shift = 3, + .pre_div_width = 4, + }, + .p[1] = { + .pre_div_shift = 3, + .pre_div_width = 4, + }, + .mux_sel_bit = 0, + .freq_tbl = clk_tbl_ce5_h_clk, + .clkr = { + .enable_reg = 0x3c60, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "ce5_h_clk_src", + .parent_data = gcc_pxo_pll8_pll0_pll14_pll18_pll11, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0_pll14_pll18_pll11), + .ops = &clk_dyn_rcg_ops, + }, + }, +}; + +static struct clk_branch ce5_h_clk = { + .halt_reg = 0x3c20, + .halt_bit = 11, + .hwcg_reg = 0x3c6c, + .hwcg_bit = 6, + .clkr = { + .enable_reg = 0x3c6c, + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "ce5_h_clk", + .parent_hws = (const struct clk_hw*[]){ + &ce5_h_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + static struct clk_regmap *gcc_ipq806x_clks[] = { [PLL0] = &pll0.clkr, [PLL0_VOTE] = &pll0_vote, @@ -2825,6 +3062,7 @@ static struct clk_regmap *gcc_ipq806x_clks[] = { [PLL4_VOTE] = &pll4_vote, [PLL8] = &pll8.clkr, [PLL8_VOTE] = &pll8_vote, + [PLL11] = &pll11.clkr, [PLL14] = &pll14.clkr, [PLL14_VOTE] = &pll14_vote, [PLL18] = &pll18.clkr, @@ -2939,6 +3177,12 @@ static struct clk_regmap *gcc_ipq806x_clks[] = { [PLL9] = &hfpll0.clkr, [PLL10] = &hfpll1.clkr, [PLL12] = &hfpll_l2.clkr, + [CE5_A_CLK_SRC] = &ce5_a_clk_src.clkr, + [CE5_A_CLK] = &ce5_a_clk.clkr, + [CE5_H_CLK_SRC] = &ce5_h_clk_src.clkr, + [CE5_H_CLK] = &ce5_h_clk.clkr, + [CE5_CORE_CLK_SRC] = &ce5_core_src.clkr, + [CE5_CORE_CLK] = &ce5_core_clk.clkr, }; static const struct qcom_reset_map gcc_ipq806x_resets[] = { From patchwork Thu Jan 20 23:20:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12719142 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD95AC433F5 for ; Thu, 20 Jan 2022 23:21:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378283AbiATXVD (ORCPT ); Thu, 20 Jan 2022 18:21:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39668 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378227AbiATXUs (ORCPT ); Thu, 20 Jan 2022 18:20:48 -0500 Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EFB57C06173F; Thu, 20 Jan 2022 15:20:47 -0800 (PST) Received: by mail-wm1-x331.google.com with SMTP id n8so14867947wmk.3; Thu, 20 Jan 2022 15:20:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=AjXtNoxCWeIUyUrNbQiYIAA3OZQBx2qW4EKDiOvy2ws=; b=Ucrroh9WAXok2oxE4m6dWt5I70dfUTErwT44FSCodido01s/fRuEL26NzgA36BOGxC kDY5mfs7F/iRFUfP16kuAGas9KO/JpFgp4KTlU1comHaKlBUZdxNli11pJq+wU9/OXg4 msoqgfxvbcBeZe6lXruVgEYJ4tbJMsSh09wGwBcPcBeMbYFmV8spzy/L6u+PYIyc7oYy Izgfdg1pcTEP0TuEId1f4oc89sTMFj0EizjfefqtJyyWDW8KdkGuFRH6xVEWVZwK62GE LpKg4i+87Hbex5wjogKCdtjp08Zyc8GdkccFeu9cxQy1MuezDu80sxbLyDtBPb0YYIdf zTZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AjXtNoxCWeIUyUrNbQiYIAA3OZQBx2qW4EKDiOvy2ws=; b=6EUKtli7jWUq1Y+j6oGXFplsWuWPfpYIKkFKaumdo1C94sRg3bGYdRp9HnoVKPcE5L PLCyPaec+A22ct9rpS8FRgbbks4GTeeq+6Xpq+j2Iy8bZik12C9GtWUNTM/t2f2WYv1s qTNikMECko0r8bse0cZPt3WTgLvkQn/yl1rf4cXAJFMsA7gGUWx4G0DipfGKk2GnejDf nYiWmI71cJYNqhbKxvdcoImhBn21U4s6+cwuKVjhZ4gwBSkeU04PlGJU7od5wdtvsMec 18i9Nc56ZeloK5XJ0Jv6usOrm+44zt+ev0slhErujKHlQGSVFDlTPopwMeXXv4X4P/B8 fHXg== X-Gm-Message-State: AOAM533+shuNbrk1vXtYqZkndWNJw1LSeT/w24SFLnpXDB30W7j/LunZ dvteVIy6NWfWnoETDw2qN5M= X-Google-Smtp-Source: ABdhPJzWFkhW5CTNJ3HxDt6zA8/cOwyIlG03P6YXMef5kNyNyAn/0m9cOVMnLPOGT7Kz9Yw+GlZMAA== X-Received: by 2002:a1c:e914:: with SMTP id q20mr1116001wmc.70.1642720846328; Thu, 20 Jan 2022 15:20:46 -0800 (PST) Received: from localhost.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id a9sm3939283wmm.32.2022.01.20.15.20.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Jan 2022 15:20:45 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Taniya Das , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 13/15] dt-bindings: reset: add ipq8064 ce5 resets Date: Fri, 21 Jan 2022 00:20:26 +0100 Message-Id: <20220120232028.6738-14-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220120232028.6738-1-ansuelsmth@gmail.com> References: <20220120232028.6738-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add ipq8064 ce5 resets needed for CryptoEngine gcc driver. Signed-off-by: Ansuel Smith --- include/dt-bindings/reset/qcom,gcc-ipq806x.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/dt-bindings/reset/qcom,gcc-ipq806x.h b/include/dt-bindings/reset/qcom,gcc-ipq806x.h index 26b6f9200620..020c9cf18751 100644 --- a/include/dt-bindings/reset/qcom,gcc-ipq806x.h +++ b/include/dt-bindings/reset/qcom,gcc-ipq806x.h @@ -163,5 +163,10 @@ #define NSS_CAL_PRBS_RST_N_RESET 154 #define NSS_LCKDT_RST_N_RESET 155 #define NSS_SRDS_N_RESET 156 +#define CRYPTO_ENG1_RESET 157 +#define CRYPTO_ENG2_RESET 158 +#define CRYPTO_ENG3_RESET 159 +#define CRYPTO_ENG4_RESET 160 +#define CRYPTO_AHB_RESET 161 #endif From patchwork Thu Jan 20 23:20:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12719141 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3ABF3C4167B for ; Thu, 20 Jan 2022 23:21:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378274AbiATXVC (ORCPT ); Thu, 20 Jan 2022 18:21:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39680 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378158AbiATXUt (ORCPT ); Thu, 20 Jan 2022 18:20:49 -0500 Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [IPv6:2a00:1450:4864:20::330]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E5882C061746; Thu, 20 Jan 2022 15:20:48 -0800 (PST) Received: by mail-wm1-x330.google.com with SMTP id r132-20020a1c448a000000b0034e043aaac7so1375327wma.5; Thu, 20 Jan 2022 15:20:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ETUvc/o8aObyUn/852ohaMGKgdelmVW4X0FnpFAGyTY=; b=blcAImInrA7OMX/4pKJ9wtamBVl2KLaS9ii7AGWG/i4ZcqfrRtZUJ46V46tTO+HePK gKvHhMUZLnoUCxXBqZHfcgxRSD7wBz6ipbbR3MIsDtYV6y14aA7z8bMydB+53L8mgpx9 eC2BzPfQGwj+/USWgIrufUKx5c1oZUPq2s3GcDyychrg6G1ELiicXYFlje/+AtcGy7kN MVThxG3sttDqL3knc1G6okGsOA1DH5u10bTF/1GRtaWo8iNzj6GNE9jJosq1YbKyqdSW a2A1YWikx+guP86jIKLiZ/RMVOypNzAEQT4WIlUsKCNsZRJVxpFiSHefMi+IIBFb95yP 2oWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ETUvc/o8aObyUn/852ohaMGKgdelmVW4X0FnpFAGyTY=; b=VgOOv0pkpXNw6cI87vcGI+AFCxFv7nC1s2oWu9WJEnQ9XnXznUOwdrGlzSwv1EWPv0 2O8ONcHkHzXaV9YmVmnzk2eQGQTxeHEiiua0tNXQxnynFBoPOjKT/iQeqmrKx6AIIhvG iR9TrL6xcRvgEviIjeWUkOQ2TVpHDbGyCdO0yhot0KTuhovIMbyY4G+vhMpFtr9uocWT YiQyg1ZY6WTlZ6dXTTLErmQfXUe4hY0Q+qS1gOJkcS8brh6upsd2D+anZHJNnZdtzjRq oHcEXxvZ/437uJlYlOqaTwOBFQWqrg2ooYzG4pseoyhM7JKoF3x6ZoDo0oTgDrLusSsJ Ycyg== X-Gm-Message-State: AOAM5310rRE5Y426AXLVDV8vpPvYWjkHodUvWkSHaIsQOrnsAoRzzyZr 8mqOSt/o8LHekyggwf2CWwYJJD1RRUw= X-Google-Smtp-Source: ABdhPJyIEuwTog2+Zu+Yt68Kvq8bRV0Zt4jzmgkS8KId/9vYCpFkNa7iXbPG4i+UjhvPnrlvbL61aQ== X-Received: by 2002:a1c:1dd0:: with SMTP id d199mr1073134wmd.121.1642720847407; Thu, 20 Jan 2022 15:20:47 -0800 (PST) Received: from localhost.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id a9sm3939283wmm.32.2022.01.20.15.20.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Jan 2022 15:20:47 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Taniya Das , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 14/15] drivers: clk: qcom: gcc-ipq806x: add CryptoEngine resets Date: Fri, 21 Jan 2022 00:20:27 +0100 Message-Id: <20220120232028.6738-15-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220120232028.6738-1-ansuelsmth@gmail.com> References: <20220120232028.6738-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add missing CryptoEngine resets. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/gcc-ipq806x.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index a86d1504a149..8f025cef2ec3 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -3314,6 +3314,11 @@ static const struct qcom_reset_map gcc_ipq806x_resets[] = { [GMAC_CORE3_RESET] = { 0x3cfc, 0 }, [GMAC_CORE4_RESET] = { 0x3d1c, 0 }, [GMAC_AHB_RESET] = { 0x3e24, 0 }, + [CRYPTO_ENG1_RESET] = { 0x3e00, 0}, + [CRYPTO_ENG2_RESET] = { 0x3e04, 0}, + [CRYPTO_ENG3_RESET] = { 0x3e08, 0}, + [CRYPTO_ENG4_RESET] = { 0x3e0c, 0}, + [CRYPTO_AHB_RESET] = { 0x3e10, 0}, [NSS_CH0_RST_RX_CLK_N_RESET] = { 0x3b60, 0 }, [NSS_CH0_RST_TX_CLK_N_RESET] = { 0x3b60, 1 }, [NSS_CH0_RST_RX_125M_N_RESET] = { 0x3b60, 2 }, From patchwork Thu Jan 20 23:20:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12719143 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D60BC433EF for ; Thu, 20 Jan 2022 23:21:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378146AbiATXVK (ORCPT ); Thu, 20 Jan 2022 18:21:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39682 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378232AbiATXUu (ORCPT ); Thu, 20 Jan 2022 18:20:50 -0500 Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 127B9C061574; Thu, 20 Jan 2022 15:20:50 -0800 (PST) Received: by mail-wm1-x32e.google.com with SMTP id f202-20020a1c1fd3000000b0034dd403f4fbso14390158wmf.1; Thu, 20 Jan 2022 15:20:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=70y9nP+1TJuyoQVHWKHYrgk62/1kbAozVgHhQoGQnWU=; b=W9FIXQ88UaSTP59Qi7+oime1sFU7XPsBBr+GgtIZuDCxabPolRSg0UVB57+j7xn3TL L4J7c3XN5cVXU9vUf/jC5K7uxhGch/2CdvfibqBaKT5alYLpdgoGJC0Sechz5wI13ueW yz1HoXFN/s6m+/l2+I2rKH/GFcdU6pu9U14eRH0Vb4jaqUZSyKndqo0sqB3evNjZHBfe 9MgvwW7Su+DfBOpYp0wZpCnECInP2+66b0NQDJscSnZgYRNWUL8Bs3pua9a6K1rwKdtY TTyirOIfrj5QFrdL/rS8eb23El1xVwL1JItJRWwdE30ei42exZSy7tk421zuJVgwzPRz gavQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=70y9nP+1TJuyoQVHWKHYrgk62/1kbAozVgHhQoGQnWU=; b=ryWacxUS5gcpzIpAapqVN/nXu+mTYaCl07RCEn222HIN73nJ8anwgGJtOQDJxRvRWK yKR4eX97TNvuCSLfXOyCwwxbraHHAkGRnfNf3Y1itRpsUsrWPugps/RLGLL8gOJKWw9k t1vNnn21+A3fqfxfRbv46TmYE1mMlsvng/aEyPna7HkSe6l20Yd1zQvNA+VLxZhgoYkj 6giLeHjOCuixBtCeQm02RV8bIPkIjwjoHl5xGZhx9dGBVIha8SDfVQDBcJBeTZIH1JSL RsrNr5O8Tqk7RJk/zeK6Sq7jMslwXunUibh+1+Jixgmb64s8oHgfTuZI8nABF7Ml9WtN ilCA== X-Gm-Message-State: AOAM533jLCkXh2hQCvUNuC97ObA1SPjKLzcf8Eo4JkOI1zUuhiZeKRir lpzOJiW8gMB0zKiEWMciGak= X-Google-Smtp-Source: ABdhPJy2EAGYqEGxCHtEc43zDu9wvxI6e81Sk5trFgKtuU1q9UCCbNWoXPBJztPhW8RkxnbwpfmtgQ== X-Received: by 2002:a05:600c:5125:: with SMTP id o37mr1107030wms.161.1642720848419; Thu, 20 Jan 2022 15:20:48 -0800 (PST) Received: from localhost.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id a9sm3939283wmm.32.2022.01.20.15.20.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Jan 2022 15:20:48 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Taniya Das , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 15/15] ARM: dts: qcom: Add syscon and cxo/pxo clock to gcc node for ipq8064 Date: Fri, 21 Jan 2022 00:20:28 +0100 Message-Id: <20220120232028.6738-16-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220120232028.6738-1-ansuelsmth@gmail.com> References: <20220120232028.6738-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add syscon compatible required for tsens driver to correctly probe driver and access the reg. Also add cxo and pxo tag and declare them as gcc clock now requires them for the ipq8064 gcc driver that has now been modernized. Signed-off-by: Ansuel Smith --- arch/arm/boot/dts/qcom-ipq8064.dtsi | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 11481313bdb6..5524a68cf3d1 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -298,13 +298,13 @@ smem: smem@41000000 { }; clocks { - cxo_board { + cxo_board: cxo_board { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; }; - pxo_board { + pxo_board: pxo_board { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; @@ -736,7 +736,9 @@ tsens_calib_backup: calib_backup@410 { }; gcc: clock-controller@900000 { - compatible = "qcom,gcc-ipq8064"; + compatible = "qcom,gcc-ipq8064", "syscon"; + clocks = <&pxo_board>, <&cxo_board>; + clock-names = "pxo", "cxo"; reg = <0x00900000 0x4000>; #clock-cells = <1>; #reset-cells = <1>;