From patchwork Tue Jan 25 15:00:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Rutland X-Patchwork-Id: 12723928 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 40AF8C433F5 for ; Tue, 25 Jan 2022 15:04:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=3A/wJ8wT335hxa/x9aX6HU+Fa/rb8nq44xefenK3THg=; b=jsJ1tRzUHFAeva a8vXZD5BzbQrZdRKdUL4sCTUXaHlvjbtdbOx6wkLU1zmMItg0UaZk4VIbYPl/svatoT2PKr5EcT89 iLN+rODLEWrdb4pFX6x4bX5STo2v4p9aRi3fojlT0DgFjDA8gfrxiGu8w9F4ybvjnfr4QjhvNVODU y+3YFC2XQbcxgOmQBpsZrAmdooMxayGl8ImXwtcjppHttg0DZc40lkSZE3BFDYl0EJ5C0bDxlRk9U 4d7GjjRl17OJrU3WVxWuzcsf5daRY1XO0NPGw9ZMwM63jUUWQKsut0+KePwmfgkg1YP2Q2LPYb7/I 43NRudyHFiiaEeZ4Ttvw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nCNKx-008F6l-9q; Tue, 25 Jan 2022 15:02:23 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nCNJh-008Ele-RW for linux-arm-kernel@lists.infradead.org; Tue, 25 Jan 2022 15:01:07 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D96FA101E; Tue, 25 Jan 2022 07:01:04 -0800 (PST) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id BC8EE3F793; Tue, 25 Jan 2022 07:01:03 -0800 (PST) From: Mark Rutland To: linux-arm-kernel@lists.infradead.org Cc: andre.przywara@arm.com, broonie@kernel.org, jaxson.han@arm.com, mark.rutland@arm.com, robin.murphy@arm.com, vladimir.murzin@arm.com, wei.chen@arm.com Subject: [bootwrapper PATCH v3 01/15] aarch64: correct ZCR_EL3.LEN initialization Date: Tue, 25 Jan 2022 15:00:43 +0000 Message-Id: <20220125150057.3936090-2-mark.rutland@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220125150057.3936090-1-mark.rutland@arm.com> References: <20220125150057.3936090-1-mark.rutland@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220125_070105_993132_EA5AC3D5 X-CRM114-Status: GOOD ( 13.01 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The ZCR_ELx.LEN field covers bits[3:0] of ZCR_ELx, and bits[8:4] are RAZ/WI, likely so that in future these can be used to extend LEN without complicating the probing of the maximum available vector length. Currently ZCR_EL3_LEN_MASK is defined as 0x1ff, covering both the LEN field and the RAZ/WI bits. To match the architecture as documented, reduce this down to 0xf, only covering the bits currently allocated to the LEN field. We can extend this in future if the LEN field is widened. As the same time, rename ZCR_EL3_LEN_MASK to ZCR_EL3_LEN_MAX, as it is used as a value rather than as a bit mask. Signed-off-by: Mark Rutland Cc: Andre Przywara Cc: Mark Brown Reviewed-by: Andre Przywara --- arch/aarch64/boot.S | 2 +- arch/aarch64/include/asm/cpu.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S index 72c6b79..ee9ddaa 100644 --- a/arch/aarch64/boot.S +++ b/arch/aarch64/boot.S @@ -123,7 +123,7 @@ ASM_FUNC(_start) msr cptr_el3, x0 isb - mov x0, #ZCR_EL3_LEN_MASK // SVE: Enable full vector len + mov x0, #ZCR_EL3_LEN_MAX // SVE: Enable full vector len msr ZCR_EL3, x0 // for EL2. 1: diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h index 63eb1c3..e3269b8 100644 --- a/arch/aarch64/include/asm/cpu.h +++ b/arch/aarch64/include/asm/cpu.h @@ -30,7 +30,7 @@ #define CPTR_EL3_EZ (1 << 8) #define ZCR_EL3 s3_6_c1_c2_0 -#define ZCR_EL3_LEN_MASK 0x1ff +#define ZCR_EL3_LEN_MAX 0xf #define SCTLR_EL1_CP15BEN (1 << 5) #define SCTLR_EL1_RES1 (3 << 28 | 3 << 22 | 1 << 11) From patchwork Tue Jan 25 15:00:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Rutland X-Patchwork-Id: 12723927 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8EB74C433F5 for ; Tue, 25 Jan 2022 15:04:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=rGu/KTiirsAYiUnKuiEWeaeDBttguShM2Kw6rhTmP28=; b=cdom6rz6f1YWyE XW2WiLvkDmlCrX9nN3z+0+Ba+1j2kGlLOWar8PEvBIIZT81bvN6hUFoUc1zlmZbY/1WaSocpCrH39 edVjxj0lxflhppz35h/ILCX5LKO+6N1ll6g38IsNZX3rFVeOxqkaNpbdDCv0u1aJ1+UCwlglJ047y 0KdflhJZQbay4RJN2DQefK62cwkIANfqEXphlvuG/x71OPwuCKC7sHQKJroM3mwochIF1IPpvbzA2 pyaVgPGEtekw+TuVDkemyknUEb+qCMimY3RcXtz/pXPg1Kfr49hCjtKAULuAFpWtJgYAZFYL/eLbg qrn+0nM3tfyllH5HDhIQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nCNLJ-008FD5-3M; Tue, 25 Jan 2022 15:02:45 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nCNJj-008EmF-IF for linux-arm-kernel@lists.infradead.org; Tue, 25 Jan 2022 15:01:09 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9B78D1063; Tue, 25 Jan 2022 07:01:06 -0800 (PST) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 807AD3F793; Tue, 25 Jan 2022 07:01:05 -0800 (PST) From: Mark Rutland To: linux-arm-kernel@lists.infradead.org Cc: andre.przywara@arm.com, broonie@kernel.org, jaxson.han@arm.com, mark.rutland@arm.com, robin.murphy@arm.com, vladimir.murzin@arm.com, wei.chen@arm.com Subject: [bootwrapper PATCH v3 02/15] aarch64: correct SCTLR_EL1_KERNEL for AA32 kernels Date: Tue, 25 Jan 2022 15:00:44 +0000 Message-Id: <20220125150057.3936090-3-mark.rutland@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220125150057.3936090-1-mark.rutland@arm.com> References: <20220125150057.3936090-1-mark.rutland@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220125_070107_672871_031A918B X-CRM114-Status: GOOD ( 11.87 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Bits [31:0] of the AArch64 SCTLR_EL1 register are architecturally mapped to bits [31:0] of the AArch32 SCTLR register. This means that any individual bit always has the same value across the two registers. Across the two registers, the same bit may have distinct meanings, distinct RESx behaviour, and distinct reset behaviour. For example, SCTLR_EL1[28] is nTLSMD, which we wich to initialize to 0b1, whereas SCTLR[28] is TRE, which we wish to initialize to 0b0. To avoid setting bits which we did not intend to, and in preparation for configuring more AArch64 RES1 bits, this patch decouples the SCTLR_EL1_KERNEL value used for AArch32 kernels from the SCTLR_EL1_RES1 definitions such that is does not inherit AArch64 SCTLR_EL1 bits which would be problematic in the AArch32 SCTLR. For now we open-code a copy of the bits defined in arch/aarch64/include/asm/cpu.h. Signed-off-by: Mark Rutland Cc: Andre Przywara Reviewed-by: Andre Przywara --- arch/aarch64/include/asm/cpu.h | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h index e3269b8..49d3f86 100644 --- a/arch/aarch64/include/asm/cpu.h +++ b/arch/aarch64/include/asm/cpu.h @@ -36,8 +36,15 @@ #define SCTLR_EL1_RES1 (3 << 28 | 3 << 22 | 1 << 11) #ifdef KERNEL_32 -/* 32-bit kernel decompressor uses CP15 barriers */ -#define SCTLR_EL1_KERNEL (SCTLR_EL1_RES1 | SCTLR_EL1_CP15BEN) +/* + * When booting a 32-bit kernel, EL1 uses AArch32 and registers which are + * architecturally mapped must be configured with the AArch32 layout. + * + * We copy the AArch32 definition of SCTLR_KERNEL here. + * + * TODO: restructure the headers to share a single definition. + */ +#define SCTLR_EL1_KERNEL (3 << 22 | 1 << 11 | 1 << 5 | 3 << 4) #define SPSR_KERNEL (SPSR_A | SPSR_I | SPSR_F | SPSR_HYP) #else #define SCTLR_EL1_KERNEL SCTLR_EL1_RES1 From patchwork Tue Jan 25 15:00:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Rutland X-Patchwork-Id: 12723929 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4287DC433EF for ; Tue, 25 Jan 2022 15:04:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=LpDSQUYAGYQ98hkkZqvgOFLZwrsJe0jyPRltIPOM494=; b=T2mZLW3Oq8VlgZ 3+/3NY0f+FqXe/ilDt1n3TJbF+Rgb5nehQbxzUEjfs0ijYGLM5vp5YUwLJ91wmZCb2PA/PU0ihiAr ZQEiP/ew7X7dGAS/hOhGuESgSegYMvOw/oirEiUilJf7HCCXD6G6lLtdWy2axnsT9NVhvHkHct0nn ILiqHVcrOBDQENBJKO1MSr9NnGF3JhrA86mgVVBEbW241ilsMcK6CLVeFCpFbHjzOQsgr6KFZsAu0 IxjNt0glfm3b5A5y+hXzWN2/G11V3re3AesnbiYjv2vL/cJEVhC6Gigm2FQ1s9Y7+IPal9QSmQJH1 VpXTz5pzxthQ9wQlkvkQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nCNLh-008FKl-V0; Tue, 25 Jan 2022 15:03:10 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nCNJl-008Emw-6h for linux-arm-kernel@lists.infradead.org; Tue, 25 Jan 2022 15:01:10 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 71027D6E; Tue, 25 Jan 2022 07:01:08 -0800 (PST) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 56BAB3F793; Tue, 25 Jan 2022 07:01:07 -0800 (PST) From: Mark Rutland To: linux-arm-kernel@lists.infradead.org Cc: andre.przywara@arm.com, broonie@kernel.org, jaxson.han@arm.com, mark.rutland@arm.com, robin.murphy@arm.com, vladimir.murzin@arm.com, wei.chen@arm.com Subject: [bootwrapper PATCH v3 03/15] Document entry requirements Date: Tue, 25 Jan 2022 15:00:45 +0000 Message-Id: <20220125150057.3936090-4-mark.rutland@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220125150057.3936090-1-mark.rutland@arm.com> References: <20220125150057.3936090-1-mark.rutland@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220125_070109_361750_D0AD3096 X-CRM114-Status: GOOD ( 13.33 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Currently the boot-wrapper only supports some combinations of exception levels, with other combinations not being supported. While we generally expect the boot-wrapper to be entered at the highest implemented exception level, the AArch32 boot-wrapper has a comment implying it supports being entered with something else owning EL3. As this would require such EL3 firmware to always be in sync with the boot-wrapper's requirements, which change over time, we don't actually support such a configuration. Some CPU state (such as CNTFRQ/CNTFRQ_EL0) needs to be initialized at the highest implemented exception level, but today the boot-wrapper only does so when entered at EL3 / Secure-PL1. Thus, today the only completely supported configurations are EL3 / Secure-PL1, and entering in other configurations is not entirely supported. The aarch64 `jump_kernel` function always writes to SCTLR_EL2, which is UNDEFINED at EL1. Hence, the aarch64 boot-wrapper does not support being entered at EL1. The aarch32 code assumes that any non-hyp mode is Secure PL1, and attempt to switch to monitor mode. If entered on a system without the security extensions, where the highest privileged mode is Non-secure PL1, this will not work. Hence the aarch32 boot-wrapper does not support being entered at Non-secure PL1. Actually supporting all of these configurations requires restructuring much of the boot-wrapper. For now, document the supported configurations in each architecture's boot.S, and remove the misleading comment from arch/aarch32/boot.S. Subsequent patches will improve the support and add support for additional configurations. There should be no functional change as a result of this patch. Signed-off-by: Mark Rutland Reviewed-by: Andre Przywara --- arch/aarch32/boot.S | 14 ++++++++++++++ arch/aarch32/psci.S | 5 ----- arch/aarch64/boot.S | 13 +++++++++++++ 3 files changed, 27 insertions(+), 5 deletions(-) diff --git a/arch/aarch32/boot.S b/arch/aarch32/boot.S index 4add338..00c432d 100644 --- a/arch/aarch32/boot.S +++ b/arch/aarch32/boot.S @@ -16,6 +16,20 @@ .arch_extension virt .section .init + + /* + * The boot-wrapper must be entered from the reset vector at the + * highest implemented exception level. The boot-wrapper only supports + * being entered in the following modes: + * + * - PL1 / EL3 (Secure) Supervisor mode + * Entering in this mode is strongly recommended. + * PL2 must be implemented. + * + * - PL2 / EL2 (Non-secure) Hypervisor mode + * Entering in this mode is partially supported. + * PSCI is not supported when entered in this mode. + */ ASM_FUNC(_start) /* Stack initialisation */ cpuid r0, r1 diff --git a/arch/aarch32/psci.S b/arch/aarch32/psci.S index dc7aeb7..e0d2972 100644 --- a/arch/aarch32/psci.S +++ b/arch/aarch32/psci.S @@ -44,11 +44,6 @@ ASM_FUNC(start_el3) /* pass through */ ASM_FUNC(start_no_el3) - /* - * For no-el3, we assume that firmware launched the boot-wrapper in - * non-secure EL2 or EL1. We assume it has its own PSCI implementation - * sitting at EL3, and that this path is only taken by primary CPU. - */ cpuid r0, r1 blx find_logical_id b psci_first_spin diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S index ee9ddaa..d682ba5 100644 --- a/arch/aarch64/boot.S +++ b/arch/aarch64/boot.S @@ -12,6 +12,19 @@ .section .init + /* + * The boot-wrapper must be entered from the reset vector at the + * highest implemented exception level. The boot-wrapper only supports + * being entered at the following exception levels: + * + * - EL3 (Secure) + * Entering at EL3 is strongly recommended. + * EL2 must be implemented. + * + * - EL2 (Non-secure) + * Entering at EL2 is partially supported. + * PSCI is not supported when entered in this exception level. + */ ASM_FUNC(_start) cpuid x0, x1 bl find_logical_id From patchwork Tue Jan 25 15:00:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Rutland X-Patchwork-Id: 12723930 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CEF58C433EF for ; Tue, 25 Jan 2022 15:05:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=YUK2TmtUuSvsTZtldJKwnFKTt4eFpb+CkSH6xu6GKTs=; b=LUFX4isLgArpOu d4mxNK14/CZy92fUE1UnhrzB5u1t1PFlDd6KGZEWEyu13WCLyR2uOAG8DdcwfyclQg1BD8dLkn1N8 TWJ7x7NG1MmqdO+vUost2YML6EQ7008pXH9BjpjuTqwmk16cidKGJSzRwN2mgKGptlBwHb0gGnz7P QWYDnk8r0Zd8iFQDJRnPbROlNoZIgTHbS+mGwJSpvVB9JCCUAiy2emAmDIZ3V5d3FjfLV4Q89lBGF nHfW9WmoT6nCWsfhdHvXQUpiycZXWxAxjfqSrGzY0OS/hhwdyhmmiBn5Q/fzdlVxJw/gdugVhU/Rr VGdMLIyYJuZKVXCIxmHw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nCNM3-008FUW-Ji; Tue, 25 Jan 2022 15:03:32 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nCNJo-008Eo8-5A for linux-arm-kernel@lists.infradead.org; Tue, 25 Jan 2022 15:01:13 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 87482D6E; Tue, 25 Jan 2022 07:01:11 -0800 (PST) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 6ABA43F793; Tue, 25 Jan 2022 07:01:10 -0800 (PST) From: Mark Rutland To: linux-arm-kernel@lists.infradead.org Cc: andre.przywara@arm.com, broonie@kernel.org, jaxson.han@arm.com, mark.rutland@arm.com, robin.murphy@arm.com, vladimir.murzin@arm.com, wei.chen@arm.com Subject: [bootwrapper PATCH v3 04/15] Add bit-field macros Date: Tue, 25 Jan 2022 15:00:46 +0000 Message-Id: <20220125150057.3936090-5-mark.rutland@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220125150057.3936090-1-mark.rutland@arm.com> References: <20220125150057.3936090-1-mark.rutland@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220125_070112_265250_A15464CD X-CRM114-Status: GOOD ( 15.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Arm architectural documentation typically defines bit-fields as `[msb,lsb]` and single-bit fields as `[bit]`. For clarity it would be helpful if we could define fields in the same way. Add helpers so that we can do so, along with helper to extract/insert bit-field values. There should be no functional change as a result of this patch. Signed-off-by: Mark Rutland Reviewed-by: Andre Przywara --- include/bits.h | 66 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) create mode 100644 include/bits.h diff --git a/include/bits.h b/include/bits.h new file mode 100644 index 0000000..5f0ad8f --- /dev/null +++ b/include/bits.h @@ -0,0 +1,66 @@ +/* + * include/bits.h - helpers for bit-field definitions. + * + * Copyright (C) 2021 ARM Limited. All rights reserved. + * + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE.txt file. + */ +#ifndef __BITS_H +#define __BITS_H + +#ifdef __ASSEMBLY__ +#define UL(x) x +#define ULL(x) x +#else +#define UL(x) x##UL +#define ULL(x) x##ULL +#endif + +/* + * Define a contiguous mask of bits with `msb` as the most significant bit and + * `lsb` as the least significant bit. The `msb` value must be greater than or + * equal to `lsb`. + * + * For example: + * - BITS(63, 63) is 0x8000000000000000 + * - BITS(63, 0) is 0xFFFFFFFFFFFFFFFF + * - BITS(0, 0) is 0x0000000000000001 + * - BITS(49, 17) is 0x0001FFFFFFFE0000 + */ +#define BITS(msb, lsb) \ + ((~ULL(0) >> (63 - msb)) & (~ULL(0) << lsb)) + +/* + * Define a mask of a single set bit `b`. + * + * For example: + * - BIT(63) is 0x8000000000000000 + * - BIT(0) is 0x0000000000000001 + * - BIT(32) is 0x0000000100000000 + */ +#define BIT(b) BITS(b, b) + +/* + * Find the least significant set bit in the contiguous set of bits in `mask`. + * + * For example: + * - BITS_LSB(0x0000000000000001) is 0 + * - BITS_LSB(0x000000000000ff00) is 8 + * - BITS_LSB(0x8000000000000000) is 63 + */ +#define BITS_LSB(mask) (__builtin_ffsll(mask) - 1) + +/* + * Extract a bit-field out of `val` described by the contiguous set of bits in + * `mask`. + * + * For example: + * - BITS_EXTRACT(0xABCD, BITS(15, 12)) is 0xA + * - BITS_EXTRACT(0xABCD, BITS(11, 8)) is 0xB + * - BITS_EXTRACT(0xABCD, BIT(7)) is 0x1 + */ +#define BITS_EXTRACT(val, mask) \ + (((val) & (mask)) >> BITS_LSB(mask)) + +#endif From patchwork Tue Jan 25 15:00:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Rutland X-Patchwork-Id: 12723931 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A3474C433F5 for ; Tue, 25 Jan 2022 15:05:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=cwy+fejhBW1n/ecPYB0E50tVM8meYTJHhvXoGiWRPtU=; b=l8ld135aVWmY7U xZggQqcL90i1WqBweXGxgbV45y9v7VVfTX81/nVzEpH7XaGp3w2JNQRRaYDZkoeo7dC1bBpy6BnSB wcNe8L4V2rwY34mfYN6uuYBnlriQZKaY9372vvcol4t4FN5P7yCEo+A/dGJvo5ZDl2oitbp3ZE3nO rZMfU3WfFJkBFLYdhV1xeOrVEfQkMStrJYYOLEx8eEI2HSogmVsJcVZW9GS1QSB/Z8Qqm6n49mr4S fEEIcmL3uHlnwPD1InEPWV4HPUC96zXIU/TtcYlvS4ks8TJMRa5tLNE03gqB4PqkuFgi8/YNGCkic lRnp+jRcdPH3dVIrWhBQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nCNMS-008FfC-OK; Tue, 25 Jan 2022 15:03:56 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nCNJr-008EpK-3a for linux-arm-kernel@lists.infradead.org; Tue, 25 Jan 2022 15:01:16 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 546AD101E; Tue, 25 Jan 2022 07:01:13 -0800 (PST) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 39B5D3F793; Tue, 25 Jan 2022 07:01:12 -0800 (PST) From: Mark Rutland To: linux-arm-kernel@lists.infradead.org Cc: andre.przywara@arm.com, broonie@kernel.org, jaxson.han@arm.com, mark.rutland@arm.com, robin.murphy@arm.com, vladimir.murzin@arm.com, wei.chen@arm.com Subject: [bootwrapper PATCH v3 05/15] aarch64: add system register accessors Date: Tue, 25 Jan 2022 15:00:47 +0000 Message-Id: <20220125150057.3936090-6-mark.rutland@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220125150057.3936090-1-mark.rutland@arm.com> References: <20220125150057.3936090-1-mark.rutland@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220125_070115_271792_EE360839 X-CRM114-Status: UNSURE ( 9.99 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org We open code the use of mrs/msr for specific registers, which is somewhat tedious. Add macros to do this generically, along with a helper to extract a specific register field. Existing C usage is converted to the new helpers, and register definitions moved to a common location. There should be no functional change as a result of this patch. Signed-off-by: Mark Rutland Reviewed-by: Andre Przywara --- arch/aarch64/include/asm/cpu.h | 41 ++++++++++++++++++++++--------- arch/aarch64/include/asm/gic-v3.h | 10 +++----- 2 files changed, 32 insertions(+), 19 deletions(-) diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h index 49d3f86..341a545 100644 --- a/arch/aarch64/include/asm/cpu.h +++ b/arch/aarch64/include/asm/cpu.h @@ -9,10 +9,14 @@ #ifndef __ASM_AARCH64_CPU_H #define __ASM_AARCH64_CPU_H +#include + #define MPIDR_ID_BITS 0xff00ffffff #define CURRENTEL_EL3 (3 << 2) +#define ID_AA64PFR0_EL1_GIC BITS(27, 24) + /* * RES1 bits, little-endian, caches and MMU off, no alignment checking, * no WXN. @@ -29,6 +33,12 @@ #define CPTR_EL3_EZ (1 << 8) +#define ICC_SRE_EL2 S3_4_C12_C9_5 +#define ICC_SRE_EL3 S3_6_C12_C12_5 +#define ICC_CTLR_EL1 S3_0_C12_C12_4 +#define ICC_CTLR_EL3 S3_6_C12_C12_4 +#define ICC_PMR_EL1 S3_0_C4_C6_0 + #define ZCR_EL3 s3_6_c1_c2_0 #define ZCR_EL3_LEN_MAX 0xf @@ -57,20 +67,27 @@ #define sevl() asm volatile ("sevl\n" : : : "memory") -static inline unsigned long read_mpidr(void) -{ - unsigned long mpidr; +#define __str(def) #def - asm volatile ("mrs %0, mpidr_el1\n" : "=r" (mpidr)); - return mpidr & MPIDR_ID_BITS; -} +#define mrs(reg) \ +({ \ + unsigned long __mrs_val; \ + asm volatile("mrs %0, " __str(reg) : "=r" (__mrs_val)); \ + __mrs_val; \ +}) -static inline uint64_t read_id_aa64pfr0(void) -{ - uint64_t val; +#define msr(reg, val) \ +do { \ + unsigned long __msr_val = val; \ + asm volatile("msr " __str(reg) ", %0" : : "r" (__msr_val)); \ +} while (0) + +#define mrs_field(reg, field) \ + BITS_EXTRACT(mrs(reg), (reg##_##field)) - asm volatile ("mrs %0, id_aa64pfr0_el1\n" : "=r" (val)); - return val; +static inline unsigned long read_mpidr(void) +{ + return mrs(mpidr_el1) & MPIDR_ID_BITS; } static inline void iciallu(void) @@ -80,7 +97,7 @@ static inline void iciallu(void) static inline int has_gicv3_sysreg(void) { - return !!((read_id_aa64pfr0() >> 24) & 0xf); + return !!mrs_field(ID_AA64PFR0_EL1, GIC); } #endif /* !__ASSEMBLY__ */ diff --git a/arch/aarch64/include/asm/gic-v3.h b/arch/aarch64/include/asm/gic-v3.h index 5b32380..2447480 100644 --- a/arch/aarch64/include/asm/gic-v3.h +++ b/arch/aarch64/include/asm/gic-v3.h @@ -9,20 +9,16 @@ #ifndef __ASM_AARCH64_GICV3_H #define __ASM_AARCH64_GICV3_H -#define ICC_SRE_EL2 "S3_4_C12_C9_5" -#define ICC_SRE_EL3 "S3_6_C12_C12_5" -#define ICC_CTLR_EL1 "S3_0_C12_C12_4" -#define ICC_CTLR_EL3 "S3_6_C12_C12_4" -#define ICC_PMR_EL1 "S3_0_C4_C6_0" +#include static inline void gic_write_icc_sre(uint32_t val) { - asm volatile ("msr " ICC_SRE_EL3 ", %0" : : "r" (val)); + msr(ICC_SRE_EL3, val); } static inline void gic_write_icc_ctlr(uint32_t val) { - asm volatile ("msr " ICC_CTLR_EL3 ", %0" : : "r" (val)); + msr(ICC_CTLR_EL3, val); } #endif From patchwork Tue Jan 25 15:00:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Rutland X-Patchwork-Id: 12723932 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 96EB4C433EF for ; Tue, 25 Jan 2022 15:05:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Tue, 25 Jan 2022 07:01:13 -0800 (PST) From: Mark Rutland To: linux-arm-kernel@lists.infradead.org Cc: andre.przywara@arm.com, broonie@kernel.org, jaxson.han@arm.com, mark.rutland@arm.com, robin.murphy@arm.com, vladimir.murzin@arm.com, wei.chen@arm.com Subject: [bootwrapper PATCH v3 06/15] aarch32: add coprocessor accessors Date: Tue, 25 Jan 2022 15:00:48 +0000 Message-Id: <20220125150057.3936090-7-mark.rutland@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220125150057.3936090-1-mark.rutland@arm.com> References: <20220125150057.3936090-1-mark.rutland@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220125_070116_039702_F9894EC5 X-CRM114-Status: GOOD ( 11.01 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org We open code the use of mrc/mcr for specific registers, which is somewhat tedious. Add macros to do this generically, along with a helper to extract a specific register field. Existing C usage is converted to the new helpers, and register definitions moved to a common location. There should be no functional change as a result of this patch. Signed-off-by: Mark Rutland Reviewed-by: Andre Przywara --- arch/aarch32/include/asm/cpu.h | 45 ++++++++++++++++++++----------- arch/aarch32/include/asm/gic-v3.h | 6 +++-- 2 files changed, 34 insertions(+), 17 deletions(-) diff --git a/arch/aarch32/include/asm/cpu.h b/arch/aarch32/include/asm/cpu.h index 105cae5..d691c7b 100644 --- a/arch/aarch32/include/asm/cpu.h +++ b/arch/aarch32/include/asm/cpu.h @@ -9,9 +9,13 @@ #ifndef __ASM_AARCH32_CPU_H #define __ASM_AARCH32_CPU_H +#include + #define MPIDR_ID_BITS 0x00ffffff #define MPIDR_INVALID (-1) +#define ID_PFR1_GIC BITS(31, 28) + /* Only RES1 bits and CP15 barriers for the kernel */ #define HSCTLR_KERNEL (3 << 28 | 3 << 22 | 1 << 18 | 1 << 16 | 1 << 11 | 3 << 4) #define SCTLR_KERNEL (3 << 22 | 1 << 11 | 1 << 5 | 3 << 4) @@ -40,32 +44,43 @@ #define sevl() asm volatile ("sev" : : : "memory") #endif -static inline unsigned long read_mpidr(void) -{ - unsigned long mpidr; +#define MPIDR "p15, 0, %0, c0, c0, 5" +#define ID_PFR1 "p15, 0, %0, c0, c1, 1" +#define ICIALLU "p15, 0, %0, c7, c5, 0" - asm volatile ("mrc p15, 0, %0, c0, c0, 5\n" : "=r" (mpidr)); - return mpidr & MPIDR_ID_BITS; -} +#define ICC_SRE "p15, 6, %0, c12, c12, 5" +#define ICC_CTLR "p15, 6, %0, c12, c12, 4" -static inline uint32_t read_id_pfr1(void) -{ - uint32_t val; +#define mrc(reg) \ +({ \ + unsigned long __mrc_val; \ + asm volatile("mrc " reg : "=r" (__mrc_val)); \ + __mrc_val; \ +}) - asm volatile ("mrc p15, 0, %0, c0, c1, 1\n" : "=r" (val)); - return val; +#define mcr(reg, val) \ +do { \ + unsigned long __mcr_val = val; \ + asm volatile("mcr " reg : : "r" (__mcr_val)); \ +} while (0) + + +#define mrc_field(reg, field) \ + BITS_EXTRACT(mrc(reg), (reg##_##field)) + +static inline unsigned long read_mpidr(void) +{ + return mrc(MPIDR) & MPIDR_ID_BITS; } static inline void iciallu(void) { - uint32_t val = 0; - - asm volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (val)); + mcr(ICIALLU, 0); } static inline int has_gicv3_sysreg(void) { - return !!((read_id_pfr1() >> 28) & 0xf); + return !!mrc_field(ID_PFR1, GIC); } #endif /* __ASSEMBLY__ */ diff --git a/arch/aarch32/include/asm/gic-v3.h b/arch/aarch32/include/asm/gic-v3.h index 65f38de..b28136a 100644 --- a/arch/aarch32/include/asm/gic-v3.h +++ b/arch/aarch32/include/asm/gic-v3.h @@ -9,14 +9,16 @@ #ifndef __ASM_AARCH32_GICV3_H #define __ASM_AARCH32_GICV3_H +#include + static inline void gic_write_icc_sre(uint32_t val) { - asm volatile ("mcr p15, 6, %0, c12, c12, 5" : : "r" (val)); + mcr(ICC_SRE, val); } static inline void gic_write_icc_ctlr(uint32_t val) { - asm volatile ("mcr p15, 6, %0, c12, c12, 4" : : "r" (val)); + mcr(ICC_CTLR, val); } #endif From patchwork Tue Jan 25 15:00:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Rutland X-Patchwork-Id: 12723933 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5894AC433F5 for ; Tue, 25 Jan 2022 15:06:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Tue, 25 Jan 2022 07:01:15 -0800 (PST) From: Mark Rutland To: linux-arm-kernel@lists.infradead.org Cc: andre.przywara@arm.com, broonie@kernel.org, jaxson.han@arm.com, mark.rutland@arm.com, robin.murphy@arm.com, vladimir.murzin@arm.com, wei.chen@arm.com Subject: [bootwrapper PATCH v3 07/15] aarch64: add mov_64 macro Date: Tue, 25 Jan 2022 15:00:49 +0000 Message-Id: <20220125150057.3936090-8-mark.rutland@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220125150057.3936090-1-mark.rutland@arm.com> References: <20220125150057.3936090-1-mark.rutland@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220125_070117_489079_4481AFD7 X-CRM114-Status: GOOD ( 11.66 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org In subsequent patches we'll need to load 64-bit values into GPRs before the CPU is in a known endianness, where we cannot use literal pools. In preparation for that, this patch adds a new `mov_64` macro to load a 64-bit value into a GPR using a sequence of MOV and MOVKs, which will function the same regardless of the CPU's endianness. At the same time, move the `cpuid` macro to use `mov_64` internally. Signed-off-by: Mark Rutland Reviewed-by: Andre Przywara --- arch/aarch64/common.S | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/aarch64/common.S b/arch/aarch64/common.S index c7171a9..3279fa9 100644 --- a/arch/aarch64/common.S +++ b/arch/aarch64/common.S @@ -9,9 +9,17 @@ #include + /* Load a 64-bit value using immediates */ + .macro mov_64 dest, val + mov \dest, #(((\val) >> 0) & 0xffff) + movk \dest, #(((\val) >> 16) & 0xffff), lsl #16 + movk \dest, #(((\val) >> 32) & 0xffff), lsl #32 + movk \dest, #(((\val) >> 48) & 0xffff), lsl #48 + .endm + /* Put MPIDR into \dest, clobber \tmp and flags */ .macro cpuid dest, tmp mrs \dest, mpidr_el1 - ldr \tmp, =MPIDR_ID_BITS + mov_64 \tmp, MPIDR_ID_BITS ands \dest, \dest, \tmp .endm From patchwork Tue Jan 25 15:00:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Rutland X-Patchwork-Id: 12723934 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 18E29C433F5 for ; Tue, 25 Jan 2022 15:07:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=O+Ns5EC4D+Fcd8RoDd+1MZY28pYgA9Qc56vNjr7ZBzE=; b=rKLJ37BzNpKbg5 IvRsndlJCqkEpjKBep2AsjkLgJULH3q5lJayh3HNQQKFc8e1lQmCD3gfr1LCKqAzRTYPpPpZ5m/0z vUAUqxfCdcLIMR4o44PvhLpnBERtgEYO8payaxbVaVixKLpKeS/wzha4DMMM8D2itvk6XsAj0Hah0 R+hrOEB9zlYCOYRvwnEZQhVZ11SQAd4qXZxB13Yx1QSNJuaTWfCY0NJHchaQdGYYr/9nS/Q9YexYe maccW6L5c3hRMghbfn+BDjfwrvoyfMthCk8bkkTuqQz2yDU2MTQoRACqFCnfJjxbj08vcybKt6vg7 O4l3PerlDgRXjIFVXwUw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nCNOD-008GXZ-M8; Tue, 25 Jan 2022 15:05:46 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nCNJv-008EqA-9f for linux-arm-kernel@lists.infradead.org; Tue, 25 Jan 2022 15:01:21 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BDF53D6E; Tue, 25 Jan 2022 07:01:18 -0800 (PST) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 985853F793; Tue, 25 Jan 2022 07:01:17 -0800 (PST) From: Mark Rutland To: linux-arm-kernel@lists.infradead.org Cc: andre.przywara@arm.com, broonie@kernel.org, jaxson.han@arm.com, mark.rutland@arm.com, robin.murphy@arm.com, vladimir.murzin@arm.com, wei.chen@arm.com Subject: [bootwrapper PATCH v3 08/15] aarch64: initialize SCTLR_ELx for the boot-wrapper Date: Tue, 25 Jan 2022 15:00:50 +0000 Message-Id: <20220125150057.3936090-9-mark.rutland@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220125150057.3936090-1-mark.rutland@arm.com> References: <20220125150057.3936090-1-mark.rutland@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220125_070119_476036_89F33231 X-CRM114-Status: GOOD ( 12.93 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The SCTLR_ELx registers contain fields which are UNKNOWN or IMPLEMENTATION DEFINED out of reset. This includes SCTLR_ELx.EE, which defines the endianness of memory accesses (e.g. reads from literal pools). Due to this, portions of boot-wrapper code are not guaranteed to work correctly. Rework the startup code to explicitly initialize SCTLR_ELx for the exception level the boot-wrapper was entered at. When entered at EL2 it's necessary to first initialise HCR_EL2.E2H as this affects the RESx behaviour of bits in SCTLR_EL2, and also aliases SCTLR_EL1 to SCTLR_EL2, which would break the initialization performed in jump_kernel. As we plan to eventually support the highest implemented EL being any of EL3/EL2/EL1, code is added to handle all of these exception levels, even though we do not currently support starting at EL1. We'll initialize other registers in subsequent patches. Signed-off-by: Mark Rutland Reviewed-by: Andre Przywara --- arch/aarch64/boot.S | 74 +++++++++++++++++++++++++++------- arch/aarch64/include/asm/cpu.h | 30 +++++++++++++- 2 files changed, 88 insertions(+), 16 deletions(-) diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S index d682ba5..204c199 100644 --- a/arch/aarch64/boot.S +++ b/arch/aarch64/boot.S @@ -26,26 +26,26 @@ * PSCI is not supported when entered in this exception level. */ ASM_FUNC(_start) - cpuid x0, x1 - bl find_logical_id - cmp x0, #MPIDR_INVALID - beq err_invalid_id - bl setup_stack - - /* - * EL3 initialisation - */ mrs x0, CurrentEL cmp x0, #CURRENTEL_EL3 - b.eq 1f + b.eq reset_at_el3 + cmp x0, #CURRENTEL_EL2 + b.eq reset_at_el2 + cmp x0, #CURRENTEL_EL1 + b.eq reset_at_el1 - mov w0, #1 - ldr x1, =flag_no_el3 - str w0, [x1] + /* Booting at EL0 is not supported */ + b . - b start_no_el3 + /* + * EL3 initialisation + */ +reset_at_el3: + mov_64 x0, SCTLR_EL3_RESET + msr sctlr_el3, x0 + isb -1: mov x0, #0x30 // RES1 + mov x0, #0x30 // RES1 orr x0, x0, #(1 << 0) // Non-secure EL1 orr x0, x0, #(1 << 8) // HVC enable @@ -143,10 +143,54 @@ ASM_FUNC(_start) ldr x0, =COUNTER_FREQ msr cntfrq_el0, x0 + cpuid x0, x1 + bl find_logical_id + cmp x0, #MPIDR_INVALID + b.eq err_invalid_id + bl setup_stack + bl gic_secure_init b start_el3 + /* + * EL2 initialization + */ +reset_at_el2: + // Ensure E2H is not in use + mov_64 x0, HCR_EL2_RESET + msr hcr_el2, x0 + isb + + mov_64 x0, SCTLR_EL2_RESET + msr sctlr_el2, x0 + isb + + b reset_no_el3 + + /* + * EL1 initialization + */ +reset_at_el1: + mov_64 x0, SCTLR_EL1_RESET + msr sctlr_el1, x0 + isb + + b reset_no_el3 + +reset_no_el3: + cpuid x0, x1 + bl find_logical_id + cmp x0, #MPIDR_INVALID + b.eq err_invalid_id + bl setup_stack + + mov w0, #1 + ldr x1, =flag_no_el3 + str w0, [x1] + + b start_no_el3 + err_invalid_id: b . diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h index 341a545..0a4085b 100644 --- a/arch/aarch64/include/asm/cpu.h +++ b/arch/aarch64/include/asm/cpu.h @@ -14,6 +14,35 @@ #define MPIDR_ID_BITS 0xff00ffffff #define CURRENTEL_EL3 (3 << 2) +#define CURRENTEL_EL2 (2 << 2) +#define CURRENTEL_EL1 (1 << 2) + +/* + * RES1 bit definitions definitions as of ARM DDI 0487G.b + * + * These includes bits which are RES1 in some configurations. + */ +#define SCTLR_EL3_RES1 \ + (BIT(29) | BIT(28) | BIT(23) | BIT(22) | BIT(18) | BIT(16) | \ + BIT(11) | BIT(5) | BIT(4)) + +#define SCTLR_EL2_RES1 \ + (BIT(29) | BIT(28) | BIT(23) | BIT(22) | BIT(20) | BIT(18) | \ + BIT(16) | BIT(11) | BIT(5) | BIT(4)) + +#define SCTLR_EL1_RES1 \ + (BIT(29) | BIT(28) | BIT(23) | BIT(22) | BIT(20) | BIT(11) | \ + BIT(8) | BIT(7) | BIT(4)) + +#define HCR_EL2_RES1 (BIT(1)) + +/* + * Initial register values required for the boot-wrapper to run out-of-reset. + */ +#define SCTLR_EL3_RESET SCTLR_EL3_RES1 +#define SCTLR_EL2_RESET SCTLR_EL2_RES1 +#define SCTLR_EL1_RESET SCTLR_EL1_RES1 +#define HCR_EL2_RESET HCR_EL2_RES1 #define ID_AA64PFR0_EL1_GIC BITS(27, 24) @@ -43,7 +72,6 @@ #define ZCR_EL3_LEN_MAX 0xf #define SCTLR_EL1_CP15BEN (1 << 5) -#define SCTLR_EL1_RES1 (3 << 28 | 3 << 22 | 1 << 11) #ifdef KERNEL_32 /* From patchwork Tue Jan 25 15:00:51 2022 Content-Type: text/plain; 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Tue, 25 Jan 2022 07:01:19 -0800 (PST) From: Mark Rutland To: linux-arm-kernel@lists.infradead.org Cc: andre.przywara@arm.com, broonie@kernel.org, jaxson.han@arm.com, mark.rutland@arm.com, robin.murphy@arm.com, vladimir.murzin@arm.com, wei.chen@arm.com Subject: [bootwrapper PATCH v3 09/15] Rework common init C code Date: Tue, 25 Jan 2022 15:00:51 +0000 Message-Id: <20220125150057.3936090-10-mark.rutland@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220125150057.3936090-1-mark.rutland@arm.com> References: <20220125150057.3936090-1-mark.rutland@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220125_070121_496471_CAE2A9E4 X-CRM114-Status: GOOD ( 19.93 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org In init_platform() we initialize a UART and announce the presence of the bootwrapper to the world. We do this relatively late in the boot-flow, and prior to this will silently ignore errors (e.g. in gic_secure_init). To make it possible to provide improved diagnostics, and to allow us to move more initialization into C, this patch reworks the init code to call a C function earlier, where we can announce the presence of the boot-wrapper and perform other initialization. In subsequent patches this will be expanded with more CPU initialization. Signed-off-by: Mark Rutland Reviewed-by: Andre Przywara --- Makefile.am | 2 +- arch/aarch32/boot.S | 5 +++++ arch/aarch64/boot.S | 4 ++++ common/boot.c | 4 ---- common/init.c | 24 ++++++++++++++++++++++++ common/platform.c | 12 +++++++----- include/platform.h | 17 +++++++++++++++++ 7 files changed, 58 insertions(+), 10 deletions(-) create mode 100644 common/init.c create mode 100644 include/platform.h diff --git a/Makefile.am b/Makefile.am index 5731a19..91a6a02 100644 --- a/Makefile.am +++ b/Makefile.am @@ -34,7 +34,7 @@ endif PSCI_CPU_OFF := 0x84000002 COMMON_SRC := common/ -COMMON_OBJ := boot.o bakery_lock.o platform.o lib.o +COMMON_OBJ := boot.o bakery_lock.o platform.o lib.o init.o ARCH_OBJ := boot.o stack.o utils.o diff --git a/arch/aarch32/boot.S b/arch/aarch32/boot.S index 00c432d..ee073ea 100644 --- a/arch/aarch32/boot.S +++ b/arch/aarch32/boot.S @@ -48,6 +48,9 @@ ASM_FUNC(_start) mov r0, #1 ldr r1, =flag_no_el3 str r0, [r1] + + bl cpu_init_bootwrapper + b start_no_el3 _switch_monitor: @@ -71,6 +74,8 @@ _monitor: ldr r0, =COUNTER_FREQ mcr p15, 0, r0, c14, c0, 0 @ CNTFRQ + bl cpu_init_bootwrapper + bl gic_secure_init /* Initialise boot method */ diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S index 204c199..7872daf 100644 --- a/arch/aarch64/boot.S +++ b/arch/aarch64/boot.S @@ -149,6 +149,8 @@ reset_at_el3: b.eq err_invalid_id bl setup_stack + bl cpu_init_bootwrapper + bl gic_secure_init b start_el3 @@ -189,6 +191,8 @@ reset_no_el3: ldr x1, =flag_no_el3 str w0, [x1] + bl cpu_init_bootwrapper + b start_no_el3 err_invalid_id: diff --git a/common/boot.c b/common/boot.c index c74d34c..29d53a4 100644 --- a/common/boot.c +++ b/common/boot.c @@ -12,8 +12,6 @@ extern unsigned long entrypoint; extern unsigned long dtb; -void init_platform(void); - void __noreturn jump_kernel(unsigned long address, unsigned long a0, unsigned long a1, @@ -62,8 +60,6 @@ void __noreturn first_spin(unsigned int cpu, unsigned long *mbox, unsigned long invalid) { if (cpu == 0) { - init_platform(); - *mbox = (unsigned long)&entrypoint; sevl(); spin(mbox, invalid, 1); diff --git a/common/init.c b/common/init.c new file mode 100644 index 0000000..9c471c9 --- /dev/null +++ b/common/init.c @@ -0,0 +1,24 @@ +/* + * init.c - common boot-wrapper initialization + * + * Copyright (C) 2021 ARM Limited. All rights reserved. + * + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE.txt file. + */ +#include +#include + +static void announce_bootwrapper(void) +{ + print_string("Boot-wrapper v0.2\r\n\r\n"); +} + +void cpu_init_bootwrapper(void) +{ + if (this_cpu_logical_id() == 0) { + init_uart(); + announce_bootwrapper(); + init_platform(); + } +} diff --git a/common/platform.c b/common/platform.c index d11f568..47bf547 100644 --- a/common/platform.c +++ b/common/platform.c @@ -1,5 +1,5 @@ /* - * platform.c - code to initialise everything required when first booting. + * platform.c - Platform initialization and I/O. * * Copyright (C) 2015 ARM Limited. All rights reserved. * @@ -7,6 +7,7 @@ * found in the LICENSE.txt file. */ +#include #include #include @@ -30,7 +31,7 @@ #define V2M_SYS(reg) ((void *)SYSREGS_BASE + V2M_SYS_##reg) #endif -static void print_string(const char *str) +void print_string(const char *str) { uint32_t flags; @@ -47,7 +48,7 @@ static void print_string(const char *str) } } -void init_platform(void) +void init_uart(void) { /* * UART initialisation (38400 8N1) @@ -58,9 +59,10 @@ void init_platform(void) raw_writel(0x70, PL011(UART_LCR_H)); /* Enable the UART, TXen and RXen */ raw_writel(0x301, PL011(UARTCR)); +} - print_string("Boot-wrapper v0.2\r\n\r\n"); - +void init_platform(void) +{ #ifdef SYSREGS_BASE /* * CLCD output site MB diff --git a/include/platform.h b/include/platform.h new file mode 100644 index 0000000..e5248e1 --- /dev/null +++ b/include/platform.h @@ -0,0 +1,17 @@ +/* + * include/platform.h - Platform initialization and I/O. + * + * Copyright (C) 2021 ARM Limited. All rights reserved. + * + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE.txt file. + */ +#ifndef __PLATFORM_H +#define __PLATFORM_H + +void print_string(const char *str); +void init_uart(void); + +void init_platform(void); + +#endif /* __PLATFORM_H */ From patchwork Tue Jan 25 15:00:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Rutland X-Patchwork-Id: 12723937 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 497A4C433EF for ; Tue, 25 Jan 2022 15:08:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=XxanBs7VSWKkQ8mUsNGb8WQ7PP0oEqwn58wIPmkEbzE=; b=nm7V72+jWHurAK mVBqyTwNSo3SnjyAduVP2YhtduReIJ8dTBfT8dPPspdVfqQLaNHeg2h3edIpk8W7rb2/gYvznfaTl 22TVh4bIeT+3TSXiAlKQ/VvPWfpORnzfB8Cuf9GgxZeppRjT8Wa96e5zGTPjgC7AyU/UwO7dMEZTf gVQeg00K/RonwYA5T8h5TKAdBw+eY8THZTx2zgCKW0X0aZvz+oUKpJiK0bkxL9uewB6pNNkygSmAs vgD53tzMZu8zYrp3OvqJIKvL5ygTip/USBpe/EzXwKUzplpS8lpciROkZuHmrwMXQGpVKndRQ71kQ mV5ZVrSvu6rXBAj0zlSw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nCNPX-008HAR-8y; Tue, 25 Jan 2022 15:07:07 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nCNJy-008EqA-PU for linux-arm-kernel@lists.infradead.org; Tue, 25 Jan 2022 15:01:24 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3E568D6E; Tue, 25 Jan 2022 07:01:22 -0800 (PST) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 220883F793; Tue, 25 Jan 2022 07:01:21 -0800 (PST) From: Mark Rutland To: linux-arm-kernel@lists.infradead.org Cc: andre.przywara@arm.com, broonie@kernel.org, jaxson.han@arm.com, mark.rutland@arm.com, robin.murphy@arm.com, vladimir.murzin@arm.com, wei.chen@arm.com Subject: [bootwrapper PATCH v3 10/15] Announce boot-wrapper mode / exception level Date: Tue, 25 Jan 2022 15:00:52 +0000 Message-Id: <20220125150057.3936090-11-mark.rutland@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220125150057.3936090-1-mark.rutland@arm.com> References: <20220125150057.3936090-1-mark.rutland@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220125_070122_957098_0369CC7D X-CRM114-Status: GOOD ( 19.01 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org When something goes wrong within the boot-wrapper, it can be very helpful to know where we started from. Add an arch_announce() function to log this early in the boot process. More information can be added here in future. This is logged ot the serial console as: | Boot-wrapper v0.2 | Entered at EL3 Signed-off-by: Mark Rutland Reviewed-by: Andre Przywara --- Makefile.am | 2 +- arch/aarch32/include/asm/cpu.h | 9 +++++++++ arch/aarch32/init.c | 29 +++++++++++++++++++++++++++++ arch/aarch64/init.c | 19 +++++++++++++++++++ common/init.c | 6 +++++- common/platform.c | 24 ++++++++++++++---------- include/platform.h | 1 + 7 files changed, 78 insertions(+), 12 deletions(-) create mode 100644 arch/aarch32/init.c create mode 100644 arch/aarch64/init.c diff --git a/Makefile.am b/Makefile.am index 91a6a02..5a0ebd2 100644 --- a/Makefile.am +++ b/Makefile.am @@ -36,7 +36,7 @@ PSCI_CPU_OFF := 0x84000002 COMMON_SRC := common/ COMMON_OBJ := boot.o bakery_lock.o platform.o lib.o init.o -ARCH_OBJ := boot.o stack.o utils.o +ARCH_OBJ := boot.o stack.o utils.o init.o if BOOTWRAPPER_32 CPPFLAGS += -DBOOTWRAPPER_32 diff --git a/arch/aarch32/include/asm/cpu.h b/arch/aarch32/include/asm/cpu.h index d691c7b..aa72204 100644 --- a/arch/aarch32/include/asm/cpu.h +++ b/arch/aarch32/include/asm/cpu.h @@ -44,6 +44,15 @@ #define sevl() asm volatile ("sev" : : : "memory") #endif +static inline unsigned long read_cpsr(void) +{ + unsigned long cpsr; + asm volatile ("mrs %0, cpsr\n" : "=r" (cpsr)); + return cpsr; +} + +#define read_cpsr_mode() (read_cpsr() & PSR_MODE_MASK) + #define MPIDR "p15, 0, %0, c0, c0, 5" #define ID_PFR1 "p15, 0, %0, c0, c1, 1" #define ICIALLU "p15, 0, %0, c7, c5, 0" diff --git a/arch/aarch32/init.c b/arch/aarch32/init.c new file mode 100644 index 0000000..785a428 --- /dev/null +++ b/arch/aarch32/init.c @@ -0,0 +1,29 @@ +/* + * init.c - common boot-wrapper initialization + * + * Copyright (C) 2021 ARM Limited. All rights reserved. + * + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE.txt file. + */ +#include +#include + +static const char *mode_string(void) +{ + switch (read_cpsr_mode()) { + case PSR_MON: + return "PL1"; + case PSR_HYP: + return "PL2 (Non-secure)"; + default: + return ""; + } +} + +void announce_arch(void) +{ + print_string("Entered at "); + print_string(mode_string()); + print_string("\r\n"); +} diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c new file mode 100644 index 0000000..82816e7 --- /dev/null +++ b/arch/aarch64/init.c @@ -0,0 +1,19 @@ +/* + * init.c - common boot-wrapper initialization + * + * Copyright (C) 2021 ARM Limited. All rights reserved. + * + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE.txt file. + */ +#include +#include + +void announce_arch(void) +{ + unsigned char el = mrs(CurrentEl) >> 2; + + print_string("Entered at EL"); + print_char('0' + el); + print_string("\r\n"); +} diff --git a/common/init.c b/common/init.c index 9c471c9..2600f73 100644 --- a/common/init.c +++ b/common/init.c @@ -11,14 +11,18 @@ static void announce_bootwrapper(void) { - print_string("Boot-wrapper v0.2\r\n\r\n"); + print_string("Boot-wrapper v0.2\r\n"); } +void announce_arch(void); + void cpu_init_bootwrapper(void) { if (this_cpu_logical_id() == 0) { init_uart(); announce_bootwrapper(); + announce_arch(); + print_string("\r\n"); init_platform(); } } diff --git a/common/platform.c b/common/platform.c index 47bf547..80d0562 100644 --- a/common/platform.c +++ b/common/platform.c @@ -31,21 +31,25 @@ #define V2M_SYS(reg) ((void *)SYSREGS_BASE + V2M_SYS_##reg) #endif -void print_string(const char *str) +void print_char(char c) { uint32_t flags; - while (*str) { - do - flags = raw_readl(PL011(UARTFR)); - while (flags & PL011_UARTFR_FIFO_FULL); + do { + flags = raw_readl(PL011(UARTFR)); + } while (flags & PL011_UARTFR_FIFO_FULL); + + raw_writel(c, PL011(UARTDR)); - raw_writel(*str++, PL011(UARTDR)); + do { + flags = raw_readl(PL011(UARTFR)); + } while (flags & PL011_UARTFR_BUSY); +} - do - flags = raw_readl(PL011(UARTFR)); - while (flags & PL011_UARTFR_BUSY); - } +void print_string(const char *str) +{ + while (*str) + print_char(*str++); } void init_uart(void) diff --git a/include/platform.h b/include/platform.h index e5248e1..237b481 100644 --- a/include/platform.h +++ b/include/platform.h @@ -9,6 +9,7 @@ #ifndef __PLATFORM_H #define __PLATFORM_H +void print_char(char c); void print_string(const char *str); void init_uart(void); From patchwork Tue Jan 25 15:00:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Rutland X-Patchwork-Id: 12723938 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6AA19C433EF for ; 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Tue, 25 Jan 2022 15:08:54 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nCNK0-008ErQ-FM for linux-arm-kernel@lists.infradead.org; Tue, 25 Jan 2022 15:01:26 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F35C1101E; Tue, 25 Jan 2022 07:01:23 -0800 (PST) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D87FF3F793; Tue, 25 Jan 2022 07:01:22 -0800 (PST) From: Mark Rutland To: linux-arm-kernel@lists.infradead.org Cc: andre.przywara@arm.com, broonie@kernel.org, jaxson.han@arm.com, mark.rutland@arm.com, robin.murphy@arm.com, vladimir.murzin@arm.com, wei.chen@arm.com Subject: [bootwrapper PATCH v3 11/15] aarch64: move the bulk of EL3 initialization to C Date: Tue, 25 Jan 2022 15:00:53 +0000 Message-Id: <20220125150057.3936090-12-mark.rutland@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220125150057.3936090-1-mark.rutland@arm.com> References: <20220125150057.3936090-1-mark.rutland@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220125_070124_642025_A94C0489 X-CRM114-Status: GOOD ( 12.94 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The majority of state that we initialize at EL3 is necessary for code at lower ELs to function, but isnt' necessary for the boot-wrapper itself. Given that, it would be better to write this in C where it can be written mode clearly, and where it will be possible to add logging/debug logic. This patch migrates the AArch64 EL3 initialization to C. There should be no functional change as a result of this patch. Signed-off-by: Mark Rutland Reviewed-by: Andre Przywara --- Makefile.am | 2 +- arch/aarch64/boot.S | 100 +-------------------------------- arch/aarch64/include/asm/cpu.h | 35 +++++++++++- arch/aarch64/init.c | 72 ++++++++++++++++++++++++ 4 files changed, 109 insertions(+), 100 deletions(-) diff --git a/Makefile.am b/Makefile.am index 5a0ebd2..a5e8e8b 100644 --- a/Makefile.am +++ b/Makefile.am @@ -155,7 +155,7 @@ $(COMMON_SRC): %.o: %.S Makefile | $(ARCH_SRC) $(CC) $(CPPFLAGS) -D__ASSEMBLY__ $(CFLAGS) $(DEFINES) -c -o $@ $< -%.o: %.c Makefile | $(COMMON_SRC) +%.o: %.c Makefile | $(ARCH_SRC) $(COMMON_SRC) $(CC) $(CPPFLAGS) $(CFLAGS) $(DEFINES) -c -o $@ $< model.lds: $(LD_SCRIPT) Makefile diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S index 7872daf..c0ec518 100644 --- a/arch/aarch64/boot.S +++ b/arch/aarch64/boot.S @@ -45,104 +45,6 @@ reset_at_el3: msr sctlr_el3, x0 isb - mov x0, #0x30 // RES1 - orr x0, x0, #(1 << 0) // Non-secure EL1 - orr x0, x0, #(1 << 8) // HVC enable - - /* Enable pointer authentication if present */ - mrs x1, id_aa64isar1_el1 - /* We check for APA+API and GPA+GPI */ - ldr x2, =((0xff << 24) | (0xff << 4)) - and x1, x1, x2 - cbz x1, 1f - - orr x0, x0, #(1 << 16) // AP key enable - orr x0, x0, #(1 << 17) // AP insn enable -1: - /* Enable TME if present */ - mrs x1, id_aa64isar0_el1 - ubfx x1, x1, #24, #4 - cbz x1, 1f - - orr x0, x0, #(1 << 34) // TME enable -1: - /* Enable FGT if present */ - mrs x1, id_aa64mmfr0_el1 - ubfx x1, x1, #56, #4 - cbz x1, 1f - - orr x0, x0, #(1 << 27) // FGT enable -1: - /* Enable ECV2 if present (allows CNTPOFF_EL2) */ - mrs x1, id_aa64mmfr0_el1 - ubfx x1, x1, #60, #4 - cmp x1, #2 - b.lt 1f - - orr x0, x0, #(1 << 28) // ECV enable -1: - /* Enable MTE if present */ - mrs x10, id_aa64pfr1_el1 - ubfx x10, x10, #8, #4 - cmp x10, #2 - b.lt 1f - - orr x0, x0, #(1 << 26) // ATA enable -1: -#ifndef KERNEL_32 - orr x0, x0, #(1 << 10) // 64-bit EL2 -#endif - msr scr_el3, x0 - - msr cptr_el3, xzr // Disable copro. traps to EL3 - - mov x0, xzr - mrs x1, id_aa64dfr0_el1 - ubfx x1, x1, #32, #4 - cbz x1, 1f - - // Enable SPE for the non-secure world. - orr x0, x0, #(0x3 << 12) - - // Do not trap PMSNEVFR_EL1 if present - cmp x1, #3 - b.lt 1f - orr x0, x0, #(1 << 36) - -1: mrs x1, id_aa64dfr0_el1 - ubfx x1, x1, #44, #4 - cbz x1, 1f - - // Enable TRBE for the non-secure world. - ldr x1, =(0x3 << 24) - orr x0, x0, x1 - -1: mrs x1, id_aa64dfr0_el1 - ubfx x1, x1, #52, #4 - cbz x1, 1f - - // Enable BRBE for the non-secure world. - ldr x1, =(0x3 << 32) - orr x0, x0, x1 - -1: msr mdcr_el3, x0 // Disable traps to EL3 - - mrs x0, id_aa64pfr0_el1 - ubfx x0, x0, #32, #4 // SVE present? - cbz x0, 1f // Skip SVE init if not - - mrs x0, cptr_el3 - orr x0, x0, #CPTR_EL3_EZ // enable SVE - msr cptr_el3, x0 - isb - - mov x0, #ZCR_EL3_LEN_MAX // SVE: Enable full vector len - msr ZCR_EL3, x0 // for EL2. - -1: - ldr x0, =COUNTER_FREQ - msr cntfrq_el0, x0 - cpuid x0, x1 bl find_logical_id cmp x0, #MPIDR_INVALID @@ -151,6 +53,8 @@ reset_at_el3: bl cpu_init_bootwrapper + bl cpu_init_el3 + bl gic_secure_init b start_el3 diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h index 0a4085b..1be2d54 100644 --- a/arch/aarch64/include/asm/cpu.h +++ b/arch/aarch64/include/asm/cpu.h @@ -34,7 +34,40 @@ (BIT(29) | BIT(28) | BIT(23) | BIT(22) | BIT(20) | BIT(11) | \ BIT(8) | BIT(7) | BIT(4)) -#define HCR_EL2_RES1 (BIT(1)) +#define MDCR_EL3_NSPB_NS_NOTRAP (UL(3) << 12) +#define MDCR_EL3_NSTB_NS_NOTRAP (UL(3) << 24) +#define MDCR_EL3_SBRBE_NOTRAP_NOPROHIBIT (UL(3) << 32) +#define MDCR_EL3_ENPMSN BIT(36) + +#define SCR_EL3_RES1 BITS(5, 4) +#define SCR_EL3_NS BIT(0) +#define SCR_EL3_HCE BIT(8) +#define SCR_EL3_RW BIT(10) +#define SCR_EL3_APK BIT(16) +#define SCR_EL3_API BIT(17) +#define SCR_EL3_ATA BIT(26) +#define SCR_EL3_FGTEN BIT(27) +#define SCR_EL3_ECVEN BIT(28) +#define SCR_EL3_TME BIT(34) + +#define HCR_EL2_RES1 BIT(1) + +#define ID_AA64DFR0_EL1_PMSVER BITS(35, 32) +#define ID_AA64DFR0_EL1_TRACEBUFFER BITS(47, 44) +#define ID_AA64DFR0_EL1_BRBE BITS(55, 52) + +#define ID_AA64ISAR0_EL1_TME BITS(27, 24) + +#define ID_AA64ISAR1_EL1_APA BITS(7, 4) +#define ID_AA64ISAR1_EL1_API BITS(11, 8) +#define ID_AA64ISAR1_EL1_GPA BITS(27, 24) +#define ID_AA64ISAR1_EL1_GPI BITS(31, 28) + +#define ID_AA64MMFR0_EL1_FGT BITS(59, 56) +#define ID_AA64MMFR0_EL1_ECV BITS(63, 60) + +#define ID_AA64PFR1_EL1_MTE BITS(11, 8) +#define ID_AA64PFR0_EL1_SVE BITS(35, 32) /* * Initial register values required for the boot-wrapper to run out-of-reset. diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c index 82816e7..74190be 100644 --- a/arch/aarch64/init.c +++ b/arch/aarch64/init.c @@ -8,6 +8,7 @@ */ #include #include +#include void announce_arch(void) { @@ -17,3 +18,74 @@ void announce_arch(void) print_char('0' + el); print_string("\r\n"); } + +static inline bool kernel_is_32bit(void) +{ +#ifdef KERNEL_32 + return true; +#else + return false; +#endif +} + +static inline bool cpu_has_pauth(void) +{ + const unsigned long id_pauth = ID_AA64ISAR1_EL1_APA | + ID_AA64ISAR1_EL1_API | + ID_AA64ISAR1_EL1_GPA | + ID_AA64ISAR1_EL1_GPI; + + return mrs(ID_AA64ISAR1_EL1) & id_pauth; +} + +void cpu_init_el3(void) +{ + unsigned long scr = SCR_EL3_RES1 | SCR_EL3_NS | SCR_EL3_HCE; + unsigned long mdcr = 0; + unsigned long cptr = 0; + + if (cpu_has_pauth()) + scr |= SCR_EL3_APK | SCR_EL3_API; + + if (mrs_field(ID_AA64ISAR0_EL1, TME)) + scr |= SCR_EL3_TME; + + if (mrs_field(ID_AA64MMFR0_EL1, FGT)) + scr |= SCR_EL3_FGTEN; + + if (mrs_field(ID_AA64MMFR0_EL1, ECV) >= 2) + scr |= SCR_EL3_ECVEN; + + if (mrs_field(ID_AA64PFR1_EL1, MTE) >= 2) + scr |= SCR_EL3_ATA; + + if (!kernel_is_32bit()) + scr |= SCR_EL3_RW; + + msr(SCR_EL3, scr); + + msr(CPTR_EL3, cptr); + + if (mrs_field(ID_AA64DFR0_EL1, PMSVER)) + mdcr |= MDCR_EL3_NSPB_NS_NOTRAP; + + if (mrs_field(ID_AA64DFR0_EL1, PMSVER) >= 3) + mdcr |= MDCR_EL3_ENPMSN; + + if (mrs_field(ID_AA64DFR0_EL1, TRACEBUFFER)) + mdcr |= MDCR_EL3_NSTB_NS_NOTRAP; + + if (mrs_field(ID_AA64DFR0_EL1, BRBE)) + mdcr |= MDCR_EL3_SBRBE_NOTRAP_NOPROHIBIT; + + msr(MDCR_EL3, mdcr); + + if (mrs_field(ID_AA64PFR0_EL1, SVE)) { + cptr |= CPTR_EL3_EZ; + msr(CPTR_EL3, cptr); + isb(); + msr(ZCR_EL3, ZCR_EL3_LEN_MAX); + } + + msr(CNTFRQ_EL0, COUNTER_FREQ); +} From patchwork Tue Jan 25 15:00:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Rutland X-Patchwork-Id: 12723939 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6272CC433F5 for ; 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Tue, 25 Jan 2022 15:09:43 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nCNK1-008EqA-Ut for linux-arm-kernel@lists.infradead.org; Tue, 25 Jan 2022 15:01:27 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A47EFD6E; Tue, 25 Jan 2022 07:01:25 -0800 (PST) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 8A0273F793; Tue, 25 Jan 2022 07:01:24 -0800 (PST) From: Mark Rutland To: linux-arm-kernel@lists.infradead.org Cc: andre.przywara@arm.com, broonie@kernel.org, jaxson.han@arm.com, mark.rutland@arm.com, robin.murphy@arm.com, vladimir.murzin@arm.com, wei.chen@arm.com Subject: [bootwrapper PATCH v3 12/15] aarch32: move the bulk of Secure PL1 initialization to C Date: Tue, 25 Jan 2022 15:00:54 +0000 Message-Id: <20220125150057.3936090-13-mark.rutland@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220125150057.3936090-1-mark.rutland@arm.com> References: <20220125150057.3936090-1-mark.rutland@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220125_070126_079608_CB665418 X-CRM114-Status: UNSURE ( 9.14 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The majority of state that we initialize at Secure PL1 is necessary for code at lower PLs to function, but isnt' necessary for the boot-wrapper itself. Given that, it would be better to write this in C where it can be written mode clearly, and where it will be possible to add logging/debug logic. This patch migrates the AArch32 Secure PL1 initialization to C. There should be no functional change as a result of this patch. Signed-off-by: Mark Rutland Reviewed-by: Andre Przywara --- arch/aarch32/boot.S | 11 +---------- arch/aarch32/include/asm/cpu.h | 9 +++++++++ arch/aarch32/init.c | 12 ++++++++++++ 3 files changed, 22 insertions(+), 10 deletions(-) diff --git a/arch/aarch32/boot.S b/arch/aarch32/boot.S index ee073ea..820957b 100644 --- a/arch/aarch32/boot.S +++ b/arch/aarch32/boot.S @@ -63,16 +63,7 @@ _monitor: /* Move the stack to Monitor mode*/ mrs sp, sp_svc - /* Setup secure registers and devices */ - mov r0, #1 @ Non-secure lower level - orr r0, #(1 << 8) @ HVC enable - mcr p15, 0, r0, c1, c1, 0 @ SCR - - mov r0, #(1 << 10 | 1 << 11) @ Enable NS access to CPACR - mcr p15, 0, r0, c1, c1, 2 @ NSACR - - ldr r0, =COUNTER_FREQ - mcr p15, 0, r0, c14, c0, 0 @ CNTFRQ + bl cpu_init_secure_pl1 bl cpu_init_bootwrapper diff --git a/arch/aarch32/include/asm/cpu.h b/arch/aarch32/include/asm/cpu.h index aa72204..c1bce9a 100644 --- a/arch/aarch32/include/asm/cpu.h +++ b/arch/aarch32/include/asm/cpu.h @@ -30,6 +30,11 @@ #define PSR_I (1 << 7) #define PSR_A (1 << 8) +#define SCR_NS BIT(0) +#define SCR_HCE BIT(8) + +#define NSACR_CP10 BIT(10) +#define NSACR_CP11 BIT(11) #define SPSR_KERNEL (PSR_A | PSR_I | PSR_F | PSR_HYP) @@ -55,11 +60,15 @@ static inline unsigned long read_cpsr(void) #define MPIDR "p15, 0, %0, c0, c0, 5" #define ID_PFR1 "p15, 0, %0, c0, c1, 1" +#define SCR "p15, 0, %0, c1, c1, 0" +#define NSACR "p15, 0, %0, c1, c1, 2" #define ICIALLU "p15, 0, %0, c7, c5, 0" #define ICC_SRE "p15, 6, %0, c12, c12, 5" #define ICC_CTLR "p15, 6, %0, c12, c12, 4" +#define CNTFRQ "p15, 0, %0, c14, c0, 0" + #define mrc(reg) \ ({ \ unsigned long __mrc_val; \ diff --git a/arch/aarch32/init.c b/arch/aarch32/init.c index 785a428..7143c66 100644 --- a/arch/aarch32/init.c +++ b/arch/aarch32/init.c @@ -27,3 +27,15 @@ void announce_arch(void) print_string(mode_string()); print_string("\r\n"); } + +void cpu_init_secure_pl1(void) +{ + unsigned long scr = SCR_NS | SCR_HCE; + unsigned long nsacr = NSACR_CP10 | NSACR_CP11; + + mcr(SCR, scr); + + mcr(NSACR, nsacr); + + mcr(CNTFRQ, COUNTER_FREQ); +} From patchwork Tue Jan 25 15:00:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Rutland X-Patchwork-Id: 12723940 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8CB89C433EF for ; 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Tue, 25 Jan 2022 15:11:20 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nCNK3-008ErQ-Oo for linux-arm-kernel@lists.infradead.org; Tue, 25 Jan 2022 15:01:29 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4C01D101E; Tue, 25 Jan 2022 07:01:27 -0800 (PST) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 3012A3F793; Tue, 25 Jan 2022 07:01:26 -0800 (PST) From: Mark Rutland To: linux-arm-kernel@lists.infradead.org Cc: andre.przywara@arm.com, broonie@kernel.org, jaxson.han@arm.com, mark.rutland@arm.com, robin.murphy@arm.com, vladimir.murzin@arm.com, wei.chen@arm.com Subject: [bootwrapper PATCH v3 13/15] Announce locations of memory objects Date: Tue, 25 Jan 2022 15:00:55 +0000 Message-Id: <20220125150057.3936090-14-mark.rutland@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220125150057.3936090-1-mark.rutland@arm.com> References: <20220125150057.3936090-1-mark.rutland@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220125_070127_934959_F1D76182 X-CRM114-Status: GOOD ( 13.16 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org To make it easier to debug boot failures, log the location of memory objects at boot time. This is logged to the serial console as: | Boot-wrapper v0.2 | Entered at EL3 | Memory layout: | [0000000080000000..0000000080001f90] => boot-wrapper | [000000008000fff8..0000000080010000] => mbox | [0000000080200000..00000000822af200] => kernel | [0000000088000000..0000000088002857] => dtb Signed-off-by: Mark Rutland Reviewed-by: Andre Przywara --- common/init.c | 27 +++++++++++++++++++++++++++ common/platform.c | 13 +++++++++++++ include/platform.h | 2 ++ model.lds.S | 20 ++++++++++++++------ 4 files changed, 56 insertions(+), 6 deletions(-) diff --git a/common/init.c b/common/init.c index 2600f73..fc74b9e 100644 --- a/common/init.c +++ b/common/init.c @@ -14,6 +14,32 @@ static void announce_bootwrapper(void) print_string("Boot-wrapper v0.2\r\n"); } +#define announce_object(object, desc) \ +do { \ + extern char object##__start[]; \ + extern char object##__end[]; \ + print_string("["); \ + print_ulong_hex((unsigned long)object##__start); \ + print_string(".."); \ + print_ulong_hex((unsigned long)object##__end); \ + print_string("] => " desc "\r\n"); \ +} while (0) + +static void announce_objects(void) +{ + print_string("Memory layout:\r\n"); + announce_object(text, "boot-wrapper"); + announce_object(mbox, "mbox"); + announce_object(kernel, "kernel"); +#ifdef XEN + announce_object(xen, "xen"); +#endif + announce_object(dtb, "dtb"); +#ifdef USE_INITRD + announce_object(filesystem, "initrd"); +#endif +} + void announce_arch(void); void cpu_init_bootwrapper(void) @@ -22,6 +48,7 @@ void cpu_init_bootwrapper(void) init_uart(); announce_bootwrapper(); announce_arch(); + announce_objects(); print_string("\r\n"); init_platform(); } diff --git a/common/platform.c b/common/platform.c index 80d0562..1607ee6 100644 --- a/common/platform.c +++ b/common/platform.c @@ -52,6 +52,19 @@ void print_string(const char *str) print_char(*str++); } +#define HEX_CHARS_PER_LONG (2 * sizeof(long)) +#define HEX_CHARS "0123456789abcdef" + +void print_ulong_hex(unsigned long val) +{ + int i; + + for (i = HEX_CHARS_PER_LONG - 1; i >= 0; i--) { + int v = (val >> (4 * i)) & 0xf; + print_char(HEX_CHARS[v]); + } +} + void init_uart(void) { /* diff --git a/include/platform.h b/include/platform.h index 237b481..c88e124 100644 --- a/include/platform.h +++ b/include/platform.h @@ -11,6 +11,8 @@ void print_char(char c); void print_string(const char *str); +void print_ulong_hex(unsigned long val); + void init_uart(void); void init_platform(void); diff --git a/model.lds.S b/model.lds.S index d4e7e13..dacaa25 100644 --- a/model.lds.S +++ b/model.lds.S @@ -35,46 +35,54 @@ SECTIONS * the boot section's *(.data) */ .kernel (PHYS_OFFSET + KERNEL_OFFSET): { - kernel = .; + kernel__start = .; KERNEL + kernel__end = .; } #ifdef XEN .xen (PHYS_OFFSET + XEN_OFFSET): { - xen = .; + xen__start = .; XEN + xen__end = .; } - entrypoint = xen; + entrypoint = xen__start; #else - entrypoint = kernel; + entrypoint = kernel__start; #endif .dtb (PHYS_OFFSET + FDT_OFFSET): { + dtb__start = .; dtb = .; ./fdt.dtb + dtb__end = .; } #ifdef USE_INITRD .filesystem (PHYS_OFFSET + FS_OFFSET): { - filesystem = .; + filesystem__start = .; FILESYSTEM - fs_size = . - filesystem; + filesystem__end = .; } #endif .boot PHYS_OFFSET: { + text__start = .; *(.init) *(.text*) *(.data* .rodata* .bss* COMMON) *(.vectors) *(.stack) PROVIDE(etext = .); + text__end = .; } .mbox (PHYS_OFFSET + MBOX_OFFSET): { + mbox__start = .; mbox = .; QUAD(0x0) + mbox__end = .; } ASSERT(etext <= (PHYS_OFFSET + TEXT_LIMIT), ".text overflow!") From patchwork Tue Jan 25 15:00:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Rutland X-Patchwork-Id: 12723941 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A7BEFC433EF for ; Tue, 25 Jan 2022 15:13:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=KGpJcEIXouyzYhC/6e+aLpWaOjNNvYnHLGJM4jhAl9w=; b=e64R3wawSlqhjC NKX8oKeH2QSe+Q9Ve42Wzf0/ofSTInMKAgyEn3E8fAt+NGZek3rJGPVj/wCTLJuX2dJbUxMxfDcWY cpKrHxCu4gxRsGmCEa3EffuS/q0ZyAem2iZpvfIn/oYMRjdYiHur2wS80e7Akulm/KDnw8yLm5Cu6 Vkc3FzRs1t7RJDcZd8j+Ov5MbOjUntKfakBX3qmRCllP7EslwLJarub3MB53r4lS9ZpdoHsgjB1/o 1Y3Fx0Enbt1haLLVhYxZsA1QEzBDmdBzcAcY3t179YsEIkFoMSvy9YmCWMno0JL83pfELZfd2V3GK vQDAW+W7sVUKd0VMePkg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nCNUU-008Izf-EG; Tue, 25 Jan 2022 15:12:15 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nCNK5-008Ev1-LE for linux-arm-kernel@lists.infradead.org; Tue, 25 Jan 2022 15:01:31 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0F489D6E; Tue, 25 Jan 2022 07:01:29 -0800 (PST) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id E690D3F793; Tue, 25 Jan 2022 07:01:27 -0800 (PST) From: Mark Rutland To: linux-arm-kernel@lists.infradead.org Cc: andre.przywara@arm.com, broonie@kernel.org, jaxson.han@arm.com, mark.rutland@arm.com, robin.murphy@arm.com, vladimir.murzin@arm.com, wei.chen@arm.com Subject: [bootwrapper PATCH v3 14/15] Rework bootmethod initialization Date: Tue, 25 Jan 2022 15:00:56 +0000 Message-Id: <20220125150057.3936090-15-mark.rutland@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220125150057.3936090-1-mark.rutland@arm.com> References: <20220125150057.3936090-1-mark.rutland@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220125_070129_829128_50EF8522 X-CRM114-Status: GOOD ( 17.90 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org We currently initialize the bootmethod late, in assembly code. This requires us to maintain the el3/no_el3 distintion late into the boot process, and means we cannot produce any helpful diagnostic when booted at an unexpected exception level. Rework things so that we initialize the bootmethod early, with a warning when things are wrong. The el3/no_el3 distinction is now irrelevant to the bootmethod code, and can be removed in subsequent patches. When a boot-wrapper configured for PSCI is entered at EL2, a warning is looged to the serial console as: | Boot-wrapper v0.2 | Entered at EL2 | Memory layout: | [0000000080000000..0000000080001f90] => boot-wrapper | [000000008000fff8..0000000080010000] => mbox | [0000000080200000..00000000822af200] => kernel | [0000000088000000..0000000088002857] => dtb | | WARNING: PSCI could not be initialized. Boot may fail Signed-off-by: Mark Rutland Reviewed-by: Andre Przywara --- Makefile.am | 1 + arch/aarch32/include/asm/cpu.h | 1 + arch/aarch32/init.c | 16 ++++++++++++++++ arch/aarch32/psci.S | 8 +------- arch/aarch32/utils.S | 9 --------- arch/aarch64/init.c | 15 +++++++++++++++ arch/aarch64/psci.S | 21 ++------------------- arch/aarch64/spin.S | 3 +++ arch/aarch64/utils.S | 9 --------- common/init.c | 7 ++++++- common/psci.c | 20 +++++++++++++++++--- include/boot.h | 7 +++++++ 12 files changed, 69 insertions(+), 48 deletions(-) diff --git a/Makefile.am b/Makefile.am index a5e8e8b..40bc5d6 100644 --- a/Makefile.am +++ b/Makefile.am @@ -48,6 +48,7 @@ ARCH_SRC := arch/aarch64/ endif if PSCI +DEFINES += -DPSCI ARCH_OBJ += psci.o COMMON_OBJ += psci.o PSCI_NODE := psci { \ diff --git a/arch/aarch32/include/asm/cpu.h b/arch/aarch32/include/asm/cpu.h index c1bce9a..3426075 100644 --- a/arch/aarch32/include/asm/cpu.h +++ b/arch/aarch32/include/asm/cpu.h @@ -63,6 +63,7 @@ static inline unsigned long read_cpsr(void) #define SCR "p15, 0, %0, c1, c1, 0" #define NSACR "p15, 0, %0, c1, c1, 2" #define ICIALLU "p15, 0, %0, c7, c5, 0" +#define MVBAR "p15, 0, %0, c12, c0, 1" #define ICC_SRE "p15, 6, %0, c12, c12, 5" #define ICC_CTLR "p15, 6, %0, c12, c12, 4" diff --git a/arch/aarch32/init.c b/arch/aarch32/init.c index 7143c66..e25f0c7 100644 --- a/arch/aarch32/init.c +++ b/arch/aarch32/init.c @@ -8,6 +8,7 @@ */ #include #include +#include static const char *mode_string(void) { @@ -39,3 +40,18 @@ void cpu_init_secure_pl1(void) mcr(CNTFRQ, COUNTER_FREQ); } + +#ifdef PSCI +extern char psci_vectors[]; + +bool cpu_init_psci_arch(void) +{ + if (read_cpsr_mode() != PSR_MON) + return false; + + mcr(MVBAR, (unsigned long)psci_vectors); + isb(); + + return true; +} +#endif diff --git a/arch/aarch32/psci.S b/arch/aarch32/psci.S index e0d2972..cdc36b0 100644 --- a/arch/aarch32/psci.S +++ b/arch/aarch32/psci.S @@ -15,7 +15,7 @@ .section .vectors .align 6 -smc_vectors: +ASM_DATA(psci_vectors) b err_exception @ Reset b err_exception @ Undef b handle_smc @ SMC @@ -39,11 +39,5 @@ handle_smc: movs pc, lr ASM_FUNC(start_el3) - ldr r0, =smc_vectors - blx setup_vector - /* pass through */ - ASM_FUNC(start_no_el3) - cpuid r0, r1 - blx find_logical_id b psci_first_spin diff --git a/arch/aarch32/utils.S b/arch/aarch32/utils.S index 5809f48..58279aa 100644 --- a/arch/aarch32/utils.S +++ b/arch/aarch32/utils.S @@ -35,12 +35,3 @@ ASM_FUNC(find_logical_id) bx lr 3: mov r0, #MPIDR_INVALID bx lr - -/* - * Setup EL3 vectors. - * r0: vector address - */ -ASM_FUNC(setup_vector) - mcr p15, 0, r0, c12, c0, 1 @ MVBAR - isb - bx lr diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c index 74190be..6677f2b 100644 --- a/arch/aarch64/init.c +++ b/arch/aarch64/init.c @@ -89,3 +89,18 @@ void cpu_init_el3(void) msr(CNTFRQ_EL0, COUNTER_FREQ); } + +#ifdef PSCI +extern char psci_vectors[]; + +bool cpu_init_psci_arch(void) +{ + if (mrs(CurrentEL) != CURRENTEL_EL3) + return false; + + msr(VBAR_EL3, (unsigned long)psci_vectors); + isb(); + + return true; +} +#endif diff --git a/arch/aarch64/psci.S b/arch/aarch64/psci.S index 8bd224b..d6ca2eb 100644 --- a/arch/aarch64/psci.S +++ b/arch/aarch64/psci.S @@ -19,7 +19,7 @@ .section .vectors, "w" .align 11 -vector: +ASM_DATA(psci_vectors) // current EL, SP_EL0 ventry err_exception // synchronous ventry err_exception // IRQ @@ -80,22 +80,5 @@ smc_exit: eret ASM_FUNC(start_el3) - ldr x0, =vector - bl setup_vector - - /* only boot the primary cpu (entry 0 in the table) */ - cpuid x0, x1 - bl find_logical_id - b psci_first_spin - -/* - * This PSCI implementation requires EL3. Without EL3 we'll only boot the - * primary cpu, all others will be trapped in an infinite loop. - */ ASM_FUNC(start_no_el3) - cpuid x0, x1 - bl find_logical_id - cbz x0, psci_first_spin -spin_dead: - wfe - b spin_dead + b psci_first_spin diff --git a/arch/aarch64/spin.S b/arch/aarch64/spin.S index 1ea1c0b..764c532 100644 --- a/arch/aarch64/spin.S +++ b/arch/aarch64/spin.S @@ -12,6 +12,9 @@ .text +ASM_FUNC(cpu_init_bootmethod) + ret + ASM_FUNC(start_el3) ASM_FUNC(start_no_el3) cpuid x0, x1 diff --git a/arch/aarch64/utils.S b/arch/aarch64/utils.S index 85c7f8a..32393cc 100644 --- a/arch/aarch64/utils.S +++ b/arch/aarch64/utils.S @@ -32,12 +32,3 @@ ASM_FUNC(find_logical_id) ret 3: mov x0, #MPIDR_INVALID ret - -/* - * Setup EL3 vectors - * x0: vector address - */ -ASM_FUNC(setup_vector) - msr VBAR_EL3, x0 - isb - ret diff --git a/common/init.c b/common/init.c index fc74b9e..3c05ac3 100644 --- a/common/init.c +++ b/common/init.c @@ -6,6 +6,7 @@ * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE.txt file. */ +#include #include #include @@ -44,7 +45,9 @@ void announce_arch(void); void cpu_init_bootwrapper(void) { - if (this_cpu_logical_id() == 0) { + unsigned int cpu = this_cpu_logical_id(); + + if (cpu == 0) { init_uart(); announce_bootwrapper(); announce_arch(); @@ -52,4 +55,6 @@ void cpu_init_bootwrapper(void) print_string("\r\n"); init_platform(); } + + cpu_init_bootmethod(cpu); } diff --git a/common/psci.c b/common/psci.c index a0e8700..5ae4255 100644 --- a/common/psci.c +++ b/common/psci.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #ifndef CPU_IDS @@ -78,12 +79,25 @@ long psci_call(unsigned long fid, unsigned long arg1, unsigned long arg2) } } -void __noreturn psci_first_spin(unsigned int cpu) +void __noreturn psci_first_spin(void) { - if (cpu == MPIDR_INVALID) - while (1); + unsigned int cpu = this_cpu_logical_id(); first_spin(cpu, branch_table + cpu, PSCI_ADDR_INVALID); unreachable(); } + +void cpu_init_bootmethod(unsigned int cpu) +{ + if (cpu_init_psci_arch()) + return; + + if (cpu == 0) { + print_string("WARNING: PSCI could not be initialized. Boot may fail\r\n\r\n"); + return; + } + + while (1) + wfe(); +} diff --git a/include/boot.h b/include/boot.h index d75e013..459d1d5 100644 --- a/include/boot.h +++ b/include/boot.h @@ -10,10 +10,17 @@ #define __BOOT_H #include +#include void __noreturn spin(unsigned long *mbox, unsigned long invalid, int is_entry); void __noreturn first_spin(unsigned int cpu, unsigned long *mbox, unsigned long invalid_addr); +void cpu_init_bootmethod(unsigned int cpu); + +#ifdef PSCI +bool cpu_init_psci_arch(void); +#endif + #endif From patchwork Tue Jan 25 15:00:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Rutland X-Patchwork-Id: 12723942 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D30C9C433F5 for ; Tue, 25 Jan 2022 15:15:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=g5h+2me8MUqDv9EHPCV3/knn/Ank1QH4ZQaVDQ1utDE=; b=YPIPIsfuW68/QB qlTGAuNpQFLgHjVzsoLFHouHk41FuXx31VPpyelcdxxnNeUyD3zF08nDj8WNZcJFd2futKa/YLhEW MW+G99u74iPpAKt035sZtpWy1EMZiq8fqzC1Ae5Ont3kCKc+L5p17/Is3+06QZEYIhoLsbz/AHt1V 79u7fcH/teDg+kKjYQ/LsRq+Kw/zHzSwCd4K4BFhmB+XUhVGLK6NxXC2CNXhydBcTiygMSn0raBQV XqAYh4PBc62dSQIFNDlGvHSMO7D72sjs2Mdppg3xFeAvjaeeTW4tCV7ziLSUnEk7rGizw0QLxuM65 atl5o11+bNSbEMZyVqMg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nCNVi-008JRJ-QC; Tue, 25 Jan 2022 15:13:31 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nCNK7-008EvX-CA for linux-arm-kernel@lists.infradead.org; Tue, 25 Jan 2022 15:01:32 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C35F0101E; Tue, 25 Jan 2022 07:01:30 -0800 (PST) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A84B23F793; Tue, 25 Jan 2022 07:01:29 -0800 (PST) From: Mark Rutland To: linux-arm-kernel@lists.infradead.org Cc: andre.przywara@arm.com, broonie@kernel.org, jaxson.han@arm.com, mark.rutland@arm.com, robin.murphy@arm.com, vladimir.murzin@arm.com, wei.chen@arm.com Subject: [bootwrapper PATCH v3 15/15] Unify start_el3 & start_no_el3 Date: Tue, 25 Jan 2022 15:00:57 +0000 Message-Id: <20220125150057.3936090-16-mark.rutland@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220125150057.3936090-1-mark.rutland@arm.com> References: <20220125150057.3936090-1-mark.rutland@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220125_070131_488683_B2D608C3 X-CRM114-Status: UNSURE ( 8.84 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Now that the start_el3 and start_no_el3 labels point at the same place, unify them into a start_bootmethod label and update callers. There should be no functional change as a result of this patch. Signed-off-by: Mark Rutland Reviewed-by: Andre Przywara --- arch/aarch32/boot.S | 5 ++--- arch/aarch32/psci.S | 3 +-- arch/aarch64/boot.S | 4 ++-- arch/aarch64/psci.S | 3 +-- arch/aarch64/spin.S | 3 +-- 5 files changed, 7 insertions(+), 11 deletions(-) diff --git a/arch/aarch32/boot.S b/arch/aarch32/boot.S index 820957b..4d16c9c 100644 --- a/arch/aarch32/boot.S +++ b/arch/aarch32/boot.S @@ -51,7 +51,7 @@ ASM_FUNC(_start) bl cpu_init_bootwrapper - b start_no_el3 + b start_bootmethod _switch_monitor: adr lr, _monitor @@ -69,8 +69,7 @@ _monitor: bl gic_secure_init - /* Initialise boot method */ - b start_el3 + b start_bootmethod err_invalid_id: b . diff --git a/arch/aarch32/psci.S b/arch/aarch32/psci.S index cdc36b0..6613b6f 100644 --- a/arch/aarch32/psci.S +++ b/arch/aarch32/psci.S @@ -38,6 +38,5 @@ handle_smc: pop {r4 - r12, lr} movs pc, lr -ASM_FUNC(start_el3) -ASM_FUNC(start_no_el3) +ASM_FUNC(start_bootmethod) b psci_first_spin diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S index c0ec518..da5fa65 100644 --- a/arch/aarch64/boot.S +++ b/arch/aarch64/boot.S @@ -57,7 +57,7 @@ reset_at_el3: bl gic_secure_init - b start_el3 + b start_bootmethod /* * EL2 initialization @@ -97,7 +97,7 @@ reset_no_el3: bl cpu_init_bootwrapper - b start_no_el3 + b start_bootmethod err_invalid_id: b . diff --git a/arch/aarch64/psci.S b/arch/aarch64/psci.S index d6ca2eb..9709dbb 100644 --- a/arch/aarch64/psci.S +++ b/arch/aarch64/psci.S @@ -79,6 +79,5 @@ smc_exit: ldp x18, x19, [sp], #16 eret -ASM_FUNC(start_el3) -ASM_FUNC(start_no_el3) +ASM_FUNC(start_bootmethod) b psci_first_spin diff --git a/arch/aarch64/spin.S b/arch/aarch64/spin.S index 764c532..375f732 100644 --- a/arch/aarch64/spin.S +++ b/arch/aarch64/spin.S @@ -15,8 +15,7 @@ ASM_FUNC(cpu_init_bootmethod) ret -ASM_FUNC(start_el3) -ASM_FUNC(start_no_el3) +ASM_FUNC(start_bootmethod) cpuid x0, x1 bl find_logical_id