From patchwork Wed Jan 26 17:39:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Emil Renner Berthing X-Patchwork-Id: 12725531 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B92E6C63682 for ; Wed, 26 Jan 2022 17:40:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243847AbiAZRkZ (ORCPT ); Wed, 26 Jan 2022 12:40:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47566 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242787AbiAZRkY (ORCPT ); Wed, 26 Jan 2022 12:40:24 -0500 Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [IPv6:2a00:1450:4864:20::332]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 883F7C06173B; Wed, 26 Jan 2022 09:40:24 -0800 (PST) Received: by mail-wm1-x332.google.com with SMTP id r126so207709wma.0; Wed, 26 Jan 2022 09:40:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5oRlbCcuicawzmgkV2o23hXqFPfzRu0vAZKHNtEWHR4=; b=Um3pXARJ4BeIUASj5MVYQFWIDYheSA0/iyk2kg6Ald8PuvizCvYXjWH9ueH8Lr3wAp bJQVHuA50D4XcAH5yCPoLIIi+DfaGC6PNrfjvOPPunfrQE1XInz/cTfB1840hs6MIOy/ /IcLzE+vfKbKQewLcT9U63WfFujfd+XPkJ5w1R0BKSJx+QI1a3dBc47TSpvc1a2shg7X L2gqR2E2KY8WRizNQiOvhdkm8zjL9KDfNuIvnwvyw/YFDn9tT6djVJdgWQjUdwgGlAIo m7z9RFFBnnJwFKx+T5xvEUlRq1HskkDrYzQscHC9/YUNNYY2GR24e3jkAWhtUtrfcswO 23kQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=5oRlbCcuicawzmgkV2o23hXqFPfzRu0vAZKHNtEWHR4=; b=ODs+NrmmY18EMnWc71YzD4Y6nPem8koXrCUHCp9UOciMk3UwORhtljjE4tfEtNMACI 22dG1eapDfExHScbYSqEVH3SI4lIDOI2q0PiSaXBd5S7JIxOjE9jZreMfFbBHL380lm9 H4MyGAscaVg3S43KMeoIHTcg0i0OaABGbmKCj72tVB3TRruH4bBo/ZQyBXpH0pD+X7fH snYJKTbH7RyX6gyhzEvQLEgxA6SHxCQLm6ktQBr2OdZbZvLyYJsFHwJlzdnMK8GyjxAU Oz7YXi1cuaTVB1xf5yhiNxaeD5ty0VqQo63YM8kJEnx1CJ2H3X2m4SefSOE9hE+IdyKC HtbA== X-Gm-Message-State: AOAM532n7KKGr/lgCHksYRS64T+8XF6KK9rXysE472hiaNx273tPTVvG 6eoBELSjTqIivEupJSkFMUyMe3m3pF8= X-Google-Smtp-Source: ABdhPJxG3a1trYRqQTea9U6xrUaHjElX/WeUanUrRG26TBzTxOSpOMv1rNIeYdZS5FOCJid/XpXsAA== X-Received: by 2002:a05:600c:5107:: with SMTP id o7mr8463573wms.161.1643218823040; Wed, 26 Jan 2022 09:40:23 -0800 (PST) Received: from stitch.. (80.71.140.73.ipv4.parknet.dk. [80.71.140.73]) by smtp.gmail.com with ESMTPSA id y2sm3498451wmj.13.2022.01.26.09.40.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jan 2022 09:40:22 -0800 (PST) Sender: Emil Renner Berthing From: Emil Renner Berthing To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: Emil Renner Berthing , Michael Turquette , Stephen Boyd , Rob Herring , Andy Shevchenko , Geert Uytterhoeven , Arnd Bergmann , Michael Zhu , Fu Wei , linux-kernel@vger.kernel.org Subject: [PATCH v1 1/7] clk: starfive: jh7100: Don't round divisor up twice Date: Wed, 26 Jan 2022 18:39:47 +0100 Message-Id: <20220126173953.1016706-2-kernel@esmil.dk> X-Mailer: git-send-email 2.35.0 In-Reply-To: <20220126173953.1016706-1-kernel@esmil.dk> References: <20220126173953.1016706-1-kernel@esmil.dk> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The problem is best illustrated by an example. Suppose a consumer wants a 4MHz clock rate from a divider with a 10MHz parent. It would then call clk_round_rate(clk, 4000000) which would call into our determine_rate() callback that correctly rounds up and finds that a divisor of 3 gives the highest possible frequency below the requested 4MHz and returns 10000000 / 3 = 3333333Hz. However the consumer would then call clk_set_rate(clk, 3333333) but since 3333333 doesn't divide 10000000 evenly our set_rate() callback would again round the divisor up and set it to 4 which results in an unnecessarily low rate of 2.5MHz. Fix it by using DIV_ROUND_CLOSEST in the set_rate() callback. Fixes: 4210be668a09 ("clk: starfive: Add JH7100 clock generator driver") Signed-off-by: Emil Renner Berthing --- drivers/clk/starfive/clk-starfive-jh7100.c | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) diff --git a/drivers/clk/starfive/clk-starfive-jh7100.c b/drivers/clk/starfive/clk-starfive-jh7100.c index 25d31afa0f87..db6a4dc203af 100644 --- a/drivers/clk/starfive/clk-starfive-jh7100.c +++ b/drivers/clk/starfive/clk-starfive-jh7100.c @@ -399,22 +399,13 @@ static unsigned long jh7100_clk_recalc_rate(struct clk_hw *hw, return div ? parent_rate / div : 0; } -static unsigned long jh7100_clk_bestdiv(struct jh7100_clk *clk, - unsigned long rate, unsigned long parent) -{ - unsigned long max = clk->max_div; - unsigned long div = DIV_ROUND_UP(parent, rate); - - return min(div, max); -} - static int jh7100_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { struct jh7100_clk *clk = jh7100_clk_from(hw); unsigned long parent = req->best_parent_rate; unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate); - unsigned long div = jh7100_clk_bestdiv(clk, rate, parent); + unsigned long div = min_t(unsigned long, DIV_ROUND_UP(parent, rate), clk->max_div); unsigned long result = parent / div; /* @@ -442,7 +433,8 @@ static int jh7100_clk_set_rate(struct clk_hw *hw, unsigned long parent_rate) { struct jh7100_clk *clk = jh7100_clk_from(hw); - unsigned long div = jh7100_clk_bestdiv(clk, rate, parent_rate); + unsigned long div = clamp(DIV_ROUND_CLOSEST(parent_rate, rate), + 1UL, (unsigned long)clk->max_div); jh7100_clk_reg_rmw(clk, JH7100_CLK_DIV_MASK, div); return 0; From patchwork Wed Jan 26 17:39:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Emil Renner Berthing X-Patchwork-Id: 12725532 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2C36C63697 for ; Wed, 26 Jan 2022 17:40:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243858AbiAZRk0 (ORCPT ); Wed, 26 Jan 2022 12:40:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47574 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229998AbiAZRkZ (ORCPT ); Wed, 26 Jan 2022 12:40:25 -0500 Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 879F0C06161C; Wed, 26 Jan 2022 09:40:25 -0800 (PST) Received: by mail-wr1-x429.google.com with SMTP id e2so377294wra.2; Wed, 26 Jan 2022 09:40:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Tl4SIasnSRxHkt3WYvHnABfPkkQKhQcnDNKteJh15Ao=; b=caiVHLH9/PmiyKUBq68GYt0VH98DhsfO90VvOoCHXrO67R3OAv8RhgEkfCboaUpY73 SteZU7vgnznVW3ExBCTDwLWHwoC8uAIkC5AOCCdPP5hRXqTkLXjFkSeN8Xxm/uIzead/ v0QPKLCwtMOp0OJAPe0TUXoFepHLbw9XvDWAaMpWgm1JSXaME7TCJW2w3wa5kwzgea3k bBcU/SkXBIFVAgxUagLVQdNi2PF/QwxVIP8Izuw7H37rWBExRkwnftT5tbXNRaxos13e lwtk241sQdvWCq30sIXuophKtI5e33ZaDhyDqT5ovlr5YxbD+8lcEXpLx0fhfUheo01R uVHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Tl4SIasnSRxHkt3WYvHnABfPkkQKhQcnDNKteJh15Ao=; b=XPqYjcgDdEe3kc9jNW42iKdl3rbpURT/hbyq9N30XJLPvSo7bGl5gOwo+X7xlaegke n099hWtb/IaSrsAV90rOyYhJsvhGYh6O9yP6/1Ylzi4203uKFsv7MUuZ9mdVt7lOI8Xr y/QMqvQnHVW8gmw5uywFmJnAe19y2Q5ifaRqjHhQ+HQYCYemFi4dQ+o9UPgQ0IYdD+M8 kcGkDd1MIpV01wdZN5ZaeWMHfj6DMGCdj34xRkoaeK73MHpYaCI5bC14PJpt7JJBdgGB SCq6GxhGKcR4shaWxHmDODHiGaSp6ELS9fr1OGrGv4PRgtG9PXEdJd8DnZw3ZwF+960d L+pw== X-Gm-Message-State: AOAM5317HlBL93qEYU/RBnr41UMciEA56uaxe+MS1I+ct8qosxc89ErP u/km5zCzWaBJHSY9Z4zZJN0PmspvT9A= X-Google-Smtp-Source: ABdhPJwLYiHN/GLiTxXDr1bcSGqm0HCx4aQ/CpoO+X6pTfms3Y3DyacTdQxgaaULeVx2sQplFMLeKA== X-Received: by 2002:a05:6000:186b:: with SMTP id d11mr10090022wri.3.1643218824136; Wed, 26 Jan 2022 09:40:24 -0800 (PST) Received: from stitch.. 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[80.71.140.73]) by smtp.gmail.com with ESMTPSA id y2sm3498451wmj.13.2022.01.26.09.40.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jan 2022 09:40:23 -0800 (PST) Sender: Emil Renner Berthing From: Emil Renner Berthing To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: Emil Renner Berthing , Michael Turquette , Stephen Boyd , Rob Herring , Andy Shevchenko , Geert Uytterhoeven , Arnd Bergmann , Michael Zhu , Fu Wei , linux-kernel@vger.kernel.org Subject: [PATCH v1 2/7] clk: starfive: jh7100: Handle audio_div clock properly Date: Wed, 26 Jan 2022 18:39:48 +0100 Message-Id: <20220126173953.1016706-3-kernel@esmil.dk> X-Mailer: git-send-email 2.35.0 In-Reply-To: <20220126173953.1016706-1-kernel@esmil.dk> References: <20220126173953.1016706-1-kernel@esmil.dk> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org It turns out the audio_div clock is a fractional divider where the lowest byte of the ctrl register is the integer part of the divider and the 2nd byte is the number of 100th added to the divider. The children of this clock is used by the audio peripherals for their sample rate clock, so round to the closest possible rate rather than always rounding down like regular dividers. Fixes: 4210be668a09 ("clk: starfive: Add JH7100 clock generator driver") Signed-off-by: Emil Renner Berthing --- drivers/clk/starfive/clk-starfive-jh7100.c | 68 +++++++++++++++++++++- 1 file changed, 67 insertions(+), 1 deletion(-) diff --git a/drivers/clk/starfive/clk-starfive-jh7100.c b/drivers/clk/starfive/clk-starfive-jh7100.c index db6a4dc203af..4b59338b5d7d 100644 --- a/drivers/clk/starfive/clk-starfive-jh7100.c +++ b/drivers/clk/starfive/clk-starfive-jh7100.c @@ -32,6 +32,13 @@ #define JH7100_CLK_MUX_MASK GENMASK(27, 24) #define JH7100_CLK_MUX_SHIFT 24 #define JH7100_CLK_DIV_MASK GENMASK(23, 0) +#define JH7100_CLK_FRAC_MASK GENMASK(15, 8) +#define JH7100_CLK_FRAC_SHIFT 8 +#define JH7100_CLK_INT_MASK GENMASK(7, 0) + +/* fractional divider min/max */ +#define JH7100_CLK_FRAC_MIN 100UL +#define JH7100_CLK_FRAC_MAX 25599UL /* clock data */ #define JH7100_GATE(_idx, _name, _flags, _parent) [_idx] = { \ @@ -55,6 +62,13 @@ .parents = { [0] = _parent }, \ } +#define JH7100_FDIV(_idx, _name, _parent) [_idx] = { \ + .name = _name, \ + .flags = 0, \ + .max = JH7100_CLK_FRAC_MAX, \ + .parents = { [0] = _parent }, \ +} + #define JH7100__MUX(_idx, _name, _nparents, ...) [_idx] = { \ .name = _name, \ .flags = 0, \ @@ -225,7 +239,7 @@ static const struct { JH7100__MUX(JH7100_CLK_USBPHY_25M, "usbphy_25m", 2, JH7100_CLK_OSC_SYS, JH7100_CLK_USBPHY_PLLDIV25M), - JH7100__DIV(JH7100_CLK_AUDIO_DIV, "audio_div", 131072, JH7100_CLK_AUDIO_ROOT), + JH7100_FDIV(JH7100_CLK_AUDIO_DIV, "audio_div", JH7100_CLK_AUDIO_ROOT), JH7100_GATE(JH7100_CLK_AUDIO_SRC, "audio_src", 0, JH7100_CLK_AUDIO_DIV), JH7100_GATE(JH7100_CLK_AUDIO_12288, "audio_12288", 0, JH7100_CLK_OSC_AUD), JH7100_GDIV(JH7100_CLK_VIN_SRC, "vin_src", 0, 4, JH7100_CLK_VIN_ROOT), @@ -440,6 +454,49 @@ static int jh7100_clk_set_rate(struct clk_hw *hw, return 0; } +static unsigned long jh7100_clk_frac_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct jh7100_clk *clk = jh7100_clk_from(hw); + u32 reg = jh7100_clk_reg_get(clk); + unsigned long div100 = 100 * (reg & JH7100_CLK_INT_MASK) + + ((reg & JH7100_CLK_FRAC_MASK) >> JH7100_CLK_FRAC_SHIFT); + + return (div100 >= JH7100_CLK_FRAC_MIN) ? 100 * parent_rate / div100 : 0; +} + +static int jh7100_clk_frac_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + unsigned long parent100 = 100 * req->best_parent_rate; + unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate); + unsigned long div100 = clamp(DIV_ROUND_CLOSEST(parent100, rate), + JH7100_CLK_FRAC_MIN, JH7100_CLK_FRAC_MAX); + unsigned long result = parent100 / div100; + + /* clamp the result as in jh7100_clk_determine_rate() above */ + if (result > req->max_rate && div100 < JH7100_CLK_FRAC_MAX) + result = parent100 / (div100 + 1); + if (result < req->min_rate && div100 > JH7100_CLK_FRAC_MIN) + result = parent100 / (div100 - 1); + + req->rate = result; + return 0; +} + +static int jh7100_clk_frac_set_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate) +{ + struct jh7100_clk *clk = jh7100_clk_from(hw); + unsigned long div100 = clamp(DIV_ROUND_CLOSEST(100 * parent_rate, rate), + JH7100_CLK_FRAC_MIN, JH7100_CLK_FRAC_MAX); + u32 value = ((div100 % 100) << JH7100_CLK_FRAC_SHIFT) | (div100 / 100); + + jh7100_clk_reg_rmw(clk, JH7100_CLK_DIV_MASK, value); + return 0; +} + static u8 jh7100_clk_get_parent(struct clk_hw *hw) { struct jh7100_clk *clk = jh7100_clk_from(hw); @@ -526,6 +583,13 @@ static const struct clk_ops jh7100_clk_div_ops = { .debug_init = jh7100_clk_debug_init, }; +static const struct clk_ops jh7100_clk_fdiv_ops = { + .recalc_rate = jh7100_clk_frac_recalc_rate, + .determine_rate = jh7100_clk_frac_determine_rate, + .set_rate = jh7100_clk_frac_set_rate, + .debug_init = jh7100_clk_debug_init, +}; + static const struct clk_ops jh7100_clk_gdiv_ops = { .enable = jh7100_clk_enable, .disable = jh7100_clk_disable, @@ -564,6 +628,8 @@ static const struct clk_ops *__init jh7100_clk_ops(u32 max) if (max & JH7100_CLK_DIV_MASK) { if (max & JH7100_CLK_ENABLE) return &jh7100_clk_gdiv_ops; + if (max == JH7100_CLK_FRAC_MAX) + return &jh7100_clk_fdiv_ops; return &jh7100_clk_div_ops; } From patchwork Wed Jan 26 17:39:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Emil Renner Berthing X-Patchwork-Id: 12725533 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E095DC63684 for ; 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(80.71.140.73.ipv4.parknet.dk. [80.71.140.73]) by smtp.gmail.com with ESMTPSA id y2sm3498451wmj.13.2022.01.26.09.40.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jan 2022 09:40:24 -0800 (PST) Sender: Emil Renner Berthing From: Emil Renner Berthing To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: Emil Renner Berthing , Michael Turquette , Stephen Boyd , Rob Herring , Andy Shevchenko , Geert Uytterhoeven , Arnd Bergmann , Michael Zhu , Fu Wei , linux-kernel@vger.kernel.org Subject: [PATCH v1 3/7] dt-bindings: clock: Add JH7100 audio clock definitions Date: Wed, 26 Jan 2022 18:39:49 +0100 Message-Id: <20220126173953.1016706-4-kernel@esmil.dk> X-Mailer: git-send-email 2.35.0 In-Reply-To: <20220126173953.1016706-1-kernel@esmil.dk> References: <20220126173953.1016706-1-kernel@esmil.dk> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add all clock outputs for the StarFive JH7100 audio clock generator. Signed-off-by: Emil Renner Berthing Acked-by: Rob Herring --- .../dt-bindings/clock/starfive-jh7100-audio.h | 41 +++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 include/dt-bindings/clock/starfive-jh7100-audio.h diff --git a/include/dt-bindings/clock/starfive-jh7100-audio.h b/include/dt-bindings/clock/starfive-jh7100-audio.h new file mode 100644 index 000000000000..fbb4eae6572b --- /dev/null +++ b/include/dt-bindings/clock/starfive-jh7100-audio.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright (C) 2021 Emil Renner Berthing + */ + +#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7100_AUDIO_H__ +#define __DT_BINDINGS_CLOCK_STARFIVE_JH7100_AUDIO_H__ + +#define JH7100_AUDCLK_ADC_MCLK 0 +#define JH7100_AUDCLK_I2S1_MCLK 1 +#define JH7100_AUDCLK_I2SADC_APB 2 +#define JH7100_AUDCLK_I2SADC_BCLK 3 +#define JH7100_AUDCLK_I2SADC_BCLK_N 4 +#define JH7100_AUDCLK_I2SADC_LRCLK 5 +#define JH7100_AUDCLK_PDM_APB 6 +#define JH7100_AUDCLK_PDM_MCLK 7 +#define JH7100_AUDCLK_I2SVAD_APB 8 +#define JH7100_AUDCLK_SPDIF 9 +#define JH7100_AUDCLK_SPDIF_APB 10 +#define JH7100_AUDCLK_PWMDAC_APB 11 +#define JH7100_AUDCLK_DAC_MCLK 12 +#define JH7100_AUDCLK_I2SDAC_APB 13 +#define JH7100_AUDCLK_I2SDAC_BCLK 14 +#define JH7100_AUDCLK_I2SDAC_BCLK_N 15 +#define JH7100_AUDCLK_I2SDAC_LRCLK 16 +#define JH7100_AUDCLK_I2S1_APB 17 +#define JH7100_AUDCLK_I2S1_BCLK 18 +#define JH7100_AUDCLK_I2S1_BCLK_N 19 +#define JH7100_AUDCLK_I2S1_LRCLK 20 +#define JH7100_AUDCLK_I2SDAC16K_APB 21 +#define JH7100_AUDCLK_APB0_BUS 22 +#define JH7100_AUDCLK_DMA1P_AHB 23 +#define JH7100_AUDCLK_USB_APB 24 +#define JH7100_AUDCLK_USB_LPM 25 +#define JH7100_AUDCLK_USB_STB 26 +#define JH7100_AUDCLK_APB_EN 27 +#define JH7100_AUDCLK_VAD_MEM 28 + +#define JH7100_AUDCLK_END 29 + +#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7100_AUDIO_H__ */ From patchwork Wed Jan 26 17:39:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Emil Renner Berthing X-Patchwork-Id: 12725534 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C1C9C63682 for ; Wed, 26 Jan 2022 17:40:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243877AbiAZRk3 (ORCPT ); Wed, 26 Jan 2022 12:40:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47590 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243866AbiAZRk2 (ORCPT ); Wed, 26 Jan 2022 12:40:28 -0500 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E6790C06161C; Wed, 26 Jan 2022 09:40:27 -0800 (PST) Received: by mail-wr1-x42c.google.com with SMTP id h21so313704wrb.8; Wed, 26 Jan 2022 09:40:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xv2b2upMAcR7nSQETF1v56wdlWnH1nAzIzdRtUFQ2Q0=; b=oaiVVtd0jXBEnibcQJNTjQPcSi168VUHbuUyejwZOlXZ4RfMGcj6cK9fONkmXmhx/d dw/23BaXyUm03VpDj/IpA5J1uHkiMAetTP/3HZDCCsWR+SPiXH87WiCjt9qjfcgZ5qy+ 209SfXUF3GpZK8gg4+Uw/homdEiCaI187xHyyjjP+JOxdseE4zccU2EyTjNbngY2gHqO oWKHlruXwFtJYjfSa0ybaG6uIFHhnk4heChTUI4wG8Z0ouzd36XFy20FoXUWHX8Sl9Ep hC3ZNIDh6eczc80Ifg6stDxuFDj2ONjmsBFgRhqM2nEI+hzrTth3Fw6JZUFrtYo1OUv2 e2Jg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=xv2b2upMAcR7nSQETF1v56wdlWnH1nAzIzdRtUFQ2Q0=; b=6Jo/GRslM1gguJvzkjPKBxTiEN5pDKSeu8MrangHru+T4AhEwP4+SRtDgjT1IRTIuA jOTEJlogmY/1OT06HVfvecIMr9SfxmFFFuRRz48z0AjAdZSRL8OVoBXzlTL2ACSvh4H4 3yCOA7P+GQoki50/wZHCGJyZlmtKdMhhG1J8bGmqvBRB1ilzoMfqbD19SmH0MLI8E82S RP63Uxzc46bekviu6X3CQgdTdeEhXGqj0SlCBowDOUr7Gn6VOFjJea554FJIZF/7PBrP 6dJvBt52l5F8GAiOsORP+vbSO02ca8LYsQQ3itvmpXVSvORB3Ax9LV18ZTVczopx2aBx lTag== X-Gm-Message-State: AOAM533CdKEyQ0Y10KK3z+8ltnzGJpW1HNlcPnVXoMgHLmOzexCvqRLW 0wJLMf5zBvYQMrFexsomDywAoKRiUWw= X-Google-Smtp-Source: ABdhPJxzL3yr9aftK53GrFMmGmt37ZMyq5qu/NkND/JthJtbNDbOYB6Tpu0vm63m2W3H++ubjw78rg== X-Received: by 2002:a05:6000:15ca:: with SMTP id y10mr2141434wry.531.1643218826533; Wed, 26 Jan 2022 09:40:26 -0800 (PST) Received: from stitch.. (80.71.140.73.ipv4.parknet.dk. [80.71.140.73]) by smtp.gmail.com with ESMTPSA id y2sm3498451wmj.13.2022.01.26.09.40.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jan 2022 09:40:25 -0800 (PST) Sender: Emil Renner Berthing From: Emil Renner Berthing To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: Emil Renner Berthing , Michael Turquette , Stephen Boyd , Rob Herring , Andy Shevchenko , Geert Uytterhoeven , Arnd Bergmann , Michael Zhu , Fu Wei , linux-kernel@vger.kernel.org Subject: [PATCH v1 4/7] dt-bindings: clock: Add starfive,jh7100-audclk bindings Date: Wed, 26 Jan 2022 18:39:50 +0100 Message-Id: <20220126173953.1016706-5-kernel@esmil.dk> X-Mailer: git-send-email 2.35.0 In-Reply-To: <20220126173953.1016706-1-kernel@esmil.dk> References: <20220126173953.1016706-1-kernel@esmil.dk> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add bindings for the audio clocks on the StarFive JH7100 RISC-V SoC. Signed-off-by: Emil Renner Berthing Reviewed-by: Rob Herring --- .../clock/starfive,jh7100-audclk.yaml | 57 +++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7100-audclk.yaml diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7100-audclk.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7100-audclk.yaml new file mode 100644 index 000000000000..8f49a1ae03f1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jh7100-audclk.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jh7100-audclk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7100 Audio Clock Generator + +maintainers: + - Emil Renner Berthing + +properties: + compatible: + const: starfive,jh7100-audclk + + reg: + maxItems: 1 + + clocks: + items: + - description: Audio source clock + - description: External 12.288MHz clock + - description: Domain 7 AHB bus clock + + clock-names: + items: + - const: audio_src + - const: audio_12288 + - const: dom7ahb_bus + + '#clock-cells': + const: 1 + description: + See for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include + + clock-controller@10480000 { + compatible = "starfive,jh7100-audclk"; + reg = <0x10480000 0x10000>; + clocks = <&clkgen JH7100_CLK_AUDIO_SRC>, + <&clkgen JH7100_CLK_AUDIO_12288>, + <&clkgen JH7100_CLK_DOM7AHB_BUS>; + clock-names = "audio_src", "audio_12288", "dom7ahb_bus"; + #clock-cells = <1>; + }; From patchwork Wed Jan 26 17:39:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Emil Renner Berthing X-Patchwork-Id: 12725535 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2F177C6369B for ; Wed, 26 Jan 2022 17:40:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243885AbiAZRka (ORCPT ); Wed, 26 Jan 2022 12:40:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47602 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243873AbiAZRk3 (ORCPT ); Wed, 26 Jan 2022 12:40:29 -0500 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3C229C06173B; Wed, 26 Jan 2022 09:40:29 -0800 (PST) Received: by mail-wr1-x42a.google.com with SMTP id s18so327778wrv.7; Wed, 26 Jan 2022 09:40:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=utzJOlRKmUIVrtRjHx/h9EYRmqdAXYNb73fmWJzmJYo=; b=ShhfaR0CXVLZKeOjQWZhazb4zVjN1sk6cZewEKW3ITUMaUznUzpSkfWbkAywi2rTjc 9D7Sxsh0c4Ctl9g8b5x/nrLKgWT7cmXq//RHuferZKv1urhyrKdUDopa+jfgJzuac1kk dreYYDH7phQ95hHTsoloBpKNvAupN5Wll/CJ1eUBvJEBUEZ4NxFgTwhNgFt8LCUk0Au9 VHaH8xgXvSsRr9apj3ZEYVgZjtyUbu9vpY+un4ral4ucFFYkMQNCvfioMgjSCBeA4LH2 AgqjSIOV9egPdvtWCfP8HGouQVxIjZ7TwiZaN46dP2i0ncOZ6kzsJ8yTISWGCm7JhESh pZMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=utzJOlRKmUIVrtRjHx/h9EYRmqdAXYNb73fmWJzmJYo=; b=lwS2tb7C27tsVx8/HA0u7MaA2X8UnbdzSP6tUJuCVLPIto4MXte1Jp6JdPapGaUDnG mstVmuffpPjRcCHrXV2MI9cKljaErwMfvuWEavxJRn2q37zaLlDM8/gqgifh+pGqVjcn a/qaysnfbbUWj0QjI98mFnSrW9qLTSC0yG/ZZLMh2OzUbzIhOJirPF94q8ubfcb66GfC ZM8mSewK8ATr7vaIoG0vr/wMYsYjUnPiH6jzLG2BdGgNrWCJjXvGbNQ3A0z/J4djZIQ8 jbuEON6tmjJweLClMZWZUSTFW/QENDPUeVQYc+uGekrY8TP2aueT0RrW0SZw5nHdU/d4 q2zg== X-Gm-Message-State: AOAM5300Xdivfw3FINcLCqg1OQb4ZpzD28quHJ//RyGP7lRqTl8SwR6r 1kOI3DiGxUUXXbv33KCcwmXCy6beIX0= X-Google-Smtp-Source: ABdhPJyKWB52VRbk+Yog7hvH/ukqMHlAba7DvFgxeWp49CSs92pfpSoS5IbJ3TKNxPLYazZXAUUEPQ== X-Received: by 2002:a05:6000:1206:: with SMTP id e6mr22871829wrx.274.1643218827754; Wed, 26 Jan 2022 09:40:27 -0800 (PST) Received: from stitch.. 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[80.71.140.73]) by smtp.gmail.com with ESMTPSA id y2sm3498451wmj.13.2022.01.26.09.40.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jan 2022 09:40:27 -0800 (PST) Sender: Emil Renner Berthing From: Emil Renner Berthing To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: Emil Renner Berthing , Michael Turquette , Stephen Boyd , Rob Herring , Andy Shevchenko , Geert Uytterhoeven , Arnd Bergmann , Michael Zhu , Fu Wei , linux-kernel@vger.kernel.org Subject: [PATCH v1 5/7] clk: starfive: jh7100: Make hw clock implementation reusable Date: Wed, 26 Jan 2022 18:39:51 +0100 Message-Id: <20220126173953.1016706-6-kernel@esmil.dk> X-Mailer: git-send-email 2.35.0 In-Reply-To: <20220126173953.1016706-1-kernel@esmil.dk> References: <20220126173953.1016706-1-kernel@esmil.dk> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The JH7100 has additional audio and video clocks at different memory ranges, but they use the same register layout. Add a header and export the starfive_jh7100_clk_ops function so the clock implementation can be reused by drivers handling these clocks. Signed-off-by: Emil Renner Berthing --- drivers/clk/starfive/clk-starfive-jh7100.c | 96 ++------------------- drivers/clk/starfive/clk-starfive-jh7100.h | 97 ++++++++++++++++++++++ 2 files changed, 104 insertions(+), 89 deletions(-) create mode 100644 drivers/clk/starfive/clk-starfive-jh7100.h diff --git a/drivers/clk/starfive/clk-starfive-jh7100.c b/drivers/clk/starfive/clk-starfive-jh7100.c index 4b59338b5d7d..a6708f9ebf4c 100644 --- a/drivers/clk/starfive/clk-starfive-jh7100.c +++ b/drivers/clk/starfive/clk-starfive-jh7100.c @@ -20,83 +20,15 @@ #include +#include "clk-starfive-jh7100.h" + /* external clocks */ #define JH7100_CLK_OSC_SYS (JH7100_CLK_END + 0) #define JH7100_CLK_OSC_AUD (JH7100_CLK_END + 1) #define JH7100_CLK_GMAC_RMII_REF (JH7100_CLK_END + 2) #define JH7100_CLK_GMAC_GR_MII_RX (JH7100_CLK_END + 3) -/* register fields */ -#define JH7100_CLK_ENABLE BIT(31) -#define JH7100_CLK_INVERT BIT(30) -#define JH7100_CLK_MUX_MASK GENMASK(27, 24) -#define JH7100_CLK_MUX_SHIFT 24 -#define JH7100_CLK_DIV_MASK GENMASK(23, 0) -#define JH7100_CLK_FRAC_MASK GENMASK(15, 8) -#define JH7100_CLK_FRAC_SHIFT 8 -#define JH7100_CLK_INT_MASK GENMASK(7, 0) - -/* fractional divider min/max */ -#define JH7100_CLK_FRAC_MIN 100UL -#define JH7100_CLK_FRAC_MAX 25599UL - -/* clock data */ -#define JH7100_GATE(_idx, _name, _flags, _parent) [_idx] = { \ - .name = _name, \ - .flags = CLK_SET_RATE_PARENT | (_flags), \ - .max = JH7100_CLK_ENABLE, \ - .parents = { [0] = _parent }, \ -} - -#define JH7100__DIV(_idx, _name, _max, _parent) [_idx] = { \ - .name = _name, \ - .flags = 0, \ - .max = _max, \ - .parents = { [0] = _parent }, \ -} - -#define JH7100_GDIV(_idx, _name, _flags, _max, _parent) [_idx] = { \ - .name = _name, \ - .flags = _flags, \ - .max = JH7100_CLK_ENABLE | (_max), \ - .parents = { [0] = _parent }, \ -} - -#define JH7100_FDIV(_idx, _name, _parent) [_idx] = { \ - .name = _name, \ - .flags = 0, \ - .max = JH7100_CLK_FRAC_MAX, \ - .parents = { [0] = _parent }, \ -} - -#define JH7100__MUX(_idx, _name, _nparents, ...) [_idx] = { \ - .name = _name, \ - .flags = 0, \ - .max = ((_nparents) - 1) << JH7100_CLK_MUX_SHIFT, \ - .parents = { __VA_ARGS__ }, \ -} - -#define JH7100_GMUX(_idx, _name, _flags, _nparents, ...) [_idx] = { \ - .name = _name, \ - .flags = _flags, \ - .max = JH7100_CLK_ENABLE | \ - (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT), \ - .parents = { __VA_ARGS__ }, \ -} - -#define JH7100__INV(_idx, _name, _parent) [_idx] = { \ - .name = _name, \ - .flags = CLK_SET_RATE_PARENT, \ - .max = JH7100_CLK_INVERT, \ - .parents = { [0] = _parent }, \ -} - -static const struct { - const char *name; - unsigned long flags; - u32 max; - u8 parents[4]; -} jh7100_clk_data[] __initconst = { +static const struct jh7100_clk_data jh7100_clk_data[] __initconst = { JH7100__MUX(JH7100_CLK_CPUNDBUS_ROOT, "cpundbus_root", 4, JH7100_CLK_OSC_SYS, JH7100_CLK_PLL0_OUT, @@ -337,21 +269,6 @@ static const struct { JH7100_GATE(JH7100_CLK_SYSERR_APB, "syserr_apb", 0, JH7100_CLK_APB2_BUS), }; -struct jh7100_clk { - struct clk_hw hw; - unsigned int idx; - unsigned int max_div; -}; - -struct jh7100_clk_priv { - /* protect clk enable and set rate/parent from happening at the same time */ - spinlock_t rmw_lock; - struct device *dev; - void __iomem *base; - struct clk_hw *pll[3]; - struct jh7100_clk reg[JH7100_CLK_PLL0_OUT]; -}; - static struct jh7100_clk *jh7100_clk_from(struct clk_hw *hw) { return container_of(hw, struct jh7100_clk, hw); @@ -623,7 +540,7 @@ static const struct clk_ops jh7100_clk_inv_ops = { .debug_init = jh7100_clk_debug_init, }; -static const struct clk_ops *__init jh7100_clk_ops(u32 max) +const struct clk_ops *starfive_jh7100_clk_ops(u32 max) { if (max & JH7100_CLK_DIV_MASK) { if (max & JH7100_CLK_ENABLE) @@ -644,6 +561,7 @@ static const struct clk_ops *__init jh7100_clk_ops(u32 max) return &jh7100_clk_inv_ops; } +EXPORT_SYMBOL_GPL(starfive_jh7100_clk_ops); static struct clk_hw *jh7100_clk_get(struct of_phandle_args *clkspec, void *data) { @@ -665,7 +583,7 @@ static int __init clk_starfive_jh7100_probe(struct platform_device *pdev) unsigned int idx; int ret; - priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + priv = devm_kzalloc(&pdev->dev, struct_size(priv, reg, JH7100_CLK_PLL0_OUT), GFP_KERNEL); if (!priv) return -ENOMEM; @@ -695,7 +613,7 @@ static int __init clk_starfive_jh7100_probe(struct platform_device *pdev) struct clk_parent_data parents[4] = {}; struct clk_init_data init = { .name = jh7100_clk_data[idx].name, - .ops = jh7100_clk_ops(max), + .ops = starfive_jh7100_clk_ops(max), .parent_data = parents, .num_parents = ((max & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT) + 1, .flags = jh7100_clk_data[idx].flags, diff --git a/drivers/clk/starfive/clk-starfive-jh7100.h b/drivers/clk/starfive/clk-starfive-jh7100.h new file mode 100644 index 000000000000..8eccd8c0a746 --- /dev/null +++ b/drivers/clk/starfive/clk-starfive-jh7100.h @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __CLK_STARFIVE_JH7100_H +#define __CLK_STARFIVE_JH7100_H + +#include +#include + +/* register fields */ +#define JH7100_CLK_ENABLE BIT(31) +#define JH7100_CLK_INVERT BIT(30) +#define JH7100_CLK_MUX_MASK GENMASK(27, 24) +#define JH7100_CLK_MUX_SHIFT 24 +#define JH7100_CLK_DIV_MASK GENMASK(23, 0) +#define JH7100_CLK_FRAC_MASK GENMASK(15, 8) +#define JH7100_CLK_FRAC_SHIFT 8 +#define JH7100_CLK_INT_MASK GENMASK(7, 0) + +/* fractional divider min/max */ +#define JH7100_CLK_FRAC_MIN 100UL +#define JH7100_CLK_FRAC_MAX 25599UL + +/* clock data */ +struct jh7100_clk_data { + const char *name; + unsigned long flags; + u32 max; + u8 parents[4]; +}; + +#define JH7100_GATE(_idx, _name, _flags, _parent) [_idx] = { \ + .name = _name, \ + .flags = CLK_SET_RATE_PARENT | (_flags), \ + .max = JH7100_CLK_ENABLE, \ + .parents = { [0] = _parent }, \ +} + +#define JH7100__DIV(_idx, _name, _max, _parent) [_idx] = { \ + .name = _name, \ + .flags = 0, \ + .max = _max, \ + .parents = { [0] = _parent }, \ +} + +#define JH7100_GDIV(_idx, _name, _flags, _max, _parent) [_idx] = { \ + .name = _name, \ + .flags = _flags, \ + .max = JH7100_CLK_ENABLE | (_max), \ + .parents = { [0] = _parent }, \ +} + +#define JH7100_FDIV(_idx, _name, _parent) [_idx] = { \ + .name = _name, \ + .flags = 0, \ + .max = JH7100_CLK_FRAC_MAX, \ + .parents = { [0] = _parent }, \ +} + +#define JH7100__MUX(_idx, _name, _nparents, ...) [_idx] = { \ + .name = _name, \ + .flags = 0, \ + .max = ((_nparents) - 1) << JH7100_CLK_MUX_SHIFT, \ + .parents = { __VA_ARGS__ }, \ +} + +#define JH7100_GMUX(_idx, _name, _flags, _nparents, ...) [_idx] = { \ + .name = _name, \ + .flags = _flags, \ + .max = JH7100_CLK_ENABLE | \ + (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT), \ + .parents = { __VA_ARGS__ }, \ +} + +#define JH7100__INV(_idx, _name, _parent) [_idx] = { \ + .name = _name, \ + .flags = CLK_SET_RATE_PARENT, \ + .max = JH7100_CLK_INVERT, \ + .parents = { [0] = _parent }, \ +} + +struct jh7100_clk { + struct clk_hw hw; + unsigned int idx; + unsigned int max_div; +}; + +struct jh7100_clk_priv { + /* protect clk enable and set rate/parent from happening at the same time */ + spinlock_t rmw_lock; + struct device *dev; + void __iomem *base; + struct clk_hw *pll[3]; + struct jh7100_clk reg[]; +}; + +const struct clk_ops *starfive_jh7100_clk_ops(u32 max); + +#endif From patchwork Wed Jan 26 17:39:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Emil Renner Berthing X-Patchwork-Id: 12725536 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2A3FFC28CF5 for ; Wed, 26 Jan 2022 17:40:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243894AbiAZRkc (ORCPT ); Wed, 26 Jan 2022 12:40:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47618 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243878AbiAZRkb (ORCPT ); Wed, 26 Jan 2022 12:40:31 -0500 Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [IPv6:2a00:1450:4864:20::330]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 75629C06174E; Wed, 26 Jan 2022 09:40:30 -0800 (PST) Received: by mail-wm1-x330.google.com with SMTP id l35-20020a05600c1d2300b0034d477271c1so296796wms.3; Wed, 26 Jan 2022 09:40:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BPag3SRsfFtkptHhSLA0oo2r5XSMa9TnGzL6mvwwMRo=; b=a8JwmXmFvUYYOUX9AvgiUtYHfiu+1fdenrXnR+SfreMqTzm8A9WPEOq5RizyrX2Q6x c13XxOIwydhRkbAvz+SzuruNXGL/hBycDD4JeEJLQUPDXBQM0XJj89pfhn4jPXSzTNSg mTEO/afksAy1tR4bjCTe66InghHWW4fxLxbv1CXrVQE4gRTjBnIvz9Dqo2//Z0UWMOf0 n6bAWNmrIZLkNjnwo1yWlopYGPkxZucEIb2aMaZNgXI1z1mgA8NsZiYS5PR6umZ88Xjs 4PfQ69EX0EucA8qe2hphV9fq+NIS6pPKfxjBoewDbl2GWMhkuNc667V/0+JXrVD+TXpn GqQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=BPag3SRsfFtkptHhSLA0oo2r5XSMa9TnGzL6mvwwMRo=; b=tYdTNdh9Nyd08cenImr/7i2TJNjvkv77iHw+mLwxx1ODcIWgxExJslAdb/nOYtgVmH JVDyliBhZGApQRZp+77PfvHZk8ohmmqIAJjX6WOFlfcICpASrw0tAPNvfOI9ylKPVfyW Zsjd/Ip/kH8a+WA4FcJTabgGtcuAOKJTjGKP1G5J8XIy7krlm44MUw76742pnahevaLd jvy5sqDngurPV+Xn22Y+n/eJB+KxBqm/WgKeVf8yVajgCICpda36X9DmMIkJ1tnHXJtB EFu/aoF+yef0LgZM/lf2n0XBiwWU6OV3jKuK/cW95OAZkkOg64cLDUFNwiUoy1jHCl9q L9lw== X-Gm-Message-State: AOAM531/jACT1CkBR+UF7DYWHvn7XYRdjdQ+HdCM3b07wQh3DSzdlwkn k3no+bxcz+/omb4/nWwF7kgSNR82+GU= X-Google-Smtp-Source: ABdhPJwl0Bf5Qu7FXpfRAgFIbFkiihwRjENkAog38O9gx4s/dJQq+Mph8DeT/sn7637JV4ixeODgSA== X-Received: by 2002:a1c:a5d0:: with SMTP id o199mr8327491wme.65.1643218828949; Wed, 26 Jan 2022 09:40:28 -0800 (PST) Received: from stitch.. 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[80.71.140.73]) by smtp.gmail.com with ESMTPSA id y2sm3498451wmj.13.2022.01.26.09.40.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jan 2022 09:40:28 -0800 (PST) Sender: Emil Renner Berthing From: Emil Renner Berthing To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: Emil Renner Berthing , Michael Turquette , Stephen Boyd , Rob Herring , Andy Shevchenko , Geert Uytterhoeven , Arnd Bergmann , Michael Zhu , Fu Wei , linux-kernel@vger.kernel.org Subject: [PATCH v1 6/7] clk: starfive: jh7100: Support more clock types Date: Wed, 26 Jan 2022 18:39:52 +0100 Message-Id: <20220126173953.1016706-7-kernel@esmil.dk> X-Mailer: git-send-email 2.35.0 In-Reply-To: <20220126173953.1016706-1-kernel@esmil.dk> References: <20220126173953.1016706-1-kernel@esmil.dk> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Unlike the system clocks there are audio clocks that combine both multiplexer/divider and gate/multiplexer/divider, so add support for that. Signed-off-by: Emil Renner Berthing --- drivers/clk/starfive/clk-starfive-jh7100.c | 26 ++++++++++++++++++++++ drivers/clk/starfive/clk-starfive-jh7100.h | 15 +++++++++++++ 2 files changed, 41 insertions(+) diff --git a/drivers/clk/starfive/clk-starfive-jh7100.c b/drivers/clk/starfive/clk-starfive-jh7100.c index a6708f9ebf4c..691aeebc7092 100644 --- a/drivers/clk/starfive/clk-starfive-jh7100.c +++ b/drivers/clk/starfive/clk-starfive-jh7100.c @@ -534,6 +534,27 @@ static const struct clk_ops jh7100_clk_gmux_ops = { .debug_init = jh7100_clk_debug_init, }; +static const struct clk_ops jh7100_clk_mdiv_ops = { + .recalc_rate = jh7100_clk_recalc_rate, + .determine_rate = jh7100_clk_determine_rate, + .get_parent = jh7100_clk_get_parent, + .set_parent = jh7100_clk_set_parent, + .set_rate = jh7100_clk_set_rate, + .debug_init = jh7100_clk_debug_init, +}; + +static const struct clk_ops jh7100_clk_gmd_ops = { + .enable = jh7100_clk_enable, + .disable = jh7100_clk_disable, + .is_enabled = jh7100_clk_is_enabled, + .recalc_rate = jh7100_clk_recalc_rate, + .determine_rate = jh7100_clk_determine_rate, + .get_parent = jh7100_clk_get_parent, + .set_parent = jh7100_clk_set_parent, + .set_rate = jh7100_clk_set_rate, + .debug_init = jh7100_clk_debug_init, +}; + static const struct clk_ops jh7100_clk_inv_ops = { .get_phase = jh7100_clk_get_phase, .set_phase = jh7100_clk_set_phase, @@ -543,6 +564,11 @@ static const struct clk_ops jh7100_clk_inv_ops = { const struct clk_ops *starfive_jh7100_clk_ops(u32 max) { if (max & JH7100_CLK_DIV_MASK) { + if (max & JH7100_CLK_MUX_MASK) { + if (max & JH7100_CLK_ENABLE) + return &jh7100_clk_gmd_ops; + return &jh7100_clk_mdiv_ops; + } if (max & JH7100_CLK_ENABLE) return &jh7100_clk_gdiv_ops; if (max == JH7100_CLK_FRAC_MAX) diff --git a/drivers/clk/starfive/clk-starfive-jh7100.h b/drivers/clk/starfive/clk-starfive-jh7100.h index 8eccd8c0a746..f116be5740a5 100644 --- a/drivers/clk/starfive/clk-starfive-jh7100.h +++ b/drivers/clk/starfive/clk-starfive-jh7100.h @@ -70,6 +70,21 @@ struct jh7100_clk_data { .parents = { __VA_ARGS__ }, \ } +#define JH7100_MDIV(_idx, _name, _max, _nparents, ...) [_idx] = { \ + .name = _name, \ + .flags = 0, \ + .max = (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT) | (_max), \ + .parents = { __VA_ARGS__ }, \ +} + +#define JH7100__GMD(_idx, _name, _flags, _max, _nparents, ...) [_idx] = { \ + .name = _name, \ + .flags = _flags, \ + .max = JH7100_CLK_ENABLE | \ + (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT) | (_max), \ + .parents = { __VA_ARGS__ }, \ +} + #define JH7100__INV(_idx, _name, _parent) [_idx] = { \ .name = _name, \ .flags = CLK_SET_RATE_PARENT, \ From patchwork Wed Jan 26 17:39:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Emil Renner Berthing X-Patchwork-Id: 12725537 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD09EC2BA4C for ; Wed, 26 Jan 2022 17:40:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242787AbiAZRkd (ORCPT ); Wed, 26 Jan 2022 12:40:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47630 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243863AbiAZRkc (ORCPT ); Wed, 26 Jan 2022 12:40:32 -0500 Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 01C75C061747; Wed, 26 Jan 2022 09:40:32 -0800 (PST) Received: by mail-wr1-x42f.google.com with SMTP id e8so450273wrc.0; Wed, 26 Jan 2022 09:40:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vzQkhLBS70dEhyFA0pnQ2jAb/yuPb18VvGMin2IIfps=; b=mZXdWA3pxNhnsRou/96wMixaVrpZViMelAElL4m1J3ccF5lVmxstPdehFg/fmNXJvp PVN8ZhlbSy8PxrQXTXB9lhrDNkqxNFoD1qeagyRg3Bis2QlrvfsLFMa2WHF4U9NPRQrw ICU8zwUBnSPetS6zBZ4SuhcYI9XhwPH0ybMeuZPxizSOvWjwMT6mWH83ktXRrzKcqBCy cR/6B+eFNfSyLiEXftrliQK8PAACongo23YqV8dLRzkQR8mG+zsYEOQRjjLpPS154zH6 sssQdCBSEiHTK2rmVhEMnf2xgThUxJGzcLMjtMSARYE3jKAYhene7kbKDDty/oOf4+g5 yr1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=vzQkhLBS70dEhyFA0pnQ2jAb/yuPb18VvGMin2IIfps=; b=lKltSBlAnq86zORHYQS6FGPjibG5IF1n3LBm21GV9abfD7Sjz7hc8w7rKvkzdq7BEH GmvCA434lbzyKkGgYZtOrioPnMB2vy0wM0V9sGDsbdVH4y0/k/12EU/YhBlJ2tOvSxXQ dC4VqYdzQ9aXZiqBCLEq6MoUGiHUaYgjTysX0iGV2rEMWUUAShbSxdIuidc1TUzEtEx6 ZCfXyuP3np+x+15V2C6OB2vtAgQTOdjIauFiOCRWbaGmsMilwDnL32BQvESkmT9UCoBj +tb5a/bBsLmpSDsQAt2yZVRn47mjNVkMYe1iq4w2JlQJBsjzn3EyqYKrBtbACe/P+ydY 6zHg== X-Gm-Message-State: AOAM5327mKC2NFfZc1oWKcPISWpY4eLDnp1nE8MoZ1RNGbrmTtQIdaEk oMFH+JMhfeidjB6mOJxlM8Tz2TNXDis= X-Google-Smtp-Source: ABdhPJwdUUNl3K0u8oQwmUALIFV2eaDwBv4Zbs+vjfk6Lx1pBSP+z1WpUlznbVyoTVXmN+0zJ7qohA== X-Received: by 2002:a5d:4c47:: with SMTP id n7mr11837502wrt.453.1643218830233; Wed, 26 Jan 2022 09:40:30 -0800 (PST) Received: from stitch.. (80.71.140.73.ipv4.parknet.dk. [80.71.140.73]) by smtp.gmail.com with ESMTPSA id y2sm3498451wmj.13.2022.01.26.09.40.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jan 2022 09:40:29 -0800 (PST) Sender: Emil Renner Berthing From: Emil Renner Berthing To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: Emil Renner Berthing , Michael Turquette , Stephen Boyd , Rob Herring , Andy Shevchenko , Geert Uytterhoeven , Arnd Bergmann , Michael Zhu , Fu Wei , linux-kernel@vger.kernel.org Subject: [PATCH v1 7/7] clk: starfive: Add JH7100 audio clock driver Date: Wed, 26 Jan 2022 18:39:53 +0100 Message-Id: <20220126173953.1016706-8-kernel@esmil.dk> X-Mailer: git-send-email 2.35.0 In-Reply-To: <20220126173953.1016706-1-kernel@esmil.dk> References: <20220126173953.1016706-1-kernel@esmil.dk> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add a driver for the audio clocks on the Starfive JH7100 RISC-V SoC. Signed-off-by: Emil Renner Berthing --- MAINTAINERS | 8 +- drivers/clk/starfive/Kconfig | 8 + drivers/clk/starfive/Makefile | 1 + .../clk/starfive/clk-starfive-jh7100-audio.c | 170 ++++++++++++++++++ 4 files changed, 183 insertions(+), 4 deletions(-) create mode 100644 drivers/clk/starfive/clk-starfive-jh7100-audio.c diff --git a/MAINTAINERS b/MAINTAINERS index ea3e6c914384..19a855f3fdca 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18376,12 +18376,12 @@ M: Ion Badulescu S: Odd Fixes F: drivers/net/ethernet/adaptec/starfire* -STARFIVE JH7100 CLOCK DRIVER +STARFIVE JH7100 CLOCK DRIVERS M: Emil Renner Berthing S: Maintained -F: Documentation/devicetree/bindings/clock/starfive,jh7100-clkgen.yaml -F: drivers/clk/starfive/clk-starfive-jh7100.c -F: include/dt-bindings/clock/starfive-jh7100.h +F: Documentation/devicetree/bindings/clock/starfive,jh7100-*.yaml +F: drivers/clk/starfive/clk-starfive-jh7100* +F: include/dt-bindings/clock/starfive-jh7100*.h STARFIVE JH7100 PINCTRL DRIVER M: Emil Renner Berthing diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig index c0fa9d5e641f..003bd2d56ce7 100644 --- a/drivers/clk/starfive/Kconfig +++ b/drivers/clk/starfive/Kconfig @@ -7,3 +7,11 @@ config CLK_STARFIVE_JH7100 help Say yes here to support the clock controller on the StarFive JH7100 SoC. + +config CLK_STARFIVE_JH7100_AUDIO + tristate "StarFive JH7100 audio clock support" + depends on CLK_STARFIVE_JH7100 + default m if SOC_STARFIVE + help + Say Y or M here to support the audio clocks on the StarFive JH7100 + SoC. diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile index 09759cc73530..0fa8ecb9ec1c 100644 --- a/drivers/clk/starfive/Makefile +++ b/drivers/clk/starfive/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 # StarFive Clock obj-$(CONFIG_CLK_STARFIVE_JH7100) += clk-starfive-jh7100.o +obj-$(CONFIG_CLK_STARFIVE_JH7100_AUDIO) += clk-starfive-jh7100-audio.o diff --git a/drivers/clk/starfive/clk-starfive-jh7100-audio.c b/drivers/clk/starfive/clk-starfive-jh7100-audio.c new file mode 100644 index 000000000000..8473a65e219b --- /dev/null +++ b/drivers/clk/starfive/clk-starfive-jh7100-audio.c @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * StarFive JH7100 Audio Clock Driver + * + * Copyright (C) 2021 Emil Renner Berthing + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-starfive-jh7100.h" + +/* external clocks */ +#define JH7100_AUDCLK_AUDIO_SRC (JH7100_AUDCLK_END + 0) +#define JH7100_AUDCLK_AUDIO_12288 (JH7100_AUDCLK_END + 1) +#define JH7100_AUDCLK_DOM7AHB_BUS (JH7100_AUDCLK_END + 2) +#define JH7100_AUDCLK_I2SADC_BCLK_IOPAD (JH7100_AUDCLK_END + 3) +#define JH7100_AUDCLK_I2SADC_LRCLK_IOPAD (JH7100_AUDCLK_END + 4) +#define JH7100_AUDCLK_I2SDAC_BCLK_IOPAD (JH7100_AUDCLK_END + 5) +#define JH7100_AUDCLK_I2SDAC_LRCLK_IOPAD (JH7100_AUDCLK_END + 6) +#define JH7100_AUDCLK_VAD_INTMEM (JH7100_AUDCLK_END + 7) + +static const struct jh7100_clk_data jh7100_audclk_data[] = { + JH7100__GMD(JH7100_AUDCLK_ADC_MCLK, "adc_mclk", 0, 15, 2, + JH7100_AUDCLK_AUDIO_SRC, + JH7100_AUDCLK_AUDIO_12288), + JH7100__GMD(JH7100_AUDCLK_I2S1_MCLK, "i2s1_mclk", 0, 15, 2, + JH7100_AUDCLK_AUDIO_SRC, + JH7100_AUDCLK_AUDIO_12288), + JH7100_GATE(JH7100_AUDCLK_I2SADC_APB, "i2sadc_apb", 0, JH7100_AUDCLK_APB0_BUS), + JH7100_MDIV(JH7100_AUDCLK_I2SADC_BCLK, "i2sadc_bclk", 31, 2, + JH7100_AUDCLK_ADC_MCLK, + JH7100_AUDCLK_I2SADC_BCLK_IOPAD), + JH7100__INV(JH7100_AUDCLK_I2SADC_BCLK_N, "i2sadc_bclk_n", JH7100_AUDCLK_I2SADC_BCLK), + JH7100_MDIV(JH7100_AUDCLK_I2SADC_LRCLK, "i2sadc_lrclk", 63, 3, + JH7100_AUDCLK_I2SADC_BCLK_N, + JH7100_AUDCLK_I2SADC_LRCLK_IOPAD, + JH7100_AUDCLK_I2SADC_BCLK), + JH7100_GATE(JH7100_AUDCLK_PDM_APB, "pdm_apb", 0, JH7100_AUDCLK_APB0_BUS), + JH7100__GMD(JH7100_AUDCLK_PDM_MCLK, "pdm_mclk", 0, 15, 2, + JH7100_AUDCLK_AUDIO_SRC, + JH7100_AUDCLK_AUDIO_12288), + JH7100_GATE(JH7100_AUDCLK_I2SVAD_APB, "i2svad_apb", 0, JH7100_AUDCLK_APB0_BUS), + JH7100__GMD(JH7100_AUDCLK_SPDIF, "spdif", 0, 15, 2, + JH7100_AUDCLK_AUDIO_SRC, + JH7100_AUDCLK_AUDIO_12288), + JH7100_GATE(JH7100_AUDCLK_SPDIF_APB, "spdif_apb", 0, JH7100_AUDCLK_APB0_BUS), + JH7100_GATE(JH7100_AUDCLK_PWMDAC_APB, "pwmdac_apb", 0, JH7100_AUDCLK_APB0_BUS), + JH7100__GMD(JH7100_AUDCLK_DAC_MCLK, "dac_mclk", 0, 15, 2, + JH7100_AUDCLK_AUDIO_SRC, + JH7100_AUDCLK_AUDIO_12288), + JH7100_GATE(JH7100_AUDCLK_I2SDAC_APB, "i2sdac_apb", 0, JH7100_AUDCLK_APB0_BUS), + JH7100_MDIV(JH7100_AUDCLK_I2SDAC_BCLK, "i2sdac_bclk", 31, 2, + JH7100_AUDCLK_DAC_MCLK, + JH7100_AUDCLK_I2SDAC_BCLK_IOPAD), + JH7100__INV(JH7100_AUDCLK_I2SDAC_BCLK_N, "i2sdac_bclk_n", JH7100_AUDCLK_I2SDAC_BCLK), + JH7100_MDIV(JH7100_AUDCLK_I2SDAC_LRCLK, "i2sdac_lrclk", 31, 2, + JH7100_AUDCLK_I2S1_MCLK, + JH7100_AUDCLK_I2SDAC_BCLK_IOPAD), + JH7100_GATE(JH7100_AUDCLK_I2S1_APB, "i2s1_apb", 0, JH7100_AUDCLK_APB0_BUS), + JH7100_MDIV(JH7100_AUDCLK_I2S1_BCLK, "i2s1_bclk", 31, 2, + JH7100_AUDCLK_I2S1_MCLK, + JH7100_AUDCLK_I2SDAC_BCLK_IOPAD), + JH7100__INV(JH7100_AUDCLK_I2S1_BCLK_N, "i2s1_bclk_n", JH7100_AUDCLK_I2S1_BCLK), + JH7100_MDIV(JH7100_AUDCLK_I2S1_LRCLK, "i2s1_lrclk", 63, 3, + JH7100_AUDCLK_I2S1_BCLK_N, + JH7100_AUDCLK_I2SDAC_LRCLK_IOPAD), + JH7100_GATE(JH7100_AUDCLK_I2SDAC16K_APB, "i2s1dac16k_apb", 0, JH7100_AUDCLK_APB0_BUS), + JH7100__DIV(JH7100_AUDCLK_APB0_BUS, "apb0_bus", 8, JH7100_AUDCLK_DOM7AHB_BUS), + JH7100_GATE(JH7100_AUDCLK_DMA1P_AHB, "dma1p_ahb", 0, JH7100_AUDCLK_DOM7AHB_BUS), + JH7100_GATE(JH7100_AUDCLK_USB_APB, "usb_apb", CLK_IGNORE_UNUSED, JH7100_AUDCLK_APB_EN), + JH7100_GDIV(JH7100_AUDCLK_USB_LPM, "usb_lpm", CLK_IGNORE_UNUSED, 4, JH7100_AUDCLK_USB_APB), + JH7100_GDIV(JH7100_AUDCLK_USB_STB, "usb_stb", CLK_IGNORE_UNUSED, 3, JH7100_AUDCLK_USB_APB), + JH7100__DIV(JH7100_AUDCLK_APB_EN, "apb_en", 8, JH7100_AUDCLK_DOM7AHB_BUS), + JH7100__MUX(JH7100_AUDCLK_VAD_MEM, "vad_mem", 2, + JH7100_AUDCLK_VAD_INTMEM, + JH7100_AUDCLK_AUDIO_12288), +}; + +static struct clk_hw *jh7100_audclk_get(struct of_phandle_args *clkspec, void *data) +{ + struct jh7100_clk_priv *priv = data; + unsigned int idx = clkspec->args[0]; + + if (idx < JH7100_AUDCLK_END) + return &priv->reg[idx].hw; + + return ERR_PTR(-EINVAL); +} + +static int jh7100_audclk_probe(struct platform_device *pdev) +{ + struct jh7100_clk_priv *priv; + unsigned int idx; + int ret; + + priv = devm_kzalloc(&pdev->dev, struct_size(priv, reg, JH7100_AUDCLK_END), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + spin_lock_init(&priv->rmw_lock); + priv->dev = &pdev->dev; + priv->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + for (idx = 0; idx < JH7100_AUDCLK_END; idx++) { + u32 max = jh7100_audclk_data[idx].max; + struct clk_parent_data parents[4] = {}; + struct clk_init_data init = { + .name = jh7100_audclk_data[idx].name, + .ops = starfive_jh7100_clk_ops(max), + .parent_data = parents, + .num_parents = ((max & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT) + 1, + .flags = jh7100_audclk_data[idx].flags, + }; + struct jh7100_clk *clk = &priv->reg[idx]; + unsigned int i; + + for (i = 0; i < init.num_parents; i++) { + unsigned int pidx = jh7100_audclk_data[idx].parents[i]; + + if (pidx < JH7100_AUDCLK_END) + parents[i].hw = &priv->reg[pidx].hw; + else if (pidx == JH7100_AUDCLK_AUDIO_SRC) + parents[i].fw_name = "audio_src"; + else if (pidx == JH7100_AUDCLK_AUDIO_12288) + parents[i].fw_name = "audio_12288"; + else if (pidx == JH7100_AUDCLK_DOM7AHB_BUS) + parents[i].fw_name = "dom7ahb_bus"; + } + + clk->hw.init = &init; + clk->idx = idx; + clk->max_div = max & JH7100_CLK_DIV_MASK; + + ret = devm_clk_hw_register(priv->dev, &clk->hw); + if (ret) + return ret; + } + + return devm_of_clk_add_hw_provider(priv->dev, jh7100_audclk_get, priv); +} + +static const struct of_device_id jh7100_audclk_match[] = { + { .compatible = "starfive,jh7100-audclk" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, jh7100_audclk_match); + +static struct platform_driver jh7100_audclk_driver = { + .probe = jh7100_audclk_probe, + .driver = { + .name = "clk-starfive-jh7100-audio", + .of_match_table = jh7100_audclk_match, + }, +}; +module_platform_driver(jh7100_audclk_driver); + +MODULE_AUTHOR("Emil Renner Berthing"); +MODULE_DESCRIPTION("StarFive JH7100 audio clock driver"); +MODULE_LICENSE("GPL v2");