From patchwork Wed Jan 26 20:36:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 12725769 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 99013C2BA4C for ; Wed, 26 Jan 2022 20:36:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 320BB10E901; Wed, 26 Jan 2022 20:36:30 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8F37B10E705; Wed, 26 Jan 2022 20:36:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643229386; x=1674765386; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fT5raPuy4gQlCWtdlnkOy0l3+TfxT0XyYHiwiGiH8uo=; b=lI9fHdrsctMT9Bp/sNs7zmjUj8buzy3tIcHMoo0WinvmytFuHfEpizbX wruxTmRwc9JXD/ySziGpC9XvbQ8PBRPWl6HpS7s8SOsnL/257ne5xUy7Q IjJ4CCYzcADSU9WANSLpe68o/7M5Pe2/EcIE61Ys5LaA8xKh73BEzutH3 3RZNnUTec67Xr/xhFyLj28L2fSAoRwRsp0PipX/YBXtINg4QMcJoSSKyQ h9cgfbR54OAsezJ91GXdiJg6QLmciIY7ogreNcwHUpYHUYFdW9s9h9a98 HWgL669rJq5P/G1mUO9dPqW2ZX5y1Ds7qZlgHUQa4i6CFHdcrSpgTGzpc w==; X-IronPort-AV: E=McAfee;i="6200,9189,10239"; a="333000494" X-IronPort-AV: E=Sophos;i="5.88,319,1635231600"; d="scan'208";a="333000494" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2022 12:36:22 -0800 X-IronPort-AV: E=Sophos;i="5.88,319,1635231600"; d="scan'208";a="581221490" Received: from lucas-s2600cw.jf.intel.com ([10.165.21.202]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2022 12:36:22 -0800 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Subject: [PATCH 01/19] dma-buf-map: Add read/write helpers Date: Wed, 26 Jan 2022 12:36:44 -0800 Message-Id: <20220126203702.1784589-2-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.35.0 In-Reply-To: <20220126203702.1784589-1-lucas.demarchi@intel.com> References: <20220126203702.1784589-1-lucas.demarchi@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, =?utf-8?q?Christian_K=C3=B6nig?= , linaro-mm-sig@lists.linaro.org, linux-media@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" In certain situations it's useful to be able to read or write to an offset that is calculated by having the memory layout given by a struct declaration. Usually we are going to read/write a u8, u16, u32 or u64. Add a pair of macros dma_buf_map_read_field()/dma_buf_map_write_field() to calculate the offset of a struct member and memcpy the data from/to the dma_buf_map. We could use readb, readw, readl, readq and the write* counterparts, however due to alignment issues this may not work on all architectures. If alignment needs to be checked to call the right function, it's not possible to decide at compile-time which function to call: so just leave the decision to the memcpy function that will do exactly that on IO memory or dereference the pointer. Cc: Sumit Semwal Cc: Christian König Cc: linux-media@vger.kernel.org Cc: dri-devel@lists.freedesktop.org Cc: linaro-mm-sig@lists.linaro.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Lucas De Marchi --- include/linux/dma-buf-map.h | 81 +++++++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/include/linux/dma-buf-map.h b/include/linux/dma-buf-map.h index 19fa0b5ae5ec..65e927d9ce33 100644 --- a/include/linux/dma-buf-map.h +++ b/include/linux/dma-buf-map.h @@ -6,6 +6,7 @@ #ifndef __DMA_BUF_MAP_H__ #define __DMA_BUF_MAP_H__ +#include #include #include @@ -229,6 +230,46 @@ static inline void dma_buf_map_clear(struct dma_buf_map *map) } } +/** + * dma_buf_map_memcpy_to_offset - Memcpy into offset of dma-buf mapping + * @dst: The dma-buf mapping structure + * @offset: The offset from which to copy + * @src: The source buffer + * @len: The number of byte in src + * + * Copies data into a dma-buf mapping with an offset. The source buffer is in + * system memory. Depending on the buffer's location, the helper picks the + * correct method of accessing the memory. + */ +static inline void dma_buf_map_memcpy_to_offset(struct dma_buf_map *dst, size_t offset, + const void *src, size_t len) +{ + if (dst->is_iomem) + memcpy_toio(dst->vaddr_iomem + offset, src, len); + else + memcpy(dst->vaddr + offset, src, len); +} + +/** + * dma_buf_map_memcpy_from_offset - Memcpy from offset of dma-buf mapping into system memory + * @dst: Destination in system memory + * @src: The dma-buf mapping structure + * @src: The offset from which to copy + * @len: The number of byte in src + * + * Copies data from a dma-buf mapping with an offset. The dest buffer is in + * system memory. Depending on the mapping location, the helper picks the + * correct method of accessing the memory. + */ +static inline void dma_buf_map_memcpy_from_offset(void *dst, const struct dma_buf_map *src, + size_t offset, size_t len) +{ + if (src->is_iomem) + memcpy_fromio(dst, src->vaddr_iomem + offset, len); + else + memcpy(dst, src->vaddr + offset, len); +} + /** * dma_buf_map_memcpy_to - Memcpy into dma-buf mapping * @dst: The dma-buf mapping structure @@ -263,4 +304,44 @@ static inline void dma_buf_map_incr(struct dma_buf_map *map, size_t incr) map->vaddr += incr; } +/** + * dma_buf_map_read_field - Read struct member from dma-buf mapping with + * arbitrary size and handling un-aligned accesses + * + * @map__: The dma-buf mapping structure + * @type__: The struct to be used containing the field to read + * @field__: Member from struct we want to read + * + * Read a value from dma-buf mapping calculating the offset and size: this assumes + * the dma-buf mapping is aligned with a a struct type__. A single u8, u16, u32 + * or u64 can be read, based on the offset and size of type__.field__. + */ +#define dma_buf_map_read_field(map__, type__, field__) ({ \ + type__ *t__; \ + typeof(t__->field__) val__; \ + dma_buf_map_memcpy_from_offset(&val__, map__, offsetof(type__, field__), \ + sizeof(t__->field__)); \ + val__; \ +}) + +/** + * dma_buf_map_write_field - Write struct member to the dma-buf mapping with + * arbitrary size and handling un-aligned accesses + * + * @map__: The dma-buf mapping structure + * @type__: The struct to be used containing the field to write + * @field__: Member from struct we want to write + * @val__: Value to be written + * + * Write a value to the dma-buf mapping calculating the offset and size. + * A single u8, u16, u32 or u64 can be written based on the offset and size of + * type__.field__. + */ +#define dma_buf_map_write_field(map__, type__, field__, val__) ({ \ + type__ *t__; \ + typeof(t__->field__) val____ = val__; \ + dma_buf_map_memcpy_to_offset(map__, offsetof(type__, field__), \ + &val____, sizeof(t__->field__)); \ +}) + #endif /* __DMA_BUF_MAP_H__ */ From patchwork Wed Jan 26 20:36:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 12725779 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 09C92C2BA4C for ; Wed, 26 Jan 2022 20:37:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7FC5610E95E; Wed, 26 Jan 2022 20:36:33 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id B41B210E421; Wed, 26 Jan 2022 20:36:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643229386; x=1674765386; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=SxwOX/KvCGehbJ+xk/iHXJSG5hnovWhcQo3g+1qN37Y=; b=bMnqugziiU2pu2cOdKPsz+7UQMnwsOah3BxrFOhlmVLE0dnTgoFXve2G ngi/e0md8M3PpB9W48vQBpqHzRjisyNslDYyOW6rEaQC5NaIkAmwuYjpC pSPvR1/iPuZEpS1c+cc7vaAqNTon4I252U35+CCnmCYeVDx8istUJg+UR unMrhH/sHhwKtD9cuJ992N2bmFIAQM5XkXAsEl1IUY1lLXvsQnhCmcEyr A6JNADEzm1OMVEMfXXevcm3OSw1QJ6FuA1bb1ksA8LRnLQ2x7DOo1pova V4cFjO/FNcNicDZRQAESbsT6+LPkl85JH46XGEIvFg6ofbR8hIAm3reRi g==; X-IronPort-AV: E=McAfee;i="6200,9189,10239"; a="333000495" X-IronPort-AV: E=Sophos;i="5.88,319,1635231600"; d="scan'208";a="333000495" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2022 12:36:22 -0800 X-IronPort-AV: E=Sophos;i="5.88,319,1635231600"; d="scan'208";a="581221493" Received: from lucas-s2600cw.jf.intel.com ([10.165.21.202]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2022 12:36:22 -0800 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Subject: [PATCH 02/19] dma-buf-map: Add helper to initialize second map Date: Wed, 26 Jan 2022 12:36:45 -0800 Message-Id: <20220126203702.1784589-3-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.35.0 In-Reply-To: <20220126203702.1784589-1-lucas.demarchi@intel.com> References: <20220126203702.1784589-1-lucas.demarchi@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, =?utf-8?q?Christian_K=C3=B6nig?= , linaro-mm-sig@lists.linaro.org, linux-media@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" When dma_buf_map struct is passed around, it's useful to be able to initialize a second map that takes care of reading/writing to an offset of the original map. Add a helper that copies the struct and add the offset to the proper address. Cc: Sumit Semwal Cc: Christian König Cc: linux-media@vger.kernel.org Cc: dri-devel@lists.freedesktop.org Cc: linaro-mm-sig@lists.linaro.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Lucas De Marchi Acked-by: Daniel Vetter --- include/linux/dma-buf-map.h | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/include/linux/dma-buf-map.h b/include/linux/dma-buf-map.h index 65e927d9ce33..3514a859f628 100644 --- a/include/linux/dma-buf-map.h +++ b/include/linux/dma-buf-map.h @@ -131,6 +131,35 @@ struct dma_buf_map { .is_iomem = false, \ } +/** + * DMA_BUF_MAP_INIT_OFFSET - Initializes struct dma_buf_map from another dma_buf_map + * @map_: The dma-buf mapping structure to copy from + * @offset: Offset to add to the other mapping + * + * Initializes a new dma_buf_struct based on another. This is the equivalent of doing: + * + * .. code-block: c + * + * dma_buf_map map = other_map; + * dma_buf_map_incr(&map, &offset); + * + * Example usage: + * + * .. code-block: c + * + * void foo(struct device *dev, struct dma_buf_map *base_map) + * { + * ... + * struct dma_buf_map = DMA_BUF_MAP_INIT_OFFSET(base_map, FIELD_OFFSET); + * ... + * } + */ +#define DMA_BUF_MAP_INIT_OFFSET(map_, offset_) (struct dma_buf_map) \ + { \ + .vaddr = (map_)->vaddr + (offset_), \ + .is_iomem = (map_)->is_iomem, \ + } + /** * dma_buf_map_set_vaddr - Sets a dma-buf mapping structure to an address in system memory * @map: The dma-buf mapping structure From patchwork Wed Jan 26 20:36:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 12725768 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 32544C2BA4C for ; Wed, 26 Jan 2022 20:36:44 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1920910E804; Wed, 26 Jan 2022 20:36:28 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id E17FB10E705; Wed, 26 Jan 2022 20:36:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643229386; x=1674765386; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=N1JcWJhtFV0j9BhbtynUEaZW700UjalgFcxpWKXF3gk=; b=M/n68IcXFJMqbNUUrmJHpqaOSz2QPfnexO1p2vlpmNYR9/cDy9A5XQUV X6/1IdXW+QY4oXyOfdhg0VhmSCBO25iCNsB8yLUBPQo8VY0NB7a4nSNcE ycM5RYEtXgzfqHylXt2irsNFFWYAk8WF7Av3QMXQvDHLDLDwoWJ7eLLvw +HpyDrt0zkRECrlVruUlLrm3gN8fya4BsRvu4ps6InDmkljLGv/1D0cMY oNfUCPTGVyim+NYv+YuOcVncd/ugVTEErJn4wkUbayf5qeJq2N6WNA8Jj JUoqIHg/XXCnkMaUUyYUlSk3Tfc5/AF/w9r7PednvXrjtDdQcD7/cb2aW w==; X-IronPort-AV: E=McAfee;i="6200,9189,10239"; a="333000496" X-IronPort-AV: E=Sophos;i="5.88,319,1635231600"; d="scan'208";a="333000496" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2022 12:36:22 -0800 X-IronPort-AV: E=Sophos;i="5.88,319,1635231600"; d="scan'208";a="581221497" Received: from lucas-s2600cw.jf.intel.com ([10.165.21.202]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2022 12:36:22 -0800 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Subject: [PATCH 03/19] drm/i915/gt: Add helper for shmem copy to dma_buf_map Date: Wed, 26 Jan 2022 12:36:46 -0800 Message-Id: <20220126203702.1784589-4-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.35.0 In-Reply-To: <20220126203702.1784589-1-lucas.demarchi@intel.com> References: <20220126203702.1784589-1-lucas.demarchi@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tvrtko Ursulin , =?utf-8?q?Thomas_Hellst?= =?utf-8?q?r=C3=B6m?= , David Airlie , dri-devel@lists.freedesktop.org, Matthew Auld Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add a variant of shmem_read() that takes a dma_buf_map pointer rather than a plain pointer as argument. It's mostly a copy __shmem_rw() but adapting the api and removing the write support since there's currently only need to use dma_buf_map as destination. Reworking __shmem_rw() to share the implementation was tempting, but finding a good balance between reuse and clarity pushed towards a little code duplication. Since the function is small, just add the similar function with a copy/paste/adapt approach. Cc: Matt Roper Cc: Joonas Lahtinen Cc: Tvrtko Ursulin Cc: David Airlie Cc: Daniel Vetter Cc: Matthew Auld Cc: Thomas Hellström Cc: Maarten Lankhorst Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/gt/shmem_utils.c | 32 +++++++++++++++++++++++++++ drivers/gpu/drm/i915/gt/shmem_utils.h | 3 +++ 2 files changed, 35 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/shmem_utils.c b/drivers/gpu/drm/i915/gt/shmem_utils.c index 0683b27a3890..d7968e68ccfb 100644 --- a/drivers/gpu/drm/i915/gt/shmem_utils.c +++ b/drivers/gpu/drm/i915/gt/shmem_utils.c @@ -3,6 +3,7 @@ * Copyright © 2020 Intel Corporation */ +#include #include #include #include @@ -123,6 +124,37 @@ static int __shmem_rw(struct file *file, loff_t off, return 0; } +int shmem_read_to_dma_buf_map(struct file *file, loff_t off, + struct dma_buf_map *map, size_t len) +{ + struct dma_buf_map map_iter = *map; + unsigned long pfn; + + for (pfn = off >> PAGE_SHIFT; len; pfn++) { + unsigned int this = + min_t(size_t, PAGE_SIZE - offset_in_page(off), len); + struct page *page; + void *vaddr; + + page = shmem_read_mapping_page_gfp(file->f_mapping, pfn, + GFP_KERNEL); + if (IS_ERR(page)) + return PTR_ERR(page); + + vaddr = kmap(page); + dma_buf_map_memcpy_to(&map_iter, vaddr + offset_in_page(off), this); + mark_page_accessed(page); + kunmap(page); + put_page(page); + + len -= this; + dma_buf_map_incr(&map_iter, this); + off = 0; + } + + return 0; +} + int shmem_read(struct file *file, loff_t off, void *dst, size_t len) { return __shmem_rw(file, off, dst, len, false); diff --git a/drivers/gpu/drm/i915/gt/shmem_utils.h b/drivers/gpu/drm/i915/gt/shmem_utils.h index c1669170c351..a3d4ce966f74 100644 --- a/drivers/gpu/drm/i915/gt/shmem_utils.h +++ b/drivers/gpu/drm/i915/gt/shmem_utils.h @@ -8,6 +8,7 @@ #include +struct dma_buf_map; struct drm_i915_gem_object; struct file; @@ -17,6 +18,8 @@ struct file *shmem_create_from_object(struct drm_i915_gem_object *obj); void *shmem_pin_map(struct file *file); void shmem_unpin_map(struct file *file, void *ptr); +int shmem_read_to_dma_buf_map(struct file *file, loff_t off, + struct dma_buf_map *map, size_t len); int shmem_read(struct file *file, loff_t off, void *dst, size_t len); int shmem_write(struct file *file, loff_t off, void *src, size_t len); From patchwork Wed Jan 26 20:36:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 12725776 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 75D07C5DF62 for ; Wed, 26 Jan 2022 20:37:06 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8E4AE10E8FE; Wed, 26 Jan 2022 20:36:32 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 018E310E802; Wed, 26 Jan 2022 20:36:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643229387; x=1674765387; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tgargJNzKlTM8tDsHk4I1m9HBRI9PHrfYBs/SzQ0JCA=; b=LY/zdgFsn+zam4oi5TjeiZHqozZQN8DQKJjMFI+duHQxP0p8kifuo7UB eLObR/ymtS2ruFMy3/Ix24EHhw7TaeB4K0ixqCkQeviZDXDr5lW5ho8Nu 17MlegvInw2aFyNy/KqXZ/cG5bDb+SZ6RIkAcnfGWhpOUYfSf2ifmFXqK eG6q8dQg+6tkbla34SziRSaBjEesXNA41wx2+9AqhwWUjDEgQ1vJPLWum cLwJcjoNFvMHN09J8/hgZTqHsYr5Pb9qpDRuZbCKirIji8mWkw2mWxxmi al40xqnNOJzn2AHiNpJKLCMAcz7Si/8pLuz8/R85tCWAIhdbDt4cE2YyQ Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10239"; a="333000498" X-IronPort-AV: E=Sophos;i="5.88,319,1635231600"; d="scan'208";a="333000498" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2022 12:36:22 -0800 X-IronPort-AV: E=Sophos;i="5.88,319,1635231600"; d="scan'208";a="581221501" Received: from lucas-s2600cw.jf.intel.com ([10.165.21.202]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2022 12:36:22 -0800 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Subject: [PATCH 04/19] drm/i915/guc: Keep dma_buf_map of ads_blob around Date: Wed, 26 Jan 2022 12:36:47 -0800 Message-Id: <20220126203702.1784589-5-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.35.0 In-Reply-To: <20220126203702.1784589-1-lucas.demarchi@intel.com> References: <20220126203702.1784589-1-lucas.demarchi@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Matthew Brost , =?utf-8?q?Thomas_Hellstr=C3=B6m?= , dri-devel@lists.freedesktop.org, Daniele Ceraolo Spurio , John Harrison Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Convert intel_guc_ads_create() and initialization to use dma_buf_map rather than plain pointer and save it in the guc struct. This will help with additional updates to the ads_blob after the creation/initialization by abstracting the IO vs system memory. Cc: Matt Roper Cc: Thomas Hellström Cc: Daniel Vetter Cc: John Harrison Cc: Matthew Brost Cc: Daniele Ceraolo Spurio Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/gt/uc/intel_guc.h | 4 +++- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 6 ++++++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h index 697d9d66acef..e2e0df1c3d91 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h @@ -6,8 +6,9 @@ #ifndef _INTEL_GUC_H_ #define _INTEL_GUC_H_ -#include #include +#include +#include #include "intel_uncore.h" #include "intel_guc_fw.h" @@ -148,6 +149,7 @@ struct intel_guc { struct i915_vma *ads_vma; /** @ads_blob: contents of the GuC ADS */ struct __guc_ads_blob *ads_blob; + struct dma_buf_map ads_map; /** @ads_regset_size: size of the save/restore regsets in the ADS */ u32 ads_regset_size; /** @ads_golden_ctxt_size: size of the golden contexts in the ADS */ diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c index 668bf4ac9b0c..c012858376f0 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c @@ -623,6 +623,11 @@ int intel_guc_ads_create(struct intel_guc *guc) if (ret) return ret; + if (i915_gem_object_is_lmem(guc->ads_vma->obj)) + dma_buf_map_set_vaddr_iomem(&guc->ads_map, (void __iomem *)guc->ads_blob); + else + dma_buf_map_set_vaddr(&guc->ads_map, guc->ads_blob); + __guc_ads_init(guc); return 0; @@ -644,6 +649,7 @@ void intel_guc_ads_destroy(struct intel_guc *guc) { i915_vma_unpin_and_release(&guc->ads_vma, I915_VMA_RELEASE_MAP); guc->ads_blob = NULL; + dma_buf_map_clear(&guc->ads_map); } static void guc_ads_private_data_reset(struct intel_guc *guc) From patchwork Wed Jan 26 20:36:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 12725770 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5A50CC2BA4C for ; Wed, 26 Jan 2022 20:36:55 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5EC9210E905; Wed, 26 Jan 2022 20:36:30 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2B02910E804; Wed, 26 Jan 2022 20:36:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643229387; x=1674765387; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=i9SXXTzxPQ1P+9nF2qf0V+DxxwDMxeYlRcXvTTY7RFc=; b=DsBnfXOfYMuNdlppXTOBs+x/XT1it6DarjwE89dlylb7tZx8jc0cHmK4 T/gVdiixKAGtnjp8Fh8Ajxlwgc/qVzXDWfCqMxqtMAWWrmMYD/+PR5oTD 1/QAnxL4rwTF0Jg9WJkuU+HSwceRFTnAaa9cyOAkXtZ9+AM1acDO1jMqt Akwl0SSKiArgBj9oG3z0Boz8ypzhys4YmwExceeQWsqfPQHAKE+j1NkPi UKipecfYkdug5bYEC7aP+z8pt6it3jAS0OQOspGYvBR04m8+i2o0ZVltH TdAYeR7il9I9fc9/0FXvdP2GQ/OYDEfJuyS1yJrxLlmLhfMGk6Qzt02fk w==; X-IronPort-AV: E=McAfee;i="6200,9189,10239"; a="333000501" X-IronPort-AV: E=Sophos;i="5.88,319,1635231600"; d="scan'208";a="333000501" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2022 12:36:23 -0800 X-IronPort-AV: E=Sophos;i="5.88,319,1635231600"; d="scan'208";a="581221504" Received: from lucas-s2600cw.jf.intel.com ([10.165.21.202]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2022 12:36:22 -0800 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Subject: [PATCH 05/19] drm/i915/guc: Add read/write helpers for ADS blob Date: Wed, 26 Jan 2022 12:36:48 -0800 Message-Id: <20220126203702.1784589-6-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.35.0 In-Reply-To: <20220126203702.1784589-1-lucas.demarchi@intel.com> References: <20220126203702.1784589-1-lucas.demarchi@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Matthew Brost , =?utf-8?q?Thomas_Hellstr=C3=B6m?= , dri-devel@lists.freedesktop.org, Daniele Ceraolo Spurio , John Harrison Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add helpers on top of dma_buf_map_read_field() / dma_buf_map_write_field() functions so they always use the right arguments and make code easier to read. Cc: Matt Roper Cc: Thomas Hellström Cc: Daniel Vetter Cc: John Harrison Cc: Matthew Brost Cc: Daniele Ceraolo Spurio Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c index c012858376f0..01d2c1ead680 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c @@ -59,6 +59,14 @@ struct __guc_ads_blob { struct guc_mmio_reg regset[0]; } __packed; +#define ads_blob_read(guc_, field_) \ + dma_buf_map_read_field(&(guc_)->ads_map, struct __guc_ads_blob, \ + field_) + +#define ads_blob_write(guc_, field_, val_) \ + dma_buf_map_write_field(&(guc_)->ads_map, struct __guc_ads_blob,\ + field_, val_) + static u32 guc_ads_regset_size(struct intel_guc *guc) { GEM_BUG_ON(!guc->ads_regset_size); From patchwork Wed Jan 26 20:36:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 12725772 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 45ECAC2BA4C for ; Wed, 26 Jan 2022 20:36:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4A6F410E949; Wed, 26 Jan 2022 20:36:31 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1EDC010E421; Wed, 26 Jan 2022 20:36:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643229387; x=1674765387; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Ywn5t+uERBPsNyA7kStV3ap4UDQVPmgaxiuknWHkU7s=; b=VPy8Sh/ZkOsEjyy4LOMJDOAFkteY9mQEw/V8qcdS3EDp3Zem1DoZWXSW o0pJK5KVYLvigYeZqxDP72fX+IFwtynk4GVV6ovk5ZsFE/D/bLgYptal9 KadJqPRXIVvAy+mRsra/U+d41zHy8H/5q7lZvtvRZL5OprZ2NJxz6eFLS 6VGBtsH2kH1YUf2BcKyQ6T34MFCFEhaQdZ9DF582TqwqrKyliiZ81EIYr e++2zPDGjjKPjfS1dhxc5VQnhhLlZUCcQ6lMxFSZE64U3o0wih0pU7SD8 xpSW33470JzhUE+3FLkGCxfINIqLYoKMjAynhps235wguOQRiBgKALrmr g==; X-IronPort-AV: E=McAfee;i="6200,9189,10239"; a="333000502" X-IronPort-AV: E=Sophos;i="5.88,319,1635231600"; d="scan'208";a="333000502" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2022 12:36:23 -0800 X-IronPort-AV: E=Sophos;i="5.88,319,1635231600"; d="scan'208";a="581221509" Received: from lucas-s2600cw.jf.intel.com ([10.165.21.202]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2022 12:36:23 -0800 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Subject: [PATCH 06/19] drm/i915/guc: Convert golden context init to dma_buf_map Date: Wed, 26 Jan 2022 12:36:49 -0800 Message-Id: <20220126203702.1784589-7-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.35.0 In-Reply-To: <20220126203702.1784589-1-lucas.demarchi@intel.com> References: <20220126203702.1784589-1-lucas.demarchi@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Matthew Brost , =?utf-8?q?Thomas_Hellstr=C3=B6m?= , dri-devel@lists.freedesktop.org, Daniele Ceraolo Spurio , John Harrison Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Now the map is saved during creation, so use it to initialize the golden context, reading from shmem and writing to either system or IO memory. Cc: Matt Roper Cc: Thomas Hellström Cc: Daniel Vetter Cc: John Harrison Cc: Matthew Brost Cc: Daniele Ceraolo Spurio Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 25 +++++++++++----------- 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c index 01d2c1ead680..bcf52ac4fe35 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c @@ -473,18 +473,17 @@ static struct intel_engine_cs *find_engine_state(struct intel_gt *gt, u8 engine_ static void guc_init_golden_context(struct intel_guc *guc) { - struct __guc_ads_blob *blob = guc->ads_blob; struct intel_engine_cs *engine; struct intel_gt *gt = guc_to_gt(guc); + struct dma_buf_map golden_context_map; u32 addr_ggtt, offset; u32 total_size = 0, alloc_size, real_size; u8 engine_class, guc_class; - u8 *ptr; if (!intel_uc_uses_guc_submission(>->uc)) return; - GEM_BUG_ON(!blob); + GEM_BUG_ON(dma_buf_map_is_null(&guc->ads_map)); /* * Go back and fill in the golden context data now that it is @@ -492,15 +491,15 @@ static void guc_init_golden_context(struct intel_guc *guc) */ offset = guc_ads_golden_ctxt_offset(guc); addr_ggtt = intel_guc_ggtt_offset(guc, guc->ads_vma) + offset; - ptr = ((u8 *)blob) + offset; + + golden_context_map = DMA_BUF_MAP_INIT_OFFSET(&guc->ads_map, offset); for (engine_class = 0; engine_class <= MAX_ENGINE_CLASS; ++engine_class) { if (engine_class == OTHER_CLASS) continue; guc_class = engine_class_to_guc_class(engine_class); - - if (!blob->system_info.engine_enabled_masks[guc_class]) + if (!ads_blob_read(guc, system_info.engine_enabled_masks[guc_class])) continue; real_size = intel_engine_context_size(gt, engine_class); @@ -511,18 +510,20 @@ static void guc_init_golden_context(struct intel_guc *guc) if (!engine) { drm_err(>->i915->drm, "No engine state recorded for class %d!\n", engine_class); - blob->ads.eng_state_size[guc_class] = 0; - blob->ads.golden_context_lrca[guc_class] = 0; + ads_blob_write(guc, ads.eng_state_size[guc_class], 0); + ads_blob_write(guc, ads.golden_context_lrca[guc_class], 0); continue; } - GEM_BUG_ON(blob->ads.eng_state_size[guc_class] != + GEM_BUG_ON(ads_blob_read(guc, ads.eng_state_size[guc_class]) != real_size - LRC_SKIP_SIZE); - GEM_BUG_ON(blob->ads.golden_context_lrca[guc_class] != addr_ggtt); + GEM_BUG_ON(ads_blob_read(guc, ads.golden_context_lrca[guc_class]) != addr_ggtt); + addr_ggtt += alloc_size; - shmem_read(engine->default_state, 0, ptr, real_size); - ptr += alloc_size; + shmem_read_to_dma_buf_map(engine->default_state, 0, + &golden_context_map, real_size); + dma_buf_map_incr(&golden_context_map, alloc_size); } GEM_BUG_ON(guc->ads_golden_ctxt_size != total_size); From patchwork Wed Jan 26 20:36:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 12725775 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E73C0C63697 for ; Wed, 26 Jan 2022 20:37:04 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9A11F10E94F; Wed, 26 Jan 2022 20:36:31 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5AFDD10E705; Wed, 26 Jan 2022 20:36:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643229387; x=1674765387; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=uwxizS0ftqSGbGdMPpj6u6yBfEnV5Zw7wY3WlI+UJD8=; b=NDNHJoAA2y7AOCpu5bYb2HeXwhxUD0X8yE3dEGI8il+vq5g25TAml/ji ss5JOUK/rGkaZfhaH4mURbJcmIjYAf5Vwyd8DJgQLFzVgTU0J0tzkK3oL D/dnSe/Y/QD2gkWxlcxz+CvPnBDr29kfAov652UaGGHA0oUIqqqsnUlnn WmTjY+WvnMqPhTeBZr3cRGAHlR/hi52JqQbkGZZk7IQMep45gSv/MCGuZ GR4vhv2vEiBDP1fQxl9PNKGeTKUJ9Zg1+6c3yH5ijur34lEzqYBoXtynU txbPnsqGlVEOIkY9mP/Z9a2+3xoxgzJq0mAz4jzlfSbZcKSrxwRkqvlw7 w==; X-IronPort-AV: E=McAfee;i="6200,9189,10239"; a="333000503" X-IronPort-AV: E=Sophos;i="5.88,319,1635231600"; d="scan'208";a="333000503" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2022 12:36:23 -0800 X-IronPort-AV: E=Sophos;i="5.88,319,1635231600"; d="scan'208";a="581221512" Received: from lucas-s2600cw.jf.intel.com ([10.165.21.202]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2022 12:36:23 -0800 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Subject: [PATCH 07/19] drm/i915/guc: Convert policies update to dma_buf_map Date: Wed, 26 Jan 2022 12:36:50 -0800 Message-Id: <20220126203702.1784589-8-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.35.0 In-Reply-To: <20220126203702.1784589-1-lucas.demarchi@intel.com> References: <20220126203702.1784589-1-lucas.demarchi@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Matthew Brost , =?utf-8?q?Thomas_Hellstr=C3=B6m?= , dri-devel@lists.freedesktop.org, Daniele Ceraolo Spurio , John Harrison Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Use dma_buf_map to write the policies update so access to IO and system memory is abstracted away. Cc: Matt Roper Cc: Thomas Hellström Cc: Daniel Vetter Cc: John Harrison Cc: Matthew Brost Cc: Daniele Ceraolo Spurio Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 41 ++++++++++++---------- 1 file changed, 23 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c index bcf52ac4fe35..2ffe5836f95e 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c @@ -130,33 +130,37 @@ static u32 guc_ads_blob_size(struct intel_guc *guc) guc_ads_private_data_size(guc); } -static void guc_policies_init(struct intel_guc *guc, struct guc_policies *policies) +static void guc_policies_init(struct intel_guc *guc) { struct intel_gt *gt = guc_to_gt(guc); struct drm_i915_private *i915 = gt->i915; + u32 global_flags = 0; - policies->dpc_promote_time = GLOBAL_POLICY_DEFAULT_DPC_PROMOTE_TIME_US; - policies->max_num_work_items = GLOBAL_POLICY_MAX_NUM_WI; + ads_blob_write(guc, policies.dpc_promote_time, + GLOBAL_POLICY_DEFAULT_DPC_PROMOTE_TIME_US); + ads_blob_write(guc, policies.max_num_work_items, + GLOBAL_POLICY_MAX_NUM_WI); - policies->global_flags = 0; if (i915->params.reset < 2) - policies->global_flags |= GLOBAL_POLICY_DISABLE_ENGINE_RESET; + global_flags |= GLOBAL_POLICY_DISABLE_ENGINE_RESET; - policies->is_valid = 1; + ads_blob_write(guc, policies.global_flags, global_flags); + ads_blob_write(guc, policies.is_valid, 1); } void intel_guc_ads_print_policy_info(struct intel_guc *guc, struct drm_printer *dp) { - struct __guc_ads_blob *blob = guc->ads_blob; - - if (unlikely(!blob)) + if (unlikely(dma_buf_map_is_null(&guc->ads_map))) return; drm_printf(dp, "Global scheduling policies:\n"); - drm_printf(dp, " DPC promote time = %u\n", blob->policies.dpc_promote_time); - drm_printf(dp, " Max num work items = %u\n", blob->policies.max_num_work_items); - drm_printf(dp, " Flags = %u\n", blob->policies.global_flags); + drm_printf(dp, " DPC promote time = %u\n", + ads_blob_read(guc, policies.dpc_promote_time)); + drm_printf(dp, " Max num work items = %u\n", + ads_blob_read(guc, policies.max_num_work_items)); + drm_printf(dp, " Flags = %u\n", + ads_blob_read(guc, policies.global_flags)); } static int guc_action_policies_update(struct intel_guc *guc, u32 policy_offset) @@ -171,23 +175,24 @@ static int guc_action_policies_update(struct intel_guc *guc, u32 policy_offset) int intel_guc_global_policies_update(struct intel_guc *guc) { - struct __guc_ads_blob *blob = guc->ads_blob; struct intel_gt *gt = guc_to_gt(guc); + u32 scheduler_policies; intel_wakeref_t wakeref; int ret; - if (!blob) + if (dma_buf_map_is_null(&guc->ads_map)) return -EOPNOTSUPP; - GEM_BUG_ON(!blob->ads.scheduler_policies); + scheduler_policies = ads_blob_read(guc, ads.scheduler_policies); + GEM_BUG_ON(!scheduler_policies); - guc_policies_init(guc, &blob->policies); + guc_policies_init(guc); if (!intel_guc_is_ready(guc)) return 0; with_intel_runtime_pm(>->i915->runtime_pm, wakeref) - ret = guc_action_policies_update(guc, blob->ads.scheduler_policies); + ret = guc_action_policies_update(guc, scheduler_policies); return ret; } @@ -557,7 +562,7 @@ static void __guc_ads_init(struct intel_guc *guc) u32 base; /* GuC scheduling policies */ - guc_policies_init(guc, &blob->policies); + guc_policies_init(guc); /* System info */ fill_engine_enable_masks(gt, &blob->system_info); From patchwork Wed Jan 26 20:36:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 12725781 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DD7D1C63684 for ; Wed, 26 Jan 2022 20:37:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7F46810E942; Wed, 26 Jan 2022 20:36:33 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 76D2410E421; Wed, 26 Jan 2022 20:36:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643229387; x=1674765387; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Wjra7qj+Jb90MP4e8anE/k/B8s165O1uD6Gx6XBX3sk=; b=aNRgE2xxfZxTAOSg9Qd6DTGwTfqyJPmMcdbLdDMbxpvz0tfXJ/Ye9o+G /ovI0SabKB6s9Nu3a2xWUEwHeaeOqes5aMVqdtlIqelH8Rb6s5mNHD96a 8JG40VAl6Lh6gwU4U+DHul0ExK+2VuEEzglSN2mZlJmZxpysEMiWqhf1G 6l35Xuif+hDIASDPU/sjfTIOWLEWThYQtXoyi2ZVEow50TRbcpGjwlHQw 2tCjd+QYXz2CmVlTnzhTr83M8phj0dIEg2OzW3X3LGNmp7sxb+0kcX+ii UYCjY9mnD18yl6t9VCSbErIQqvksGDX/FjsLnT80iFxSAikdLW/JnFEI1 Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10239"; a="333000504" X-IronPort-AV: E=Sophos;i="5.88,319,1635231600"; d="scan'208";a="333000504" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2022 12:36:23 -0800 X-IronPort-AV: E=Sophos;i="5.88,319,1635231600"; d="scan'208";a="581221516" Received: from lucas-s2600cw.jf.intel.com ([10.165.21.202]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2022 12:36:23 -0800 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Subject: [PATCH 08/19] drm/i915/guc: Convert engine record to dma_buf_map Date: Wed, 26 Jan 2022 12:36:51 -0800 Message-Id: <20220126203702.1784589-9-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.35.0 In-Reply-To: <20220126203702.1784589-1-lucas.demarchi@intel.com> References: <20220126203702.1784589-1-lucas.demarchi@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Matthew Brost , =?utf-8?q?Thomas_Hellstr=C3=B6m?= , dri-devel@lists.freedesktop.org, Daniele Ceraolo Spurio , John Harrison Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Use dma_buf_map to read fields from the dma_blob so access to IO and system memory is abstracted away. Cc: Matt Roper Cc: Thomas Hellström Cc: Daniel Vetter Cc: John Harrison Cc: Matthew Brost Cc: Daniele Ceraolo Spurio Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 14 ++++++-------- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h | 3 ++- drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 11 +++++++---- 3 files changed, 15 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c index 2ffe5836f95e..fe1e71adfca1 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c @@ -698,18 +698,16 @@ void intel_guc_ads_reset(struct intel_guc *guc) u32 intel_guc_engine_usage_offset(struct intel_guc *guc) { - struct __guc_ads_blob *blob = guc->ads_blob; - u32 base = intel_guc_ggtt_offset(guc, guc->ads_vma); - u32 offset = base + ptr_offset(blob, engine_usage); - - return offset; + return intel_guc_ggtt_offset(guc, guc->ads_vma) + + offsetof(struct __guc_ads_blob, engine_usage); } -struct guc_engine_usage_record *intel_guc_engine_usage(struct intel_engine_cs *engine) +struct dma_buf_map intel_guc_engine_usage_record_map(struct intel_engine_cs *engine) { struct intel_guc *guc = &engine->gt->uc.guc; - struct __guc_ads_blob *blob = guc->ads_blob; u8 guc_class = engine_class_to_guc_class(engine->class); + size_t offset = offsetof(struct __guc_ads_blob, + engine_usage.engines[guc_class][ilog2(engine->logical_mask)]); - return &blob->engine_usage.engines[guc_class][ilog2(engine->logical_mask)]; + return DMA_BUF_MAP_INIT_OFFSET(&guc->ads_map, offset); } diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h index e74c110facff..27f5b1f9ddac 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h @@ -7,6 +7,7 @@ #define _INTEL_GUC_ADS_H_ #include +#include struct intel_guc; struct drm_printer; @@ -18,7 +19,7 @@ void intel_guc_ads_init_late(struct intel_guc *guc); void intel_guc_ads_reset(struct intel_guc *guc); void intel_guc_ads_print_policy_info(struct intel_guc *guc, struct drm_printer *p); -struct guc_engine_usage_record *intel_guc_engine_usage(struct intel_engine_cs *engine); +struct dma_buf_map intel_guc_engine_usage_record_map(struct intel_engine_cs *engine); u32 intel_guc_engine_usage_offset(struct intel_guc *guc); #endif diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index db9615dcb0ec..57bfb4ad0ab8 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -1125,14 +1125,17 @@ __extend_last_switch(struct intel_guc *guc, u64 *prev_start, u32 new_start) *prev_start = ((u64)gt_stamp_hi << 32) | new_start; } +#define record_read(map_, field_) \ + dma_buf_map_read_field(map_, struct guc_engine_usage_record, field_) + static void guc_update_engine_gt_clks(struct intel_engine_cs *engine) { - struct guc_engine_usage_record *rec = intel_guc_engine_usage(engine); + struct dma_buf_map rec_map = intel_guc_engine_usage_record_map(engine); struct intel_engine_guc_stats *stats = &engine->stats.guc; struct intel_guc *guc = &engine->gt->uc.guc; - u32 last_switch = rec->last_switch_in_stamp; - u32 ctx_id = rec->current_context_index; - u32 total = rec->total_runtime; + u32 last_switch = record_read(&rec_map, last_switch_in_stamp); + u32 ctx_id = record_read(&rec_map, current_context_index); + u32 total = record_read(&rec_map, total_runtime); lockdep_assert_held(&guc->timestamp.lock); From patchwork Wed Jan 26 20:36:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 12725786 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 545E4C5DF62 for ; Wed, 26 Jan 2022 20:37:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B9ACF10E963; Wed, 26 Jan 2022 20:36:44 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9CFFD10E802; Wed, 26 Jan 2022 20:36:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643229387; x=1674765387; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IrlXjlrSWxXOy2UwGYcFGyJqa/q0NhSjnDXBLVc54aM=; b=PF6ElnBFQKkhQxfe/7+bqkSQ1NVaqiHcfvyxwetyvgQtHZMHi6HGrabz CGiwIczEVw9wAdPCDunMjV6hkemhdUdG2mfMLy9rGf09of4UBDTTJyl9/ azrIDS/oHZBvBt0sRVVi9Mykvzz3z3rbQJsHs9QLstfDnXvTNdyrac6wV L8zu2gQkC91ljMau63OFUWB0SqA5pIAsK5TnL8e/hlyCiNR4jOa/LKHUI Ge7LVt0wMHEKFeBgNCWXw8wwmvTp9eM90k5T93A2JGLaJGQbcvfLbGdPc MtjkME+OgY5arDCwYEDyNshWLDxCaSkczprOKXwWYHE/24j5TI+a7gYPU w==; X-IronPort-AV: E=McAfee;i="6200,9189,10239"; a="333000505" X-IronPort-AV: E=Sophos;i="5.88,319,1635231600"; d="scan'208";a="333000505" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2022 12:36:23 -0800 X-IronPort-AV: E=Sophos;i="5.88,319,1635231600"; d="scan'208";a="581221519" Received: from lucas-s2600cw.jf.intel.com ([10.165.21.202]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2022 12:36:23 -0800 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Subject: [PATCH 09/19] dma-buf-map: Add wrapper over memset Date: Wed, 26 Jan 2022 12:36:52 -0800 Message-Id: <20220126203702.1784589-10-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.35.0 In-Reply-To: <20220126203702.1784589-1-lucas.demarchi@intel.com> References: <20220126203702.1784589-1-lucas.demarchi@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, =?utf-8?q?Christian_K=C3=B6nig?= , linaro-mm-sig@lists.linaro.org, linux-media@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Just like memcpy_toio(), there is also need to write a direct value to a memory block. Add dma_buf_map_memset() to abstract memset() vs memset_io() Cc: Matt Roper Cc: Sumit Semwal Cc: Christian König Cc: linux-media@vger.kernel.org Cc: dri-devel@lists.freedesktop.org Cc: linaro-mm-sig@lists.linaro.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Lucas De Marchi --- include/linux/dma-buf-map.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/include/linux/dma-buf-map.h b/include/linux/dma-buf-map.h index 3514a859f628..c9fb04264cd0 100644 --- a/include/linux/dma-buf-map.h +++ b/include/linux/dma-buf-map.h @@ -317,6 +317,23 @@ static inline void dma_buf_map_memcpy_to(struct dma_buf_map *dst, const void *sr memcpy(dst->vaddr, src, len); } +/** + * dma_buf_map_memset - Memset into dma-buf mapping + * @dst: The dma-buf mapping structure + * @value: The value to set + * @len: The number of bytes to set in dst + * + * Set value in dma-buf mapping. Depending on the buffer's location, the helper + * picks the correct method of accessing the memory. + */ +static inline void dma_buf_map_memset(struct dma_buf_map *dst, int value, size_t len) +{ + if (dst->is_iomem) + memset_io(dst->vaddr_iomem, value, len); + else + memset(dst->vaddr, value, len); +} + /** * dma_buf_map_incr - Increments the address stored in a dma-buf mapping * @map: The dma-buf mapping structure From patchwork Wed Jan 26 20:36:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 12725771 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 70AEEC2BA4C for ; Wed, 26 Jan 2022 20:36:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4A3E410E948; Wed, 26 Jan 2022 20:36:31 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id A71F110E804; Wed, 26 Jan 2022 20:36:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643229387; x=1674765387; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=YL9g6mxphtGpceT8p5dx9hnpQ0pfIWes8938xxVyozA=; b=ZEPDutx/8UKOqv2pU+K0wzxaqT/jZp5eufNPfcYMfqfegJloxiMC3GPA 5pxU/poMMtNyPQap8eHvXkOpM3EA5149hq2Zkbn7rCYVwHmuAGLvc12Dk A3ONCI/uc2DPTptVmm81UgqxLaLLUenzzLUMPHwb52QSi3GLUrvBpbw5g TxM8U8GYFw2OHOejbY4Uf1FACBhxP9sCEYCQR3OtTXoUGC2QfNbYW0nEz ofozXma80UvTz0ID/q4KFBRPx0kfjCNzcvDFZM9QwvCshg+INgLU20vRr uSUq/WfdDxk94G2ab19b3vhRW53/LHRTRO/vDDxQCvPkfdMioNhR4ZumB Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10239"; a="333000508" X-IronPort-AV: E=Sophos;i="5.88,319,1635231600"; d="scan'208";a="333000508" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2022 12:36:24 -0800 X-IronPort-AV: E=Sophos;i="5.88,319,1635231600"; d="scan'208";a="581221522" Received: from lucas-s2600cw.jf.intel.com ([10.165.21.202]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2022 12:36:23 -0800 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Subject: [PATCH 10/19] drm/i915/guc: Convert guc_ads_private_data_reset to dma_buf_map Date: Wed, 26 Jan 2022 12:36:53 -0800 Message-Id: <20220126203702.1784589-11-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.35.0 In-Reply-To: <20220126203702.1784589-1-lucas.demarchi@intel.com> References: <20220126203702.1784589-1-lucas.demarchi@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Matthew Brost , =?utf-8?q?Thomas_Hellstr=C3=B6m?= , dri-devel@lists.freedesktop.org, Daniele Ceraolo Spurio , John Harrison Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Use dma_buf_map_memset() to zero the private data as ADS may be either on system or IO memory. Cc: Matt Roper Cc: Thomas Hellström Cc: Daniel Vetter Cc: John Harrison Cc: Matthew Brost Cc: Daniele Ceraolo Spurio Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c index fe1e71adfca1..15990c229b54 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c @@ -668,14 +668,15 @@ void intel_guc_ads_destroy(struct intel_guc *guc) static void guc_ads_private_data_reset(struct intel_guc *guc) { + struct dma_buf_map map = + DMA_BUF_MAP_INIT_OFFSET(&guc->ads_map, guc_ads_private_data_offset(guc)); u32 size; size = guc_ads_private_data_size(guc); if (!size) return; - memset((void *)guc->ads_blob + guc_ads_private_data_offset(guc), 0, - size); + dma_buf_map_memset(&map, 0, size); } /** From patchwork Wed Jan 26 20:36:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 12725777 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F17FCC63684 for ; Wed, 26 Jan 2022 20:37:07 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 23B8810E944; Wed, 26 Jan 2022 20:36:33 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id B737510E421; Wed, 26 Jan 2022 20:36:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643229387; x=1674765387; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tQtmaVrXl7+K/Uv3zF/T300SRczXaYeJygF3204NcJE=; b=Qg7isgOwBlHkuVTqKK1tmAgNFUKmSOIKS50Wj+C0a1O7sG2ca+IRJFkv 6/yKdSTdJhSOTDYzrLe/RHcGj+cgTBUcN1THh3uHmMZIKvzTceb/M0es1 tkb+qUNg0Nl8jXsWaqNxDSAztkpeOP2HuT+St/EJ9SIBN/5UTxJdggPns CRrJWAkQ0+rXD6N7f5bncI7uN3ahRXxbcE9u49g9AoPAeVS0Ap/ED6fOY UnemgBQRExPW0AE4kgqStf6Ugf/siii3MhCfxCKH2K/dyQQnb3cCaFOJf XQYxzzX9JqzvEZCkGasaB+7ErCmAbLs6lsZazhvtFvxD/bennxYUfC2VM Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10239"; a="333000511" X-IronPort-AV: E=Sophos;i="5.88,319,1635231600"; d="scan'208";a="333000511" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2022 12:36:24 -0800 X-IronPort-AV: E=Sophos;i="5.88,319,1635231600"; d="scan'208";a="581221525" Received: from lucas-s2600cw.jf.intel.com ([10.165.21.202]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2022 12:36:24 -0800 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Subject: [PATCH 11/19] drm/i915/guc: Convert golden context prep to dma_buf_map Date: Wed, 26 Jan 2022 12:36:54 -0800 Message-Id: <20220126203702.1784589-12-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.35.0 In-Reply-To: <20220126203702.1784589-1-lucas.demarchi@intel.com> References: <20220126203702.1784589-1-lucas.demarchi@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Matthew Brost , =?utf-8?q?Thomas_Hellstr=C3=B6m?= , dri-devel@lists.freedesktop.org, Daniele Ceraolo Spurio , John Harrison Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Use the saved ads_map to prepare the golden context. One difference from the init context is that this function can be called before there is a gem object (and thus the guc->ads_map) to calculare the size of the golden context that should be allocated for that object. So in this case the function needs to be prepared for not having the system_info with enabled engines filled out. To accomplish that an info_map is prepared on the side to point either to the gem object or the local variable on the stack. This allows making fill_engine_enable_masks() operate always with a dma_buf_map argument. Cc: Matt Roper Cc: Thomas Hellström Cc: Daniel Vetter Cc: John Harrison Cc: Matthew Brost Cc: Daniele Ceraolo Spurio Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 52 +++++++++++++--------- 1 file changed, 32 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c index 15990c229b54..dd9ec47eed16 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c @@ -67,6 +67,12 @@ struct __guc_ads_blob { dma_buf_map_write_field(&(guc_)->ads_map, struct __guc_ads_blob,\ field_, val_) +#define info_map_write(map_, field_, val_) \ + dma_buf_map_write_field(map_, struct guc_gt_system_info, field_, val_) + +#define info_map_read(map_, field_) \ + dma_buf_map_read_field(map_, struct guc_gt_system_info, field_) + static u32 guc_ads_regset_size(struct intel_guc *guc) { GEM_BUG_ON(!guc->ads_regset_size); @@ -378,24 +384,24 @@ static void guc_mmio_reg_state_init(struct intel_guc *guc, } static void fill_engine_enable_masks(struct intel_gt *gt, - struct guc_gt_system_info *info) + struct dma_buf_map *info_map) { - info->engine_enabled_masks[GUC_RENDER_CLASS] = 1; - info->engine_enabled_masks[GUC_BLITTER_CLASS] = 1; - info->engine_enabled_masks[GUC_VIDEO_CLASS] = VDBOX_MASK(gt); - info->engine_enabled_masks[GUC_VIDEOENHANCE_CLASS] = VEBOX_MASK(gt); + info_map_write(info_map, engine_enabled_masks[GUC_RENDER_CLASS], 1); + info_map_write(info_map, engine_enabled_masks[GUC_BLITTER_CLASS], 1); + info_map_write(info_map, engine_enabled_masks[GUC_VIDEO_CLASS], VDBOX_MASK(gt)); + info_map_write(info_map, engine_enabled_masks[GUC_VIDEOENHANCE_CLASS], VEBOX_MASK(gt)); } #define LR_HW_CONTEXT_SIZE (80 * sizeof(u32)) #define LRC_SKIP_SIZE (LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE) -static int guc_prep_golden_context(struct intel_guc *guc, - struct __guc_ads_blob *blob) +static int guc_prep_golden_context(struct intel_guc *guc) { struct intel_gt *gt = guc_to_gt(guc); u32 addr_ggtt, offset; u32 total_size = 0, alloc_size, real_size; u8 engine_class, guc_class; - struct guc_gt_system_info *info, local_info; + struct guc_gt_system_info local_info; + struct dma_buf_map info_map; /* * Reserve the memory for the golden contexts and point GuC at it but @@ -409,14 +415,15 @@ static int guc_prep_golden_context(struct intel_guc *guc, * GuC will also validate that the LRC base + size fall within the * allowed GGTT range. */ - if (blob) { + if (!dma_buf_map_is_null(&guc->ads_map)) { offset = guc_ads_golden_ctxt_offset(guc); addr_ggtt = intel_guc_ggtt_offset(guc, guc->ads_vma) + offset; - info = &blob->system_info; + info_map = DMA_BUF_MAP_INIT_OFFSET(&guc->ads_map, + offsetof(struct __guc_ads_blob, system_info)); } else { memset(&local_info, 0, sizeof(local_info)); - info = &local_info; - fill_engine_enable_masks(gt, info); + dma_buf_map_set_vaddr(&info_map, &local_info); + fill_engine_enable_masks(gt, &info_map); } for (engine_class = 0; engine_class <= MAX_ENGINE_CLASS; ++engine_class) { @@ -425,14 +432,14 @@ static int guc_prep_golden_context(struct intel_guc *guc, guc_class = engine_class_to_guc_class(engine_class); - if (!info->engine_enabled_masks[guc_class]) + if (!info_map_read(&info_map, engine_enabled_masks[guc_class])) continue; real_size = intel_engine_context_size(gt, engine_class); alloc_size = PAGE_ALIGN(real_size); total_size += alloc_size; - if (!blob) + if (dma_buf_map_is_null(&guc->ads_map)) continue; /* @@ -446,12 +453,15 @@ static int guc_prep_golden_context(struct intel_guc *guc, * what comes before it in the context image (which is identical * on all engines). */ - blob->ads.eng_state_size[guc_class] = real_size - LRC_SKIP_SIZE; - blob->ads.golden_context_lrca[guc_class] = addr_ggtt; + ads_blob_write(guc, ads.eng_state_size[guc_class], + real_size - LRC_SKIP_SIZE); + ads_blob_write(guc, ads.golden_context_lrca[guc_class], + addr_ggtt); + addr_ggtt += alloc_size; } - if (!blob) + if (dma_buf_map_is_null(&guc->ads_map)) return total_size; GEM_BUG_ON(guc->ads_golden_ctxt_size != total_size); @@ -559,13 +569,15 @@ static void __guc_ads_init(struct intel_guc *guc) struct intel_gt *gt = guc_to_gt(guc); struct drm_i915_private *i915 = gt->i915; struct __guc_ads_blob *blob = guc->ads_blob; + struct dma_buf_map info_map = DMA_BUF_MAP_INIT_OFFSET(&guc->ads_map, + offsetof(struct __guc_ads_blob, system_info)); u32 base; /* GuC scheduling policies */ guc_policies_init(guc); /* System info */ - fill_engine_enable_masks(gt, &blob->system_info); + fill_engine_enable_masks(gt, &info_map); blob->system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_SLICE_ENABLED] = hweight8(gt->info.sseu.slice_mask); @@ -581,7 +593,7 @@ static void __guc_ads_init(struct intel_guc *guc) } /* Golden contexts for re-initialising after a watchdog reset */ - guc_prep_golden_context(guc, blob); + guc_prep_golden_context(guc); guc_mapping_table_init(guc_to_gt(guc), &blob->system_info); @@ -624,7 +636,7 @@ int intel_guc_ads_create(struct intel_guc *guc) guc->ads_regset_size = ret; /* Likewise the golden contexts: */ - ret = guc_prep_golden_context(guc, NULL); + ret = guc_prep_golden_context(guc); if (ret < 0) return ret; guc->ads_golden_ctxt_size = ret; From patchwork Wed Jan 26 20:36:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 12725778 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 96EBCC5DF62 for ; Wed, 26 Jan 2022 20:37:09 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6D25310E94B; Wed, 26 Jan 2022 20:36:31 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id C4EFA10E705; Wed, 26 Jan 2022 20:36:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643229387; x=1674765387; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5kSZoar6nlEfqZa5tDaufHgc1xCfnJq/vZPkOM+Iu0k=; b=cH/pnI9UyaKoX82ht4fRnLN69Th4XjTdNPpPSNay4WNWT8woPzeZ10tE 0ZJmtd1u23ecoDG+TEuSQIggk+OcmCmZH3Uf5O2tk4h19yBg+c5fwHUHv kw95sdLW7//uqCivg2zsBvuY9paTbzAaFArcfj+zHhd8gfT/bH2ttcRo+ Z2iZnEizg1HWtd0qdbfHpLhzFwIEH1ZOOq0gl9nsj9O1Agl/9w/ve1XEP 9Af19jiKJfXJrRKb34y/bgVH1/EYZszeOLFRXKUdXcVV5smc/z06iakI1 luskz4wpASVxWl5lf5GUQo3meLOdXWa4yXyjrzGYw1PpumURByfS1s59E Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10239"; a="333000512" X-IronPort-AV: E=Sophos;i="5.88,319,1635231600"; d="scan'208";a="333000512" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2022 12:36:24 -0800 X-IronPort-AV: E=Sophos;i="5.88,319,1635231600"; d="scan'208";a="581221528" Received: from lucas-s2600cw.jf.intel.com ([10.165.21.202]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2022 12:36:24 -0800 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Subject: [PATCH 12/19] drm/i915/guc: Replace check for golden context size Date: Wed, 26 Jan 2022 12:36:55 -0800 Message-Id: <20220126203702.1784589-13-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.35.0 In-Reply-To: <20220126203702.1784589-1-lucas.demarchi@intel.com> References: <20220126203702.1784589-1-lucas.demarchi@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Matthew Brost , =?utf-8?q?Thomas_Hellstr=C3=B6m?= , dri-devel@lists.freedesktop.org, Daniele Ceraolo Spurio , John Harrison Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" In the other places in this function, guc->ads_map is being protected from access when it's not yet set. However the last check is actually about guc->ads_golden_ctxt_size been set before. These checks should always match as the size is initialized on the first call to guc_prep_golden_context(), but it's clearer if we have a single return and check for guc->ads_golden_ctxt_size. This is just a readability improvement, no change in behavior. Cc: Matt Roper Cc: Thomas Hellström Cc: Daniel Vetter Cc: John Harrison Cc: Matthew Brost Cc: Daniele Ceraolo Spurio Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c index dd9ec47eed16..8e4768289792 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c @@ -461,10 +461,10 @@ static int guc_prep_golden_context(struct intel_guc *guc) addr_ggtt += alloc_size; } - if (dma_buf_map_is_null(&guc->ads_map)) - return total_size; + /* Make sure current size matches what we calculated previously */ + if (guc->ads_golden_ctxt_size) + GEM_BUG_ON(guc->ads_golden_ctxt_size != total_size); - GEM_BUG_ON(guc->ads_golden_ctxt_size != total_size); return total_size; } From patchwork Wed Jan 26 20:36:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 12725774 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5AA4FC5DF62 for ; Wed, 26 Jan 2022 20:37:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BA1E510E954; Wed, 26 Jan 2022 20:36:31 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id D991510E802; Wed, 26 Jan 2022 20:36:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643229388; x=1674765388; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wvaX2JPdSHUYHOOHVGj913/CgerpbT8u5T6WEedTlfM=; b=i7kpZvRjLWtARpZ5YVz6vEpA9388dXBfglwJtsFAerV+vahXgP9Wltvt KB6/MrV9N5lVgFoeaV4uyWvDgtv3cFGkuD++V6qfcFqZ9N2hGcgcsLRLH 7qoLBp1o6h5xSqcz83DqUjSQYPul8rFZ8RHNElO0pB3c8xes8f0T8UkWC t8TlWEr5nS4pFWjLfgG40Hmu9/I4Gr6rolmSfMODd9ICrSRd4JQ0KT1ys qRNqvrLLsltyjvr1/iUfTNteJ+7inJYPqsF6wjMgpLnuAz2Fjw2f+opHg i+ZfXzI839y9hb1SODZA484bWDiDU7qybslwaNB0IvjbuliRKyLjHQDZp A==; X-IronPort-AV: E=McAfee;i="6200,9189,10239"; a="333000513" X-IronPort-AV: E=Sophos;i="5.88,319,1635231600"; d="scan'208";a="333000513" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2022 12:36:24 -0800 X-IronPort-AV: E=Sophos;i="5.88,319,1635231600"; d="scan'208";a="581221531" Received: from lucas-s2600cw.jf.intel.com ([10.165.21.202]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2022 12:36:24 -0800 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Subject: [PATCH 13/19] drm/i915/guc: Convert mapping table to dma_buf_map Date: Wed, 26 Jan 2022 12:36:56 -0800 Message-Id: <20220126203702.1784589-14-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.35.0 In-Reply-To: <20220126203702.1784589-1-lucas.demarchi@intel.com> References: <20220126203702.1784589-1-lucas.demarchi@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Matthew Brost , =?utf-8?q?Thomas_Hellstr=C3=B6m?= , dri-devel@lists.freedesktop.org, Daniele Ceraolo Spurio , John Harrison Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Use dma_buf_map to write the fields system_info.mapping_table[][]. Since we already have the info_map around where needed, just use it instead of going through guc->ads_map. Cc: Matt Roper Cc: Thomas Hellström Cc: Daniel Vetter Cc: John Harrison Cc: Matthew Brost Cc: Daniele Ceraolo Spurio Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c index 8e4768289792..dca7c3db9cdd 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c @@ -204,7 +204,7 @@ int intel_guc_global_policies_update(struct intel_guc *guc) } static void guc_mapping_table_init(struct intel_gt *gt, - struct guc_gt_system_info *system_info) + struct dma_buf_map *info_map) { unsigned int i, j; struct intel_engine_cs *engine; @@ -213,14 +213,14 @@ static void guc_mapping_table_init(struct intel_gt *gt, /* Table must be set to invalid values for entries not used */ for (i = 0; i < GUC_MAX_ENGINE_CLASSES; ++i) for (j = 0; j < GUC_MAX_INSTANCES_PER_CLASS; ++j) - system_info->mapping_table[i][j] = - GUC_MAX_INSTANCES_PER_CLASS; + info_map_write(info_map, mapping_table[i][j], + GUC_MAX_INSTANCES_PER_CLASS); for_each_engine(engine, gt, id) { u8 guc_class = engine_class_to_guc_class(engine->class); - system_info->mapping_table[guc_class][ilog2(engine->logical_mask)] = - engine->instance; + info_map_write(info_map, mapping_table[guc_class][ilog2(engine->logical_mask)], + engine->instance); } } @@ -595,7 +595,7 @@ static void __guc_ads_init(struct intel_guc *guc) /* Golden contexts for re-initialising after a watchdog reset */ guc_prep_golden_context(guc); - guc_mapping_table_init(guc_to_gt(guc), &blob->system_info); + guc_mapping_table_init(guc_to_gt(guc), &info_map); base = intel_guc_ggtt_offset(guc, guc->ads_vma); From patchwork Wed Jan 26 20:36:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 12725773 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1CE25C5DF62 for ; Wed, 26 Jan 2022 20:37:01 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 854DA10E94E; Wed, 26 Jan 2022 20:36:31 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id EDE0410E8F3; Wed, 26 Jan 2022 20:36:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643229388; x=1674765388; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=bzf6lc9bApX/ewfhTO1t8CcPepjuy6Uh0vmFT+3QfBg=; b=eIlUoM8zRNwBO6HAoD+8pzUZag1WTcy2HMDXo5p4ksdnDfNupkXu8a9i OVf/MUF/GeJPv+2RWwKzqKJ9LluaNfS3eMsMjrNG5GAA8/KPxwV88nEE4 9Xa2yyte7PdvPYs4wZsC1f8hDv1LiI3oo5V7Iv/oiGKjoC9AYyO5OXrqM 5DL+Fp/bJQmeEI0f+dfz2ZHyTVJzSq9Q3UPQF1C0MeO6btTnPlABDr1lZ T2TppJVvZqgniFkzYsaEeGjWHK+ty6576/zkBKVnu/nr0ym8CxzATqSNh J8X46HaCujlYzGDzmFwGPNaz4OOCeKa6QBqfgm7YSGAo6s1pGmoRZxMzt Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10239"; a="333000514" X-IronPort-AV: E=Sophos;i="5.88,319,1635231600"; d="scan'208";a="333000514" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2022 12:36:24 -0800 X-IronPort-AV: E=Sophos;i="5.88,319,1635231600"; d="scan'208";a="581221534" Received: from lucas-s2600cw.jf.intel.com ([10.165.21.202]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2022 12:36:24 -0800 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Subject: [PATCH 14/19] drm/i915/guc: Convert capture list to dma_buf_map Date: Wed, 26 Jan 2022 12:36:57 -0800 Message-Id: <20220126203702.1784589-15-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.35.0 In-Reply-To: <20220126203702.1784589-1-lucas.demarchi@intel.com> References: <20220126203702.1784589-1-lucas.demarchi@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Matthew Brost , =?utf-8?q?Thomas_Hellstr=C3=B6m?= , dri-devel@lists.freedesktop.org, Daniele Ceraolo Spurio , John Harrison Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Use dma_buf_map to write the fields ads.capture_*. Cc: Matt Roper Cc: Thomas Hellström Cc: Daniel Vetter Cc: John Harrison Cc: Matthew Brost Cc: Daniele Ceraolo Spurio Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c index dca7c3db9cdd..cad1e325656e 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c @@ -544,7 +544,7 @@ static void guc_init_golden_context(struct intel_guc *guc) GEM_BUG_ON(guc->ads_golden_ctxt_size != total_size); } -static void guc_capture_list_init(struct intel_guc *guc, struct __guc_ads_blob *blob) +static void guc_capture_list_init(struct intel_guc *guc) { int i, j; u32 addr_ggtt, offset; @@ -556,11 +556,11 @@ static void guc_capture_list_init(struct intel_guc *guc, struct __guc_ads_blob * for (i = 0; i < GUC_CAPTURE_LIST_INDEX_MAX; i++) { for (j = 0; j < GUC_MAX_ENGINE_CLASSES; j++) { - blob->ads.capture_instance[i][j] = addr_ggtt; - blob->ads.capture_class[i][j] = addr_ggtt; + ads_blob_write(guc, ads.capture_instance[i][j], addr_ggtt); + ads_blob_write(guc, ads.capture_class[i][j], addr_ggtt); } - blob->ads.capture_global[i] = addr_ggtt; + ads_blob_write(guc, ads.capture_global[i], addr_ggtt); } } @@ -600,7 +600,7 @@ static void __guc_ads_init(struct intel_guc *guc) base = intel_guc_ggtt_offset(guc, guc->ads_vma); /* Capture list for hang debug */ - guc_capture_list_init(guc, blob); + guc_capture_list_init(guc); /* ADS */ blob->ads.scheduler_policies = base + ptr_offset(blob, policies); From patchwork Wed Jan 26 20:36:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 12725780 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 74EECC5DF62 for ; Wed, 26 Jan 2022 20:37:12 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3315610E959; Wed, 26 Jan 2022 20:36:32 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2024910E8FE; Wed, 26 Jan 2022 20:36:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643229388; x=1674765388; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=LbTosOrCfB7wWrLdZDqMQP13uw25WBqYFqJiDa+F50Y=; b=bSRfmSnV7ryo5Thx+Ndb9v4+q2GN0mQAantTX+Jag4aYhl33WNTpBzM3 HRfrX1pm4bX6LqbrkfwA8ZykdxFY6DwNUoS5+c74lBPRbNFI+XEx1H0rW Rs8bK30FaPlVLg+mPqQRcx8f2YEtuj8Rlzn7FiJUi38hyX+aK/l/nZAco OSV00anBCdatOo51XnTZ6wFYWBPg3MkD6kQuutYqGwZhovxrPzZnLhenq FiHm1K86Ih67zgQcoOcCzIWj2T27Yz0ci5K+/kvHwpE9/Xn/RjvfN2Aoz Pb+BWIMhVbTuR0dfEhgO+2LUw7lzpeVtUdCqm58GDsPOWOnWpodUYIz4K w==; X-IronPort-AV: E=McAfee;i="6200,9189,10239"; a="333000516" X-IronPort-AV: E=Sophos;i="5.88,319,1635231600"; d="scan'208";a="333000516" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2022 12:36:25 -0800 X-IronPort-AV: E=Sophos;i="5.88,319,1635231600"; d="scan'208";a="581221537" Received: from lucas-s2600cw.jf.intel.com ([10.165.21.202]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2022 12:36:24 -0800 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Subject: [PATCH 15/19] drm/i915/guc: Prepare for error propagation Date: Wed, 26 Jan 2022 12:36:58 -0800 Message-Id: <20220126203702.1784589-16-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.35.0 In-Reply-To: <20220126203702.1784589-1-lucas.demarchi@intel.com> References: <20220126203702.1784589-1-lucas.demarchi@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Matthew Brost , =?utf-8?q?Thomas_Hellstr=C3=B6m?= , dri-devel@lists.freedesktop.org, Daniele Ceraolo Spurio , John Harrison Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Currently guc_mmio_reg_add() relies on having enough memory available in the array to add a new slot. It uses `GEM_BUG_ON(count >= regset->size);` to protect going above the threshold. In order to allow guc_mmio_reg_add() to handle the memory allocation by itself, it must return an error in case of failures. Adjust return code so this error can be propagated to the callers of guc_mmio_reg_add() and guc_mmio_regset_init(). No intended change in behavior. Cc: Matt Roper Cc: Thomas Hellström Cc: Daniel Vetter Cc: John Harrison Cc: Matthew Brost Cc: Daniele Ceraolo Spurio Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 31 +++++++++++++--------- 1 file changed, 18 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c index cad1e325656e..73ca34de44f7 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c @@ -244,8 +244,8 @@ static int guc_mmio_reg_cmp(const void *a, const void *b) return (int)ra->offset - (int)rb->offset; } -static void guc_mmio_reg_add(struct temp_regset *regset, - u32 offset, u32 flags) +static long __must_check guc_mmio_reg_add(struct temp_regset *regset, + u32 offset, u32 flags) { u32 count = regset->used; struct guc_mmio_reg reg = { @@ -264,7 +264,7 @@ static void guc_mmio_reg_add(struct temp_regset *regset, */ if (bsearch(®, regset->registers, count, sizeof(reg), guc_mmio_reg_cmp)) - return; + return 0; slot = ®set->registers[count]; regset->used++; @@ -277,6 +277,8 @@ static void guc_mmio_reg_add(struct temp_regset *regset, swap(slot[1], slot[0]); } + + return 0; } #define GUC_MMIO_REG_ADD(regset, reg, masked) \ @@ -284,32 +286,35 @@ static void guc_mmio_reg_add(struct temp_regset *regset, i915_mmio_reg_offset((reg)), \ (masked) ? GUC_REGSET_MASKED : 0) -static void guc_mmio_regset_init(struct temp_regset *regset, - struct intel_engine_cs *engine) +static int guc_mmio_regset_init(struct temp_regset *regset, + struct intel_engine_cs *engine) { const u32 base = engine->mmio_base; struct i915_wa_list *wal = &engine->wa_list; struct i915_wa *wa; unsigned int i; + int ret = 0; regset->used = 0; - GUC_MMIO_REG_ADD(regset, RING_MODE_GEN7(base), true); - GUC_MMIO_REG_ADD(regset, RING_HWS_PGA(base), false); - GUC_MMIO_REG_ADD(regset, RING_IMR(base), false); + ret |= GUC_MMIO_REG_ADD(regset, RING_MODE_GEN7(base), true); + ret |= GUC_MMIO_REG_ADD(regset, RING_HWS_PGA(base), false); + ret |= GUC_MMIO_REG_ADD(regset, RING_IMR(base), false); for (i = 0, wa = wal->list; i < wal->count; i++, wa++) - GUC_MMIO_REG_ADD(regset, wa->reg, wa->masked_reg); + ret |= GUC_MMIO_REG_ADD(regset, wa->reg, wa->masked_reg); /* Be extra paranoid and include all whitelist registers. */ for (i = 0; i < RING_MAX_NONPRIV_SLOTS; i++) - GUC_MMIO_REG_ADD(regset, - RING_FORCE_TO_NONPRIV(base, i), - false); + ret |= GUC_MMIO_REG_ADD(regset, + RING_FORCE_TO_NONPRIV(base, i), + false); /* add in local MOCS registers */ for (i = 0; i < GEN9_LNCFCMOCS_REG_COUNT; i++) - GUC_MMIO_REG_ADD(regset, GEN9_LNCFCMOCS(i), false); + ret |= GUC_MMIO_REG_ADD(regset, GEN9_LNCFCMOCS(i), false); + + return ret ? -1 : 0; } static int guc_mmio_reg_state_query(struct intel_guc *guc) From patchwork Wed Jan 26 20:36:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 12725782 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6E427C2BA4C for ; Wed, 26 Jan 2022 20:37:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E0D6210E962; Wed, 26 Jan 2022 20:36:33 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2DB9110E901; Wed, 26 Jan 2022 20:36:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643229388; x=1674765388; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Fqdo8Qx3lC6ixji+P86gIq1aCMVCtnLlM8T1Sfq3SdA=; b=N5uXbfjMba/fpzEY05zlCleYmX8/qDM7WYI80UeqWe0iR59DDezweKzu jJUFjs6DZJ07iAOPCMDPM2DPVgPuQF9hRbima5p5RbnUOkdhMnyxv/qfa NtSzRoUcxw1OHDEz5zM1wsimHa6o9i9zPUhVrb0QFn3W3bhefriy42LRq GEXmf+KTB38vtiXKXWfPXqM2jKJc9n0mwWhBfxuNa6N/H4tLZVTmEVS3r sOZn7hKpMkpL5n5BFvk63XlTMgerarYJbEboFdNmhqLGJJBn9O8H8ad0B RjjvAnGrIVmmMsR0VmVZq1FRa15EH1OE1A0biRv8iYpdbbLakBv+7z5RE w==; X-IronPort-AV: E=McAfee;i="6200,9189,10239"; a="333000517" X-IronPort-AV: E=Sophos;i="5.88,319,1635231600"; d="scan'208";a="333000517" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2022 12:36:25 -0800 X-IronPort-AV: E=Sophos;i="5.88,319,1635231600"; d="scan'208";a="581221540" Received: from lucas-s2600cw.jf.intel.com ([10.165.21.202]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2022 12:36:25 -0800 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Subject: [PATCH 16/19] drm/i915/guc: Use a single pass to calculate regset Date: Wed, 26 Jan 2022 12:36:59 -0800 Message-Id: <20220126203702.1784589-17-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.35.0 In-Reply-To: <20220126203702.1784589-1-lucas.demarchi@intel.com> References: <20220126203702.1784589-1-lucas.demarchi@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Matthew Brost , =?utf-8?q?Thomas_Hellstr=C3=B6m?= , dri-devel@lists.freedesktop.org, Daniele Ceraolo Spurio , John Harrison Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The ADS initialitazion was using 2 passes to calculate the regset sent to GuC to initialize each engine: the first pass to just have the final object size and the second to set each register in place in the final gem object. However in order to maintain an ordered set of registers to pass to guc, each register needs to be added and moved in the final array. The second phase may actually happen in IO memory rather than system memory and accessing IO memory by simply dereferencing the pointer doesn't work on all architectures. Other places of the ADS initializaition were converted to use the dma_buf_map API, but here there may be a lot more accesses to IO memory. So, instead of following that same approach, convert the regset initialization to calculate the final array in 1 pass and in the second pass that array is just copied to its final location, updating the pointers for each engine written to the ADS blob. One important thing is that struct temp_regset now have different semantics: `registers` continues to track the registers of a single engine, however the other fields are updated together, according to the newly added `storage`, which tracks the memory allocated for all the registers. So rename some of these fields and add a __mmio_reg_add(): this function (possibly) allocates memory and operates on the storage pointer while guc_mmio_reg_add() continues to manage the registers pointer. On a Tiger Lake system using enable_guc=3, the following log message is now seen: [ 187.334310] i915 0000:00:02.0: [drm:intel_guc_ads_create [i915]] Used 4 KB for temporary ADS regset This change has also been tested on an ARM64 host with DG2 and other discrete graphics cards. Cc: Matt Roper Cc: Thomas Hellström Cc: Daniel Vetter Cc: John Harrison Cc: Matthew Brost Cc: Daniele Ceraolo Spurio Signed-off-by: Lucas De Marchi Reported-by: kernel test robot Reported-by: kernel test robot Reported-by: kernel test robot --- drivers/gpu/drm/i915/gt/uc/intel_guc.h | 7 ++ drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 117 +++++++++++++-------- 2 files changed, 79 insertions(+), 45 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h index e2e0df1c3d91..4c852eee3ad8 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h @@ -152,6 +152,13 @@ struct intel_guc { struct dma_buf_map ads_map; /** @ads_regset_size: size of the save/restore regsets in the ADS */ u32 ads_regset_size; + /** + * @ads_regset_count: number of save/restore registers in the ADS for + * each engine + */ + u32 ads_regset_count[I915_NUM_ENGINES]; + /** @ads_regset: save/restore regsets in the ADS */ + struct guc_mmio_reg *ads_regset; /** @ads_golden_ctxt_size: size of the golden contexts in the ADS */ u32 ads_golden_ctxt_size; /** @ads_engine_usage_size: size of engine usage in the ADS */ diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c index 73ca34de44f7..390101ee3661 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c @@ -226,14 +226,13 @@ static void guc_mapping_table_init(struct intel_gt *gt, /* * The save/restore register list must be pre-calculated to a temporary - * buffer of driver defined size before it can be generated in place - * inside the ADS. + * buffer before it can be copied inside the ADS. */ -#define MAX_MMIO_REGS 128 /* Arbitrary size, increase as needed */ struct temp_regset { struct guc_mmio_reg *registers; - u32 used; - u32 size; + struct guc_mmio_reg *storage; + u32 storage_used; + u32 storage_max; }; static int guc_mmio_reg_cmp(const void *a, const void *b) @@ -244,18 +243,44 @@ static int guc_mmio_reg_cmp(const void *a, const void *b) return (int)ra->offset - (int)rb->offset; } +static struct guc_mmio_reg * __must_check +__mmio_reg_add(struct temp_regset *regset, struct guc_mmio_reg *reg) +{ + u32 pos = regset->storage_used; + struct guc_mmio_reg *slot; + + if (pos >= regset->storage_max) { + size_t size = ALIGN((pos + 1) * sizeof(*slot), PAGE_SIZE); + struct guc_mmio_reg *r = krealloc(regset->storage, + size, GFP_KERNEL); + if (!r) { + WARN_ONCE(1, "Incomplete regset list: can't add register (%d)\n", + -ENOMEM); + return ERR_PTR(-ENOMEM); + } + + regset->registers = r + (regset->registers - regset->storage); + regset->storage = r; + regset->storage_max = size / sizeof(*slot); + } + + slot = ®set->storage[pos]; + regset->storage_used++; + *slot = *reg; + + return slot; +} + static long __must_check guc_mmio_reg_add(struct temp_regset *regset, u32 offset, u32 flags) { - u32 count = regset->used; + u32 count = regset->storage_used - (regset->registers - regset->storage); struct guc_mmio_reg reg = { .offset = offset, .flags = flags, }; struct guc_mmio_reg *slot; - GEM_BUG_ON(count >= regset->size); - /* * The mmio list is built using separate lists within the driver. * It's possible that at some point we may attempt to add the same @@ -266,9 +291,9 @@ static long __must_check guc_mmio_reg_add(struct temp_regset *regset, sizeof(reg), guc_mmio_reg_cmp)) return 0; - slot = ®set->registers[count]; - regset->used++; - *slot = reg; + slot = __mmio_reg_add(regset, ®); + if (IS_ERR(slot)) + return PTR_ERR(slot); while (slot-- > regset->registers) { GEM_BUG_ON(slot[0].offset == slot[1].offset); @@ -295,7 +320,11 @@ static int guc_mmio_regset_init(struct temp_regset *regset, unsigned int i; int ret = 0; - regset->used = 0; + /* + * Each engine's registers point to a new start relative to + * storage + */ + regset->registers = regset->storage + regset->storage_used; ret |= GUC_MMIO_REG_ADD(regset, RING_MODE_GEN7(base), true); ret |= GUC_MMIO_REG_ADD(regset, RING_HWS_PGA(base), false); @@ -317,32 +346,28 @@ static int guc_mmio_regset_init(struct temp_regset *regset, return ret ? -1 : 0; } -static int guc_mmio_reg_state_query(struct intel_guc *guc) +static long guc_mmio_reg_state_create(struct intel_guc *guc) { struct intel_gt *gt = guc_to_gt(guc); struct intel_engine_cs *engine; enum intel_engine_id id; - struct temp_regset temp_set; - u32 total; + struct temp_regset temp_set = {}; + long total = 0; - /* - * Need to actually build the list in order to filter out - * duplicates and other such data dependent constructions. - */ - temp_set.size = MAX_MMIO_REGS; - temp_set.registers = kmalloc_array(temp_set.size, - sizeof(*temp_set.registers), - GFP_KERNEL); - if (!temp_set.registers) - return -ENOMEM; - - total = 0; for_each_engine(engine, gt, id) { - guc_mmio_regset_init(&temp_set, engine); - total += temp_set.used; + u32 used = temp_set.storage_used; + + if (guc_mmio_regset_init(&temp_set, engine) < 0) + return -1; + + guc->ads_regset_count[id] = temp_set.storage_used - used; + total += guc->ads_regset_count[id]; } - kfree(temp_set.registers); + guc->ads_regset = temp_set.storage; + + drm_dbg(&guc_to_gt(guc)->i915->drm, "Used %lu KB for temporary ADS regset\n", + (temp_set.storage_max * sizeof(struct guc_mmio_reg)) >> 10); return total * sizeof(struct guc_mmio_reg); } @@ -352,40 +377,38 @@ static void guc_mmio_reg_state_init(struct intel_guc *guc, { struct intel_gt *gt = guc_to_gt(guc); struct intel_engine_cs *engine; + struct guc_mmio_reg *ads_registers; enum intel_engine_id id; - struct temp_regset temp_set; - struct guc_mmio_reg_set *ads_reg_set; u32 addr_ggtt, offset; - u8 guc_class; offset = guc_ads_regset_offset(guc); addr_ggtt = intel_guc_ggtt_offset(guc, guc->ads_vma) + offset; - temp_set.registers = (struct guc_mmio_reg *)(((u8 *)blob) + offset); - temp_set.size = guc->ads_regset_size / sizeof(temp_set.registers[0]); + ads_registers = (struct guc_mmio_reg *)(((u8 *)blob) + offset); + + memcpy(ads_registers, guc->ads_regset, guc->ads_regset_size); for_each_engine(engine, gt, id) { + u32 count = guc->ads_regset_count[id]; + struct guc_mmio_reg_set *ads_reg_set; + u8 guc_class; + /* Class index is checked in class converter */ GEM_BUG_ON(engine->instance >= GUC_MAX_INSTANCES_PER_CLASS); guc_class = engine_class_to_guc_class(engine->class); ads_reg_set = &blob->ads.reg_state_list[guc_class][engine->instance]; - guc_mmio_regset_init(&temp_set, engine); - if (!temp_set.used) { + if (!count) { ads_reg_set->address = 0; ads_reg_set->count = 0; continue; } ads_reg_set->address = addr_ggtt; - ads_reg_set->count = temp_set.used; + ads_reg_set->count = count; - temp_set.size -= temp_set.used; - temp_set.registers += temp_set.used; - addr_ggtt += temp_set.used * sizeof(struct guc_mmio_reg); + addr_ggtt += count * sizeof(struct guc_mmio_reg); } - - GEM_BUG_ON(temp_set.size); } static void fill_engine_enable_masks(struct intel_gt *gt, @@ -634,8 +657,11 @@ int intel_guc_ads_create(struct intel_guc *guc) GEM_BUG_ON(guc->ads_vma); - /* Need to calculate the reg state size dynamically: */ - ret = guc_mmio_reg_state_query(guc); + /* + * Create reg state size dynamically on system memory to be copied to + * the final ads blob on gt init/reset + */ + ret = guc_mmio_reg_state_create(guc); if (ret < 0) return ret; guc->ads_regset_size = ret; @@ -681,6 +707,7 @@ void intel_guc_ads_destroy(struct intel_guc *guc) i915_vma_unpin_and_release(&guc->ads_vma, I915_VMA_RELEASE_MAP); guc->ads_blob = NULL; dma_buf_map_clear(&guc->ads_map); + kfree(guc->ads_regset); } static void guc_ads_private_data_reset(struct intel_guc *guc) From patchwork Wed Jan 26 20:37:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 12725785 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A08BAC2BA4C for ; Wed, 26 Jan 2022 20:37:28 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B91BF10E95A; Wed, 26 Jan 2022 20:36:44 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5832B10E905; Wed, 26 Jan 2022 20:36:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643229388; x=1674765388; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=nAOdyzWpMBIDR4UoBoQpVEZ/NUm8W56CiB6CYm9l6HI=; b=OFu/Rpz5cMSy1tUYyJUIlrfqpbZzWgErQtWMKZSJ1LqpH2CXTbJSrEb0 3sA2XdC9Cg/p1vUXFWjasf0EHI3jTs/j3G+K5w+weHctX/h8FtCls1TMU z91KssreVdA5GFoXbJnd10sBh7Gh/CjV0wCe7g6IjXRnLaIlm86BkIlFQ e0jgE7bLp+xAXcOUz67Sxk4LsxeRulReauaDR4zWHTcuCkjtWHz/Wz13e XXzPoAJXFLsNYWWBG8CtHePPnHqowmYPzVaAUP4x2bn90XPZNAQqCP8uS Zqc1NUiPZVfxvKonTyROymxwphkKA/MFZzd0snXrWORDGpaRyBKxVTi2R g==; X-IronPort-AV: E=McAfee;i="6200,9189,10239"; a="333000520" X-IronPort-AV: E=Sophos;i="5.88,319,1635231600"; d="scan'208";a="333000520" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2022 12:36:26 -0800 X-IronPort-AV: E=Sophos;i="5.88,319,1635231600"; d="scan'208";a="581221543" Received: from lucas-s2600cw.jf.intel.com ([10.165.21.202]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2022 12:36:25 -0800 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Subject: [PATCH 17/19] drm/i915/guc: Convert guc_mmio_reg_state_init to dma_buf_map Date: Wed, 26 Jan 2022 12:37:00 -0800 Message-Id: <20220126203702.1784589-18-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.35.0 In-Reply-To: <20220126203702.1784589-1-lucas.demarchi@intel.com> References: <20220126203702.1784589-1-lucas.demarchi@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Matthew Brost , =?utf-8?q?Thomas_Hellstr=C3=B6m?= , dri-devel@lists.freedesktop.org, Daniele Ceraolo Spurio , John Harrison Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Now that the regset list is prepared, convert guc_mmio_reg_state_init() to use dma_buf_map to copy the array to the final location and initialize additional fields in ads.reg_state_list. Cc: Matt Roper Cc: Thomas Hellström Cc: Daniel Vetter Cc: John Harrison Cc: Matthew Brost Cc: Daniele Ceraolo Spurio Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 30 +++++++++++++--------- 1 file changed, 18 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c index 390101ee3661..cb0f543b0e86 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c @@ -372,40 +372,46 @@ static long guc_mmio_reg_state_create(struct intel_guc *guc) return total * sizeof(struct guc_mmio_reg); } -static void guc_mmio_reg_state_init(struct intel_guc *guc, - struct __guc_ads_blob *blob) +static void guc_mmio_reg_state_init(struct intel_guc *guc) { + struct dma_buf_map ads_regset_map; struct intel_gt *gt = guc_to_gt(guc); struct intel_engine_cs *engine; - struct guc_mmio_reg *ads_registers; enum intel_engine_id id; u32 addr_ggtt, offset; offset = guc_ads_regset_offset(guc); addr_ggtt = intel_guc_ggtt_offset(guc, guc->ads_vma) + offset; - ads_registers = (struct guc_mmio_reg *)(((u8 *)blob) + offset); + ads_regset_map = DMA_BUF_MAP_INIT_OFFSET(&guc->ads_map, offset); - memcpy(ads_registers, guc->ads_regset, guc->ads_regset_size); + dma_buf_map_memcpy_to(&ads_regset_map, guc->ads_regset, + guc->ads_regset_size); for_each_engine(engine, gt, id) { u32 count = guc->ads_regset_count[id]; - struct guc_mmio_reg_set *ads_reg_set; u8 guc_class; /* Class index is checked in class converter */ GEM_BUG_ON(engine->instance >= GUC_MAX_INSTANCES_PER_CLASS); guc_class = engine_class_to_guc_class(engine->class); - ads_reg_set = &blob->ads.reg_state_list[guc_class][engine->instance]; if (!count) { - ads_reg_set->address = 0; - ads_reg_set->count = 0; + ads_blob_write(guc, + ads.reg_state_list[guc_class][engine->instance].address, + 0); + ads_blob_write(guc, + ads.reg_state_list[guc_class][engine->instance].count, + 0); continue; } - ads_reg_set->address = addr_ggtt; - ads_reg_set->count = count; + ads_blob_write(guc, + ads.reg_state_list[guc_class][engine->instance].address, + addr_ggtt); + ads_blob_write(guc, + ads.reg_state_list[guc_class][engine->instance].count, + count); addr_ggtt += count * sizeof(struct guc_mmio_reg); } @@ -635,7 +641,7 @@ static void __guc_ads_init(struct intel_guc *guc) blob->ads.gt_system_info = base + ptr_offset(blob, system_info); /* MMIO save/restore list */ - guc_mmio_reg_state_init(guc, blob); + guc_mmio_reg_state_init(guc); /* Private Data */ blob->ads.private_data = base + guc_ads_private_data_offset(guc); From patchwork Wed Jan 26 20:37:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 12725783 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CBEE8C5DF62 for ; Wed, 26 Jan 2022 20:37:16 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 15C6010E96A; Wed, 26 Jan 2022 20:36:34 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 605C210E911; Wed, 26 Jan 2022 20:36:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643229388; x=1674765388; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=EitKDHH9Pk9BnYi2AVNYWFlVpS4Zy78+E5JlLFovTXk=; b=bcuu0UJjUBdO/74AR7/DXkVUQc2PAr8UHN82qetoSDhc7SHljDClV+1o Kus2Ku1U9dwhF+SMzUcIKZhM3Jmi/RpXp9J99K0ttTu35edSgS+VKR1Ll lE+9c8k1JkssD8P7l6TMGkC0JIYa+CGr4q6mFcWsuGWRKhcFGnzTL3YcD bALDEhUx9E0lHZUDYpyvfjZtaH2TvHfBcho/yCCsReJIedoHGlmstATP0 gPmKxxUNb2Yw449HG7OyBsIvbC5Xzp/T0N0egFFK8uG7XjqX9JvxJY7xW lNepKiVM2GB0AeoQof5nlQ7c1oCaoG3E42xqA5lx5ACqm4m9LXrIdXCFg Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10239"; a="333000521" X-IronPort-AV: E=Sophos;i="5.88,319,1635231600"; d="scan'208";a="333000521" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2022 12:36:26 -0800 X-IronPort-AV: E=Sophos;i="5.88,319,1635231600"; d="scan'208";a="581221547" Received: from lucas-s2600cw.jf.intel.com ([10.165.21.202]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2022 12:36:25 -0800 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Subject: [PATCH 18/19] drm/i915/guc: Convert __guc_ads_init to dma_buf_map Date: Wed, 26 Jan 2022 12:37:01 -0800 Message-Id: <20220126203702.1784589-19-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.35.0 In-Reply-To: <20220126203702.1784589-1-lucas.demarchi@intel.com> References: <20220126203702.1784589-1-lucas.demarchi@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Matthew Brost , =?utf-8?q?Thomas_Hellstr=C3=B6m?= , dri-devel@lists.freedesktop.org, Daniele Ceraolo Spurio , John Harrison Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Now that all the called functions from __guc_ads_init() are converted to use ads_map, stop using ads_blob in __guc_ads_init(). Cc: Matt Roper Cc: Thomas Hellström Cc: Daniel Vetter Cc: John Harrison Cc: Matthew Brost Cc: Daniele Ceraolo Spurio Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 25 ++++++++++++---------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c index cb0f543b0e86..30edac93afbf 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c @@ -602,7 +602,6 @@ static void __guc_ads_init(struct intel_guc *guc) { struct intel_gt *gt = guc_to_gt(guc); struct drm_i915_private *i915 = gt->i915; - struct __guc_ads_blob *blob = guc->ads_blob; struct dma_buf_map info_map = DMA_BUF_MAP_INIT_OFFSET(&guc->ads_map, offsetof(struct __guc_ads_blob, system_info)); u32 base; @@ -613,17 +612,18 @@ static void __guc_ads_init(struct intel_guc *guc) /* System info */ fill_engine_enable_masks(gt, &info_map); - blob->system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_SLICE_ENABLED] = - hweight8(gt->info.sseu.slice_mask); - blob->system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_VDBOX_SFC_SUPPORT_MASK] = - gt->info.vdbox_sfc_access; + ads_blob_write(guc, system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_SLICE_ENABLED], + hweight8(gt->info.sseu.slice_mask)); + ads_blob_write(guc, system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_VDBOX_SFC_SUPPORT_MASK], + gt->info.vdbox_sfc_access); if (GRAPHICS_VER(i915) >= 12 && !IS_DGFX(i915)) { u32 distdbreg = intel_uncore_read(gt->uncore, GEN12_DIST_DBS_POPULATED); - blob->system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_DOORBELL_COUNT_PER_SQIDI] = - ((distdbreg >> GEN12_DOORBELLS_PER_SQIDI_SHIFT) & - GEN12_DOORBELLS_PER_SQIDI) + 1; + ads_blob_write(guc, + system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_DOORBELL_COUNT_PER_SQIDI], + ((distdbreg >> GEN12_DOORBELLS_PER_SQIDI_SHIFT) + & GEN12_DOORBELLS_PER_SQIDI) + 1); } /* Golden contexts for re-initialising after a watchdog reset */ @@ -637,14 +637,17 @@ static void __guc_ads_init(struct intel_guc *guc) guc_capture_list_init(guc); /* ADS */ - blob->ads.scheduler_policies = base + ptr_offset(blob, policies); - blob->ads.gt_system_info = base + ptr_offset(blob, system_info); + ads_blob_write(guc, ads.scheduler_policies, base + + offsetof(struct __guc_ads_blob, policies)); + ads_blob_write(guc, ads.gt_system_info, base + + offsetof(struct __guc_ads_blob, system_info)); /* MMIO save/restore list */ guc_mmio_reg_state_init(guc); /* Private Data */ - blob->ads.private_data = base + guc_ads_private_data_offset(guc); + ads_blob_write(guc, ads.private_data, base + + guc_ads_private_data_offset(guc)); i915_gem_object_flush_map(guc->ads_vma->obj); } From patchwork Wed Jan 26 20:37:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 12725784 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CC8BEC5DF62 for ; Wed, 26 Jan 2022 20:37:26 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 82B3710E8F3; Wed, 26 Jan 2022 20:36:39 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id A904E10E91D; Wed, 26 Jan 2022 20:36:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643229388; x=1674765388; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3jmDiWUEtRCn5pgI7a3cD0afFPjqoS4Yz9KjtGbG6yg=; b=UBGbpB3T3caIShLsAgYJQ56P7Gcgf6ttSGLRkDR2qbCcpVBjyTV8Y8JT OG2RlxvU1Zk9y/iTJqmopY3AzQkKtz7gwIJZto/2RqWo+AD3Dt3Fd9BCa CzJMC8/Lt3omfhzGiCrjZ4cj4rU2DX7s8y29KQci0kS3wlHv+LP6mgx+Y 6WWo8k/mbdUR/IoAomljzm/CC2F5HhzQWpXw9P9OJ4IO3gKmZ70Nye4EQ 3JHhL109plqMUn7k+PC9UK4rhSD22DdfKlLqi/aNFuZaH3ZnoqM+aQCJX tqofjzdJa7XUy64kRGfe44/0ZCVz2jPLk2T2+xtqs5mHBwjTKwL6M/U9w g==; X-IronPort-AV: E=McAfee;i="6200,9189,10239"; a="333000523" X-IronPort-AV: E=Sophos;i="5.88,319,1635231600"; d="scan'208";a="333000523" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2022 12:36:26 -0800 X-IronPort-AV: E=Sophos;i="5.88,319,1635231600"; d="scan'208";a="581221550" Received: from lucas-s2600cw.jf.intel.com ([10.165.21.202]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2022 12:36:25 -0800 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Subject: [PATCH 19/19] drm/i915/guc: Remove plain ads_blob pointer Date: Wed, 26 Jan 2022 12:37:02 -0800 Message-Id: <20220126203702.1784589-20-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.35.0 In-Reply-To: <20220126203702.1784589-1-lucas.demarchi@intel.com> References: <20220126203702.1784589-1-lucas.demarchi@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Matthew Brost , =?utf-8?q?Thomas_Hellstr=C3=B6m?= , dri-devel@lists.freedesktop.org, Daniele Ceraolo Spurio , John Harrison Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Now we have the access to content of GuC ADS either using dma_buf_map API or using a temporary buffer. Remove guc->ads_blob as there shouldn't be updates using the bare pointer anymore. Cc: Matt Roper Cc: Thomas Hellström Cc: Daniel Vetter Cc: John Harrison Cc: Matthew Brost Cc: Daniele Ceraolo Spurio Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/gt/uc/intel_guc.h | 3 +-- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 8 ++++---- 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h index 4c852eee3ad8..7349483d0e35 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h @@ -147,8 +147,7 @@ struct intel_guc { /** @ads_vma: object allocated to hold the GuC ADS */ struct i915_vma *ads_vma; - /** @ads_blob: contents of the GuC ADS */ - struct __guc_ads_blob *ads_blob; + /** @ads_map: contents of the GuC ADS */ struct dma_buf_map ads_map; /** @ads_regset_size: size of the save/restore regsets in the ADS */ u32 ads_regset_size; diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c index 30edac93afbf..b87269081650 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c @@ -661,6 +661,7 @@ static void __guc_ads_init(struct intel_guc *guc) */ int intel_guc_ads_create(struct intel_guc *guc) { + void *ads_blob; u32 size; int ret; @@ -685,14 +686,14 @@ int intel_guc_ads_create(struct intel_guc *guc) size = guc_ads_blob_size(guc); ret = intel_guc_allocate_and_map_vma(guc, size, &guc->ads_vma, - (void **)&guc->ads_blob); + &ads_blob); if (ret) return ret; if (i915_gem_object_is_lmem(guc->ads_vma->obj)) - dma_buf_map_set_vaddr_iomem(&guc->ads_map, (void __iomem *)guc->ads_blob); + dma_buf_map_set_vaddr_iomem(&guc->ads_map, (void __iomem *)ads_blob); else - dma_buf_map_set_vaddr(&guc->ads_map, guc->ads_blob); + dma_buf_map_set_vaddr(&guc->ads_map, ads_blob); __guc_ads_init(guc); @@ -714,7 +715,6 @@ void intel_guc_ads_init_late(struct intel_guc *guc) void intel_guc_ads_destroy(struct intel_guc *guc) { i915_vma_unpin_and_release(&guc->ads_vma, I915_VMA_RELEASE_MAP); - guc->ads_blob = NULL; dma_buf_map_clear(&guc->ads_map); kfree(guc->ads_regset); }