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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?nvhGbmmaNOW0bFdXM73ad6SEpARf?= =?utf-8?q?V4me4ahzRX5nohhvbVSrzYBNVCxKzuuPc1iLpv9JmeG9aKaVwhPQqhIxsryn6i/ai?= =?utf-8?q?1HDxp/gf2hcdXLzdYNpPu3NJif4cvPl9F/JzunQQAP6uyf7VXHHf73LHRO32+untB?= =?utf-8?q?BTwS2cuV/Re9Nl5i7j/v/XNqI9xIEvexruZJ9JEozvN7qe+ik7zVfPQe0hjmHtvFM?= =?utf-8?q?gEyR3hhS2+A7X907us6Ae0pOYbw9/Jy8VRZswHcEt1eyYP+IUE9KPdTipI5YH8QCJ?= =?utf-8?q?W9DNA2ksBE05/OzK+dsbkw99BIYPSaswJ1DD307ZI0Y2Kkr4+CnGigBqajYPVE7BU?= =?utf-8?q?QP91RtSyfKTryIN+LX81u5YVVpK8R6jaNlms4j9q79fR1gZ5pvOAhPD5bbttdGCyk?= =?utf-8?q?kTtwCBFrVf05sg0uelr9WTs3QF1p4g62GA6Kg85DJZhOxyqI+ne44HA3OHxdTBGzi?= =?utf-8?q?62uCQgeImIQA3mUDmHrJ5XBtSraD2h1ad2PAV4F/0kise44UZ1ieYx7wLuIaK6JO1?= =?utf-8?q?tWE2mh86u8ivpQm15PtR7y7u44iQOervQ3w4X8nn9Y/JYifH9iV9V3lKdOjTMqtkN?= =?utf-8?q?uztfY65ZUIDZjCzZlsysXysn2gkETX7c06rtii93oHOG5rhC3EapnQArRas+9EmFl?= =?utf-8?q?6VMc18FLE7UxAzQAjwGWt84drzgjllABWNDHg789SFzFiXTk0mJ7SkWeWCLdbKILR?= =?utf-8?q?P4zIb8oWSy3mZYdpAd5L9UKNyBqT127HBnbSkwSM0LavXC0tSZ9Fmf3YXTWhe6qbV?= =?utf-8?q?NPvNL2hlefeAr5X+3qgHKjUOekfOPuUY72UcUK8WMSAplUL1+rM/ltgNP760FgSqO?= =?utf-8?q?s1HnkjQAo7JYXUKg9rUV32Wjdh3SRvMqBNhDvQbOb2qnIvwIVu236LLs1walqiLRh?= =?utf-8?q?oA35PilH6j59xAq90iRTSk2cIHFNvs1nWbYU+K1FXyxCacSk3CGrMs3zp6Z7XuVth?= =?utf-8?q?Y893Fe5kHe4xiqs7U5sSAQw09TN7+dS8chaNaKzaShGsAIJTmY+8/ft1UMCXie8RL?= =?utf-8?q?xDfXxCdkBU4Rg0FwY1xysixfa/aTQirVEWSvhvQXBSmEe+qSx+UMMK1mYCDNt6OY6?= =?utf-8?q?xUDCDB0LoDBLH4UVbGshd064e6t4PPzYh72K7NnKt+82/j5efyZXForABxxeRQNBN?= =?utf-8?q?dMmPwq8VFmt3aTJEX873T+/D1DyxR9fsfWbFAL7bR3u4p6IdxgNOkxeNnvF4sEnmR?= =?utf-8?q?cUgUqGrU2qUx6uM9gIFNNnThVEXYRSeH+kT6gFpvvB4E9pF9hAyPINHCldZ7JSqbd?= =?utf-8?q?d5L6ow3r27gCbKCmQQiQGTsgA/QE98kbE6JFQCVNV5geoCPzprqcTMsB1ySfnJr1u?= =?utf-8?q?kApUCiA4Kh7aken9gLoOZsrSi3p1rq/rywIwyDAQM9vLgyIfX1Y22uy0dt6jEQ2Xw?= =?utf-8?q?6MGGHs0IuEhIISeJAGnZEQvoeZn6pPXvUskVuGjqs4JkWVk+KSEXP9GUQtM9eqsM9?= =?utf-8?q?snXEYXTyv9J8Z+cUW8HZz6AW+z29ABowRpbLweHkZpF9zCyAmKZJ+GuWK6WdNQcrQ?= =?utf-8?q?prFFGHTD5cKb2842osL+dnX3zc5emQONuWR6rjF7PSOuc7cONukmpIs=3D?= X-OriginatorOrg: suse.com X-MS-Exchange-CrossTenant-Network-Message-Id: 048d5f07-3993-4d26-eb03-08d9e1a78f1f X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB5600.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jan 2022 15:13:22.8219 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f7a17af6-1c5c-4a36-aa8b-f5be247aa4ba X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: q18XtsG3DTNpb9Wb9JRcMuVRco87c/+MvE/SAB8Hm7nZwKjrAZR80pBCv8tZWnJ61VVMpwui1Msgz3JWW9fhoA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB8PR04MB6683 From: Artem Bityutskiy Enable local interrupts before requesting C1 on the last two generations of Intel Xeon platforms: Sky Lake, Cascade Lake, Cooper Lake, Ice Lake. This decreases average C1 interrupt latency by about 5-10%, as measured with the 'wult' tool. The '->enter()' function of the driver enters C-states with local interrupts disabled by executing the 'monitor' and 'mwait' pair of instructions. If an interrupt happens, the CPU exits the C-state and continues executing instructions after 'mwait'. It does not jump to the interrupt handler, because local interrupts are disabled. The cpuidle subsystem enables interrupts a bit later, after doing some housekeeping. With this patch, we enable local interrupts before requesting C1. In this case, if the CPU wakes up because of an interrupt, it will jump to the interrupt handler right away. The cpuidle housekeeping will be done after the pending interrupt(s) are handled. Enabling interrupts before entering a C-state has measurable impact for faster C-states, like C1. Deeper, but slower C-states like C6 do not really benefit from this sort of change, because their latency is a lot higher comparing to the delay added by cpuidle housekeeping. This change was also tested with cyclictest and dbench. In case of Ice Lake, the average cyclictest latency decreased by 5.1%, and the average 'dbench' throughput increased by about 0.8%. Both tests were run for 4 hours with only C1 enabled (all other idle states, including 'POLL', were disabled). CPU frequency was pinned to HFM, and uncore frequency was pinned to the maximum value. The other platforms had similar single-digit percentage improvements. It is worth noting that this patch affects 'cpuidle' statistics a tiny bit. Before this patch, C1 residency did not include the interrupt handling time, but with this patch, it will include it. This is similar to what happens in case of the 'POLL' state, which also runs with interrupts enabled. Suggested-by: Len Brown Signed-off-by: Artem Bityutskiy [Linux commit: c227233ad64c77e57db738ab0e46439db71822a3] We don't have a pointer into cpuidle_state_table[] readily available. To compensate, propagate the flag into struct acpi_processor_cx. Unlike Linux we want to - disable IRQs again after MWAITing, as subsequently invoked functions assume so, - avoid enabling IRQs if cstate_restore_tsc() is not a no-op, to avoid interfering with, in particular, the time rendezvous. Signed-off-by: Jan Beulich Acked-by: Roger Pau Monné --- RFC: I'm not entirely certain that we want to take this, i.e. whether we're as much worried about interrupt latency. RFC: I was going back and forth between putting the local_irq_enable() ahead of or after cpu_is_haltable(). --- v3: Propagate flag to struct acpi_processor_cx. Don't set flag when TSC may stop whild in a C-state. v2: New. --- a/xen/arch/x86/cpu/mwait-idle.c +++ b/xen/arch/x86/cpu/mwait-idle.c @@ -108,6 +108,11 @@ static const struct cpuidle_state { #define CPUIDLE_FLAG_DISABLED 0x1 /* + * Enable interrupts before entering the C-state. On some platforms and for + * some C-states, this may measurably decrease interrupt latency. + */ +#define CPUIDLE_FLAG_IRQ_ENABLE 0x8000 +/* * Set this flag for states where the HW flushes the TLB for us * and so we don't need cross-calls to keep it consistent. * If this flag is set, SW flushes the TLB, so even if the @@ -539,7 +544,7 @@ static struct cpuidle_state __read_mostl static struct cpuidle_state __read_mostly skx_cstates[] = { { .name = "C1", - .flags = MWAIT2flg(0x00), + .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_IRQ_ENABLE, .exit_latency = 2, .target_residency = 2, }, @@ -561,7 +566,7 @@ static struct cpuidle_state __read_mostl static const struct cpuidle_state icx_cstates[] = { { .name = "C1", - .flags = MWAIT2flg(0x00), + .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_IRQ_ENABLE, .exit_latency = 1, .target_residency = 1, }, @@ -842,9 +847,15 @@ static void mwait_idle(void) update_last_cx_stat(power, cx, before); - if (cpu_is_haltable(cpu)) + if (cpu_is_haltable(cpu)) { + if (cx->irq_enable_early) + local_irq_enable(); + mwait_idle_with_hints(cx->address, MWAIT_ECX_INTERRUPT_BREAK); + local_irq_disable(); + } + after = alternative_call(cpuidle_get_tick); cstate_restore_tsc(); @@ -1335,6 +1346,11 @@ static int mwait_idle_cpu_init(struct no cx->latency = cpuidle_state_table[cstate].exit_latency; cx->target_residency = cpuidle_state_table[cstate].target_residency; + if ((cpuidle_state_table[cstate].flags & + CPUIDLE_FLAG_IRQ_ENABLE) && + /* cstate_restore_tsc() needs to be a no-op */ + boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) + cx->irq_enable_early = true; dev->count++; } --- a/xen/include/xen/cpuidle.h +++ b/xen/include/xen/cpuidle.h @@ -42,6 +42,7 @@ struct acpi_processor_cx u8 idx; u8 type; /* ACPI_STATE_Cn */ u8 entry_method; /* ACPI_CSTATE_EM_xxx */ + bool irq_enable_early; u32 address; u32 latency; u32 target_residency; From patchwork Thu Jan 27 15:13:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 12726898 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 794F0C433EF for ; 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rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: [PATCH v3 2/2] x86/mwait-idle: squash stats update when not actually entering C-state Content-Language: en-US From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , Wei Liu , =?utf-8?q?Roger_Pau_Monn=C3=A9?= References: In-Reply-To: X-ClientProxiedBy: AM6P195CA0025.EURP195.PROD.OUTLOOK.COM (2603:10a6:209:81::38) To VI1PR04MB5600.eurprd04.prod.outlook.com (2603:10a6:803:e7::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 917a67c5-ee72-4c07-7e0c-08d9e1a79ea8 X-MS-TrafficTypeDiagnostic: DB8PR04MB6683:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:10000; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: DJcZPDBMuG0vJrK1J+pjqi9GyilvI6u1x+H3hCH3FrHO4kqCFKKZ9HilYiXAIDSc0TeKLnLLO/9E7m56oWbasUOv8KyBJLpmjlWktmK/SHBCS/eE8WkiESNlL6CzY7XQzioTG7RlHFzeqtLdg8kDpIC1TwKbfN8dQUBZgwjiOb8DCu990zb49V+PFjJlLLHr4LRCQXnCMrNu9ELAcsPt3Xywbphd9LZ6+6vepo5AawYq52vU4QB5sxpePXvn08f7PX9f7LYN2Whwife4e/iHD5X+5e7IhJtqvq/pX9BTyxFj2i7jn5QLhHeIAgEFtu0ZySQT9WVc75kNTF4gl32ogi2PBlw4GYhbI4OevHpWlPen1IwJTZ7Y/VE26ADbV2ln6pAQRVy0A7Qb5okvfn4+vMctiQKHgUSoQZ5Kc4/ArbblCMuoZHzp+e/l+J0BPvlRf5Q9GZkfTzOvJoGJTbaEUQBVijSbzz+jZc0dpecc+Mw0QbnLLEAG/XoPWccSOmtPR+2n7FIZKW6xymCM2tY4cCeoeE2ONo47b7fQ1C10KWFOmsMyw+8fsupiC82b99FdeEDYxH72iCooeLYIW8bqRO1X3tOHxLrksVa+mE6lKU9e8qnQxpjCMUka48EA7a1C0jrGo26D2NS7wy4XAfOn3zGNpx0mig0HUqCwrLIP13RfKbxUIOSeru35vPtftXRGSeFR7Be5JboXOPJUbr2MdYyZiKBdPabwtzqfujVmcavqNzKHvs9l8AOJOozmlI1T X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:VI1PR04MB5600.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230001)(366004)(6512007)(508600001)(2906002)(26005)(86362001)(186003)(2616005)(6486002)(31696002)(83380400001)(66946007)(6916009)(316002)(54906003)(15650500001)(5660300002)(36756003)(4326008)(8676002)(31686004)(38100700002)(6506007)(66476007)(8936002)(66556008)(43740500002)(45980500001)(20210929001);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?9WmBM2YmtjHyXJH5iBgG1Cczv4eg?= =?utf-8?q?5xxAIxui5lEORFliwdFQFiF3/+Jl9qXxHxNOHsA8Pn1M6QrU+xrJ3b4synTgr3YCV?= =?utf-8?q?NXS/+eT3n74mtkbHuVw8amrGp0sChvGhbpBslxUtT6kqR4iCQpaysllNtsuFjdvEE?= =?utf-8?q?+ZAEeGH+6vV4Ldrw48k3O/fEzTPndi8NIXJ1ASZAC1w/YqTBxx1X8Ei37Wn9fOiGt?= =?utf-8?q?qVoFx5ub3W4TBpTtirp5/aMEr7RdNEqftU4pZz44XQajjSp+2PvUwpT7DsOYCMFCb?= =?utf-8?q?DQaM1+skHbcWqfTMGxxpr3rAs7WFKGBr84e0i0ElK9btDbXEGb9dVPgvETB7wvLQ3?= =?utf-8?q?wtrHcmLv3KdE1Llt5l9IVdTTp8hHIKk0Mn86EWg0VSbY0tMwAkFHe44PYW1iUgkqM?= =?utf-8?q?JUQO++bA45DJkwR8Nuie972ZhM1Y9wMIrl2YJ6HvVqILfp6/ItnWxW73NCcwvS8na?= =?utf-8?q?r1BpaoDaY1j/FH3HVkXakxsYwkxkHee+q15je+sdFq1qBUw+ETqtM62zIdx7pwxl7?= =?utf-8?q?IlMhq9O54R5Kaje0ORMOAu39nKttzfOurRxRpN6X/LYBZgw6varhi9rD9tfGRPFYw?= =?utf-8?q?oxN5Gej5rMZ2SII+/aCtowd3z9buQLLv/K+oSLv+ER6txJpfUTewPftAx2aNHPPcR?= =?utf-8?q?qxrAhMZ8dIfVPLI/2m9STpyf8E6TO+xKBd9dIGowdrvVztIaS4tlLwI2FzRKCDh1A?= =?utf-8?q?c/KBaIv+JSHmNbHIbhmUtPxwfCV/2pEM8LRmX/PR2yVn7sfF/k6pVt27YT+XqaaqA?= =?utf-8?q?OA5neuuNPe7YyPpl2wR0qQVAnZu/pI/Wgb3eBaGHd9OyUy6j+W5EyS3oESyXQmgk8?= =?utf-8?q?+zwW7Z2PpwrpFKF1zpm7rkJRM52uBd5FCgpo/Ke4AfRD5B7kmqFEn5LT4zuDzNfH+?= =?utf-8?q?D3ziNllt3RtDyFy5JM3bJcy6+rl2NJ2Y/yv2u1gpYnU8ORFA34fwnjvYodbBXtWJu?= =?utf-8?q?YQN7Zq/Csj6htN0NxhhKnl+91Od2lVKT01yYwR2S8bbZcn+bTv8zfniKdY5x/V6Lb?= =?utf-8?q?Pm5sYgq7XB3BoT+SgVBkdHWAMexMQJs/zLC7hXVycRfi0E33xvSP9NAKeyY22wYB9?= =?utf-8?q?IOy+VUVrOGd/j896n4zJ1yup4ucV70huQ4SkL6DzRIx/YMzXif+AUSQIYPWXx569u?= =?utf-8?q?DZ45/AGfuIp/raEG+m9chh2VFnVeFzrbpAljrghDpfaMzdXlpisUcjBA9Eqen+Vu2?= =?utf-8?q?/fRrx+7THRa0ggInPNsrYiox7E6dyBKqedBkzWcqaq2NnZpyUIDGO9U84XgW7GPdb?= =?utf-8?q?fvz6wDMZ8ndywFKG+AWN91ekcO70ftpysuMVIey20TOPNwAqrska4B3i9BNZ3xVgZ?= =?utf-8?q?IVf1osqQtAnV1WF6HGwTScPcl5rd82eC6RRqJuSFIW2iaaEIz+4BV1x0eUjI5T2Cz?= =?utf-8?q?XCIrGJkq5WoSUY4C55ATJ3ZCMkED5k5DhDy3KQ+F7f3VkS50P+MMUe6I53I6y9eB8?= =?utf-8?q?das6yldTnRvZpCGbyQGVPIEDteiT/DNa/J3zxv8bdLhApRNrKbABPTLLd9XUwuJ2W?= =?utf-8?q?CQlNY7v0hGc9JayXkvZCvlNU/wCKg65Aase7J5p0s5KnQ3mL1cCRz5w=3D?= X-OriginatorOrg: suse.com X-MS-Exchange-CrossTenant-Network-Message-Id: 917a67c5-ee72-4c07-7e0c-08d9e1a79ea8 X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB5600.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jan 2022 15:13:48.8360 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f7a17af6-1c5c-4a36-aa8b-f5be247aa4ba X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: SszrsmfOrgtHE1Q8VPFjGX3ABaL7clHQsdMb9m3tI/DN3uwTY+0mlNufUE20N90N63rdBj19jxZtGyrTw3xvtw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB8PR04MB6683 While we don't want to skip calling update_idle_stats(), arrange for it to not increment the overall time spent in the state we didn't really enter. Signed-off-by: Jan Beulich Acked-by: Roger Pau Monné --- RFC: If we wanted to also move the tracing, then I think the part ahead of the if() also would need moving. At that point we could as well move update_last_cx_stat(), too, which afaict would allow skipping update_idle_stats() on the "else" path (which therefore would go away). Yet then, with the setting of power->safe_state moved up a little (which imo it should have been anyway) the two cpu_is_haltable() invocations would only have the lapic_timer_off() invocation left in between. This would then seem to call for simply ditching the 2nd one - acpi-idle also doesn't have a 2nd instance. TBD: For the tracing I wonder if that really needs to come ahead of the local_irq_enable(). Maybe trace_exit_reason() needs to, but quite certainly TRACE_6D() doesn't. --- v3: Also move cstate_restore_tsc() invocation and split ones to update_idle_stats(). v2: New. --- a/xen/arch/x86/cpu/mwait-idle.c +++ b/xen/arch/x86/cpu/mwait-idle.c @@ -854,17 +854,23 @@ static void mwait_idle(void) mwait_idle_with_hints(cx->address, MWAIT_ECX_INTERRUPT_BREAK); local_irq_disable(); - } - after = alternative_call(cpuidle_get_tick); + after = alternative_call(cpuidle_get_tick); + + cstate_restore_tsc(); + + /* Now back in C0. */ + update_idle_stats(power, cx, before, after); + } else { + /* Never left C0. */ + after = alternative_call(cpuidle_get_tick); + update_idle_stats(power, cx, after, after); + } - cstate_restore_tsc(); trace_exit_reason(irq_traced); TRACE_6D(TRC_PM_IDLE_EXIT, cx->type, after, irq_traced[0], irq_traced[1], irq_traced[2], irq_traced[3]); - /* Now back in C0. */ - update_idle_stats(power, cx, before, after); local_irq_enable(); if (!(lapic_timer_reliable_states & (1 << cx->type)))