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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT022.mail.protection.outlook.com (10.13.175.199) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4930.15 via Frontend Transport; Thu, 27 Jan 2022 20:41:34 +0000 Received: from yaz-ethanolx.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.18; Thu, 27 Jan 2022 14:41:33 -0600 From: Yazen Ghannam To: CC: , , , , , , , Yazen Ghannam Subject: [PATCH v4 01/24] EDAC/amd64: Define Data Fabric operations Date: Thu, 27 Jan 2022 20:40:52 +0000 Message-ID: <20220127204115.384161-2-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220127204115.384161-1-yazen.ghannam@amd.com> References: <20220127204115.384161-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e6bd5d02-1723-4404-9f00-08d9e1d5688a X-MS-TrafficTypeDiagnostic: MN2PR12MB3456:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8882; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jan 2022 20:41:34.5959 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e6bd5d02-1723-4404-9f00-08d9e1d5688a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT022.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB3456 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Define a stub to hold operations for different Data Fabric versions. This will be filled in following patches. Set the operations at init-time as appropriate for each model/family group. Also, start a glossary of acronyms used in the translation code. Signed-off-by: Yazen Ghannam --- Link: https://lore.kernel.org/r/20211028175728.121452-6-yazen.ghannam@amd.com v3->v4: * Started glossary. * Included pr_debug() for failing case. v2->v3: * Was patch 6 in v2. * "df_ops" is set at init time. v1->v2: * New in v2. drivers/edac/amd64_edac.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index fba609ada0e6..639dfbea3348 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -988,6 +988,12 @@ static int sys_addr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr) return csrow; } +/* + * Glossary of acronyms used in address translation for Zen-based systems + * + * DF = Data Fabric + */ + /* Protect the PCI config register pairs used for DF indirect access. */ static DEFINE_MUTEX(df_indirect_mutex); @@ -1058,6 +1064,14 @@ struct addr_ctx { u8 inst_id; }; +struct data_fabric_ops { +}; + +struct data_fabric_ops df2_ops = { +}; + +struct data_fabric_ops *df_ops; + static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) { u64 dram_base_addr, dram_limit_addr, dram_hole_base; @@ -1072,6 +1086,11 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr struct addr_ctx ctx; + if (!df_ops) { + pr_debug("Data Fabric Operations not set"); + return -EINVAL; + } + memset(&ctx, 0, sizeof(ctx)); /* Start from the normalized address */ @@ -3958,6 +3977,7 @@ static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt) if (pvt->model >= 0x10 && pvt->model <= 0x2f) { fam_type = &family_types[F17_M10H_CPUS]; pvt->ops = &family_types[F17_M10H_CPUS].ops; + df_ops = &df2_ops; break; } else if (pvt->model >= 0x30 && pvt->model <= 0x3f) { fam_type = &family_types[F17_M30H_CPUS]; @@ -3976,6 +3996,7 @@ static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt) case 0x18: fam_type = &family_types[F17_CPUS]; pvt->ops = &family_types[F17_CPUS].ops; + df_ops = &df2_ops; if (pvt->fam == 0x18) family_types[F17_CPUS].ctl_name = "F18h"; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jan 2022 20:41:38.9060 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3689b4b9-385b-4add-47af-08d9e1d56b1c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT063.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1499 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Add helper functions to read the DramOffset register and to remove the offset from the calculated address. The helper functions will be expanded in future DF versions. Rename the "base" variable to "map_num" to indicate that this is the address map number. An address map is defined with a base and limit value. The map_num variable is used to select the proper base and limit registers to use for the address translation. Signed-off-by: Yazen Ghannam --- Link: https://lore.kernel.org/r/20211028175728.121452-7-yazen.ghannam@amd.com v3->v4: * Include pr_debug() on failure. * Remove leading whitespace in function pointer. v2->v3: * Was patch 7 in v2. * Dropped "df_regs" use. v1->v2: * Moved from arch/x86 to EDAC. * Add function to data_fabric_ops. drivers/edac/amd64_edac.c | 60 ++++++++++++++++++++++++++++++--------- 1 file changed, 46 insertions(+), 14 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 639dfbea3348..837bca7eb1ff 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1057,21 +1057,62 @@ static int df_indirect_read_broadcast(u16 node, u8 func, u16 reg, u32 *lo) return __df_indirect_read(node, func, reg, DF_BROADCAST, lo); } +/* Use "reg_" prefix for raw register values. */ struct addr_ctx { u64 ret_addr; u32 tmp; + u32 reg_dram_offset; u16 nid; u8 inst_id; + u8 map_num; }; struct data_fabric_ops { + u64 (*get_hi_addr_offset)(struct addr_ctx *ctx); }; +static u64 get_hi_addr_offset_df2(struct addr_ctx *ctx) +{ + return (ctx->reg_dram_offset & GENMASK_ULL(31, 20)) << 8; +} + struct data_fabric_ops df2_ops = { + .get_hi_addr_offset = get_hi_addr_offset_df2, }; struct data_fabric_ops *df_ops; +static int get_dram_offset_reg(struct addr_ctx *ctx) +{ + /* Read D18F0x1B4 (DramOffset) */ + if (df_indirect_read_instance(ctx->nid, 0, 0x1B4, ctx->inst_id, &ctx->reg_dram_offset)) + return -EINVAL; + + return 0; +} + +static int remove_dram_offset(struct addr_ctx *ctx) +{ + if (get_dram_offset_reg(ctx)) { + pr_debug("Failed to get DRAM Offset register"); + return -EINVAL; + } + + ctx->map_num = 0; + + /* Remove HiAddrOffset from normalized address, if enabled: */ + if (ctx->reg_dram_offset & BIT(0)) { + u64 hi_addr_offset = df_ops->get_hi_addr_offset(ctx); + + if (ctx->ret_addr >= hi_addr_offset) { + ctx->ret_addr -= hi_addr_offset; + ctx->map_num = 1; + } + } + + return 0; +} + static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) { u64 dram_base_addr, dram_limit_addr, dram_hole_base; @@ -1080,7 +1121,7 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets; u8 intlv_addr_sel, intlv_addr_bit; u8 num_intlv_bits, hashed_bit; - u8 lgcy_mmio_hole_en, base = 0; + u8 lgcy_mmio_hole_en; u8 cs_mask, cs_id = 0; bool hash_enabled = false; @@ -1099,22 +1140,13 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr ctx.nid = nid; ctx.inst_id = umc; - /* Read D18F0x1B4 (DramOffset), check if base 1 is used. */ - if (df_indirect_read_instance(nid, 0, 0x1B4, umc, &ctx.tmp)) + if (remove_dram_offset(&ctx)) { + pr_debug("Failed to remove DRAM offset"); goto out_err; - - /* Remove HiAddrOffset from normalized address, if enabled: */ - if (ctx.tmp & BIT(0)) { - u64 hi_addr_offset = (ctx.tmp & GENMASK_ULL(31, 20)) << 8; - - if (norm_addr >= hi_addr_offset) { - ctx.ret_addr -= hi_addr_offset; - base = 1; - } } /* Read D18F0x110 (DramBaseAddress). */ - if (df_indirect_read_instance(nid, 0, 0x110 + (8 * base), umc, &ctx.tmp)) + if (df_indirect_read_instance(nid, 0, 0x110 + (8 * ctx.map_num), umc, &ctx.tmp)) goto out_err; /* Check if address range is valid. */ @@ -1137,7 +1169,7 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr } /* Read D18F0x114 (DramLimitAddress). */ - if (df_indirect_read_instance(nid, 0, 0x114 + (8 * base), umc, &ctx.tmp)) + if (df_indirect_read_instance(nid, 0, 0x114 + (8 * ctx.map_num), umc, &ctx.tmp)) goto out_err; intlv_num_sockets = (ctx.tmp >> 8) & 0x1; From patchwork Thu Jan 27 20:40:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12727356 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0F84C433EF for ; Thu, 27 Jan 2022 20:41:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344119AbiA0Ulm (ORCPT ); Thu, 27 Jan 2022 15:41:42 -0500 Received: from mail-dm6nam12on2073.outbound.protection.outlook.com ([40.107.243.73]:3035 "EHLO NAM12-DM6-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1344106AbiA0Ull (ORCPT ); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jan 2022 20:41:39.7028 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 02362252-403b-4855-dd5d-08d9e1d56b95 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT063.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB3694 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Move the reading of the base and limit registers into a helper function. Save the raw values in the context struct as they will be parsed later. Signed-off-by: Yazen Ghannam --- Link: https://lore.kernel.org/r/20211028175728.121452-8-yazen.ghannam@amd.com v3->v4: * Include pr_debug() on failure. v2->v3: * Was patch 8 in v2. * Dropped "df_regs" use. v1->v2: * Moved from arch/x86 to EDAC. drivers/edac/amd64_edac.c | 51 ++++++++++++++++++++++++--------------- 1 file changed, 32 insertions(+), 19 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 837bca7eb1ff..d1af1ce716f9 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1062,6 +1062,8 @@ struct addr_ctx { u64 ret_addr; u32 tmp; u32 reg_dram_offset; + u32 reg_base_addr; + u32 reg_limit_addr; u16 nid; u8 inst_id; u8 map_num; @@ -1113,6 +1115,27 @@ static int remove_dram_offset(struct addr_ctx *ctx) return 0; } +static int get_dram_addr_map(struct addr_ctx *ctx) +{ + /* Read D18F0x110 (DramBaseAddress). */ + if (df_indirect_read_instance(ctx->nid, 0, 0x110 + (8 * ctx->map_num), + ctx->inst_id, &ctx->reg_base_addr)) + return -EINVAL; + + /* Check if address range is valid. */ + if (!(ctx->reg_base_addr & BIT(0))) { + pr_debug("Invalid DramBaseAddress range: 0x%x.\n", ctx->reg_base_addr); + return -EINVAL; + } + + /* Read D18F0x114 (DramLimitAddress). */ + if (df_indirect_read_instance(ctx->nid, 0, 0x114 + (8 * ctx->map_num), + ctx->inst_id, &ctx->reg_limit_addr)) + return -EINVAL; + + return 0; +} + static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) { u64 dram_base_addr, dram_limit_addr, dram_hole_base; @@ -1145,21 +1168,15 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr goto out_err; } - /* Read D18F0x110 (DramBaseAddress). */ - if (df_indirect_read_instance(nid, 0, 0x110 + (8 * ctx.map_num), umc, &ctx.tmp)) - goto out_err; - - /* Check if address range is valid. */ - if (!(ctx.tmp & BIT(0))) { - pr_err("%s: Invalid DramBaseAddress range: 0x%x.\n", - __func__, ctx.tmp); + if (get_dram_addr_map(&ctx)) { + pr_debug("Failed to get DRAM address map"); goto out_err; } - lgcy_mmio_hole_en = ctx.tmp & BIT(1); - intlv_num_chan = (ctx.tmp >> 4) & 0xF; - intlv_addr_sel = (ctx.tmp >> 8) & 0x7; - dram_base_addr = (ctx.tmp & GENMASK_ULL(31, 12)) << 16; + lgcy_mmio_hole_en = ctx.reg_base_addr & BIT(1); + intlv_num_chan = (ctx.reg_base_addr >> 4) & 0xF; + intlv_addr_sel = (ctx.reg_base_addr >> 8) & 0x7; + dram_base_addr = (ctx.reg_base_addr & GENMASK_ULL(31, 12)) << 16; /* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */ if (intlv_addr_sel > 3) { @@ -1168,13 +1185,9 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr goto out_err; } - /* Read D18F0x114 (DramLimitAddress). */ - if (df_indirect_read_instance(nid, 0, 0x114 + (8 * ctx.map_num), umc, &ctx.tmp)) - goto out_err; - - intlv_num_sockets = (ctx.tmp >> 8) & 0x1; - intlv_num_dies = (ctx.tmp >> 10) & 0x3; - dram_limit_addr = ((ctx.tmp & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0); + intlv_num_sockets = (ctx.reg_limit_addr >> 8) & 0x1; + intlv_num_dies = (ctx.reg_limit_addr >> 10) & 0x3; + dram_limit_addr = ((ctx.reg_limit_addr & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0); intlv_addr_bit = intlv_addr_sel + 8; From patchwork Thu Jan 27 20:40:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12727357 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52B3BC433F5 for ; Thu, 27 Jan 2022 20:41:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344128AbiA0Ulv (ORCPT ); Thu, 27 Jan 2022 15:41:51 -0500 Received: from mail-dm6nam11on2040.outbound.protection.outlook.com ([40.107.223.40]:18688 "EHLO NAM11-DM6-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1344127AbiA0Ulo (ORCPT ); Thu, 27 Jan 2022 15:41:44 -0500 ARC-Seal: i=1; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jan 2022 20:41:40.5308 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: edc86d2e-1077-44c4-37a7-08d9e1d56c14 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT063.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB2995 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Define a helper function to find the interleaving mode. Define a DF2-specific function now. Future DF versions will have their own functions. Use an enumeration for the interleaving modes to give a human-readable value. Save the interleaving mode in the context struct, since this will be used in multiple functions. Multiple interleaving modes support hashing, so save a boolean in the context struct to check if hashing is enabled. This boolean will be replaced with a function pointer in a later patch. Signed-off-by: Yazen Ghannam --- Link: https://lore.kernel.org/r/20211028175728.121452-9-yazen.ghannam@amd.com v3->v4: * Remove leading whitespace in function pointer definition. * Include pr_debug() on failure. v2->v3: * Was patch 9 in v2. * Updated commit message. v1->v2: * Moved from arch/x86 to EDAC. * Add new function to data_fabric_ops. drivers/edac/amd64_edac.c | 37 ++++++++++++++++++++++++++++++++++--- 1 file changed, 34 insertions(+), 3 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index d1af1ce716f9..4e83a9be4724 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1057,8 +1057,16 @@ static int df_indirect_read_broadcast(u16 node, u8 func, u16 reg, u32 *lo) return __df_indirect_read(node, func, reg, DF_BROADCAST, lo); } +/* These are mapped 1:1 to the hardware values. Special cases are set at > 0x20. */ +enum intlv_modes { + NONE = 0x00, + NOHASH_2CH = 0x01, + DF2_HASH_2CH = 0x21, +}; + /* Use "reg_" prefix for raw register values. */ struct addr_ctx { + enum intlv_modes intlv_mode; u64 ret_addr; u32 tmp; u32 reg_dram_offset; @@ -1067,10 +1075,12 @@ struct addr_ctx { u16 nid; u8 inst_id; u8 map_num; + bool hash_enabled; }; struct data_fabric_ops { u64 (*get_hi_addr_offset)(struct addr_ctx *ctx); + int (*get_intlv_mode)(struct addr_ctx *ctx); }; static u64 get_hi_addr_offset_df2(struct addr_ctx *ctx) @@ -1078,8 +1088,26 @@ static u64 get_hi_addr_offset_df2(struct addr_ctx *ctx) return (ctx->reg_dram_offset & GENMASK_ULL(31, 20)) << 8; } +static int get_intlv_mode_df2(struct addr_ctx *ctx) +{ + ctx->intlv_mode = (ctx->reg_base_addr >> 4) & 0xF; + + if (ctx->intlv_mode == 8) { + ctx->intlv_mode = DF2_HASH_2CH; + ctx->hash_enabled = true; + } + + if (ctx->intlv_mode != NONE && + ctx->intlv_mode != NOHASH_2CH && + ctx->intlv_mode != DF2_HASH_2CH) + return -EINVAL; + + return 0; +} + struct data_fabric_ops df2_ops = { .get_hi_addr_offset = get_hi_addr_offset_df2, + .get_intlv_mode = get_intlv_mode_df2, }; struct data_fabric_ops *df_ops; @@ -1146,7 +1174,6 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr u8 num_intlv_bits, hashed_bit; u8 lgcy_mmio_hole_en; u8 cs_mask, cs_id = 0; - bool hash_enabled = false; struct addr_ctx ctx; @@ -1173,6 +1200,11 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr goto out_err; } + if (df_ops->get_intlv_mode(&ctx)) { + pr_debug("Failed to get interleave mode"); + goto out_err; + } + lgcy_mmio_hole_en = ctx.reg_base_addr & BIT(1); intlv_num_chan = (ctx.reg_base_addr >> 4) & 0xF; intlv_addr_sel = (ctx.reg_base_addr >> 8) & 0x7; @@ -1200,7 +1232,6 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr case 7: intlv_num_chan = 4; break; case 8: intlv_num_chan = 1; - hash_enabled = true; break; default: pr_err("%s: Invalid number of interleaved channels %d.\n", @@ -1302,7 +1333,7 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr ctx.ret_addr += (BIT_ULL(32) - dram_hole_base); } - if (hash_enabled) { + if (ctx.hash_enabled) { /* Save some parentheses and grab ls-bit at the end. */ hashed_bit = (ctx.ret_addr >> 12) ^ (ctx.ret_addr >> 18) ^ From patchwork Thu Jan 27 20:40:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12727358 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA025C433EF for ; Thu, 27 Jan 2022 20:41:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344116AbiA0Ulw (ORCPT ); Thu, 27 Jan 2022 15:41:52 -0500 Received: from mail-dm6nam11on2084.outbound.protection.outlook.com ([40.107.223.84]:41569 "EHLO NAM11-DM6-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1344097AbiA0Ulo (ORCPT ); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jan 2022 20:41:42.0776 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a6d2f354-bbb4-483e-3c13-08d9e1d56d00 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT063.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4063 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Move the address denormalization into a separate helper function. This will be further refactored in later patches. Add the interleave address bit and the CS ID to the context struct. These values will be used by multiple functions. Signed-off-by: Yazen Ghannam --- Link: https://lore.kernel.org/r/20211028175728.121452-10-yazen.ghannam@amd.com v3->v4: * Include pr_debug() on failure. v2->v3: * Was patch 10 in v2. v1->v2: * Moved from arch/x86 to EDAC. drivers/edac/amd64_edac.c | 153 +++++++++++++++++++++----------------- 1 file changed, 84 insertions(+), 69 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 4e83a9be4724..9c61e3fa231a 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1075,6 +1075,8 @@ struct addr_ctx { u16 nid; u8 inst_id; u8 map_num; + u8 intlv_addr_bit; + u8 cs_id; bool hash_enabled; }; @@ -1164,64 +1166,24 @@ static int get_dram_addr_map(struct addr_ctx *ctx) return 0; } -static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) +static int denormalize_addr(struct addr_ctx *ctx) { - u64 dram_base_addr, dram_limit_addr, dram_hole_base; - u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask; u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets; - u8 intlv_addr_sel, intlv_addr_bit; - u8 num_intlv_bits, hashed_bit; - u8 lgcy_mmio_hole_en; - u8 cs_mask, cs_id = 0; - - struct addr_ctx ctx; - - if (!df_ops) { - pr_debug("Data Fabric Operations not set"); - return -EINVAL; - } - - memset(&ctx, 0, sizeof(ctx)); - - /* Start from the normalized address */ - ctx.ret_addr = norm_addr; - - ctx.nid = nid; - ctx.inst_id = umc; - - if (remove_dram_offset(&ctx)) { - pr_debug("Failed to remove DRAM offset"); - goto out_err; - } - - if (get_dram_addr_map(&ctx)) { - pr_debug("Failed to get DRAM address map"); - goto out_err; - } - - if (df_ops->get_intlv_mode(&ctx)) { - pr_debug("Failed to get interleave mode"); - goto out_err; - } - - lgcy_mmio_hole_en = ctx.reg_base_addr & BIT(1); - intlv_num_chan = (ctx.reg_base_addr >> 4) & 0xF; - intlv_addr_sel = (ctx.reg_base_addr >> 8) & 0x7; - dram_base_addr = (ctx.reg_base_addr & GENMASK_ULL(31, 12)) << 16; + u8 intlv_addr_sel = (ctx->reg_base_addr >> 8) & 0x7; + u8 num_intlv_bits, cs_mask = 0; /* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */ if (intlv_addr_sel > 3) { pr_err("%s: Invalid interleave address select %d.\n", __func__, intlv_addr_sel); - goto out_err; + return -EINVAL; } - intlv_num_sockets = (ctx.reg_limit_addr >> 8) & 0x1; - intlv_num_dies = (ctx.reg_limit_addr >> 10) & 0x3; - dram_limit_addr = ((ctx.reg_limit_addr & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0); + intlv_num_sockets = (ctx->reg_limit_addr >> 8) & 0x1; + intlv_num_dies = (ctx->reg_limit_addr >> 10) & 0x3; - intlv_addr_bit = intlv_addr_sel + 8; + ctx->intlv_addr_bit = intlv_addr_sel + 8; /* Re-use intlv_num_chan by setting it equal to log2(#channels) */ switch (intlv_num_chan) { @@ -1236,7 +1198,7 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr default: pr_err("%s: Invalid number of interleaved channels %d.\n", __func__, intlv_num_chan); - goto out_err; + return -EINVAL; } num_intlv_bits = intlv_num_chan; @@ -1244,7 +1206,7 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr if (intlv_num_dies > 2) { pr_err("%s: Invalid number of interleaved nodes/dies %d.\n", __func__, intlv_num_dies); - goto out_err; + return -EINVAL; } num_intlv_bits += intlv_num_dies; @@ -1256,7 +1218,7 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr if (num_intlv_bits > 4) { pr_err("%s: Invalid interleave bits %d.\n", __func__, num_intlv_bits); - goto out_err; + return -EINVAL; } if (num_intlv_bits > 0) { @@ -1269,41 +1231,43 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr * umc/channel# as instance id of the coherent slave * for FICAA. */ - if (df_indirect_read_instance(nid, 0, 0x50, umc, &ctx.tmp)) - goto out_err; + if (df_indirect_read_instance(ctx->nid, 0, 0x50, ctx->inst_id, &ctx->tmp)) + return -EINVAL; - cs_fabric_id = (ctx.tmp >> 8) & 0xFF; + cs_fabric_id = (ctx->tmp >> 8) & 0xFF; die_id_bit = 0; /* If interleaved over more than 1 channel: */ if (intlv_num_chan) { die_id_bit = intlv_num_chan; cs_mask = (1 << die_id_bit) - 1; - cs_id = cs_fabric_id & cs_mask; + ctx->cs_id = cs_fabric_id & cs_mask; } sock_id_bit = die_id_bit; /* Read D18F1x208 (SystemFabricIdMask). */ if (intlv_num_dies || intlv_num_sockets) - if (df_indirect_read_broadcast(nid, 1, 0x208, &ctx.tmp)) - goto out_err; + if (df_indirect_read_broadcast(ctx->nid, 1, 0x208, &ctx->tmp)) + return -EINVAL; /* If interleaved over more than 1 die. */ if (intlv_num_dies) { sock_id_bit = die_id_bit + intlv_num_dies; - die_id_shift = (ctx.tmp >> 24) & 0xF; - die_id_mask = (ctx.tmp >> 8) & 0xFF; + die_id_shift = (ctx->tmp >> 24) & 0xF; + die_id_mask = (ctx->tmp >> 8) & 0xFF; - cs_id |= ((cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit; + ctx->cs_id |= ((cs_fabric_id & die_id_mask) + >> die_id_shift) << die_id_bit; } /* If interleaved over more than 1 socket. */ if (intlv_num_sockets) { - socket_id_shift = (ctx.tmp >> 28) & 0xF; - socket_id_mask = (ctx.tmp >> 16) & 0xFF; + socket_id_shift = (ctx->tmp >> 28) & 0xF; + socket_id_mask = (ctx->tmp >> 16) & 0xFF; - cs_id |= ((cs_fabric_id & socket_id_mask) >> socket_id_shift) << sock_id_bit; + ctx->cs_id |= ((cs_fabric_id & socket_id_mask) + >> socket_id_shift) << sock_id_bit; } /* @@ -1314,12 +1278,63 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr * bits there are. "intlv_addr_bit" tells us how many "Y" bits * there are (where "I" starts). */ - temp_addr_y = ctx.ret_addr & GENMASK_ULL(intlv_addr_bit - 1, 0); - temp_addr_i = (cs_id << intlv_addr_bit); - temp_addr_x = (ctx.ret_addr & GENMASK_ULL(63, intlv_addr_bit)) << num_intlv_bits; - ctx.ret_addr = temp_addr_x | temp_addr_i | temp_addr_y; + temp_addr_y = ctx->ret_addr & GENMASK_ULL(ctx->intlv_addr_bit - 1, 0); + temp_addr_i = (ctx->cs_id << ctx->intlv_addr_bit); + temp_addr_x = (ctx->ret_addr & GENMASK_ULL(63, ctx->intlv_addr_bit)) + << num_intlv_bits; + ctx->ret_addr = temp_addr_x | temp_addr_i | temp_addr_y; } + return 0; +} + +static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) +{ + u64 dram_base_addr, dram_limit_addr, dram_hole_base; + + u8 hashed_bit; + u8 lgcy_mmio_hole_en; + + struct addr_ctx ctx; + + if (!df_ops) { + pr_debug("Data Fabric Operations not set"); + return -EINVAL; + } + + memset(&ctx, 0, sizeof(ctx)); + + /* We start from the normalized address */ + ctx.ret_addr = norm_addr; + + ctx.nid = nid; + ctx.inst_id = umc; + + if (remove_dram_offset(&ctx)) { + pr_debug("Failed to remove DRAM offset"); + goto out_err; + } + + if (get_dram_addr_map(&ctx)) { + pr_debug("Failed to get DRAM address map"); + goto out_err; + } + + if (df_ops->get_intlv_mode(&ctx)) { + pr_debug("Failed to get interleave mode"); + goto out_err; + } + + if (denormalize_addr(&ctx)) { + pr_debug("Failed to denormalize address"); + goto out_err; + } + + lgcy_mmio_hole_en = ctx.reg_base_addr & BIT(1); + dram_base_addr = (ctx.reg_base_addr & GENMASK_ULL(31, 12)) << 16; + + dram_limit_addr = ((ctx.reg_limit_addr & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0); + /* Add dram base address */ ctx.ret_addr += dram_base_addr; @@ -1339,12 +1354,12 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr (ctx.ret_addr >> 18) ^ (ctx.ret_addr >> 21) ^ (ctx.ret_addr >> 30) ^ - cs_id; + ctx.cs_id; hashed_bit &= BIT(0); - if (hashed_bit != ((ctx.ret_addr >> intlv_addr_bit) & BIT(0))) - ctx.ret_addr ^= BIT(intlv_addr_bit); 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Thu, 27 Jan 2022 20:41:43 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT063.mail.protection.outlook.com (10.13.175.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4930.15 via Frontend Transport; Thu, 27 Jan 2022 20:41:42 +0000 Received: from yaz-ethanolx.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.18; Thu, 27 Jan 2022 14:41:39 -0600 From: Yazen Ghannam To: CC: , , , , , , , Yazen Ghannam Subject: [PATCH v4 06/24] EDAC/amd64: Define function to add DRAM base and hole Date: Thu, 27 Jan 2022 20:40:57 +0000 Message-ID: <20220127204115.384161-7-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220127204115.384161-1-yazen.ghannam@amd.com> References: <20220127204115.384161-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ea53beee-c25b-436b-3414-08d9e1d56d7c X-MS-TrafficTypeDiagnostic: MWHPR12MB1199:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2733; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jan 2022 20:41:42.8900 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ea53beee-c25b-436b-3414-08d9e1d56d7c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT063.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1199 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Move adding of DRAM base and hole into a separate helper function. Signed-off-by: Yazen Ghannam --- Link: https://lore.kernel.org/r/20211028175728.121452-11-yazen.ghannam@amd.com v3->v4: * Include pr_debug() on failure. v2->v3: * Was patch 11 in v2. v1->v2: * Moved from arch/x86 to EDAC. drivers/edac/amd64_edac.c | 43 +++++++++++++++++++++++---------------- 1 file changed, 26 insertions(+), 17 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 9c61e3fa231a..350204eadb27 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1288,12 +1288,32 @@ static int denormalize_addr(struct addr_ctx *ctx) return 0; } -static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) +static int add_base_and_hole(struct addr_ctx *ctx) { - u64 dram_base_addr, dram_limit_addr, dram_hole_base; + u64 dram_base_addr = (ctx->reg_base_addr & GENMASK_ULL(31, 12)) << 16; + + /* Add dram base address */ + ctx->ret_addr += dram_base_addr; + + /* If legacy MMIO hole enabled */ + if (ctx->reg_base_addr & BIT(1)) { + u32 dram_hole_base; + + if (df_indirect_read_broadcast(ctx->nid, 0, 0x104, &dram_hole_base)) + return -EINVAL; + + dram_hole_base &= GENMASK(31, 24); + if (ctx->ret_addr >= dram_hole_base) + ctx->ret_addr += (BIT_ULL(32) - dram_hole_base); + } + + return 0; +} +static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) +{ + u64 dram_limit_addr; u8 hashed_bit; - u8 lgcy_mmio_hole_en; struct addr_ctx ctx; @@ -1330,22 +1350,11 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr goto out_err; } - lgcy_mmio_hole_en = ctx.reg_base_addr & BIT(1); - dram_base_addr = (ctx.reg_base_addr & GENMASK_ULL(31, 12)) << 16; - dram_limit_addr = ((ctx.reg_limit_addr & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0); - /* Add dram base address */ - ctx.ret_addr += dram_base_addr; - - /* If legacy MMIO hole enabled */ - if (lgcy_mmio_hole_en) { - if (df_indirect_read_broadcast(nid, 0, 0x104, &ctx.tmp)) - goto out_err; - - dram_hole_base = ctx.tmp & GENMASK(31, 24); - if (ctx.ret_addr >= dram_hole_base) - ctx.ret_addr += (BIT_ULL(32) - dram_hole_base); + if (add_base_and_hole(&ctx)) { + pr_debug("Failed to add DRAM base address and hole"); + goto out_err; } if (ctx.hash_enabled) { From patchwork Thu Jan 27 20:40:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12727361 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 612ACC4332F for ; Thu, 27 Jan 2022 20:41:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344149AbiA0Ulw (ORCPT ); Thu, 27 Jan 2022 15:41:52 -0500 Received: from mail-mw2nam12on2059.outbound.protection.outlook.com ([40.107.244.59]:41440 "EHLO NAM12-MW2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1344135AbiA0Ulp (ORCPT ); Thu, 27 Jan 2022 15:41:45 -0500 ARC-Seal: i=1; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jan 2022 20:41:43.4525 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4ca49c76-bbf1-4380-0727-08d9e1d56dd2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT063.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR1201MB0206 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Move the dehashing code into a separate helper function. Define a DF2-specific function for the current code. Specific helper functions will be added for future DF versions. The dehashing function used is based on the interleaving mode rather than the Data Fabric version. So save the function pointer in the context struct. The use of "df2" in the name of the current function is only because the interleaving mode using it only appears on Data Fabric 2 systems. Signed-off-by: Yazen Ghannam --- Link: https://lore.kernel.org/r/20211028175728.121452-12-yazen.ghannam@amd.com v3->v4: * Include pr_debug() on failure. v2->v3: * Was patch 12 in v2. v1->v2: * Moved from arch/x86 to EDAC. * Add new function pointer in ctx struct. drivers/edac/amd64_edac.c | 36 +++++++++++++++++++++--------------- 1 file changed, 21 insertions(+), 15 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 350204eadb27..da2d0d9ce406 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1077,7 +1077,7 @@ struct addr_ctx { u8 map_num; u8 intlv_addr_bit; u8 cs_id; - bool hash_enabled; + int (*dehash_addr)(struct addr_ctx *ctx); }; struct data_fabric_ops { @@ -1090,13 +1090,29 @@ static u64 get_hi_addr_offset_df2(struct addr_ctx *ctx) return (ctx->reg_dram_offset & GENMASK_ULL(31, 20)) << 8; } +static int dehash_addr_df2(struct addr_ctx *ctx) +{ + u8 hashed_bit = (ctx->ret_addr >> 12) ^ + (ctx->ret_addr >> 18) ^ + (ctx->ret_addr >> 21) ^ + (ctx->ret_addr >> 30) ^ + ctx->cs_id; + + hashed_bit &= BIT(0); + + if (hashed_bit != ((ctx->ret_addr >> ctx->intlv_addr_bit) & BIT(0))) + ctx->ret_addr ^= BIT(ctx->intlv_addr_bit); + + return 0; +} + static int get_intlv_mode_df2(struct addr_ctx *ctx) { ctx->intlv_mode = (ctx->reg_base_addr >> 4) & 0xF; if (ctx->intlv_mode == 8) { ctx->intlv_mode = DF2_HASH_2CH; - ctx->hash_enabled = true; + ctx->dehash_addr = dehash_addr_df2; } if (ctx->intlv_mode != NONE && @@ -1313,7 +1329,6 @@ static int add_base_and_hole(struct addr_ctx *ctx) static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) { u64 dram_limit_addr; - u8 hashed_bit; struct addr_ctx ctx; @@ -1357,18 +1372,9 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr goto out_err; } - if (ctx.hash_enabled) { - /* Save some parentheses and grab ls-bit at the end. */ - hashed_bit = (ctx.ret_addr >> 12) ^ - (ctx.ret_addr >> 18) ^ - (ctx.ret_addr >> 21) ^ - (ctx.ret_addr >> 30) ^ - ctx.cs_id; - - hashed_bit &= BIT(0); - - if (hashed_bit != ((ctx.ret_addr >> ctx.intlv_addr_bit) & BIT(0))) - ctx.ret_addr ^= BIT(ctx.intlv_addr_bit); + if (ctx.dehash_addr && ctx.dehash_addr(&ctx)) { + pr_debug("Failed to dehash address"); + goto out_err; } /* Is calculated system address is above DRAM limit address? */ From patchwork Thu Jan 27 20:40:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12727359 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99D2BC43219 for ; Thu, 27 Jan 2022 20:41:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344118AbiA0Uly (ORCPT ); Thu, 27 Jan 2022 15:41:54 -0500 Received: from mail-sn1anam02on2055.outbound.protection.outlook.com ([40.107.96.55]:12311 "EHLO NAM02-SN1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1344143AbiA0Ulr (ORCPT ); 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Signed-off-by: Yazen Ghannam --- Link: https://lore.kernel.org/r/20211028175728.121452-13-yazen.ghannam@amd.com v3->v4: * Include pr_debug() on failure. v2->v3: * Was patch 13 in v2. v1->v2: * Moved from arch/x86 to EDAC. drivers/edac/amd64_edac.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index da2d0d9ce406..139dca3a3ba4 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1326,10 +1326,20 @@ static int add_base_and_hole(struct addr_ctx *ctx) return 0; } -static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) +static int addr_over_limit(struct addr_ctx *ctx) { - u64 dram_limit_addr; + u64 dram_limit_addr = ((ctx->reg_limit_addr & GENMASK_ULL(31, 12)) << 16) + | GENMASK_ULL(27, 0); + + /* Is calculated system address above DRAM limit address? */ + if (ctx->ret_addr > dram_limit_addr) + return -EINVAL; + + return 0; +} +static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) +{ struct addr_ctx ctx; if (!df_ops) { @@ -1365,8 +1375,6 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr goto out_err; } - dram_limit_addr = ((ctx.reg_limit_addr & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0); - if (add_base_and_hole(&ctx)) { pr_debug("Failed to add DRAM base address and hole"); goto out_err; @@ -1377,9 +1385,10 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr goto out_err; } - /* Is calculated system address is above DRAM limit address? */ - if (ctx.ret_addr > dram_limit_addr) + if (addr_over_limit(&ctx)) { + pr_debug("Calculated address is over limit"); goto out_err; + } *sys_addr = ctx.ret_addr; return 0; From patchwork Thu Jan 27 20:41:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12727366 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B7ACC433EF for ; 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Thu, 27 Jan 2022 14:41:40 -0600 From: Yazen Ghannam To: CC: , , , , , , , Yazen Ghannam Subject: [PATCH v4 09/24] EDAC/amd64: Remove goto statements Date: Thu, 27 Jan 2022 20:41:00 +0000 Message-ID: <20220127204115.384161-10-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220127204115.384161-1-yazen.ghannam@amd.com> References: <20220127204115.384161-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ce1eca47-221d-4cc8-3e38-08d9e1d56efe X-MS-TrafficTypeDiagnostic: CO6PR12MB5427:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2276; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: VovFsceUefgWjuB4T9TGM9xPrXOV99xMsHls58zFKIZjCW2cpgvk9R1W9BsHFvSejNqzWLDxHnOoVkgK/52TUo3xXesKkXFe6uwqmCTif71E+Agc3X1wiNWezNQkOA+RlXthx2j/oqfczs5yk6ecDeVzzUrWXJV5ddYUCqQuNjFc62UhrimrM2A51N23rLK/i4k3daYUmNDEwjaiPQFQOGZovQ6XIpqIvIimbKLZgI9vHgImh89j/KRMcNq0TvhdF0LyJBDlOtemK3Ztx527xqIXNoa8LGW5/9cw7NraiC9hdmqPmljJmFQ9ch61MQOfMUMWqybiJaxVL2hCCivyvV1/jInRS8vgygpSBcJhPql69RdsQP4jXZsDMSBW+mj2ijrUCTJNC60XVZtzGeD9bjFu71faonnhhS/J3SMV1S86qZSW/x+c9eqQ8lcVkUf+Yl7o156hm3aFO01z0xXia5T4tuRuBj26fL+/STruiRp9flubcHrP3vi131ns4Alpk6lZvX7oevybwqB/El9ctwOWM0ye5s5pA6aga7ataFS6Z4o1OLowQwywyN6p1sS0GOXiPlYmFsRkjToT/nlBppc0a2ZdHB9Ufmt/OrIQArHsLViwhe7bZfHpVL1ZVfcPV/NvIRZRWbAjugpH2UfP9RBgM5vfHnzW8dEpbndzifHCdjVd4+nE8Fb7/EhXlCfrtUkSUJtv1EihvOTJ2Do3pi3B6mEOkvNwid9DOCjAtDuRqp73kJlQVeVzgSz1NHh2OoPsPGKq1FxJYqqlUk+E+5a0IlKDOQe+2JHo97gig6s= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230001)(4636009)(36840700001)(46966006)(40470700004)(86362001)(6916009)(316002)(508600001)(47076005)(6666004)(70206006)(70586007)(4326008)(44832011)(5660300002)(8936002)(8676002)(7696005)(36860700001)(356005)(36756003)(26005)(40460700003)(966005)(81166007)(82310400004)(2906002)(2616005)(1076003)(54906003)(16526019)(426003)(186003)(336012)(83380400001)(36900700001)(20210929001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jan 2022 20:41:45.4044 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ce1eca47-221d-4cc8-3e38-08d9e1d56efe X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT028.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR12MB5427 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org ...and just return error codes directly. Signed-off-by: Yazen Ghannam --- Link: https://lore.kernel.org/r/20211028175728.121452-14-yazen.ghannam@amd.com v3->v4: * No change. v2->v3: * Was patch 14 in v2. v1->v2: * Moved from arch/x86 to EDAC. drivers/edac/amd64_edac.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 139dca3a3ba4..d568ad886d35 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1357,44 +1357,41 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr if (remove_dram_offset(&ctx)) { pr_debug("Failed to remove DRAM offset"); - goto out_err; + return -EINVAL; } if (get_dram_addr_map(&ctx)) { pr_debug("Failed to get DRAM address map"); - goto out_err; + return -EINVAL; } if (df_ops->get_intlv_mode(&ctx)) { pr_debug("Failed to get interleave mode"); - goto out_err; + return -EINVAL; } if (denormalize_addr(&ctx)) { pr_debug("Failed to denormalize address"); - goto out_err; + return -EINVAL; } if (add_base_and_hole(&ctx)) { pr_debug("Failed to add DRAM base address and hole"); - goto out_err; + return -EINVAL; } if (ctx.dehash_addr && ctx.dehash_addr(&ctx)) { pr_debug("Failed to dehash address"); - goto out_err; + return -EINVAL; } if (addr_over_limit(&ctx)) { pr_debug("Calculated address is over limit"); - goto out_err; + return -EINVAL; } *sys_addr = ctx.ret_addr; return 0; - -out_err: - return -EINVAL; } static int get_channel_from_ecc_syndrome(struct mem_ctl_info *, u16); From patchwork Thu Jan 27 20:41:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12727362 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D1C3C4321E for ; Thu, 27 Jan 2022 20:41:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344168AbiA0Ulx (ORCPT ); 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Thu, 27 Jan 2022 14:41:41 -0600 From: Yazen Ghannam To: CC: , , , , , , , Yazen Ghannam Subject: [PATCH v4 10/24] EDAC/amd64: Define function to get Interleave Address Bit Date: Thu, 27 Jan 2022 20:41:01 +0000 Message-ID: <20220127204115.384161-11-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220127204115.384161-1-yazen.ghannam@amd.com> References: <20220127204115.384161-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 678671f8-5ad9-4536-c82d-08d9e1d56f3e X-MS-TrafficTypeDiagnostic: DM6PR12MB4418:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4714; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: bhEdCuTeId93Mi8HUqEgqw2J+gJT9ELS93QJZ7ch4zalRt+DTqwOXq/Ouo10mWBQpfy/ymFmKSh6vcuVxhA5xndWnj6wj7lw7AZLyw1zOy+vN6FHucEz6MpJBFmap/LfhjaONr7EIzxFXe90U2RZemcmUE+ljzr44SrPyZlboh0Ue/ac/WOryJPSLva1OWlJHEqejR0jbkXxAIa6ny69d+XMjtwUHa06OYQZeveXzjLWpzTASE1WWZK39GEA7xp0RhV/ViQyyxHBlOtrcV/XobnJOdPzbs65h3ETR5L+0Yc+5Tq0eebSPak6DuuIFk8FrH+ks1VX+1v5l7gW6Yo/E8wyTsrRvX7MUEGLDJ3VOKB2BwkDvIaDZHhmgU4Oj5Z0FhKGzMCob1sfttCGEuptLFIXCwhqS2L656WBZKi7cNYdbPsMsWlBk1Y/7iqR2e8j2rsH5SVoD3pT1nYUNrj7hUrZ7lZ9vQ6vLAUi6Dq5nzZ3FB2nUXbt/wFSnDfhrOHADyJVKu8RkqhdWQTUHbNmqAlPm9MiTVUGxN0nAY2pJYclpNQ3iM2wIpzVnh/yCoTgZCjpYWbzrri438z/6g46qIT7kgtbpar+OTj9QaQrmS2OR9JtSmpVoubnj84AwQFh8i5bjnYa9f/zqtmwWZyWGdtWRvZqvE0jA5mbZFOp0d0y/hZcMDLKWu3IIUmTgRiDv6niwuuXxLvBAthfCPLlomlWlOSvJjfilmBjzF0Xzya82cyQ08/MZotw7RGS0xJUxdRK+VL16e8wfKt4NLMRV59fgipIT0LCo7ynLCRc3ks= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230001)(4636009)(40470700004)(36840700001)(46966006)(8676002)(36756003)(4326008)(70206006)(70586007)(8936002)(47076005)(5660300002)(6916009)(44832011)(40460700003)(316002)(36860700001)(54906003)(82310400004)(83380400001)(81166007)(356005)(186003)(7696005)(86362001)(2616005)(26005)(6666004)(16526019)(426003)(336012)(1076003)(966005)(2906002)(508600001)(36900700001)(20210929001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jan 2022 20:41:45.8430 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 678671f8-5ad9-4536-c82d-08d9e1d56f3e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT063.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4418 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Move code to find the interleave address bit into a separate helper function. Signed-off-by: Yazen Ghannam --- Link: https://lore.kernel.org/r/20211028175728.121452-16-yazen.ghannam@amd.com v3->v4: * No change. v2->v3: * Was patch 16 in v2. v1->v2: * Moved from arch/x86 to EDAC. drivers/edac/amd64_edac.c | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index d568ad886d35..53d9c4b1c233 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1182,25 +1182,33 @@ static int get_dram_addr_map(struct addr_ctx *ctx) return 0; } -static int denormalize_addr(struct addr_ctx *ctx) +static int get_intlv_addr_bit(struct addr_ctx *ctx) { - u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask; - u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets; u8 intlv_addr_sel = (ctx->reg_base_addr >> 8) & 0x7; - u8 num_intlv_bits, cs_mask = 0; /* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */ if (intlv_addr_sel > 3) { - pr_err("%s: Invalid interleave address select %d.\n", - __func__, intlv_addr_sel); + pr_debug("Invalid interleave address select %d.\n", intlv_addr_sel); return -EINVAL; } + ctx->intlv_addr_bit = intlv_addr_sel + 8; + + return 0; +} + +static int denormalize_addr(struct addr_ctx *ctx) +{ + u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask; + u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets; + u8 num_intlv_bits, cs_mask = 0; + + if (get_intlv_addr_bit(ctx)) + return -EINVAL; + intlv_num_sockets = (ctx->reg_limit_addr >> 8) & 0x1; intlv_num_dies = (ctx->reg_limit_addr >> 10) & 0x3; - ctx->intlv_addr_bit = intlv_addr_sel + 8; - /* Re-use intlv_num_chan by setting it equal to log2(#channels) */ switch (intlv_num_chan) { case 0: intlv_num_chan = 0; break; From patchwork Thu Jan 27 20:41:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12727363 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74B05C4167B for ; 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Thu, 27 Jan 2022 14:41:41 -0600 From: Yazen Ghannam To: CC: , , , , , , , Yazen Ghannam Subject: [PATCH v4 11/24] EDAC/amd64: Skip denormalization if no interleaving Date: Thu, 27 Jan 2022 20:41:02 +0000 Message-ID: <20220127204115.384161-12-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220127204115.384161-1-yazen.ghannam@amd.com> References: <20220127204115.384161-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a0bd9119-e304-407c-ea77-08d9e1d56f4c X-MS-TrafficTypeDiagnostic: DM5PR12MB2407:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5516; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: k0O1HniytTaa3wNV7/MgdlWiyOFTdid76r9AgGQ5lPBJcPbc8qg/IsFOQ26mrt8+kQNWb+kQFwRMCIBR/3Y43iEXTW/3C337Mn2ygsv8ZkTuJYIQkc6O2o3IYJuUjURlHPG0TCxxYx0iISo4bYCRE49t0iZ4zBWUc3ecW0f5KRoarY5wzEmw/PZ0wYgZcU71DSJMc9Ls8/a5+XeI3AWvoSHnfUNYO24eUOTVxlqvnNvB2WCV5GvlfjsGqvcBbdyIEUzflDL56jsWqH96ys3ZS0tPiUrW4mVHGCaGfXZWlGQMMF+GwtRTR2zJsCsktH77JFdfuW1Un78HkRA2Ssdmv7B+EG3VvpSXryMMffAmMqHqP5mbE+fB6T/oojXqaYohPhTBsQX4d8mTP2LDJgpdlceX5C4jURH3NscUMuukk3C9S85Y+wmvAJXjU7hP0OMlWeFObWjZj1WiSwNxEdzOitYNZUb1Nhx8k+fNMhkdAxFcsx9INncdSWa6w0iIseUXM6oSX/Bhf26J25shmn+ny2d+Ui4uFLNnf59u/1i3HNwzv72TD3qGEFuGVECXTMU5CKoLx/xj6wb2dHQtXSSLJ1mkQXW20n6xmxe04PIc0yXK+nYaGSPeqUWp/6rB9y8ErfB1fugoQLH3oYZJr/rSZZK27kPBE6iqqq6jwoidW0EwUFVOqb7dj+HAcnlrV48bHyL0KymJIZAoiBnbxe+9zZJvD+Rpl+qYkqFWmwEu/rMd28uNM6Te+cZmEHtXNQR4gg+KFQBwK4ePVQM1QPj3vWiQUvH/0TYIsFLx4EyLbzKBrtq2CpKYNYG9PAxmTch7hYNprmit8+KUh89mXRR8IONTpLTYAXPpf6AAatJSopV9th2u+raKYFP0T3TVZjh5 X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(46966006)(40470700004)(36840700001)(4744005)(1076003)(316002)(44832011)(5660300002)(8936002)(54906003)(40460700003)(4326008)(81166007)(86362001)(8676002)(426003)(2906002)(82310400004)(70586007)(2616005)(47076005)(16526019)(186003)(6666004)(7696005)(6916009)(36756003)(26005)(36860700001)(70206006)(966005)(508600001)(356005)(336012)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jan 2022 20:41:45.9200 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a0bd9119-e304-407c-ea77-08d9e1d56f4c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT028.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB2407 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Denormalization doesn't apply to the "no interleaving" mode, so return early without error in this case. Signed-off-by: Yazen Ghannam --- Link: https://lore.kernel.org/r/20211028175728.121452-17-yazen.ghannam@amd.com v3->v4: * No change. v2->v3: * Was patch 17 in v2. v1->v2: * Moved from arch/x86 to EDAC. drivers/edac/amd64_edac.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 53d9c4b1c233..b75311acbe13 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1203,6 +1203,10 @@ static int denormalize_addr(struct addr_ctx *ctx) u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets; u8 num_intlv_bits, cs_mask = 0; + /* Return early if no interleaving. */ + if (ctx->intlv_mode == NONE) + return 0; + if (get_intlv_addr_bit(ctx)) return -EINVAL; From patchwork Thu Jan 27 20:41:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12727367 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2EA3CC43217 for ; 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Thu, 27 Jan 2022 14:41:41 -0600 From: Yazen Ghannam To: CC: , , , , , , , Yazen Ghannam Subject: [PATCH v4 12/24] EDAC/amd64: Define function to get number of interleaved channels Date: Thu, 27 Jan 2022 20:41:03 +0000 Message-ID: <20220127204115.384161-13-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220127204115.384161-1-yazen.ghannam@amd.com> References: <20220127204115.384161-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 79944e87-69bc-4276-d024-08d9e1d56fb5 X-MS-TrafficTypeDiagnostic: BY5PR12MB4115:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:530; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 0JHcvOGvSXIclGDOpobCC503EVg1lZME1Wkq3/e7hjaB4VEff4Rqc+ub7uWl9nDcoaHk5bTAgPrOi/dIiVihQul8p4pAr1wLfyHlT0SLm+jLRfLb/x8sL0PzkBqlaHAQNBD7hO17/kYX9JSTEOoUsj6MC7iACytb3895DCXKVZptB6ukSMN+kXJZIL9cY1j+7U3eK+f0ClmO9W69z/uLTqz6YjJAuCcl1uvFdwXjrLK3Xz4Rzm2VUauT8rvcDIW8Q5sLXPrDHjoUdON4/qw/x03NH+Nb2+/mLaZJF304dGXd8W1Rng0uDqE6zd+2DcKLCRksfJsxOPu0Q3Me7ZEOSDC/DUwZc7C9ttyZ3jtxZx59fzKyNXzEgslhiT+mTB+l4mQ0OxtcI0l0INGgwRI9QCLrMQyn4P/3OKyR3Z/yWgFyKDJ6Sq95fM+CRpXHTqpzgRxXX5HPqTxAmb675o8hxCRR7fOmhd8YiwDtQgPRezu9Gf2inGE3Yed9V1kgZmzOuADxctajrQrIexJWC50KoFHCIFOlsqqQNUuNqIzLwvK6t6ch5kvoG92B2g0s5TkRGJ23P5pw06vyD5BANkQhqweAYvwmfTHSeVziXoOdfVFCp9AVrQrroOqGIEngrBPNyEXGpwCTI7F5SpMHkJ3CC3f7HrmVqrGHPCIEGo/sAs2PhIDtUS+//OZxL56rBcEb8HToVzDVEEK66oC/HIIpiB+sVSbFw5trDS2tounxa7+ayokmDdZzZ1/QA0jx7BPQGLeYbrnppZNhIMS4A0WrbJiCKfJjyQvICiwY2s0Ears= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230001)(4636009)(46966006)(40470700004)(36840700001)(82310400004)(2906002)(426003)(186003)(316002)(26005)(5660300002)(47076005)(86362001)(1076003)(2616005)(336012)(6916009)(54906003)(16526019)(83380400001)(4326008)(966005)(36756003)(70206006)(70586007)(356005)(8676002)(6666004)(8936002)(7696005)(44832011)(508600001)(81166007)(40460700003)(36860700001)(36900700001)(20210929001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jan 2022 20:41:46.6074 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 79944e87-69bc-4276-d024-08d9e1d56fb5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT028.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4115 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Move number of interleaved channel calculation to a separate helper function. Drop unused cases. Signed-off-by: Yazen Ghannam --- Link: https://lore.kernel.org/r/20211028175728.121452-18-yazen.ghannam@amd.com v3->v4: * No change. v2->v3: * Was patch 18 in v2. v1->v2: * Moved from arch/x86 to EDAC. drivers/edac/amd64_edac.c | 42 +++++++++++++++++++++------------------ 1 file changed, 23 insertions(+), 19 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index b75311acbe13..87439374a076 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1076,6 +1076,7 @@ struct addr_ctx { u8 inst_id; u8 map_num; u8 intlv_addr_bit; + u8 intlv_num_chan; u8 cs_id; int (*dehash_addr)(struct addr_ctx *ctx); }; @@ -1197,10 +1198,27 @@ static int get_intlv_addr_bit(struct addr_ctx *ctx) return 0; } +static void get_intlv_num_chan(struct addr_ctx *ctx) +{ + /* Save the log2(# of channels). */ + switch (ctx->intlv_mode) { + case NONE: + ctx->intlv_num_chan = 0; + break; + case NOHASH_2CH: + case DF2_HASH_2CH: + ctx->intlv_num_chan = 1; + break; + default: + /* Valid interleaving modes where checked earlier. */ + break; + } +} + static int denormalize_addr(struct addr_ctx *ctx) { u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask; - u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets; + u8 intlv_num_dies, intlv_num_sockets; u8 num_intlv_bits, cs_mask = 0; /* Return early if no interleaving. */ @@ -1213,23 +1231,9 @@ static int denormalize_addr(struct addr_ctx *ctx) intlv_num_sockets = (ctx->reg_limit_addr >> 8) & 0x1; intlv_num_dies = (ctx->reg_limit_addr >> 10) & 0x3; - /* Re-use intlv_num_chan by setting it equal to log2(#channels) */ - switch (intlv_num_chan) { - case 0: intlv_num_chan = 0; break; - case 1: intlv_num_chan = 1; break; - case 3: intlv_num_chan = 2; break; - case 5: intlv_num_chan = 3; break; - case 7: intlv_num_chan = 4; break; - - case 8: intlv_num_chan = 1; - break; - default: - pr_err("%s: Invalid number of interleaved channels %d.\n", - __func__, intlv_num_chan); - return -EINVAL; - } + get_intlv_num_chan(ctx); - num_intlv_bits = intlv_num_chan; + num_intlv_bits = ctx->intlv_num_chan; if (intlv_num_dies > 2) { pr_err("%s: Invalid number of interleaved nodes/dies %d.\n", @@ -1266,8 +1270,8 @@ static int denormalize_addr(struct addr_ctx *ctx) die_id_bit = 0; /* If interleaved over more than 1 channel: */ - if (intlv_num_chan) { - die_id_bit = intlv_num_chan; + if (ctx->intlv_num_chan) { + die_id_bit = ctx->intlv_num_chan; cs_mask = (1 << die_id_bit) - 1; ctx->cs_id = cs_fabric_id & cs_mask; } From patchwork Thu Jan 27 20:41:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12727364 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB6B5C433F5 for ; Thu, 27 Jan 2022 20:41:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344165AbiA0Ulz (ORCPT ); Thu, 27 Jan 2022 15:41:55 -0500 Received: from mail-bn7nam10on2059.outbound.protection.outlook.com ([40.107.92.59]:47457 "EHLO NAM10-BN7-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1344172AbiA0Ulu (ORCPT ); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jan 2022 20:41:46.7335 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: da71b557-d95b-4f68-abb1-08d9e1d56fc6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT063.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB3936 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Move parsing of the number of interleaved dies to a separate helper function. This will be expanded for future DF versions. Also, drop an unneeded assert to match the reference code. Signed-off-by: Yazen Ghannam --- Link: https://lore.kernel.org/r/20211028175728.121452-19-yazen.ghannam@amd.com v3->v4: * Remove leading whitespace in function pointer. v2->v3: * Was patch 19 in v2. v1->v2: * Moved from arch/x86 to EDAC. * Add new function to data_fabric_ops. drivers/edac/amd64_edac.c | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 87439374a076..2973b7b5e8a2 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1077,6 +1077,7 @@ struct addr_ctx { u8 map_num; u8 intlv_addr_bit; u8 intlv_num_chan; + u8 intlv_num_dies; u8 cs_id; int (*dehash_addr)(struct addr_ctx *ctx); }; @@ -1084,6 +1085,7 @@ struct addr_ctx { struct data_fabric_ops { u64 (*get_hi_addr_offset)(struct addr_ctx *ctx); int (*get_intlv_mode)(struct addr_ctx *ctx); + void (*get_intlv_num_dies)(struct addr_ctx *ctx); }; static u64 get_hi_addr_offset_df2(struct addr_ctx *ctx) @@ -1124,9 +1126,15 @@ static int get_intlv_mode_df2(struct addr_ctx *ctx) return 0; } +static void get_intlv_num_dies_df2(struct addr_ctx *ctx) +{ + ctx->intlv_num_dies = (ctx->reg_limit_addr >> 10) & 0x3; +} + struct data_fabric_ops df2_ops = { .get_hi_addr_offset = get_hi_addr_offset_df2, .get_intlv_mode = get_intlv_mode_df2, + .get_intlv_num_dies = get_intlv_num_dies_df2, }; struct data_fabric_ops *df_ops; @@ -1218,7 +1226,7 @@ static void get_intlv_num_chan(struct addr_ctx *ctx) static int denormalize_addr(struct addr_ctx *ctx) { u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask; - u8 intlv_num_dies, intlv_num_sockets; + u8 intlv_num_sockets; u8 num_intlv_bits, cs_mask = 0; /* Return early if no interleaving. */ @@ -1229,19 +1237,12 @@ static int denormalize_addr(struct addr_ctx *ctx) return -EINVAL; intlv_num_sockets = (ctx->reg_limit_addr >> 8) & 0x1; - intlv_num_dies = (ctx->reg_limit_addr >> 10) & 0x3; get_intlv_num_chan(ctx); + df_ops->get_intlv_num_dies(ctx); num_intlv_bits = ctx->intlv_num_chan; - - if (intlv_num_dies > 2) { - pr_err("%s: Invalid number of interleaved nodes/dies %d.\n", - __func__, intlv_num_dies); - return -EINVAL; - } - - num_intlv_bits += intlv_num_dies; + num_intlv_bits += ctx->intlv_num_dies; /* Add a bit if sockets are interleaved. */ num_intlv_bits += intlv_num_sockets; @@ -1279,13 +1280,13 @@ static int denormalize_addr(struct addr_ctx *ctx) sock_id_bit = die_id_bit; /* Read D18F1x208 (SystemFabricIdMask). */ - if (intlv_num_dies || intlv_num_sockets) + if (ctx->intlv_num_dies || intlv_num_sockets) if (df_indirect_read_broadcast(ctx->nid, 1, 0x208, &ctx->tmp)) return -EINVAL; /* If interleaved over more than 1 die. */ - if (intlv_num_dies) { - sock_id_bit = die_id_bit + intlv_num_dies; + if (ctx->intlv_num_dies) { + sock_id_bit = die_id_bit + ctx->intlv_num_dies; die_id_shift = (ctx->tmp >> 24) & 0xF; die_id_mask = (ctx->tmp >> 8) & 0xFF; From patchwork Thu Jan 27 20:41:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12727368 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02CBAC433FE for ; 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Thu, 27 Jan 2022 14:41:42 -0600 From: Yazen Ghannam To: CC: , , , , , , , Yazen Ghannam Subject: [PATCH v4 14/24] EDAC/amd64: Define function to get number of interleaved sockets Date: Thu, 27 Jan 2022 20:41:05 +0000 Message-ID: <20220127204115.384161-15-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220127204115.384161-1-yazen.ghannam@amd.com> References: <20220127204115.384161-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e577b19c-dd83-4e99-67f8-08d9e1d57010 X-MS-TrafficTypeDiagnostic: BYAPR12MB2790:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4941; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 3e43JqwW9NL87Ija0JSiHOJ6rHc7CaDayslL7ERmvxMSRE6MEjUse0zSPJ4XD65yER4SwprUJoIYzEJq9N3eeyaCQLlLfLjpHhOqZl4UeZsUjBbuY0xGJ6udaYTSDOSB+T/d8hH+FfAFye+HSCEisUWA+KclNOlVekh7PgjVJddJ7IEf13QJfkgpiyty3qfPyeVhht2ZzDqRK+i1GDpOHJUVH1Sbt/rZrv+JxbBwSHriAltnOrjnT//iN0oEtmu2YXaz1cc1w5mTp8icaMX/hfXsU1VSLWa+NmAYaiz/xZPbXmrdUeltIZ3olPcsU6V62hNPMGqDpuciURxeY3fiMvZXMR41+Jw2tYJ67dqPTMWE8jAOcIXr5d9wZHoY5ryNWOtdu6zoFkiXYPQrGHntBbwNBwh7EbexFkEJ/Y1ydygY5mlV4+ezUgGC4JnTL62lV4sFr0qwIbMnJYCm/BrmqYu8c3puMy+VeNo6sBYQjJBXpfoBJyP8hfUS6K6RBapI4bPxC3a222lml8XDIwMpQbVX1xE755WaSYiIzTyVTnzpevtedjcLct+SK9Q5TAzLBL7kNnPg7lOABHAii+WjZR+2FbjSRj3DbvfSTfbPDKrsMNoIzAvXvms4qqbEl5d0Tg+cwoaCtvK5ed5dHpzRhr7SW/iOhKfXrr4e2dn5h8TXdjs2MTCoT2ONL9mQ/l+uBt2PZ48b4LfaR1DO+aOAK5mH+ONyZ705f2ey0/e1IaP/AUxebfd3f1UMgYZHg/ib8qjX0t09Bb70aHAmaADxvcMSEd94TWL3pm8IG4X38bkdjMwJ0MBus9YHJpFmvC9rIST9Hf3fAtQNO701H9y7eQ6A8H26Q/cgn3ZQw9GfFmc7gvHxNnN2VRQTKAuMzsvg X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(46966006)(40470700004)(36840700001)(70586007)(26005)(2906002)(47076005)(2616005)(7696005)(36756003)(508600001)(356005)(8676002)(54906003)(40460700003)(5660300002)(82310400004)(4326008)(316002)(86362001)(36860700001)(6666004)(966005)(8936002)(16526019)(70206006)(81166007)(44832011)(6916009)(426003)(83380400001)(186003)(1076003)(336012)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jan 2022 20:41:47.2011 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e577b19c-dd83-4e99-67f8-08d9e1d57010 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT028.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB2790 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Move parsing of the number of interleaved sockets to a separate helper function. This will be expanded for future DF versions. Signed-off-by: Yazen Ghannam --- Link: https://lore.kernel.org/r/20211028175728.121452-20-yazen.ghannam@amd.com v3->v4: * Remove leading whitespace in function pointer. v2->v3: * Was patch 20 in v2. v1->v2: * Moved from arch/x86 to EDAC. * Add new function to data_fabric_ops. drivers/edac/amd64_edac.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 2973b7b5e8a2..898f53eaaff3 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1078,6 +1078,7 @@ struct addr_ctx { u8 intlv_addr_bit; u8 intlv_num_chan; u8 intlv_num_dies; + u8 intlv_num_sockets; u8 cs_id; int (*dehash_addr)(struct addr_ctx *ctx); }; @@ -1086,6 +1087,7 @@ struct data_fabric_ops { u64 (*get_hi_addr_offset)(struct addr_ctx *ctx); int (*get_intlv_mode)(struct addr_ctx *ctx); void (*get_intlv_num_dies)(struct addr_ctx *ctx); + void (*get_intlv_num_sockets)(struct addr_ctx *ctx); }; static u64 get_hi_addr_offset_df2(struct addr_ctx *ctx) @@ -1131,10 +1133,16 @@ static void get_intlv_num_dies_df2(struct addr_ctx *ctx) ctx->intlv_num_dies = (ctx->reg_limit_addr >> 10) & 0x3; } +static void get_intlv_num_sockets_df2(struct addr_ctx *ctx) +{ + ctx->intlv_num_sockets = (ctx->reg_limit_addr >> 8) & 0x1; +} + struct data_fabric_ops df2_ops = { .get_hi_addr_offset = get_hi_addr_offset_df2, .get_intlv_mode = get_intlv_mode_df2, .get_intlv_num_dies = get_intlv_num_dies_df2, + .get_intlv_num_sockets = get_intlv_num_sockets_df2, }; struct data_fabric_ops *df_ops; @@ -1226,7 +1234,6 @@ static void get_intlv_num_chan(struct addr_ctx *ctx) static int denormalize_addr(struct addr_ctx *ctx) { u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask; - u8 intlv_num_sockets; u8 num_intlv_bits, cs_mask = 0; /* Return early if no interleaving. */ @@ -1236,16 +1243,13 @@ static int denormalize_addr(struct addr_ctx *ctx) if (get_intlv_addr_bit(ctx)) return -EINVAL; - intlv_num_sockets = (ctx->reg_limit_addr >> 8) & 0x1; - get_intlv_num_chan(ctx); df_ops->get_intlv_num_dies(ctx); + df_ops->get_intlv_num_sockets(ctx); num_intlv_bits = ctx->intlv_num_chan; num_intlv_bits += ctx->intlv_num_dies; - - /* Add a bit if sockets are interleaved. */ - num_intlv_bits += intlv_num_sockets; + num_intlv_bits += ctx->intlv_num_sockets; /* Assert num_intlv_bits <= 4 */ if (num_intlv_bits > 4) { @@ -1280,7 +1284,7 @@ static int denormalize_addr(struct addr_ctx *ctx) sock_id_bit = die_id_bit; /* Read D18F1x208 (SystemFabricIdMask). */ - if (ctx->intlv_num_dies || intlv_num_sockets) + if (ctx->intlv_num_dies || ctx->intlv_num_sockets) if (df_indirect_read_broadcast(ctx->nid, 1, 0x208, &ctx->tmp)) return -EINVAL; @@ -1295,7 +1299,7 @@ static int denormalize_addr(struct addr_ctx *ctx) } /* If interleaved over more than 1 socket. */ - if (intlv_num_sockets) { + if (ctx->intlv_num_sockets) { socket_id_shift = (ctx->tmp >> 28) & 0xF; socket_id_mask = (ctx->tmp >> 16) & 0xFF; From patchwork Thu Jan 27 20:41:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12727369 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB8B5C433EF for ; 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Thu, 27 Jan 2022 14:41:43 -0600 From: Yazen Ghannam To: CC: , , , , , , , Yazen Ghannam Subject: [PATCH v4 15/24] EDAC/amd64: Remove unnecessary assert Date: Thu, 27 Jan 2022 20:41:06 +0000 Message-ID: <20220127204115.384161-16-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220127204115.384161-1-yazen.ghannam@amd.com> References: <20220127204115.384161-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 4016249b-1289-4850-05fc-08d9e1d57045 X-MS-TrafficTypeDiagnostic: MW2PR12MB2346:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3826; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: e8afZxvSocMRHloDSuZr2pjNxMZH6kIXRSOIwIQ1O/mLNZ1Z1QdtHOUVADDca5wYJzBSKGKI5HMEXUEon5XH5EMg0UFztalfVUuTkuRBfDGtDsUsHFxIL4xwsl+woCk5BEA+6UvBU/IovNQ8EvXvmIU0QesUvZXAIi7hgn5tXR/m6Dk+qOtyazHrEaXyQpZDr9Ek2j/ydurvr2HHRlYjE4It9XLjXx2BQ1BD/7kive6R1KMjuMMWedNE6XG3TsZsc0zqcSCOVxQZsohZSyFYdMu+VZ8OXy30Q+bp2BXB8mUBp0irDaqKjVkflcjhRET9LrGD1ynmRjN3GkYUCTD3+ZjJSv2VQUNw7A0mEkUjvvcVjVy01UN0fqr4EYKk5zW68/gY/GWGa9y+mY92FlmBHO6FomYIYxPqjvnbD8/wnc94SMCwfAXuuTZm3HDt0JqDdrhfgFiML4OUWsQxko/Gk6+R6TAYt3rGKnt0TE06HYlbXTEBv1r+z6gZEQ55Bex8ptjJHbEyxZDTmMgW+m+pWTc3yaV1pbs8GSM1i+VrE3BCU9vf/+9weUjVVtW2vJO6GPFLB8hbKmf9zKkUyi1dHGV+6bctniCaZiKcDfy5x1FHfl3LVzWi/f8Y7vDzJB9YYLMKvrXrxvseuzxGkG4yaATzTRSK6RX3ffy47z3u/nnLlm/O/UApfEEzbNhUjtFe8bEAZSAG4ivmaKOzpJyu6rz3owIHYNZOleu9ul0Z3ibH8EmyVUJb7a41xgFvm/mL1gS4vmgeqryP5xRHxq5S7yQLL7oUnmngGS7/h4pBkGQ= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230001)(4636009)(36840700001)(46966006)(40470700004)(83380400001)(86362001)(336012)(2906002)(54906003)(40460700003)(6666004)(6916009)(426003)(47076005)(7696005)(5660300002)(36756003)(4326008)(82310400004)(508600001)(8936002)(966005)(8676002)(36860700001)(186003)(16526019)(44832011)(356005)(81166007)(70586007)(26005)(4744005)(1076003)(2616005)(70206006)(316002)(36900700001)(20210929001);DIR:OUT;SFP:1101; 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Signed-off-by: Yazen Ghannam --- Link: https://lore.kernel.org/r/20211028175728.121452-21-yazen.ghannam@amd.com v3->v4: * No change. v2->v3: * Was patch 21 in v2. v1->v2: * Moved from arch/x86 to EDAC. drivers/edac/amd64_edac.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 898f53eaaff3..c3342f0bec45 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1251,13 +1251,6 @@ static int denormalize_addr(struct addr_ctx *ctx) num_intlv_bits += ctx->intlv_num_dies; num_intlv_bits += ctx->intlv_num_sockets; - /* Assert num_intlv_bits <= 4 */ - if (num_intlv_bits > 4) { - pr_err("%s: Invalid interleave bits %d.\n", - __func__, num_intlv_bits); - return -EINVAL; - } - if (num_intlv_bits > 0) { u64 temp_addr_x, temp_addr_i, temp_addr_y; u8 die_id_bit, sock_id_bit, cs_fabric_id; From patchwork Thu Jan 27 20:41:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12727365 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E62E0C4167E for ; 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Thu, 27 Jan 2022 14:41:43 -0600 From: Yazen Ghannam To: CC: , , , , , , , Yazen Ghannam Subject: [PATCH v4 16/24] EDAC/amd64: Define function to make space for CS ID Date: Thu, 27 Jan 2022 20:41:07 +0000 Message-ID: <20220127204115.384161-17-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220127204115.384161-1-yazen.ghannam@amd.com> References: <20220127204115.384161-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 7a0c4294-6e42-44a3-0497-08d9e1d57157 X-MS-TrafficTypeDiagnostic: DM5PR12MB2519:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8273; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 5cYPoqNRTDuWKk1dNi1BQKWAS3cTWuylvGrkU+1xKEIJ0mlshi6KAv420pjsJTdv7K0DXpPnKzaoQXa/6MspZXJJGJNlR+nW5id6L/48YWA5//ybCfSgxbxgU0jh/40ZIqS8D8v7rqPd+dwryNm0Lr4f/wJm3P75XwUA7iVkUH5rD1lB54UOAuJiuEjBfSkZSGDhnearYDLaSTGWtsA9XAk1k70uO1CkG/XtGi48b85DZikT4nfk9sIKdwZqMqad7Itl13aoggDf4Z+O7/d69gn8JHrwdjT98HiAZVvxAkMF/7kZUYY+XvFO2qdxiez8SxbtZl4sluqSzAagUZAL1E8zKCcvLK4j4epnhQWubfXgC/QclG+5YJ7uCQGZ1BBPWkUyrVxQHWFMPfS5O0IKkMDOLxxASA/gSdFE38PowBnKjca9tmhh0sWV1QNVaqDbhec60YoFNos2iNcl9ZJtSc6wZGjzdHjLxbA2By3bXMnhnYYgSuhwk7BxwOlPfsSN9gv+I6JzDK89s7Qjaf68iZCWjP06i9PP9zKGVAUv46igV/nYRYCb1D6qv6VKUwKqQJeiYx0S65TMBK8rLQQii9RwqNtWPdBfmUEvg8u00xV3qA7q4REDQT30sGfaSskxvL440GNs+cC9fFQW3GbADL6rqmIntcbyb7FtGKpKc4KcaEabC0rCOK3tVq+iAGqb32XEZOAgKSrYhxMpwsrlYOk5i1HP8Z/WvFEELBzINFpOiCCu+vp1V3rcNKFUjfM/axaIhzPV0z/7pCP/h6DvWk5NfyZEldJEHnpABzq/xxE= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230001)(4636009)(40470700004)(36840700001)(46966006)(8676002)(8936002)(70206006)(4326008)(70586007)(36860700001)(86362001)(316002)(356005)(5660300002)(36756003)(81166007)(2906002)(44832011)(40460700003)(54906003)(426003)(336012)(6916009)(82310400004)(47076005)(26005)(966005)(7696005)(6666004)(2616005)(508600001)(186003)(1076003)(16526019)(83380400001)(36900700001)(20210929001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jan 2022 20:41:49.3416 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7a0c4294-6e42-44a3-0497-08d9e1d57157 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT028.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB2519 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Move code that makes a gap for the CS ID into a separate helper function. The exact bits to use vary based on interleaving mode. New interleaving modes in future DF versions will be added as new cases. Also, introduce a helper function that does the bit manipulation to make the gap. The current version of this function is "simple", and future interleaving modes may reuse this or use a more advanced function. Signed-off-by: Yazen Ghannam --- Link: https://lore.kernel.org/r/20211028175728.121452-22-yazen.ghannam@amd.com v3->v4: * Added glossary entry. v2->v3: * Was patch 22 in v2. v1->v2: * Moved from arch/x86 to EDAC. * Added new function pointer to ctx struct. drivers/edac/amd64_edac.c | 38 ++++++++++++++++++++++++++++++-------- 1 file changed, 30 insertions(+), 8 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index c3342f0bec45..f5b1902e04ac 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -991,6 +991,7 @@ static int sys_addr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr) /* * Glossary of acronyms used in address translation for Zen-based systems * + * CS = Coherent Slave * DF = Data Fabric */ @@ -1081,6 +1082,7 @@ struct addr_ctx { u8 intlv_num_sockets; u8 cs_id; int (*dehash_addr)(struct addr_ctx *ctx); + void (*make_space_for_cs_id)(struct addr_ctx *ctx); }; struct data_fabric_ops { @@ -1090,6 +1092,29 @@ struct data_fabric_ops { void (*get_intlv_num_sockets)(struct addr_ctx *ctx); }; +static void expand_bits(u8 start_bit, u8 num_bits, u64 *value) +{ + u64 temp1, temp2; + + if (start_bit == 0) { + *value <<= num_bits; + return; + } + + temp1 = *value & GENMASK_ULL(start_bit - 1, 0); + temp2 = (*value & GENMASK_ULL(63, start_bit)) << num_bits; + *value = temp1 | temp2; +} + +static void make_space_for_cs_id_simple(struct addr_ctx *ctx) +{ + u8 num_intlv_bits = ctx->intlv_num_chan; + + num_intlv_bits += ctx->intlv_num_dies; + num_intlv_bits += ctx->intlv_num_sockets; + expand_bits(ctx->intlv_addr_bit, num_intlv_bits, &ctx->ret_addr); +} + static u64 get_hi_addr_offset_df2(struct addr_ctx *ctx) { return (ctx->reg_dram_offset & GENMASK_ULL(31, 20)) << 8; @@ -1120,6 +1145,8 @@ static int get_intlv_mode_df2(struct addr_ctx *ctx) ctx->dehash_addr = dehash_addr_df2; } + ctx->make_space_for_cs_id = make_space_for_cs_id_simple; + if (ctx->intlv_mode != NONE && ctx->intlv_mode != NOHASH_2CH && ctx->intlv_mode != DF2_HASH_2CH) @@ -1247,13 +1274,11 @@ static int denormalize_addr(struct addr_ctx *ctx) df_ops->get_intlv_num_dies(ctx); df_ops->get_intlv_num_sockets(ctx); - num_intlv_bits = ctx->intlv_num_chan; - num_intlv_bits += ctx->intlv_num_dies; - num_intlv_bits += ctx->intlv_num_sockets; + ctx->make_space_for_cs_id(ctx); if (num_intlv_bits > 0) { - u64 temp_addr_x, temp_addr_i, temp_addr_y; u8 die_id_bit, sock_id_bit, cs_fabric_id; + u64 temp_addr_i; /* * Read FabricBlockInstanceInformation3_CS[BlockFabricID]. @@ -1308,11 +1333,8 @@ static int denormalize_addr(struct addr_ctx *ctx) * bits there are. "intlv_addr_bit" tells us how many "Y" bits * there are (where "I" starts). */ - temp_addr_y = ctx->ret_addr & GENMASK_ULL(ctx->intlv_addr_bit - 1, 0); temp_addr_i = (ctx->cs_id << ctx->intlv_addr_bit); - temp_addr_x = (ctx->ret_addr & GENMASK_ULL(63, ctx->intlv_addr_bit)) - << num_intlv_bits; - ctx->ret_addr = temp_addr_x | temp_addr_i | temp_addr_y; + ctx->ret_addr |= temp_addr_i; } return 0; From patchwork Thu Jan 27 20:41:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12727373 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AFE25C4321E for ; Thu, 27 Jan 2022 20:42:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344255AbiA0UmC (ORCPT ); Thu, 27 Jan 2022 15:42:02 -0500 Received: from mail-bn7nam10on2048.outbound.protection.outlook.com ([40.107.92.48]:20192 "EHLO NAM10-BN7-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1344178AbiA0Ulv (ORCPT ); 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Thu, 27 Jan 2022 20:41:49 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT063.mail.protection.outlook.com (10.13.175.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4930.15 via Frontend Transport; Thu, 27 Jan 2022 20:41:49 +0000 Received: from yaz-ethanolx.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.18; Thu, 27 Jan 2022 14:41:44 -0600 From: Yazen Ghannam To: CC: , , , , , , , Yazen Ghannam Subject: [PATCH v4 17/24] EDAC/amd64: Define function to calculate CS ID Date: Thu, 27 Jan 2022 20:41:08 +0000 Message-ID: <20220127204115.384161-18-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220127204115.384161-1-yazen.ghannam@amd.com> References: <20220127204115.384161-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ed089ab5-c444-45d5-a419-08d9e1d5716c X-MS-TrafficTypeDiagnostic: DM6PR12MB4716:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7691; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jan 2022 20:41:49.4989 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ed089ab5-c444-45d5-a419-08d9e1d5716c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT063.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4716 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Move code used to calculate the CS ID into a separate helper function. Drop redundant code comment about reading DF register. The "num_intlv_bits" variable is left uninitialized as it will be removed in a later patch. Signed-off-by: Yazen Ghannam --- Link: https://lore.kernel.org/r/20211028175728.121452-23-yazen.ghannam@amd.com v3->v4: * Include pr_debug() on failure. v2->v3: * Was patch 23 in v2. v1->v2: * Moved from arch/x86 to EDAC. drivers/edac/amd64_edac.c | 100 ++++++++++++++++++++------------------ 1 file changed, 52 insertions(+), 48 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index f5b1902e04ac..b2bcd8ea1a06 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1258,10 +1258,55 @@ static void get_intlv_num_chan(struct addr_ctx *ctx) } } -static int denormalize_addr(struct addr_ctx *ctx) +static int calculate_cs_id(struct addr_ctx *ctx) { u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask; - u8 num_intlv_bits, cs_mask = 0; + u8 die_id_bit, sock_id_bit, cs_fabric_id, cs_mask = 0; + + /* Read D18F0x50 (FabricBlockInstanceInformation3). */ + if (df_indirect_read_instance(ctx->nid, 0, 0x50, ctx->inst_id, &ctx->tmp)) + return -EINVAL; + + cs_fabric_id = (ctx->tmp >> 8) & 0xFF; + die_id_bit = 0; + + /* If interleaved over more than 1 channel: */ + if (ctx->intlv_num_chan) { + die_id_bit = ctx->intlv_num_chan; + cs_mask = (1 << die_id_bit) - 1; + ctx->cs_id = cs_fabric_id & cs_mask; + } + + sock_id_bit = die_id_bit; + + /* Read D18F1x208 (SystemFabricIdMask). */ + if (ctx->intlv_num_dies || ctx->intlv_num_sockets) + if (df_indirect_read_broadcast(ctx->nid, 1, 0x208, &ctx->tmp)) + return -EINVAL; + + /* If interleaved over more than 1 die: */ + if (ctx->intlv_num_dies) { + sock_id_bit = die_id_bit + ctx->intlv_num_dies; + die_id_shift = (ctx->tmp >> 24) & 0xF; + die_id_mask = (ctx->tmp >> 8) & 0xFF; + + ctx->cs_id |= ((cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit; + } + + /* If interleaved over more than 1 socket: */ + if (ctx->intlv_num_sockets) { + socket_id_shift = (ctx->tmp >> 28) & 0xF; + socket_id_mask = (ctx->tmp >> 16) & 0xFF; + + ctx->cs_id |= ((cs_fabric_id & socket_id_mask) >> socket_id_shift) << sock_id_bit; + } + + return 0; +} + +static int denormalize_addr(struct addr_ctx *ctx) +{ + u8 num_intlv_bits; /* Return early if no interleaving. */ if (ctx->intlv_mode == NONE) @@ -1276,55 +1321,14 @@ static int denormalize_addr(struct addr_ctx *ctx) ctx->make_space_for_cs_id(ctx); + if (calculate_cs_id(ctx)) { + pr_debug("Failed to calculate CS ID"); + return -EINVAL; + } + if (num_intlv_bits > 0) { - u8 die_id_bit, sock_id_bit, cs_fabric_id; u64 temp_addr_i; - /* - * Read FabricBlockInstanceInformation3_CS[BlockFabricID]. - * This is the fabric id for this coherent slave. Use - * umc/channel# as instance id of the coherent slave - * for FICAA. - */ - if (df_indirect_read_instance(ctx->nid, 0, 0x50, ctx->inst_id, &ctx->tmp)) - return -EINVAL; - - cs_fabric_id = (ctx->tmp >> 8) & 0xFF; - die_id_bit = 0; - - /* If interleaved over more than 1 channel: */ - if (ctx->intlv_num_chan) { - die_id_bit = ctx->intlv_num_chan; - cs_mask = (1 << die_id_bit) - 1; - ctx->cs_id = cs_fabric_id & cs_mask; - } - - sock_id_bit = die_id_bit; - - /* Read D18F1x208 (SystemFabricIdMask). */ - if (ctx->intlv_num_dies || ctx->intlv_num_sockets) - if (df_indirect_read_broadcast(ctx->nid, 1, 0x208, &ctx->tmp)) - return -EINVAL; - - /* If interleaved over more than 1 die. */ - if (ctx->intlv_num_dies) { - sock_id_bit = die_id_bit + ctx->intlv_num_dies; - die_id_shift = (ctx->tmp >> 24) & 0xF; - die_id_mask = (ctx->tmp >> 8) & 0xFF; - - ctx->cs_id |= ((cs_fabric_id & die_id_mask) - >> die_id_shift) << die_id_bit; - } - - /* If interleaved over more than 1 socket. */ - if (ctx->intlv_num_sockets) { - socket_id_shift = (ctx->tmp >> 28) & 0xF; - socket_id_mask = (ctx->tmp >> 16) & 0xFF; - - ctx->cs_id |= ((cs_fabric_id & socket_id_mask) - >> socket_id_shift) << sock_id_bit; - } - /* * The pre-interleaved address consists of XXXXXXIIIYYYYY * where III is the ID for this CS, and XXXXXXYYYYY are the From patchwork Thu Jan 27 20:41:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12727371 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1614C433F5 for ; Thu, 27 Jan 2022 20:42:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344218AbiA0Ul6 (ORCPT ); Thu, 27 Jan 2022 15:41:58 -0500 Received: from mail-dm3nam07on2085.outbound.protection.outlook.com ([40.107.95.85]:24033 "EHLO NAM02-DM3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1344152AbiA0Ulx (ORCPT ); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jan 2022 20:41:49.9978 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c2e5786e-c047-48a5-25ad-08d9e1d571bb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT028.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB3191 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Move the code that inserts the CS ID into the address into a separate helper function. Save the function pointer in the context struct. It will be set based on interleaving mode rather than Data Fabric version. This will be expanded for new interleaving modes added in future Data Fabric versions. Signed-off-by: Yazen Ghannam --- Link: https://lore.kernel.org/r/20211028175728.121452-24-yazen.ghannam@amd.com v3->v4: * No change. v2->v3: * Was patch 24 in v2. v1->v2: * Moved from arch/x86 to EDAC. * Added function pointer to ctx struct. drivers/edac/amd64_edac.c | 24 ++++++++---------------- 1 file changed, 8 insertions(+), 16 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index b2bcd8ea1a06..e3db4e98fe58 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1083,6 +1083,7 @@ struct addr_ctx { u8 cs_id; int (*dehash_addr)(struct addr_ctx *ctx); void (*make_space_for_cs_id)(struct addr_ctx *ctx); + void (*insert_cs_id)(struct addr_ctx *ctx); }; struct data_fabric_ops { @@ -1115,6 +1116,11 @@ static void make_space_for_cs_id_simple(struct addr_ctx *ctx) expand_bits(ctx->intlv_addr_bit, num_intlv_bits, &ctx->ret_addr); } +static void insert_cs_id_simple(struct addr_ctx *ctx) +{ + ctx->ret_addr |= (ctx->cs_id << ctx->intlv_addr_bit); +} + static u64 get_hi_addr_offset_df2(struct addr_ctx *ctx) { return (ctx->reg_dram_offset & GENMASK_ULL(31, 20)) << 8; @@ -1146,6 +1152,7 @@ static int get_intlv_mode_df2(struct addr_ctx *ctx) } ctx->make_space_for_cs_id = make_space_for_cs_id_simple; + ctx->insert_cs_id = insert_cs_id_simple; if (ctx->intlv_mode != NONE && ctx->intlv_mode != NOHASH_2CH && @@ -1306,8 +1313,6 @@ static int calculate_cs_id(struct addr_ctx *ctx) static int denormalize_addr(struct addr_ctx *ctx) { - u8 num_intlv_bits; - /* Return early if no interleaving. */ if (ctx->intlv_mode == NONE) return 0; @@ -1326,20 +1331,7 @@ static int denormalize_addr(struct addr_ctx *ctx) return -EINVAL; } - if (num_intlv_bits > 0) { - u64 temp_addr_i; - - /* - * The pre-interleaved address consists of XXXXXXIIIYYYYY - * where III is the ID for this CS, and XXXXXXYYYYY are the - * address bits from the post-interleaved address. - * "num_intlv_bits" has been calculated to tell us how many "I" - * bits there are. "intlv_addr_bit" tells us how many "Y" bits - * there are (where "I" starts). - */ - temp_addr_i = (ctx->cs_id << ctx->intlv_addr_bit); - ctx->ret_addr |= temp_addr_i; - } + ctx->insert_cs_id(ctx); return 0; } From patchwork Thu Jan 27 20:41:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12727370 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 564D8C43219 for ; Thu, 27 Jan 2022 20:42:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344249AbiA0UmB (ORCPT ); Thu, 27 Jan 2022 15:42:01 -0500 Received: from mail-dm6nam12on2069.outbound.protection.outlook.com ([40.107.243.69]:31360 "EHLO NAM12-DM6-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1344166AbiA0Uly (ORCPT ); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jan 2022 20:41:50.2333 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bafc23e4-6016-4c6b-b093-08d9e1d571dc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT063.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4256 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Move code that gets the CS Fabric ID into a separate helper function. This will be expanded for future DF versions. The bitfield used for this value may be larger than the 8 bits currently used. So make it a u16 type which is large enough to hold all known sizes of this bitfield across DF versions. Also, call this function early as future DF versions may need the value early. Signed-off-by: Yazen Ghannam --- Link: https://lore.kernel.org/r/20211028175728.121452-25-yazen.ghannam@amd.com v3->v4: * Remove leading whitespace in function pointer. * Include pr_debug() in failure. v2->v3: * Was patch 25 in v2. v1->v2: * Moved from arch/x86 to EDAC. * Added function to data_fabric_ops. drivers/edac/amd64_edac.c | 35 ++++++++++++++++++++++++----------- 1 file changed, 24 insertions(+), 11 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index e3db4e98fe58..7891c2e93d53 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1073,6 +1073,7 @@ struct addr_ctx { u32 reg_dram_offset; u32 reg_base_addr; u32 reg_limit_addr; + u16 cs_fabric_id; u16 nid; u8 inst_id; u8 map_num; @@ -1089,6 +1090,7 @@ struct addr_ctx { struct data_fabric_ops { u64 (*get_hi_addr_offset)(struct addr_ctx *ctx); int (*get_intlv_mode)(struct addr_ctx *ctx); + int (*get_cs_fabric_id)(struct addr_ctx *ctx); void (*get_intlv_num_dies)(struct addr_ctx *ctx); void (*get_intlv_num_sockets)(struct addr_ctx *ctx); }; @@ -1172,11 +1174,23 @@ static void get_intlv_num_sockets_df2(struct addr_ctx *ctx) ctx->intlv_num_sockets = (ctx->reg_limit_addr >> 8) & 0x1; } +static int get_cs_fabric_id_df2(struct addr_ctx *ctx) +{ + /* Read D18F0x50 (FabricBlockInstanceInformation3). */ + if (df_indirect_read_instance(ctx->nid, 0, 0x50, ctx->inst_id, &ctx->tmp)) + return -EINVAL; + + ctx->cs_fabric_id = (ctx->tmp >> 8) & 0xFF; + + return 0; +} + struct data_fabric_ops df2_ops = { .get_hi_addr_offset = get_hi_addr_offset_df2, .get_intlv_mode = get_intlv_mode_df2, .get_intlv_num_dies = get_intlv_num_dies_df2, .get_intlv_num_sockets = get_intlv_num_sockets_df2, + .get_cs_fabric_id = get_cs_fabric_id_df2, }; struct data_fabric_ops *df_ops; @@ -1268,20 +1282,13 @@ static void get_intlv_num_chan(struct addr_ctx *ctx) static int calculate_cs_id(struct addr_ctx *ctx) { u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask; - u8 die_id_bit, sock_id_bit, cs_fabric_id, cs_mask = 0; - - /* Read D18F0x50 (FabricBlockInstanceInformation3). */ - if (df_indirect_read_instance(ctx->nid, 0, 0x50, ctx->inst_id, &ctx->tmp)) - return -EINVAL; - - cs_fabric_id = (ctx->tmp >> 8) & 0xFF; - die_id_bit = 0; + u8 die_id_bit = 0, sock_id_bit, cs_mask = 0; /* If interleaved over more than 1 channel: */ if (ctx->intlv_num_chan) { die_id_bit = ctx->intlv_num_chan; cs_mask = (1 << die_id_bit) - 1; - ctx->cs_id = cs_fabric_id & cs_mask; + ctx->cs_id = ctx->cs_fabric_id & cs_mask; } sock_id_bit = die_id_bit; @@ -1297,7 +1304,7 @@ static int calculate_cs_id(struct addr_ctx *ctx) die_id_shift = (ctx->tmp >> 24) & 0xF; die_id_mask = (ctx->tmp >> 8) & 0xFF; - ctx->cs_id |= ((cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit; + ctx->cs_id |= ((ctx->cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit; } /* If interleaved over more than 1 socket: */ @@ -1305,7 +1312,8 @@ static int calculate_cs_id(struct addr_ctx *ctx) socket_id_shift = (ctx->tmp >> 28) & 0xF; socket_id_mask = (ctx->tmp >> 16) & 0xFF; - ctx->cs_id |= ((cs_fabric_id & socket_id_mask) >> socket_id_shift) << sock_id_bit; + ctx->cs_id |= ((ctx->cs_fabric_id & socket_id_mask) + >> socket_id_shift) << sock_id_bit; } return 0; @@ -1387,6 +1395,11 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr ctx.nid = nid; ctx.inst_id = umc; + if (df_ops->get_cs_fabric_id(&ctx)) { + pr_debug("Failed to get CS Fabric ID"); + return -EINVAL; + } + if (remove_dram_offset(&ctx)) { pr_debug("Failed to remove DRAM offset"); return -EINVAL; From patchwork Thu Jan 27 20:41:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12727372 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EAD71C4332F for ; Thu, 27 Jan 2022 20:42:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344160AbiA0UmA (ORCPT ); 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Thu, 27 Jan 2022 14:41:45 -0600 From: Yazen Ghannam To: CC: , , , , , , , Yazen Ghannam Subject: [PATCH v4 20/24] EDAC/amd64: Define function to find shift and mask values Date: Thu, 27 Jan 2022 20:41:11 +0000 Message-ID: <20220127204115.384161-21-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220127204115.384161-1-yazen.ghannam@amd.com> References: <20220127204115.384161-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5b0642f1-89c6-452d-463c-08d9e1d57256 X-MS-TrafficTypeDiagnostic: MW3PR12MB4394:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6790; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: MFx4pLzjPWxRMAYts3H0e9/TUpNJnPyUAdoyHLSezZu3dbDQr1sO9mxqHlB3XdpdtIy8yHLCu4N5zejj/2I5OH84Kn1caQv/T9e+aQc68yndBUYS7RmlligD0bC2xyd2b1WHUgdimx1aoB7bY7B2vWTb5OoxOzhkzWigz16m9ReNl0RkL9oheFr7maESs8Aim6IMjWsfNlQwqvx8wBoAzDLk1TgVjxxJ0+t+gQOx5aLzjwF3FluQnZW4aLn86hKngLBmiMWEHiJvB05GG7GEDQMr5XB8xI8xFYFPRl6UdwWGF+8j3+4W7KyTPeKtmKBWQ/kMjXPRHquqRHoO6lOyETDn1hT+dFkPpc+dRCRai/VMhLlVAbTnO6OA9fRhHRdBtQ5+iANe0QJMB8u4+IlDaRMjjk+9ZSibgpKEj7b2vF7+I2kspud5eXUvIWTq4XvUPQFrR0kt19ItRhJktkg8VbBLXHCtbmCevog0TltT14i9Fvpw4PVJPHFUMpLTKg975HpQDUsgNXZ2M+0ouPMY/7GxegSz6l96k0FF9kAFIOCpeYAKjpnYCPTxlEwmshBwWDafkJnv7crS66zNt0VK8YdaV8TEQyHR7hqqlmMucnnyg4ca1p0T4b/WXuaRQbiHyMjOMapQ+cZHGNyR2d5e62/tB6qw+NXN3R6MWx2ghQs3TA8qQBdjLT7yPYQRd10ZXj8GqO7eX1BHGIEsa8HaD0xyAROcUcm0LXpve3OZsavwaC12/0CRXyWWa9fj68FxCbPLSE6Gx5LDNs1C2Z7U5dlTb9Xb8WzFxOTJwSInTqpv5LXsvHR1KuF6b6qztcZO X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230001)(4636009)(36840700001)(40470700004)(46966006)(36860700001)(81166007)(82310400004)(356005)(47076005)(6666004)(7696005)(26005)(44832011)(966005)(36756003)(5660300002)(2616005)(54906003)(2906002)(6916009)(186003)(508600001)(40460700003)(1076003)(16526019)(4326008)(8936002)(8676002)(70586007)(70206006)(83380400001)(316002)(86362001)(336012)(426003)(37363002)(36900700001)(20210929001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jan 2022 20:41:51.0301 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5b0642f1-89c6-452d-463c-08d9e1d57256 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT063.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4394 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Move code to find the shift and mask values used in die and socket interleaving into separate helper functions. These will be expanded for future DF versions. Make the die_id_mask and socket_id_mask values u16 type to accommodate larger bitfields in future DF versions. Also, move reading of the System Fabric ID Mask register into get_masks(). This will be expanded for future DF versions. Call get_masks() early since future DF versions may need these values early. Signed-off-by: Yazen Ghannam --- Link: https://lore.kernel.org/r/20211028175728.121452-26-yazen.ghannam@amd.com v3->v4: * Remove leading whitespace in function pointers. * Include pr_debug() in failure. v2->v3: * Was patch 26 in v2. * Remove early code related to "df_ops". v1->v2: * Moved from arch/x86 to EDAC. * Added functions to data_fabric_ops. drivers/edac/amd64_edac.c | 59 ++++++++++++++++++++++++++++++--------- 1 file changed, 46 insertions(+), 13 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 7891c2e93d53..ac7919010063 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1073,7 +1073,10 @@ struct addr_ctx { u32 reg_dram_offset; u32 reg_base_addr; u32 reg_limit_addr; + u32 reg_fab_id_mask0; u16 cs_fabric_id; + u16 die_id_mask; + u16 socket_id_mask; u16 nid; u8 inst_id; u8 map_num; @@ -1089,8 +1092,11 @@ struct addr_ctx { struct data_fabric_ops { u64 (*get_hi_addr_offset)(struct addr_ctx *ctx); + u8 (*get_die_id_shift)(struct addr_ctx *ctx); + u8 (*get_socket_id_shift)(struct addr_ctx *ctx); int (*get_intlv_mode)(struct addr_ctx *ctx); int (*get_cs_fabric_id)(struct addr_ctx *ctx); + int (*get_masks)(struct addr_ctx *ctx); void (*get_intlv_num_dies)(struct addr_ctx *ctx); void (*get_intlv_num_sockets)(struct addr_ctx *ctx); }; @@ -1185,12 +1191,37 @@ static int get_cs_fabric_id_df2(struct addr_ctx *ctx) return 0; } +static int get_masks_df2(struct addr_ctx *ctx) +{ + /* Read D18F1x208 (SystemFabricIdMask). */ + if (df_indirect_read_broadcast(ctx->nid, 1, 0x208, &ctx->reg_fab_id_mask0)) + return -EINVAL; + + ctx->die_id_mask = (ctx->reg_fab_id_mask0 >> 8) & 0xFF; + ctx->socket_id_mask = (ctx->reg_fab_id_mask0 >> 16) & 0xFF; + + return 0; +} + +static u8 get_die_id_shift_df2(struct addr_ctx *ctx) +{ + return (ctx->reg_fab_id_mask0 >> 24) & 0xF; +} + +static u8 get_socket_id_shift_df2(struct addr_ctx *ctx) +{ + return (ctx->reg_fab_id_mask0 >> 28) & 0xF; +} + struct data_fabric_ops df2_ops = { .get_hi_addr_offset = get_hi_addr_offset_df2, .get_intlv_mode = get_intlv_mode_df2, .get_intlv_num_dies = get_intlv_num_dies_df2, .get_intlv_num_sockets = get_intlv_num_sockets_df2, .get_cs_fabric_id = get_cs_fabric_id_df2, + .get_masks = get_masks_df2, + .get_die_id_shift = get_die_id_shift_df2, + .get_socket_id_shift = get_socket_id_shift_df2, }; struct data_fabric_ops *df_ops; @@ -1281,7 +1312,6 @@ static void get_intlv_num_chan(struct addr_ctx *ctx) static int calculate_cs_id(struct addr_ctx *ctx) { - u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask; u8 die_id_bit = 0, sock_id_bit, cs_mask = 0; /* If interleaved over more than 1 channel: */ @@ -1291,28 +1321,26 @@ static int calculate_cs_id(struct addr_ctx *ctx) ctx->cs_id = ctx->cs_fabric_id & cs_mask; } - sock_id_bit = die_id_bit; + /* Return early if no die interleaving and no socket interleaving. */ + if (!(ctx->intlv_num_dies || ctx->intlv_num_sockets)) + return 0; - /* Read D18F1x208 (SystemFabricIdMask). */ - if (ctx->intlv_num_dies || ctx->intlv_num_sockets) - if (df_indirect_read_broadcast(ctx->nid, 1, 0x208, &ctx->tmp)) - return -EINVAL; + sock_id_bit = die_id_bit; /* If interleaved over more than 1 die: */ if (ctx->intlv_num_dies) { - sock_id_bit = die_id_bit + ctx->intlv_num_dies; - die_id_shift = (ctx->tmp >> 24) & 0xF; - die_id_mask = (ctx->tmp >> 8) & 0xFF; + u8 die_id_shift = df_ops->get_die_id_shift(ctx); - ctx->cs_id |= ((ctx->cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit; + sock_id_bit = die_id_bit + ctx->intlv_num_dies; + ctx->cs_id |= ((ctx->cs_fabric_id & ctx->die_id_mask) + >> die_id_shift) << die_id_bit; } /* If interleaved over more than 1 socket: */ if (ctx->intlv_num_sockets) { - socket_id_shift = (ctx->tmp >> 28) & 0xF; - socket_id_mask = (ctx->tmp >> 16) & 0xFF; + u8 socket_id_shift = df_ops->get_socket_id_shift(ctx); - ctx->cs_id |= ((ctx->cs_fabric_id & socket_id_mask) + ctx->cs_id |= ((ctx->cs_fabric_id & ctx->socket_id_mask) >> socket_id_shift) << sock_id_bit; } @@ -1395,6 +1423,11 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr ctx.nid = nid; ctx.inst_id = umc; + if (df_ops->get_masks(&ctx)) { + pr_debug("Failed to get masks"); + return -EINVAL; + } + if (df_ops->get_cs_fabric_id(&ctx)) { pr_debug("Failed to get CS Fabric ID"); return -EINVAL; From patchwork Thu Jan 27 20:41:12 2022 Content-Type: text/plain; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT063.mail.protection.outlook.com (10.13.175.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4930.15 via Frontend Transport; Thu, 27 Jan 2022 20:41:51 +0000 Received: from yaz-ethanolx.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.18; Thu, 27 Jan 2022 14:41:45 -0600 From: Yazen Ghannam To: CC: , , , , , , , Yazen Ghannam Subject: [PATCH v4 21/24] EDAC/amd64: Update CS ID calculation to match reference code Date: Thu, 27 Jan 2022 20:41:12 +0000 Message-ID: <20220127204115.384161-22-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220127204115.384161-1-yazen.ghannam@amd.com> References: <20220127204115.384161-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 39659b0a-4336-44cd-2dbe-08d9e1d572a0 X-MS-TrafficTypeDiagnostic: BYAPR12MB5704:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6790; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jan 2022 20:41:51.5144 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 39659b0a-4336-44cd-2dbe-08d9e1d572a0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT063.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB5704 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Redo the current CS ID calculations to match the reference code. Helper functions are introduced that will be expanded for future DF versions. Use u16 type for dst_fabric_id and component_id_mask values to accommodate larger bitfields in future DF versions. Signed-off-by: Yazen Ghannam --- Link: https://lore.kernel.org/r/20211028175728.121452-27-yazen.ghannam@amd.com v3->v4: * Remove leading whitespace in function pointers. v2->v3: * Was patch 27 in v2. v1->v2: * Moved from arch/x86 to EDAC. * Added functions to data_fabric_ops. drivers/edac/amd64_edac.c | 52 ++++++++++++++++++++++++++------------- 1 file changed, 35 insertions(+), 17 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index ac7919010063..e293aefd486e 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1092,6 +1092,8 @@ struct addr_ctx { struct data_fabric_ops { u64 (*get_hi_addr_offset)(struct addr_ctx *ctx); + u16 (*get_dst_fabric_id)(struct addr_ctx *ctx); + u16 (*get_component_id_mask)(struct addr_ctx *ctx); u8 (*get_die_id_shift)(struct addr_ctx *ctx); u8 (*get_socket_id_shift)(struct addr_ctx *ctx); int (*get_intlv_mode)(struct addr_ctx *ctx); @@ -1213,6 +1215,16 @@ static u8 get_socket_id_shift_df2(struct addr_ctx *ctx) return (ctx->reg_fab_id_mask0 >> 28) & 0xF; } +static u16 get_dst_fabric_id_df2(struct addr_ctx *ctx) +{ + return ctx->reg_limit_addr & 0xFF; +} + +static u16 get_component_id_mask_df2(struct addr_ctx *ctx) +{ + return (~(ctx->socket_id_mask | ctx->die_id_mask)) & 0xFF; +} + struct data_fabric_ops df2_ops = { .get_hi_addr_offset = get_hi_addr_offset_df2, .get_intlv_mode = get_intlv_mode_df2, @@ -1222,6 +1234,8 @@ struct data_fabric_ops df2_ops = { .get_masks = get_masks_df2, .get_die_id_shift = get_die_id_shift_df2, .get_socket_id_shift = get_socket_id_shift_df2, + .get_dst_fabric_id = get_dst_fabric_id_df2, + .get_component_id_mask = get_component_id_mask_df2, }; struct data_fabric_ops *df_ops; @@ -1310,38 +1324,42 @@ static void get_intlv_num_chan(struct addr_ctx *ctx) } } -static int calculate_cs_id(struct addr_ctx *ctx) +static u8 calc_level_bits(u8 id, u8 level_mask, u8 shift, u8 mask, u8 num_bits) { - u8 die_id_bit = 0, sock_id_bit, cs_mask = 0; + return (((id & level_mask) >> shift) & mask) << num_bits; +} - /* If interleaved over more than 1 channel: */ - if (ctx->intlv_num_chan) { - die_id_bit = ctx->intlv_num_chan; - cs_mask = (1 << die_id_bit) - 1; - ctx->cs_id = ctx->cs_fabric_id & cs_mask; - } +static int calculate_cs_id(struct addr_ctx *ctx) +{ + u16 dst_fabric_id = df_ops->get_dst_fabric_id(ctx); + u16 mask, num_intlv_bits = ctx->intlv_num_chan; - /* Return early if no die interleaving and no socket interleaving. */ - if (!(ctx->intlv_num_dies || ctx->intlv_num_sockets)) - return 0; + mask = df_ops->get_component_id_mask(ctx); + ctx->cs_id = (ctx->cs_fabric_id & mask) - (dst_fabric_id & mask); - sock_id_bit = die_id_bit; + mask = (1 << num_intlv_bits) - 1; + ctx->cs_id &= mask; /* If interleaved over more than 1 die: */ if (ctx->intlv_num_dies) { u8 die_id_shift = df_ops->get_die_id_shift(ctx); - sock_id_bit = die_id_bit + ctx->intlv_num_dies; - ctx->cs_id |= ((ctx->cs_fabric_id & ctx->die_id_mask) - >> die_id_shift) << die_id_bit; + mask = (1 << ctx->intlv_num_dies) - 1; + + ctx->cs_id |= calc_level_bits(ctx->cs_fabric_id, ctx->die_id_mask, + die_id_shift, mask, num_intlv_bits); + + num_intlv_bits += ctx->intlv_num_dies; } /* If interleaved over more than 1 socket: */ if (ctx->intlv_num_sockets) { u8 socket_id_shift = df_ops->get_socket_id_shift(ctx); - ctx->cs_id |= ((ctx->cs_fabric_id & ctx->socket_id_mask) - >> socket_id_shift) << sock_id_bit; + mask = (1 << ctx->intlv_num_sockets) - 1; + + ctx->cs_id |= calc_level_bits(ctx->cs_fabric_id, ctx->socket_id_mask, + socket_id_shift, mask, num_intlv_bits); } return 0; From patchwork Thu Jan 27 20:41:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12727375 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 600B0C433EF for ; Thu, 27 Jan 2022 20:42:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344131AbiA0UmH (ORCPT ); Thu, 27 Jan 2022 15:42:07 -0500 Received: from mail-bn7nam10on2058.outbound.protection.outlook.com ([40.107.92.58]:34074 "EHLO NAM10-BN7-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1344202AbiA0Ul5 (ORCPT ); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jan 2022 20:41:51.7008 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 186d5c3f-aa1d-4abd-0199-08d9e1d572bf X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT028.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4040 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org The reference code for DF2 hashing was changed to XOR the interleave address bit rather than the CS ID. Match that here. Signed-off-by: Yazen Ghannam --- Link: https://lore.kernel.org/r/20211028175728.121452-28-yazen.ghannam@amd.com v3->v4: * No change. v2->v3: * Was patch 28 in v2. v1->v2: * Moved from arch/x86 to EDAC. drivers/edac/amd64_edac.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index e293aefd486e..601ececf5106 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1142,7 +1142,7 @@ static int dehash_addr_df2(struct addr_ctx *ctx) (ctx->ret_addr >> 18) ^ (ctx->ret_addr >> 21) ^ (ctx->ret_addr >> 30) ^ - ctx->cs_id; + (ctx->ret_addr >> ctx->intlv_addr_bit); hashed_bit &= BIT(0); From patchwork Thu Jan 27 20:41:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12727377 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1419C4332F for ; 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Thu, 27 Jan 2022 14:41:46 -0600 From: Yazen Ghannam To: CC: , , , , , , , Yazen Ghannam Subject: [PATCH v4 23/24] EDAC/amd64: Define function to get interleave address select bit Date: Thu, 27 Jan 2022 20:41:14 +0000 Message-ID: <20220127204115.384161-24-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220127204115.384161-1-yazen.ghannam@amd.com> References: <20220127204115.384161-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 0c4e6769-8097-4c77-7596-08d9e1d5730b X-MS-TrafficTypeDiagnostic: BL0PR12MB5507:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3173; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 9SnBt1hAGBwRVrvAvfYWcIf2A8hK839fUZryBpe4sRIE7LDR5YMc5zFtKQVL6NzK2LwGQnyxZygwrgjU5FCGS/R0ki+53ifKhTlxOGcBYXzVmYKv06GijYWtz9UCQSiFQR0se1+tFX539Z6CJgQDi2/O02qcYVVQ4biwcdfE34tx0Q9JS+Wx++U7qWN4KRjrJ62zzMBod+fzMndXzYSN5w8k9nqbQREzKkAXiGu1FQyosZWzwQgjrBMpexfqWboeFIlsDjqlCzp+b4UkY07T5HeqmPBSMt6Y96K9XoV1Nf9rFPCNtWxAz0H2JdXWPhka4L5Ev1hAZot/G50ImOg+qTLWgsypWu7N2RgarqX0kHXUQp7AJLZKo2gdn2kGlwEO48UJVEGc+czRd51I/Ekg9OL0KIwSl+1nofDulZ+Q3ipMqgonoAb+N3BL0XUdYaWkS+KVPJ4+hGd+y+pDd4p/pfOg1R9b1SJqADAaUtZJhkHjgPX1ZJ5aCsKCSv0gS95Cejjlg4OAbCRZ5OqBjfnZrvnwMXCOWOTaOyStTXGRbqvq7cr8plMKYSTd9y1kLPum/UO+bTN/hOKB8muQnTfAVt/5ja9/j7G0lc8xVeoyP3HqfWktQQVYm4lwdUIIZ/cq2tKz+CxgEFc74AdGKwMFscxlJx68zhaZCyQBip2hqvfoyYcCTGLYeZ/caGgBURwO32tbLYmZud3bx0+Xg/fKsPfsvriK/UxRsUmaVAh1CM0z5Qp00/6McJ/4NwplNj2hwme8A6yMRSWkEzqLxp1hAZBtUJ+wUaZTKKxeerJMhdo= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230001)(4636009)(46966006)(40470700004)(36840700001)(7696005)(6666004)(54906003)(47076005)(508600001)(82310400004)(83380400001)(86362001)(316002)(966005)(81166007)(6916009)(40460700003)(36756003)(4326008)(44832011)(1076003)(16526019)(336012)(426003)(186003)(26005)(36860700001)(2616005)(70586007)(356005)(8936002)(5660300002)(70206006)(2906002)(8676002)(36900700001)(20210929001);DIR:OUT;SFP:1101; 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Signed-off-by: Yazen Ghannam --- Link: https://lore.kernel.org/r/20211028175728.121452-29-yazen.ghannam@amd.com v3->v4: * Remove leading whitespace in function pointer. v2->v3: * Was patch 29 in v2. v1->v2: * New in v2. drivers/edac/amd64_edac.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 601ececf5106..34405c8940fb 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1096,6 +1096,7 @@ struct data_fabric_ops { u16 (*get_component_id_mask)(struct addr_ctx *ctx); u8 (*get_die_id_shift)(struct addr_ctx *ctx); u8 (*get_socket_id_shift)(struct addr_ctx *ctx); + u8 (*get_intlv_addr_sel)(struct addr_ctx *ctx); int (*get_intlv_mode)(struct addr_ctx *ctx); int (*get_cs_fabric_id)(struct addr_ctx *ctx); int (*get_masks)(struct addr_ctx *ctx); @@ -1172,6 +1173,11 @@ static int get_intlv_mode_df2(struct addr_ctx *ctx) return 0; } +static u8 get_intlv_addr_sel_df2(struct addr_ctx *ctx) +{ + return (ctx->reg_base_addr >> 8) & 0x7; +} + static void get_intlv_num_dies_df2(struct addr_ctx *ctx) { ctx->intlv_num_dies = (ctx->reg_limit_addr >> 10) & 0x3; @@ -1228,6 +1234,7 @@ static u16 get_component_id_mask_df2(struct addr_ctx *ctx) struct data_fabric_ops df2_ops = { .get_hi_addr_offset = get_hi_addr_offset_df2, .get_intlv_mode = get_intlv_mode_df2, + .get_intlv_addr_sel = get_intlv_addr_sel_df2, .get_intlv_num_dies = get_intlv_num_dies_df2, .get_intlv_num_sockets = get_intlv_num_sockets_df2, .get_cs_fabric_id = get_cs_fabric_id_df2, @@ -1294,7 +1301,7 @@ static int get_dram_addr_map(struct addr_ctx *ctx) static int get_intlv_addr_bit(struct addr_ctx *ctx) { - u8 intlv_addr_sel = (ctx->reg_base_addr >> 8) & 0x7; + u8 intlv_addr_sel = df_ops->get_intlv_addr_sel(ctx); /* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */ if (intlv_addr_sel > 3) { From patchwork Thu Jan 27 20:41:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12727374 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B13AC433FE for ; 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Thu, 27 Jan 2022 14:41:47 -0600 From: Yazen Ghannam To: CC: , , , , , , , Yazen Ghannam Subject: [PATCH v4 24/24] EDAC/amd64: Add support for address translation on DF3 systems Date: Thu, 27 Jan 2022 20:41:15 +0000 Message-ID: <20220127204115.384161-25-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220127204115.384161-1-yazen.ghannam@amd.com> References: <20220127204115.384161-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 39f3dd8b-c110-4068-0e36-08d9e1d5732f X-MS-TrafficTypeDiagnostic: PH0PR12MB5403:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5236; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: WiwT/OUBwsZvTqdmllbHQt/BSldy4T5PhKyRj8bw9SJnFRbhZHdhLOJUX1QzP8ZZVS5POyNzPUMnZ0FENgFXcKG2sFHzsmdE5jCuV3mCHrM6RYa1EBUYlP3FGhki0bcnpQeEEHsOAHQqrhdf8/tGdWmsllTsPuuRF101N97wYGXkQMh36C5/2VM2Q4i9+YUvo5m81d3nhs9TTZtM0MrwudjOVmwVoSlcuBpnRh9NOq1UDTdl91x/HSxYqLKz/3bl6fsPh8Zjy9qV5HhE8bgYWMyZTNFmjdbIiVaBXWX4g2B8jC0jyV4zA7b91NubDswnoBZIvZFHQHZiynCbNetHwTB7WQ2AfjO5375MxbpEgtcslI2SPqRdz0d48iPFj7zAVR5skR7+UvpZgeeukOGfM3O8nnqn+w4hUEf2xURrn2nXDs3RsJnpblCtgHthnfvmW83ZBSKWQvkXY3fgpvSDODF1nguE4oy7P6p4YJ2I7TQDvucUQYEc1xzE3lttf+VC4VpmgBnYO7fwORDEI2jbu32AimuTBPqbw4Lv0xh1j3/gJzrCVnda4pWTrS6uf17SRPqlfCtbKVrjvkU4huNTnGhjc5auls8Jp7T7CtpPlZFU2u1gE9DSX/77MV1YO1XcuqDmUHZQAK6nPBbuwvrjC+7e9Qw5OT16PDuoKBdtThlSwodK2BownJ0bCZ7wHU+1E1EHyDWlcdyf6qYm5Je1xkapweZqMispHcrhDqTucFdT9kM4q8mtzmBvV0BpR8KS9PBUAboVqIgq7raWM5NjDXF45ftaiIq4bWF9LGdRGy+hzpB2B9Qaso/TbI1zYIunTVP1Bre7ZHQ0i0XyMclHy1rBenWvMck/wb6IvFGUHY/XStEPR5sQqKth0tfd17+k X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(40470700004)(46966006)(356005)(1076003)(508600001)(70586007)(5660300002)(82310400004)(40460700003)(26005)(316002)(36756003)(6666004)(6916009)(44832011)(8676002)(7696005)(2616005)(86362001)(966005)(2906002)(4326008)(70206006)(36860700001)(81166007)(54906003)(16526019)(8936002)(186003)(47076005)(83380400001)(336012)(426003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jan 2022 20:41:52.4352 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 39f3dd8b-c110-4068-0e36-08d9e1d5732f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT028.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5403 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org DF3-based systems (Rome and later) support new interleaving modes and a number of bit fields have changed or moved entirely. Add support for these new modes and fields. Refactoring should be minimal due to earlier changes, and most updates will be additions. Signed-off-by: Yazen Ghannam --- Link: https://lore.kernel.org/r/20211028175728.121452-30-yazen.ghannam@amd.com v3->v4: * Added glossary entry. v2->v3: * Was patch 30 in v2. * Drop "df_regs" use. * Set "df_ops" during module init. v1->v2: * Moved from arch/x86 to EDAC. * Use function pointers as needed. drivers/edac/amd64_edac.c | 188 +++++++++++++++++++++++++++++++++++++- 1 file changed, 186 insertions(+), 2 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 34405c8940fb..d213f9ecab16 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -991,6 +991,7 @@ static int sys_addr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr) /* * Glossary of acronyms used in address translation for Zen-based systems * + * COD = Cluster-on-Die * CS = Coherent Slave * DF = Data Fabric */ @@ -1062,6 +1063,11 @@ static int df_indirect_read_broadcast(u16 node, u8 func, u16 reg, u32 *lo) enum intlv_modes { NONE = 0x00, NOHASH_2CH = 0x01, + NOHASH_4CH = 0x03, + NOHASH_8CH = 0x05, + HASH_COD4_2CH = 0x0C, + HASH_COD2_4CH = 0x0D, + HASH_COD1_8CH = 0x0E, DF2_HASH_2CH = 0x21, }; @@ -1074,6 +1080,7 @@ struct addr_ctx { u32 reg_base_addr; u32 reg_limit_addr; u32 reg_fab_id_mask0; + u32 reg_fab_id_mask1; u16 cs_fabric_id; u16 die_id_mask; u16 socket_id_mask; @@ -1085,6 +1092,7 @@ struct addr_ctx { u8 intlv_num_dies; u8 intlv_num_sockets; u8 cs_id; + u8 node_id_shift; int (*dehash_addr)(struct addr_ctx *ctx); void (*make_space_for_cs_id)(struct addr_ctx *ctx); void (*insert_cs_id)(struct addr_ctx *ctx); @@ -1245,6 +1253,168 @@ struct data_fabric_ops df2_ops = { .get_component_id_mask = get_component_id_mask_df2, }; +static u64 get_hi_addr_offset_df3(struct addr_ctx *ctx) +{ + return (ctx->reg_dram_offset & GENMASK_ULL(31, 12)) << 16; +} + +static void make_space_for_cs_id_cod_hash(struct addr_ctx *ctx) +{ + u8 num_intlv_bits = ctx->intlv_num_chan; + + num_intlv_bits += ctx->intlv_num_sockets; + expand_bits(ctx->intlv_addr_bit, 1, &ctx->ret_addr); + if (num_intlv_bits > 1) + expand_bits(12, num_intlv_bits - 1, &ctx->ret_addr); +} + +static void insert_cs_id_cod_hash(struct addr_ctx *ctx) +{ + ctx->ret_addr |= ((ctx->cs_id & 0x1) << ctx->intlv_addr_bit); + ctx->ret_addr |= ((ctx->cs_id & 0xE) << 11); +} + +static int dehash_addr_df3(struct addr_ctx *ctx) +{ + u8 hashed_bit, intlv_ctl_64k, intlv_ctl_2M, intlv_ctl_1G; + + /* Read D18F0x3F8 (DfGlobalCtrl). */ + if (df_indirect_read_broadcast(0, 0, 0x3F8, &ctx->tmp)) + return -EINVAL; + + intlv_ctl_64k = !!((ctx->tmp >> 20) & 0x1); + intlv_ctl_2M = !!((ctx->tmp >> 21) & 0x1); + intlv_ctl_1G = !!((ctx->tmp >> 22) & 0x1); + + hashed_bit = (ctx->ret_addr >> 14) ^ + ((ctx->ret_addr >> 18) & intlv_ctl_64k) ^ + ((ctx->ret_addr >> 23) & intlv_ctl_2M) ^ + ((ctx->ret_addr >> 32) & intlv_ctl_1G) ^ + (ctx->ret_addr >> ctx->intlv_addr_bit); + + hashed_bit &= BIT(0); + + if (hashed_bit != ((ctx->ret_addr >> ctx->intlv_addr_bit) & BIT(0))) + ctx->ret_addr ^= BIT(ctx->intlv_addr_bit); + + if (ctx->intlv_mode != HASH_COD2_4CH && + ctx->intlv_mode != HASH_COD1_8CH) + return 0; + + hashed_bit = (ctx->ret_addr >> 12) ^ + ((ctx->ret_addr >> 16) & intlv_ctl_64k) ^ + ((ctx->ret_addr >> 21) & intlv_ctl_2M) ^ + ((ctx->ret_addr >> 30) & intlv_ctl_1G); + + hashed_bit &= BIT(0); + + if (hashed_bit != ((ctx->ret_addr >> 12) & BIT(0))) + ctx->ret_addr ^= BIT(12); + + if (ctx->intlv_mode != HASH_COD1_8CH) + return 0; + + hashed_bit = (ctx->ret_addr >> 13) ^ + ((ctx->ret_addr >> 17) & intlv_ctl_64k) ^ + ((ctx->ret_addr >> 22) & intlv_ctl_2M) ^ + ((ctx->ret_addr >> 31) & intlv_ctl_1G); + + hashed_bit &= BIT(0); + + if (hashed_bit != ((ctx->ret_addr >> 13) & BIT(0))) + ctx->ret_addr ^= BIT(13); + + return 0; +} + +static int get_intlv_mode_df3(struct addr_ctx *ctx) +{ + ctx->intlv_mode = (ctx->reg_base_addr >> 2) & 0xF; + + if (ctx->intlv_mode == HASH_COD4_2CH || + ctx->intlv_mode == HASH_COD2_4CH || + ctx->intlv_mode == HASH_COD1_8CH) { + ctx->make_space_for_cs_id = make_space_for_cs_id_cod_hash; + ctx->insert_cs_id = insert_cs_id_cod_hash; + ctx->dehash_addr = dehash_addr_df3; + } else { + ctx->make_space_for_cs_id = make_space_for_cs_id_simple; + ctx->insert_cs_id = insert_cs_id_simple; + } + + return 0; +} + +static u8 get_intlv_addr_sel_df3(struct addr_ctx *ctx) +{ + return (ctx->reg_base_addr >> 9) & 0x7; +} + +static void get_intlv_num_dies_df3(struct addr_ctx *ctx) +{ + ctx->intlv_num_dies = (ctx->reg_base_addr >> 6) & 0x3; +} + +static void get_intlv_num_sockets_df3(struct addr_ctx *ctx) +{ + ctx->intlv_num_sockets = (ctx->reg_base_addr >> 8) & 0x1; +} + +static u8 get_die_id_shift_df3(struct addr_ctx *ctx) +{ + return ctx->node_id_shift; +} + +static u8 get_socket_id_shift_df3(struct addr_ctx *ctx) +{ + return ((ctx->reg_fab_id_mask1 >> 8) & 0x3) + ctx->node_id_shift; +} + +static int get_masks_df3(struct addr_ctx *ctx) +{ + /* Read D18F1x208 (SystemFabricIdMask). */ + if (df_indirect_read_broadcast(ctx->nid, 1, 0x208, &ctx->reg_fab_id_mask0)) + return -EINVAL; + + /* Read D18F1x20C (SystemFabricIdMask1) */ + if (df_indirect_read_broadcast(0, 1, 0x20C, &ctx->reg_fab_id_mask1)) + return -EINVAL; + + ctx->node_id_shift = ctx->reg_fab_id_mask1 & 0xF; + + ctx->die_id_mask = (ctx->reg_fab_id_mask1 >> 16) & 0x7; + ctx->die_id_mask <<= ctx->node_id_shift; + + ctx->socket_id_mask = (ctx->reg_fab_id_mask1 >> 24) & 0x7; + ctx->socket_id_mask <<= ctx->node_id_shift; + + return 0; +} + +static u16 get_dst_fabric_id_df3(struct addr_ctx *ctx) +{ + return ctx->reg_limit_addr & 0x3FF; +} + +static u16 get_component_id_mask_df3(struct addr_ctx *ctx) +{ + return ctx->reg_fab_id_mask0 & 0x3FF; +} + +struct data_fabric_ops df3_ops = { + .get_hi_addr_offset = get_hi_addr_offset_df3, + .get_intlv_mode = get_intlv_mode_df3, + .get_intlv_addr_sel = get_intlv_addr_sel_df3, + .get_intlv_num_dies = get_intlv_num_dies_df3, + .get_intlv_num_sockets = get_intlv_num_sockets_df3, + .get_cs_fabric_id = get_cs_fabric_id_df2, + .get_masks = get_masks_df3, + .get_die_id_shift = get_die_id_shift_df3, + .get_socket_id_shift = get_socket_id_shift_df3, + .get_dst_fabric_id = get_dst_fabric_id_df3, + .get_component_id_mask = get_component_id_mask_df3, +}; + struct data_fabric_ops *df_ops; static int get_dram_offset_reg(struct addr_ctx *ctx) @@ -1303,8 +1473,8 @@ static int get_intlv_addr_bit(struct addr_ctx *ctx) { u8 intlv_addr_sel = df_ops->get_intlv_addr_sel(ctx); - /* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */ - if (intlv_addr_sel > 3) { + /* {0, 1, 2, 3, 4} map to address bits {8, 9, 10, 11, 12} respectively */ + if (intlv_addr_sel > 4) { pr_debug("Invalid interleave address select %d.\n", intlv_addr_sel); return -EINVAL; } @@ -1322,9 +1492,18 @@ static void get_intlv_num_chan(struct addr_ctx *ctx) ctx->intlv_num_chan = 0; break; case NOHASH_2CH: + case HASH_COD4_2CH: case DF2_HASH_2CH: ctx->intlv_num_chan = 1; break; + case NOHASH_4CH: + case HASH_COD2_4CH: + ctx->intlv_num_chan = 2; + break; + case NOHASH_8CH: + case HASH_COD1_8CH: + ctx->intlv_num_chan = 3; + break; default: /* Valid interleaving modes where checked earlier. */ break; @@ -4197,14 +4376,17 @@ static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt) } else if (pvt->model >= 0x30 && pvt->model <= 0x3f) { fam_type = &family_types[F17_M30H_CPUS]; pvt->ops = &family_types[F17_M30H_CPUS].ops; + df_ops = &df3_ops; break; } else if (pvt->model >= 0x60 && pvt->model <= 0x6f) { fam_type = &family_types[F17_M60H_CPUS]; pvt->ops = &family_types[F17_M60H_CPUS].ops; + df_ops = &df3_ops; break; } else if (pvt->model >= 0x70 && pvt->model <= 0x7f) { fam_type = &family_types[F17_M70H_CPUS]; pvt->ops = &family_types[F17_M70H_CPUS].ops; + df_ops = &df3_ops; break; } fallthrough; @@ -4226,6 +4408,7 @@ static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt) fam_type = &family_types[F17_M70H_CPUS]; pvt->ops = &family_types[F17_M70H_CPUS].ops; fam_type->ctl_name = "F19h_M20h"; + df_ops = &df3_ops; break; } else if (pvt->model >= 0x50 && pvt->model <= 0x5f) { fam_type = &family_types[F19_M50H_CPUS]; @@ -4241,6 +4424,7 @@ static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt) fam_type = &family_types[F19_CPUS]; pvt->ops = &family_types[F19_CPUS].ops; family_types[F19_CPUS].ctl_name = "F19h"; + df_ops = &df3_ops; break; default: