From patchwork Fri Jan 28 18:52:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramalingam C X-Patchwork-Id: 12728948 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 05243C433EF for ; Fri, 28 Jan 2022 18:52:18 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EACA910E64A; Fri, 28 Jan 2022 18:52:16 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 13DDF10E5CB; Fri, 28 Jan 2022 18:52:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643395932; x=1674931932; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PzzBi2+LB1Na/jfOueySihbt7n2cABn4KoK4T5UK9d0=; b=FnU42RD76ABGPpLJDZ7/Z+ByKxDh7seEE4h84OreJYz5laADwkw8jw0n +RA4zgYMIO8YIIfiEiMCld9yofBbXwvdS6eG9sUMx1W1WTb1JXz1RKck5 lu0/ojMAg6zBUgE5IzSILK7k/zGDZ4R2Ppq5l8ammv9vYWNwMYj63ZBO4 XkHCJwT5koVdrOVkazFKtP/f+uTyTC4pczmOB6w3GrDyIMIiD/v42CLR6 QmzLwHbRdymO1zUl/COyK7/y8vO7w+JH0x/GzVy1+7uOreHbaXVTjjeSP jH+NFY31bsB53Jo5y2MWMpPXpHyc891+BWj4hMPlBNfZ0UDfg2YO64sSA Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10240"; a="310490186" X-IronPort-AV: E=Sophos;i="5.88,324,1635231600"; d="scan'208";a="310490186" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2022 10:52:11 -0800 X-IronPort-AV: E=Sophos;i="5.88,324,1635231600"; d="scan'208";a="625718024" Received: from ramaling-i9x.iind.intel.com ([10.203.144.108]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2022 10:52:08 -0800 From: Ramalingam C To: intel-gfx , dri-devel Subject: [PATCH 1/5] drm/i915/dg2: Add Wa_22011450934 Date: Sat, 29 Jan 2022 00:22:05 +0530 Message-Id: <20220128185209.18077-2-ramalingam.c@intel.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220128185209.18077-1-ramalingam.c@intel.com> References: <20220128185209.18077-1-ramalingam.c@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Hellstrom Thomas , Matthew Auld , Chris Wilson Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" An indirect ctx wabb is implemented as per Wa_22011450934 to avoid rcs restore hang during context restore of a preempted context in GPGPU mode Signed-off-by: Ramalingam C cc: Chris Wilson Acked-by: Matthew Auld --- drivers/gpu/drm/i915/gt/intel_lrc.c | 28 ++++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 4 ++++ 2 files changed, 32 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 89a95a125fc8..8440f4b0f613 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1165,6 +1165,29 @@ gen12_emit_cmd_buf_wa(const struct intel_context *ce, u32 *cs) return cs; } +/* + * On DG2 during context restore of a preempted context in GPGPU mode, + * RCS restore hang is detected. This is extremely timing dependent. + * To address this below sw wabb is implemented for DG2 A steppings. + */ +static u32 * +dg2_emit_rcs_hang_wabb(const struct intel_context *ce, u32 *cs) +{ + *cs++ = MI_LOAD_REGISTER_IMM(1); + *cs++ = i915_mmio_reg_offset(GEN12_STATE_ACK_DEBUG); + *cs++ = 0x21; + + *cs++ = MI_LOAD_REGISTER_REG; + *cs++ = i915_mmio_reg_offset(RING_NOPID(ce->engine->mmio_base)); + *cs++ = i915_mmio_reg_offset(GEN12_CULLBIT1); + + *cs++ = MI_LOAD_REGISTER_REG; + *cs++ = i915_mmio_reg_offset(RING_NOPID(ce->engine->mmio_base)); + *cs++ = i915_mmio_reg_offset(GEN12_CULLBIT2); + + return cs; +} + static u32 * gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs) { @@ -1172,6 +1195,11 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs) cs = gen12_emit_cmd_buf_wa(ce, cs); cs = gen12_emit_restore_scratch(ce, cs); + /* Wa_22011450934:dg2 */ + if (IS_DG2_GRAPHICS_STEP(ce->engine->i915, G10, STEP_A0, STEP_B0) || + IS_DG2_GRAPHICS_STEP(ce->engine->i915, G11, STEP_A0, STEP_B0)) + cs = dg2_emit_rcs_hang_wabb(ce, cs); + /* Wa_16013000631:dg2 */ if (IS_DG2_GRAPHICS_STEP(ce->engine->i915, G10, STEP_B0, STEP_C0) || IS_DG2_G11(ce->engine->i915)) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ec48406eb37a..3f94f4b5ef6c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -12026,4 +12026,8 @@ enum skl_power_gate { #define SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731C) #define MSC_MSAA_REODER_BUF_BYPASS_DISABLE REG_BIT(14) +#define GEN12_CULLBIT1 _MMIO(0x6100) +#define GEN12_CULLBIT2 _MMIO(0x7030) +#define GEN12_STATE_ACK_DEBUG _MMIO(0x20BC) + #endif /* _I915_REG_H_ */ From patchwork Fri Jan 28 18:52:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramalingam C X-Patchwork-Id: 12728950 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 76947C433FE for ; Fri, 28 Jan 2022 18:52:22 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 59C0710E752; Fri, 28 Jan 2022 18:52:19 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3BC5710E752; Fri, 28 Jan 2022 18:52:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643395937; x=1674931937; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=QJdXPyU5oTAxDiQoh/0/qeoqVUU5wh9YcGZsW6UH1UI=; b=E/fGaOjnD1k0jI9RbHlPn2sozPU82QZjxoWYU6HBAo6ghk041SeIUCH1 3JSyk12GazTu8RO1RhuHOULMtnOQgynS4cayy9TvaZNeYAcZXjlyDWwEz goo8sgLrNQ/uSlR/vKaHGKojSF4JEs8IQ+zaCdkc6TciZ7uufRnfZr8zz 9yWnLAWhTISnownJb2FLekJsrrZ0H0IyFzLByfIk5JcTdG8ltsodgFD4C pmGGO0bPx7cZPRq7waFjEd968kSbDyz95uUT43fQy95OxOKG5pyNcE8eh J6u3CEnK/lXHehLa1GwLbGdWy40PMkxsXzYhRy6WNPfYZGP21o/qJyvTM Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10240"; a="310490195" X-IronPort-AV: E=Sophos;i="5.88,324,1635231600"; d="scan'208";a="310490195" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2022 10:52:12 -0800 X-IronPort-AV: E=Sophos;i="5.88,324,1635231600"; d="scan'208";a="625718046" Received: from ramaling-i9x.iind.intel.com ([10.203.144.108]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2022 10:52:10 -0800 From: Ramalingam C To: intel-gfx , dri-devel Subject: [PATCH 2/5] drm/i915: align the plane_vma to min_page_size of stolen mem Date: Sat, 29 Jan 2022 00:22:06 +0530 Message-Id: <20220128185209.18077-3-ramalingam.c@intel.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220128185209.18077-1-ramalingam.c@intel.com> References: <20220128185209.18077-1-ramalingam.c@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Hellstrom Thomas , Matthew Auld , Chris P Wilson Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Align the plane vma size to the stolem memory regions' min_page_size. Signed-off-by: Ramalingam C cc: Matthew Auld cc: Chris P Wilson Reviewed-by: Matthew Auld --- drivers/gpu/drm/i915/display/intel_plane_initial.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c index e4186a0b8edb..543877998078 100644 --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c @@ -46,17 +46,18 @@ static struct i915_vma * initial_plane_vma(struct drm_i915_private *i915, struct intel_initial_plane_config *plane_config) { + struct intel_memory_region *mem = i915->mm.stolen_region; struct drm_i915_gem_object *obj; struct i915_vma *vma; u32 base, size; - if (plane_config->size == 0) + if (!mem || plane_config->size == 0) return NULL; base = round_down(plane_config->base, I915_GTT_MIN_ALIGNMENT); size = round_up(plane_config->base + plane_config->size, - I915_GTT_MIN_ALIGNMENT); + mem->min_page_size); size -= base; /* From patchwork Fri Jan 28 18:52:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramalingam C X-Patchwork-Id: 12728949 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CB5DAC433EF for ; Fri, 28 Jan 2022 18:52:20 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 14C0C10E6D9; Fri, 28 Jan 2022 18:52:19 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id AD57B10E6D9; Fri, 28 Jan 2022 18:52:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643395937; x=1674931937; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=KsIBZZ4VxWwVy1BlaR+Adfd3mV1tuB07oNSgHkb7Yqc=; b=av+LXLrkZ3bAe8HknNS305qAHXlii4AXBdrFXhV9/bUnWxAdBuXDUoAN XtRou/wx4/G8crJMk0iJ0nz/zFwkDlDHfXppLvWuLFLJxWYB6f+HvMTIp 7jicGGrCCFzJo4DgtEYc8QZn6ACCnRCORWpJTDH40Rcmp1DaeD4IubNxu 46bvQwJr3AUxv0c7m/Re/YaMC0wewbP6bLA32xwnmGPVLqJIgaTzvLcE5 TNO/C+/pWWWLM2NVHF/edAhQLgQLCRNRkwi9sNqUBwBmxqN3Xh8y5YPvb RKNGofiUKQxmvMITU1SqneOrAVypjm0wTjFQHm7F+fSXawGczF+C1TCzl w==; X-IronPort-AV: E=McAfee;i="6200,9189,10240"; a="310490200" X-IronPort-AV: E=Sophos;i="5.88,324,1635231600"; d="scan'208";a="310490200" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2022 10:52:14 -0800 X-IronPort-AV: E=Sophos;i="5.88,324,1635231600"; d="scan'208";a="625718060" Received: from ramaling-i9x.iind.intel.com ([10.203.144.108]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2022 10:52:12 -0800 From: Ramalingam C To: intel-gfx , dri-devel Subject: [PATCH 3/5] drm/i915: More gt idling time with guc submission Date: Sat, 29 Jan 2022 00:22:07 +0530 Message-Id: <20220128185209.18077-4-ramalingam.c@intel.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220128185209.18077-1-ramalingam.c@intel.com> References: <20220128185209.18077-1-ramalingam.c@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Matthew Brost , Hellstrom Thomas , Matthew Auld Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On i915_selftest@live@gt_timelines, we create many contexts in loop and create and submit request and then destoy contexts. Destroying the context needs to disable scheduling, wait for G2H, deregister context and wait for G2H to destroy each context. Idling of the gt has to wait for all this to complete which is taking ~3sec for this test. Hence we are increasing the igt_flush_test's timeout for gt idling to 3Sec. Signed-off-by: Ramalingam C cc: Matthew Brost Acked-by: Matthew Auld --- drivers/gpu/drm/i915/selftests/igt_flush_test.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/selftests/igt_flush_test.c b/drivers/gpu/drm/i915/selftests/igt_flush_test.c index b84594601d30..b484e12df417 100644 --- a/drivers/gpu/drm/i915/selftests/igt_flush_test.c +++ b/drivers/gpu/drm/i915/selftests/igt_flush_test.c @@ -19,7 +19,7 @@ int igt_flush_test(struct drm_i915_private *i915) cond_resched(); - if (intel_gt_wait_for_idle(gt, HZ) == -ETIME) { + if (intel_gt_wait_for_idle(gt, HZ * 3) == -ETIME) { pr_err("%pS timed out, cancelling all further testing.\n", __builtin_return_address(0)); From patchwork Fri Jan 28 18:52:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramalingam C X-Patchwork-Id: 12728951 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 95972C433F5 for ; Fri, 28 Jan 2022 18:52:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8B7C310E818; Fri, 28 Jan 2022 18:52:30 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 028C310E76F; Fri, 28 Jan 2022 18:52:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643395938; x=1674931938; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PS1m/23XRkcfXAhz6RTQAnh4TmNL9PFELEsRwE9opwc=; b=RAB2GBNZtWqLCIFi+z3GhEtlrze9B3uKQ9if2rj8CtqYM3903/m723Dx LeOS8Xc7cgtSQIZXZCpE7bv7fTGqimsCgh/yLXAxQ9XyoEh3A/1kamJmm ChRv0gkiSzjymB9qjUconQWPhuRZg5f6WeIfH7W4Yqski0qiLZ3DydPMT Okr6mL2Bca91gVlFsPNqzJmegOOT6GvrDED8i8enHpsznoqWZIDyIuWRZ ZLKp3yUGgMb33Lc2hkHcNfiLNIp65UxpG6zsB0zWU4n/5n9HMYJlLgWdo LUX361VG4s/R3wwujgXG1eD/sumKBdXtWZihWLsjifanCHpYcQm+D70PB g==; X-IronPort-AV: E=McAfee;i="6200,9189,10240"; a="310490208" X-IronPort-AV: E=Sophos;i="5.88,324,1635231600"; d="scan'208";a="310490208" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2022 10:52:17 -0800 X-IronPort-AV: E=Sophos;i="5.88,324,1635231600"; d="scan'208";a="625718077" Received: from ramaling-i9x.iind.intel.com ([10.203.144.108]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2022 10:52:14 -0800 From: Ramalingam C To: intel-gfx , dri-devel Subject: [PATCH 4/5] drm/i915/dg2: Add Wa_22011100796 Date: Sat, 29 Jan 2022 00:22:08 +0530 Message-Id: <20220128185209.18077-5-ramalingam.c@intel.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220128185209.18077-1-ramalingam.c@intel.com> References: <20220128185209.18077-1-ramalingam.c@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Hellstrom Thomas , Matthew Auld , Rodrigo Vivi , Bruce Chang Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Bruce Chang Whenever Full soft reset is required, reset all individual engines first, and then do a full soft reset. Signed-off-by: Bruce Chang cc: Matt Roper Cc: Rodrigo Vivi Signed-off-by: Ramalingam C Acked-by: Matthew Auld --- drivers/gpu/drm/i915/gt/intel_reset.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c index 6f2821cca409..5fae56b89319 100644 --- a/drivers/gpu/drm/i915/gt/intel_reset.c +++ b/drivers/gpu/drm/i915/gt/intel_reset.c @@ -600,6 +600,15 @@ static int gen8_reset_engines(struct intel_gt *gt, */ } + /* + * Wa_22011100796:dg2, whenever Full soft reset is required, + * reset all individual engines firstly, and then do a full soft reset. + * + * This is best effort, so ignore any error from the initial reset. + */ + if (IS_DG2(gt->i915) && engine_mask == ALL_ENGINES) + gen11_reset_engines(gt, gt->info.engine_mask, 0); + if (GRAPHICS_VER(gt->i915) >= 11) ret = gen11_reset_engines(gt, engine_mask, retry); else From patchwork Fri Jan 28 18:52:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramalingam C X-Patchwork-Id: 12728952 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BF99DC433FE for ; Fri, 28 Jan 2022 18:52:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A2FE110E839; Fri, 28 Jan 2022 18:52:30 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id BF00E10E7E6; Fri, 28 Jan 2022 18:52:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643395940; x=1674931940; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ovHvM3IodaKvzqteIAV3pVOZXXDnULNc713QriI7oww=; b=lE6rk+rk3Hp7NyrO1n8cfyso0ceJ1Eu1epHIRBl/V3HVqiPx7q2PXKPa 46BehYyRsgn27tpTuJnhyD0fo6Bpg+G5mrsNypCgwyeZ67sCq/kZ8QJvG eXNBqtf+4n8jxlc2ryyh6aZhd1ncx2RXe70XK7Ui7Or/NMyxTX+56S5IH aWjEEohV7mfGuL8eg74fEQgvkHZ3n6IgG+hdcXR9NTzC7ji/DhS0WgECN qCehFhGsK9/ekd+FJJ/fDHr1wleP9ngfK3+OghMUKE2jBJ4wXsIeNmd99 1aPWaEuxLUHY5+l9Dk4AqGqGKs29+zIiaErtv1MlpsXENd5AGsPkJBhOq Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10240"; a="310490214" X-IronPort-AV: E=Sophos;i="5.88,324,1635231600"; d="scan'208";a="310490214" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2022 10:52:19 -0800 X-IronPort-AV: E=Sophos;i="5.88,324,1635231600"; d="scan'208";a="625718084" Received: from ramaling-i9x.iind.intel.com ([10.203.144.108]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2022 10:52:17 -0800 From: Ramalingam C To: intel-gfx , dri-devel Subject: [PATCH 5/5] drm/i915/guc: Allow user to override driver load failure without GuC Date: Sat, 29 Jan 2022 00:22:09 +0530 Message-Id: <20220128185209.18077-6-ramalingam.c@intel.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220128185209.18077-1-ramalingam.c@intel.com> References: <20220128185209.18077-1-ramalingam.c@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stuart Summers , Hellstrom Thomas , Matthew Auld , Radhakrishna Sripada Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Stuart Summers The driver is set currently to fail modprobe when GuC is disabled (enable_guc=0) after GuC has been loaded on a previous modprobe. For GuC deprivilege, the BIOS is setting the locked bit, so the driver always considers the GuC to have been loaded and thus does not support enable_guc=0 on these platforms. There are some debug scenarios where loading without GuC can be interesting. Add a new feature flag for GuC deprivilege and a mode (enable_guc=0x80) which can be exclusively set to skip the locked bit check. cc: Radhakrishna Sripada Signed-off-by: Stuart Summers Signed-off-by: Daniele Ceraolo Spurio Signed-off-by: Ramalingam C --- drivers/gpu/drm/i915/gt/uc/intel_uc.c | 17 +++++++++++++++-- drivers/gpu/drm/i915/i915_params.h | 1 + 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c index da199aa6989f..a1376dbd04fe 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c @@ -108,7 +108,7 @@ static void __confirm_options(struct intel_uc *uc) "Incompatible option enable_guc=%d - %s\n", i915->params.enable_guc, "GuC submission is N/A"); - if (i915->params.enable_guc & ~ENABLE_GUC_MASK) + if (i915->params.enable_guc & ~(ENABLE_GUC_MASK | ENABLE_GUC_DO_NOT_LOAD_GUC)) drm_info(&i915->drm, "Incompatible option enable_guc=%d - %s\n", i915->params.enable_guc, "undocumented flag"); @@ -416,8 +416,21 @@ static bool uc_is_wopcm_locked(struct intel_uc *uc) (intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET) & GUC_WOPCM_OFFSET_VALID); } +static inline bool skip_lock_check(struct drm_i915_private *i915) +{ + /* + * For platforms with GuC deprivilege, if a user *really* wants + * to run without GuC, let that happen by setting enable_guc=0x80. + */ + return (HAS_GUC_DEPRIVILEGE(i915) && + (i915->params.enable_guc & ENABLE_GUC_DO_NOT_LOAD_GUC) && + !(i915->params.enable_guc & ~ENABLE_GUC_DO_NOT_LOAD_GUC)); +} + static int __uc_check_hw(struct intel_uc *uc) { + struct drm_i915_private *i915 = uc_to_gt(uc)->i915; + if (!intel_uc_supports_guc(uc)) return 0; @@ -426,7 +439,7 @@ static int __uc_check_hw(struct intel_uc *uc) * before on this system after reboot, otherwise we risk GPU hangs. * To check if GuC was loaded before we look at WOPCM registers. */ - if (uc_is_wopcm_locked(uc)) + if (uc_is_wopcm_locked(uc) && likely(!skip_lock_check(i915))) return -EIO; return 0; diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index c9d53ff910a0..8996ba2cc3a8 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -32,6 +32,7 @@ struct drm_printer; #define ENABLE_GUC_SUBMISSION BIT(0) #define ENABLE_GUC_LOAD_HUC BIT(1) +#define ENABLE_GUC_DO_NOT_LOAD_GUC BIT(7) #define ENABLE_GUC_MASK GENMASK(1, 0) /*